US20110189850A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US20110189850A1 US20110189850A1 US13/084,623 US201113084623A US2011189850A1 US 20110189850 A1 US20110189850 A1 US 20110189850A1 US 201113084623 A US201113084623 A US 201113084623A US 2011189850 A1 US2011189850 A1 US 2011189850A1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- An LSI multilayered interconnection generally has a structure in which a barrier metal is formed on the side surfaces and bottom surface of a copper (Cu) film as an interconnection so as to surround the Cu film.
- Cu copper
- JP. 2006-5010 describes a semiconductor device having a multilayered interconnection structure using a porous low-k film as an interlayer dielectric film, and a method of manufacturing the device.
- a semiconductor device comprising: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a first interconnection formed in a trench formed in the first insulating film; a first barrier film formed between the first interconnection and the first insulating film; and a second insulating film formed on an upper surface of the first interconnection, and formed in a first hollow portion between a side surface of the first barrier film and the first insulating film, the second insulating film being formed from the upper surface of the first interconnection to a depth higher than a bottom surface of the first interconnection, and the first hollow portion being formed below a bottom surface of the second insulating film.
- a semiconductor device comprising: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a second insulating film formed on the first insulating film; a first interconnection formed in a trench formed in the first insulating film and the second insulating film; a first barrier film formed between the first interconnection and the first insulating film and the second insulating film; and a third insulating film formed on an upper surface of the first interconnection, and also formed in a first hollow portion between a side surface of the first barrier film and the first insulating film and the second insulating film, the third insulating film being formed from the upper surface of the first interconnection to a depth higher than a bottom surface of the first interconnection, and the first hollow portion being formed below the third insulating film.
- a semiconductor device manufacturing method comprising: forming a first insulating film on a semiconductor substrate; forming a trench in the first insulating film; forming a barrier film on a side and bottom surface of the trench; forming an interconnection on the barrier film in the trench; and forming a hollow portion between the barrier film and the first insulating film by removing a low-carbon (C)-concentration portion of the first insulating film which exists near a side surface of the barrier film.
- C low-carbon
- FIGS. 1A to 1D , 2 A to 2 D, and 3 A to 3 D are sectional views showing the manufacturing process of a semiconductor device according to a first embodiment
- FIGS. 4A to 4E , 5 A to 5 D, and 6 A to 6 D are sectional views showing the manufacturing process of a semiconductor device according to a second embodiment
- FIGS. 7A and 7B are sectional views showing the manufacturing process of a semiconductor device according to a third embodiment
- FIGS. 8A to 8D are sectional views showing the manufacturing process of a semiconductor device according to a fourth embodiment.
- the first embodiment uses Cu as an interconnection, and low-k SiOC as a layer in which a via hole and the interconnection are formed.
- a 50-200 nm thick SiO 2 film (insulating film) 2 is deposited on a silicon (Si) substrate (semiconductor substrate) 1 by plasma CVD.
- a 100-300 nm thick, low-k SiOC film (insulating film) 3 is deposited on the SiO 2 film 2 by plasma CVD.
- a trench 31 for an interconnection is formed in the SiOC film 3 by plasma etching.
- a portion 32 in which the C (carbon) concentration is made lower than that in other portions of the SiOC film 3 by plasma damage is formed on the sidewalls and bottom surface of the interconnection trench 31 .
- the thickness of the portion 32 is 2-10 nm.
- a 5-15 nm thick barrier metal (barrier film) 4 made of Ti or Ta is deposited on the SiOC film 3 and in the interconnection trench 31 by sputtering.
- a Cu film is deposited on the barrier metal 4 by sputtering, and another Cu film is formed on the former Cu film by plating, thereby forming a 1-2 ⁇ m thick Cu film 5 .
- the Cu film 5 on the SiOC film 3 is polished by CMP (Chemical Mechanical Polishing) and left in the trench 31 . After this step, an upper edge of the low-C-concentration portion 32 is exposed.
- CMP Chemical Mechanical Polishing
- the low-C-concentration portion 32 on the side surfaces of the barrier metal 4 is dissolved away by a weak acid, thereby forming gaps 321 (hollows or air gaps) between the side surfaces of the barrier metal 4 and the SiOC film 3 .
- a 15-50 nm thick diffusion barrier film (insulating film) 6 made of, e.g., SiCN or SiC as a generally used material is deposited on the SiOC film 3 and Cu film (interconnection) 5 by coating or ALD.
- the diffusion barrier film 6 is filled in the gaps 321 to a depth of about 1 ⁇ 2 the thickness of the Cu film 5 .
- the diffusion barrier film 6 is formed from the upper surface of the Cu film 5 to a depth higher than the bottom surface of the Cu film 5 , so the gaps 321 remain below the bottom surface of the diffusion barrier film 6 .
- a 50-150 nm thick, low-k SiOC film (insulating film) 7 is deposited on the diffusion barrier film 6 by plasma CVD.
- a via hole and a trench 71 for an upper interconnection are formed in the SiOC film 7 by plasma etching.
- a portion 72 in which the C concentration is made lower than that in other portions of the SiOC film 7 by plasma damage is formed in the via hole, on the sidewalls and bottom surface of the upper interconnection trench 71 , and on the sidewalls of the trench of the via hole.
- the thickness of the portion 72 is 2-5 nm.
- the material of the diffusion barrier film 6 is desirably selected so as to increase the selectivity of the SiOC film 7 to the diffusion barrier film 6 .
- a 5-15 nm thick barrier metal (barrier film) 8 made of Ti or Ta is deposited on the SiOC film 7 and in the via hole and upper interconnection trench 71 by sputtering.
- a Cu film (seed Cu film) is deposited on the barrier metal 8 by sputtering, and another Cu film is formed on the seed Cu film by plating, thereby depositing a 1-2 ⁇ m thick Cu film 9 .
- the Cu film 9 on the SiOC film 7 is polished by CMP and is formed in the trench 71 .
- An upper edge of the low-C-concentration portion 72 is exposed.
- the low-C-concentration portion 72 on the side surfaces of the barrier metal 8 are dissolved away by a weak acid, thereby forming gaps (hollows) between the side surfaces of the barrier metal 8 and the SiOC film 7 .
- a 15-50 nm thick diffusion barrier film (insulating film) 10 made of, e.g., SiCN or SiC as a generally used material is deposited on the SiOC film 7 and Cu film (interconnection) 9 by coating or ALD.
- the diffusion barrier film 10 is filled in gaps 721 to a depth of about 1 ⁇ 2 the thickness of the Cu film 9 .
- the diffusion barrier film 10 is formed from the upper surface of the Cu film 9 to a depth higher than the bottom surface of the Cu film 9 , so the gaps 721 remain below the bottom surface of the diffusion barrier film 10 .
- the low-C-concentration portions 32 and 72 which are formed on the sidewalls of the interconnection trenches 31 and 71 formed in the SiOC films 3 and 7 and readily adsorb moisture are removed. This makes it possible to suppress oxidation of the barrier metals 4 and 8 by moisture and reduce the capacitance of the SiOC film. Also, when stacking an insulating film on the diffusion barrier film 6 and forming a via hole in this insulating film by the damascene method, if misalignment occurs between the via hole and lower interconnection 5 , no gap-like shape may be formed on the sidewalls of the lower interconnection because the gaps are filled with the diffusion barrier film. When the structure as described above is used, therefore, in a multilayered interconnection Cu leak from any Cu interconnection in multilayer may be reduced.
- the diffusion barrier film is filled in the gaps 321 or 721 between the barrier metal and low-k SiOC film to a depth of about 1 ⁇ 2 the thickness of the Cu film.
- the depth of filling can be determined by adjusting the source gas amount and the plasma output. This depth may be a depth by which the diffusion barrier film 6 or 10 is not completely filled in the gaps 321 or 721 , i.e., a depth smaller than the thickness of the Cu film. The depth may also be smaller than or equal to or larger than 1 ⁇ 2 the thickness of the Cu film.
- the diffusion barrier film to be formed on the Cu film 9 is filled in the gap between the barrier metal and low-k SiOC film. That is, this embodiment uses the same material as the film to be formed on the Cu film 9 and the film to be filled in the gaps. However, different materials may also be used as the film to be formed on the Cu film 9 and the film to be filled in the gaps.
- the film formation step need only be performed once. This makes it possible to reduce the manufacturing cost compared to the case where different materials are used.
- the dual damascene interconnection has a stacked structure including lower and upper insulating films, i.e., using low-k SiOC (the lower insulating film) as a layer in which a via hole is formed, and low-k organic C x H y (the upper insulating film) as a layer in which the interconnection is formed.
- low-k SiOC the lower insulating film
- C x H y the upper insulating film
- a 50-200 nm thick SiO 2 film 2 is deposited on an Si substrate 1 by plasma CVD.
- a 50-100 nm thick, low-k organic C X H y film (insulating film) 11 is deposited on the SiO 2 film 2 by coating.
- a 50-100 nm thick CMP protective film (insulating film) 12 made of low-k SiOC is deposited on the organic C x H y film 11 by plasma CVD.
- a trench 121 for an interconnection is formed in the CMP protective film 12 and organic C x H y film 11 by plasma etching.
- a portion 122 in which the C concentration is made lower than that in other portions of the CMP protective film 12 and organic C x H y film 11 by plasma damage is formed on the sidewalls of the interconnection trench 121 .
- the thickness of the portion 122 is 2-10 nm.
- a 5-15 nm thick barrier metal (barrier film) 4 made of Ti or Ta is deposited on the CMP protective film 12 and in the interconnection trench 121 by sputtering.
- a seed Cu film is deposited on the barrier metal 4 by sputtering, and another Cu film is formed on the former Cu film by plating, thereby forming a 1-2 ⁇ m thick Cu film 5 .
- the Cu film 5 on the CMP protective film 12 is polished by CMP and is formed in the trench 121 .
- the low-C-concentration portion 122 on the side surfaces of the barrier metal 4 is dissolved away by a liquid chemical, thereby forming gaps 321 (hollows or air gaps) between the side surfaces of the barrier metal 4 and the CMP protective film 12 and organic C x H y film 11 .
- a 15-50 nm thick diffusion barrier film (insulating film) 6 made of, e.g., SiCN or SiC as a generally used material is deposited on the CMP protective film 12 and Cu film (interconnection) 5 by coating or ALD.
- the diffusion barrier film 6 is filled in the gaps 321 to a depth of about 1 ⁇ 2 the thickness of the Cu film 5 .
- a 50-150 nm thick, low-k SiOC film (insulating film) 13 is deposited on the diffusion barrier film 6 by plasma CVD.
- a via hole is formed in the SiOC film (insulating film) 13 in a later step.
- a 50-100 nm thick, low-k organic C x H y film (insulating film) 14 is deposited on the SiOC film 13 by coating.
- An interconnection is formed in the organic C x H y film (insulating film) 14 in a later step.
- a 50-200 nm thick CMP protective film (insulating film) 15 made of low-k SiOC is deposited on the organic C x H y film 14 by plasma CVD.
- a via hole and a trench 71 for an upper interconnection are formed in the diffusion barrier film 6 , SiOC film 13 , organic C x H y film 14 , and CMP protective film 15 by plasma etching.
- a portion 72 in which the C concentration is made lower than that in other portions of the CMP protective film 15 , organic C x H y film 14 , and SiOC film 13 by plasma damage is formed in the via hole, on the sidewalls and bottom surface of the upper interconnection trench 71 , and on the sidewalls of the via hole.
- the thickness of the portion 72 is 2-10 nm.
- a 5-15 nm thick barrier metal (barrier film) 8 made of Ti or Ta is deposited on the CMP protective film 15 and in the via hole and upper interconnection trench 71 by sputtering.
- a Cu film is deposited on the barrier metal 8 by sputtering, and another Cu film is formed on the former Cu film by plating, thereby forming a 1-2 ⁇ m thick Cu film 9 .
- the Cu film 9 on the CMP protective film 15 is polished by CMP and left behind in only the trench 71 .
- the low-C-concentration portion 72 on the side surfaces of the barrier metal 8 are dissolved away by a liquid chemical, thereby forming gaps 721 (hollows or air gaps) between the side surfaces of the barrier metal 8 and the CMP protective film 15 and organic C x H y film 14 .
- a 15-50 nm thick barrier insulating film 16 made of, e.g., SiN, SiCN, or SiC is deposited on the CMP protective film 15 and Cu film (interconnection) 9 by plasma CVD, thermal CVD, or ALD.
- the barrier insulating film 16 is filled in the gaps 721 to a depth almost equal to the thickness of the CMP protective film 15 .
- the stacked structure of the insulating films SiOC film and organic C x H y
- oxidation of the barrier metals by moisture can be suppressed by removing the low-C-concentration portion on the sidewalls of the interconnection trench as in the first embodiment.
- the damascene method when stacking an insulating film on the diffusion barrier film and forming a via hole in this insulating film by the damascene method, if misalignment occurs between the via hole and lower interconnection, gap-like shape is not formed on the sidewalls of the lower interconnection because the gaps are filled with the diffusion barrier film.
- the structure as described above is used, therefore, in a multilayered interconnection Cu leak from any Cu interconnection in multilayer may be reduced.
- the diffusion barrier film is filled in the gap between the barrier metal and low-k SiOC film and organic C x H y film.
- the depth of filling may be a depth by which the diffusion barrier film is not completely filled in the gap, i.e., a depth smaller than the thickness of the Cu film.
- the depth of filling can be determined by adjusting the source gas amount and the plasma output.
- FIGS. 7A and 7B the same reference numerals as in FIGS. 4A to 4E , 5 A to 5 D, and 6 A to 6 D denote the same parts.
- the same processes as those shown in FIGS. 4A to 6C of the second embodiment are performed.
- plasma processing is performed using a reducing gas such as H 2 or NH 3 . Consequently, as shown in FIG. 7A , an organic C x H y film (lower film) 14 near a barrier metal 8 is partially etched to form a gap 722 below a CMP protective film (upper film) 15 made of SiOC.
- the width of the gap 722 formed between the side surface of the barrier metal 8 and the organic C x H y film 14 is larger than that of a gap 723 formed between the side surfaces of the barrier metal 8 and the CMP protective film 15 .
- the width of the gap 722 is 2-3 nm, i.e., about 1 ⁇ 3 the distance between adjacent Cu films 9 .
- a 15-50 nm thick barrier insulating film 16 made of, e.g., SiN, SiCN, or SiC is deposited on the CMP protective film 15 and Cu film 9 by plasma CVD.
- the barrier insulating film 16 is filled in the gap 723 between the side surface of the barrier metal 8 and the CMP protective film 15 .
- the viscosity or coverage of the barrier insulating film 16 may be adjusted beforehand to such an extent that the upper portions of the sidewalls of an interconnection trench are filled.
- the interconnection structure thus formed oxidation of the barrier metal by moisture can be suppressed by removing the low-C-concentration portion on the sidewalls of the interconnection trench, as in the first and second embodiments.
- the gap is formed between adjacent interconnections, although the gap is not a through air gap. This very effectively reduces the capacitance of the organic C x H y film.
- the problem of misalignment can be solved in the same manner as in the first and second embodiments.
- the gap 722 is formed below the CMP protective film 15 made of SiOC by etching the organic C x H y film 14 near the barrier metal 8 , and the width of the gap 722 can be freely determined by adjusting the time of the plasma processing using the reducing gas.
- self-forming barrier material 41 is formed in the trench by physical vapor deposition (PVD) or the like.
- a seed Cu (not shown in FIG. 8A ) is formed on the material 41 by PVD or the like.
- a 1-2 ⁇ m thick Cu film 51 is formed on the seed Cu by plating.
- annealing is provided so as to form a self-forming barrier material 41 .
- a low-C-concentration portion 32 is formed between the material 41 and the SiOC film 3 , on a side and bottom of the trench.
- annealing (a heat treatment) is performed within the temperature range of 200° C. to 300° C. If Mn atoms or Al atoms remain in the seed Cu alloy of the Cu film 51 , this annealing can form the same barrier film 41 on the outer peripheral portions, i.e., the side portions, and bottom portion of the Cu film 51 .
- the MnO x (Si y ) and Al 2 O 3 barriers thus formed have adhesion to Cu higher than that of a normal diffusion barrier insulating film. This makes it possible to obtain good EM characteristics in addition to the effects of the first embodiment.
- the Cu film 51 on the SiOC film 3 is polished by CMP and is formed in the trench. An upper edge of the low-C-concentration portion 32 is exposed. As shown in FIG. 8C , the low-C-concentration portion 32 on the side surfaces of the material 41 is dissolved away by a weak acid, thereby forming gaps 321 (hollows or air gaps) between the Cu film 51 and SiOC film 3 .
- a 15-50 nm thick diffusion barrier film 61 made of a silicon-containing material such as SiC x is deposited on the SiOC film 3 and Cu film (interconnection) 51 by coating or ALD.
- the diffusion barrier film 61 is filled in the gaps 321 to a depth of about 1 ⁇ 2 the thickness of the Cu film 51 . Note that the depth of filling can be freely determined in the same manner as in the first embodiment.
- MnO x (Si y ) as a self-forming barrier material is used as the barrier material of a Cu film by applying the structure of the fourth embodiment to the third embodiment, the barrier is exposed to the air gap portion, so large effects on the water penetration resistance and oxidation resistance can be expected.
- the multilayered interconnection is required to decrease the value of resistance (R) ⁇ capacitance (C).
- R resistance
- C capacitor capacitance
- Cu copper
- a low-k insulating film is used in an insulating film portion surrounding the interconnection material.
- Examples of an insulating film having a particularly low dielectric constant are SiO x C y , C x H y , SiO x C y and C x H y containing pores, and stacked structures of these materials.
- SiO x C y or C x H y film is formed using the plasma process that is used when forming an interconnection or a trench for a via. In this step, the film readily suffers plasma damage (C is easily released). This phenomenon occurs on the sidewall portion of the interconnection trench. In each of the above embodiments, this portion is removed by the WET processing after CMP, and a material such as SiCN or SiC having a high etching selectivity to SiO x C y or C x H y is filled as an etching stopper in the portion from which the low-C-concentration portion is removed.
- Each embodiment of the present invention can provide a semiconductor device that prevents oxidation of a barrier film surrounding an interconnection layer and prevents the leak of Cu from a Cu interconnection, and a method of manufacturing the device.
- the above-mentioned embodiments can be practiced not only singly but also in the form of an appropriate combination.
- the aforesaid embodiments include inventions in various stages, so inventions in various stages can also be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.
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Abstract
A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.
Description
- This application is a continuation of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 12/276,796 filed Nov. 24, 2008, and claims the benefit of priority under 35 U.S.C. §119 from Japanese Patent Application No. 2007-307745 filed Nov. 28, 2007, the entire contents of each of which are incorporated herein by reference.
- 1. Field of the Invention
- An LSI multilayered interconnection generally has a structure in which a barrier metal is formed on the side surfaces and bottom surface of a copper (Cu) film as an interconnection so as to surround the Cu film.
- 2. Description of the Related Art
- Note that JP. 2006-5010 describes a semiconductor device having a multilayered interconnection structure using a porous low-k film as an interlayer dielectric film, and a method of manufacturing the device.
- According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a first interconnection formed in a trench formed in the first insulating film; a first barrier film formed between the first interconnection and the first insulating film; and a second insulating film formed on an upper surface of the first interconnection, and formed in a first hollow portion between a side surface of the first barrier film and the first insulating film, the second insulating film being formed from the upper surface of the first interconnection to a depth higher than a bottom surface of the first interconnection, and the first hollow portion being formed below a bottom surface of the second insulating film.
- According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a second insulating film formed on the first insulating film; a first interconnection formed in a trench formed in the first insulating film and the second insulating film; a first barrier film formed between the first interconnection and the first insulating film and the second insulating film; and a third insulating film formed on an upper surface of the first interconnection, and also formed in a first hollow portion between a side surface of the first barrier film and the first insulating film and the second insulating film, the third insulating film being formed from the upper surface of the first interconnection to a depth higher than a bottom surface of the first interconnection, and the first hollow portion being formed below the third insulating film.
- According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: forming a first insulating film on a semiconductor substrate; forming a trench in the first insulating film; forming a barrier film on a side and bottom surface of the trench; forming an interconnection on the barrier film in the trench; and forming a hollow portion between the barrier film and the first insulating film by removing a low-carbon (C)-concentration portion of the first insulating film which exists near a side surface of the barrier film.
-
FIGS. 1A to 1D , 2A to 2D, and 3A to 3D are sectional views showing the manufacturing process of a semiconductor device according to a first embodiment;FIGS. 4A to 4E , 5A to 5D, and 6A to 6D are sectional views showing the manufacturing process of a semiconductor device according to a second embodiment;FIGS. 7A and 7B are sectional views showing the manufacturing process of a semiconductor device according to a third embodiment; andFIGS. 8A to 8D are sectional views showing the manufacturing process of a semiconductor device according to a fourth embodiment. - Embodiments will be explained below with reference to the accompanying drawing.
- The first embodiment uses Cu as an interconnection, and low-k SiOC as a layer in which a via hole and the interconnection are formed.
- As shown in
FIG. 1A , a 50-200 nm thick SiO2 film (insulating film) 2 is deposited on a silicon (Si) substrate (semiconductor substrate) 1 by plasma CVD. Then, as shown inFIG. 1B , a 100-300 nm thick, low-k SiOC film (insulating film) 3 is deposited on the SiO2 film 2 by plasma CVD. - As shown in
FIG. 1C , atrench 31 for an interconnection is formed in theSiOC film 3 by plasma etching. In this step, aportion 32 in which the C (carbon) concentration is made lower than that in other portions of theSiOC film 3 by plasma damage is formed on the sidewalls and bottom surface of theinterconnection trench 31. The thickness of theportion 32 is 2-10 nm. - As shown in
FIG. 1D , a 5-15 nm thick barrier metal (barrier film) 4 made of Ti or Ta is deposited on theSiOC film 3 and in theinterconnection trench 31 by sputtering. In addition, a Cu film is deposited on thebarrier metal 4 by sputtering, and another Cu film is formed on the former Cu film by plating, thereby forming a 1-2 μmthick Cu film 5. - As shown in
FIG. 2A , theCu film 5 on theSiOC film 3 is polished by CMP (Chemical Mechanical Polishing) and left in thetrench 31. After this step, an upper edge of the low-C-concentration portion 32 is exposed. - As shown in
FIG. 2B , the low-C-concentration portion 32 on the side surfaces of thebarrier metal 4 is dissolved away by a weak acid, thereby forming gaps 321 (hollows or air gaps) between the side surfaces of thebarrier metal 4 and theSiOC film 3. - As shown in
FIG. 2C , a 15-50 nm thick diffusion barrier film (insulating film) 6 made of, e.g., SiCN or SiC as a generally used material is deposited on theSiOC film 3 and Cu film (interconnection) 5 by coating or ALD. In this step, thediffusion barrier film 6 is filled in thegaps 321 to a depth of about ½ the thickness of theCu film 5. In other words, thediffusion barrier film 6 is formed from the upper surface of theCu film 5 to a depth higher than the bottom surface of theCu film 5, so thegaps 321 remain below the bottom surface of thediffusion barrier film 6. - As shown in
FIG. 2D , a 50-150 nm thick, low-k SiOC film (insulating film) 7 is deposited on thediffusion barrier film 6 by plasma CVD. Then, as shownFIG. 3A , a via hole and atrench 71 for an upper interconnection are formed in theSiOC film 7 by plasma etching. In this step, aportion 72 in which the C concentration is made lower than that in other portions of theSiOC film 7 by plasma damage is formed in the via hole, on the sidewalls and bottom surface of theupper interconnection trench 71, and on the sidewalls of the trench of the via hole. The thickness of theportion 72 is 2-5 nm. The material of thediffusion barrier film 6 is desirably selected so as to increase the selectivity of theSiOC film 7 to thediffusion barrier film 6. - As shown in
FIG. 3B , a 5-15 nm thick barrier metal (barrier film) 8 made of Ti or Ta is deposited on theSiOC film 7 and in the via hole andupper interconnection trench 71 by sputtering. In addition, a Cu film (seed Cu film) is deposited on thebarrier metal 8 by sputtering, and another Cu film is formed on the seed Cu film by plating, thereby depositing a 1-2 μmthick Cu film 9. After that, as shown inFIG. 3C , theCu film 9 on theSiOC film 7 is polished by CMP and is formed in thetrench 71. An upper edge of the low-C-concentration portion 72 is exposed. Then, the low-C-concentration portion 72 on the side surfaces of thebarrier metal 8 are dissolved away by a weak acid, thereby forming gaps (hollows) between the side surfaces of thebarrier metal 8 and theSiOC film 7. - As shown in
FIG. 3D , a 15-50 nm thick diffusion barrier film (insulating film) 10 made of, e.g., SiCN or SiC as a generally used material is deposited on theSiOC film 7 and Cu film (interconnection) 9 by coating or ALD. In this step, thediffusion barrier film 10 is filled ingaps 721 to a depth of about ½ the thickness of theCu film 9. In other words, thediffusion barrier film 10 is formed from the upper surface of theCu film 9 to a depth higher than the bottom surface of theCu film 9, so thegaps 721 remain below the bottom surface of thediffusion barrier film 10. - In the interconnection structure thus formed, the low-C-
concentration portions interconnection trenches SiOC films barrier metals diffusion barrier film 6 and forming a via hole in this insulating film by the damascene method, if misalignment occurs between the via hole andlower interconnection 5, no gap-like shape may be formed on the sidewalls of the lower interconnection because the gaps are filled with the diffusion barrier film. When the structure as described above is used, therefore, in a multilayered interconnection Cu leak from any Cu interconnection in multilayer may be reduced. - Note that in the above first embodiment, the diffusion barrier film is filled in the
gaps diffusion barrier film gaps - Note also that in the above first embodiment, the diffusion barrier film to be formed on the
Cu film 9 is filled in the gap between the barrier metal and low-k SiOC film. That is, this embodiment uses the same material as the film to be formed on theCu film 9 and the film to be filled in the gaps. However, different materials may also be used as the film to be formed on theCu film 9 and the film to be filled in the gaps. When the same material is used as in the first embodiment, i.e., when the film to be formed on theCu film 9 and the film to be filled in the gaps are integrated, the film formation step need only be performed once. This makes it possible to reduce the manufacturing cost compared to the case where different materials are used. - In the second embodiment, Cu is used as an interconnection, and the dual damascene interconnection has a stacked structure including lower and upper insulating films, i.e., using low-k SiOC (the lower insulating film) as a layer in which a via hole is formed, and low-k organic CxHy (the upper insulating film) as a layer in which the interconnection is formed. Note that in
FIGS. 4A to 4E , 5A to 5D, and 6A to 6D, the same reference numerals as inFIGS. 1A to 1D , 2A to 2D, and 3A to 3D denote the same parts. - As shown in
FIG. 4A , a 50-200 nm thick SiO2 film 2 is deposited on anSi substrate 1 by plasma CVD. Then, as shown inFIG. 4B , a 50-100 nm thick, low-k organic CX Hy film (insulating film) 11 is deposited on the SiO2 film 2 by coating. In addition, a 50-100 nm thick CMP protective film (insulating film) 12 made of low-k SiOC is deposited on the organic CxHy film 11 by plasma CVD. - As shown in
FIG. 4C , atrench 121 for an interconnection is formed in the CMPprotective film 12 and organic CxHy film 11 by plasma etching. In this step, aportion 122 in which the C concentration is made lower than that in other portions of the CMPprotective film 12 and organic CxHy film 11 by plasma damage is formed on the sidewalls of theinterconnection trench 121. The thickness of theportion 122 is 2-10 nm. - As shown in
FIG. 4D , a 5-15 nm thick barrier metal (barrier film) 4 made of Ti or Ta is deposited on the CMPprotective film 12 and in theinterconnection trench 121 by sputtering. In addition, a seed Cu film is deposited on thebarrier metal 4 by sputtering, and another Cu film is formed on the former Cu film by plating, thereby forming a 1-2 μmthick Cu film 5. - As shown in
FIG. 4E , theCu film 5 on the CMPprotective film 12 is polished by CMP and is formed in thetrench 121. Subsequently, as shown inFIG. 5A , the low-C-concentration portion 122 on the side surfaces of thebarrier metal 4 is dissolved away by a liquid chemical, thereby forming gaps 321 (hollows or air gaps) between the side surfaces of thebarrier metal 4 and the CMPprotective film 12 and organic CxHy film 11. - As shown in
FIG. 5B , a 15-50 nm thick diffusion barrier film (insulating film) 6 made of, e.g., SiCN or SiC as a generally used material is deposited on the CMPprotective film 12 and Cu film (interconnection) 5 by coating or ALD. In this step, thediffusion barrier film 6 is filled in thegaps 321 to a depth of about ½ the thickness of theCu film 5. - As shown in
FIG. 5C , a 50-150 nm thick, low-k SiOC film (insulating film) 13 is deposited on thediffusion barrier film 6 by plasma CVD. A via hole is formed in the SiOC film (insulating film) 13 in a later step. Then, a 50-100 nm thick, low-k organic CxHy film (insulating film) 14 is deposited on theSiOC film 13 by coating. An interconnection is formed in the organic CxHy film (insulating film) 14 in a later step. Furthermore, a 50-200 nm thick CMP protective film (insulating film) 15 made of low-k SiOC is deposited on the organic CxHy film 14 by plasma CVD. - As shown
FIG. 5D , a via hole and atrench 71 for an upper interconnection are formed in thediffusion barrier film 6,SiOC film 13, organic CxHy film 14, and CMPprotective film 15 by plasma etching. In this step, aportion 72 in which the C concentration is made lower than that in other portions of the CMPprotective film 15, organic CxHy film 14, andSiOC film 13 by plasma damage is formed in the via hole, on the sidewalls and bottom surface of theupper interconnection trench 71, and on the sidewalls of the via hole. The thickness of theportion 72 is 2-10 nm. - As shown in
FIG. 6A , a 5-15 nm thick barrier metal (barrier film) 8 made of Ti or Ta is deposited on the CMPprotective film 15 and in the via hole andupper interconnection trench 71 by sputtering. In addition, a Cu film is deposited on thebarrier metal 8 by sputtering, and another Cu film is formed on the former Cu film by plating, thereby forming a 1-2 μmthick Cu film 9. - As shown in
FIG. 6B , theCu film 9 on the CMPprotective film 15 is polished by CMP and left behind in only thetrench 71. Subsequently, as shown inFIG. 6C , the low-C-concentration portion 72 on the side surfaces of thebarrier metal 8 are dissolved away by a liquid chemical, thereby forming gaps 721 (hollows or air gaps) between the side surfaces of thebarrier metal 8 and the CMPprotective film 15 and organic CxHy film 14. - As shown in
FIG. 6D , a 15-50 nm thickbarrier insulating film 16 made of, e.g., SiN, SiCN, or SiC is deposited on the CMPprotective film 15 and Cu film (interconnection) 9 by plasma CVD, thermal CVD, or ALD. In this step, thebarrier insulating film 16 is filled in thegaps 721 to a depth almost equal to the thickness of the CMPprotective film 15. - When the stacked structure of the insulating films (SiOC film and organic CxHy) is used as described above, oxidation of the barrier metals by moisture can be suppressed by removing the low-C-concentration portion on the sidewalls of the interconnection trench as in the first embodiment. Also, when stacking an insulating film on the diffusion barrier film and forming a via hole in this insulating film by the damascene method, if misalignment occurs between the via hole and lower interconnection, gap-like shape is not formed on the sidewalls of the lower interconnection because the gaps are filled with the diffusion barrier film. When the structure as described above is used, therefore, in a multilayered interconnection Cu leak from any Cu interconnection in multilayer may be reduced.
- Note that in the above second embodiment, the diffusion barrier film is filled in the gap between the barrier metal and low-k SiOC film and organic CxHy film. The depth of filling may be a depth by which the diffusion barrier film is not completely filled in the gap, i.e., a depth smaller than the thickness of the Cu film. The depth of filling can be determined by adjusting the source gas amount and the plasma output.
- Note that in
FIGS. 7A and 7B , the same reference numerals as inFIGS. 4A to 4E , 5A to 5D, and 6A to 6D denote the same parts. - In the third embodiment, the same processes as those shown in
FIGS. 4A to 6C of the second embodiment are performed. After that, plasma processing is performed using a reducing gas such as H2 or NH3. Consequently, as shown inFIG. 7A , an organic CxHy film (lower film) 14 near abarrier metal 8 is partially etched to form agap 722 below a CMP protective film (upper film) 15 made of SiOC. The width of thegap 722 formed between the side surface of thebarrier metal 8 and the organic CxHy film 14 is larger than that of agap 723 formed between the side surfaces of thebarrier metal 8 and the CMPprotective film 15. The width of thegap 722 is 2-3 nm, i.e., about ⅓ the distance betweenadjacent Cu films 9. - Then, as shown in
FIG. 7B , a 15-50 nm thickbarrier insulating film 16 made of, e.g., SiN, SiCN, or SiC is deposited on the CMPprotective film 15 andCu film 9 by plasma CVD. In this step, thebarrier insulating film 16 is filled in thegap 723 between the side surface of thebarrier metal 8 and the CMPprotective film 15. In this case, the viscosity or coverage of thebarrier insulating film 16 may be adjusted beforehand to such an extent that the upper portions of the sidewalls of an interconnection trench are filled. - In the interconnection structure thus formed, oxidation of the barrier metal by moisture can be suppressed by removing the low-C-concentration portion on the sidewalls of the interconnection trench, as in the first and second embodiments. In addition, the gap is formed between adjacent interconnections, although the gap is not a through air gap. This very effectively reduces the capacitance of the organic CxHy film. Furthermore, the problem of misalignment can be solved in the same manner as in the first and second embodiments.
- Note that in the third embodiment described above, the
gap 722 is formed below the CMPprotective film 15 made of SiOC by etching the organic CxHy film 14 near thebarrier metal 8, and the width of thegap 722 can be freely determined by adjusting the time of the plasma processing using the reducing gas. - In the fourth embodiment, the case where MnOx(Siy) as a self-forming barrier material is used as the barrier material of a Cu film will be explained. Note that in
FIGS. 8A to 8D , the same reference numerals as inFIGS. 1A to 1D , 2A to 2D, and 3A to 3D denote the same parts. - In the fourth embodiment, the same processes as those shown in
FIGS. 1A to 1C of the first embodiment are performed. After that, as shown inFIG. 8A , self-formingbarrier material 41 is formed in the trench by physical vapor deposition (PVD) or the like. A seed Cu (not shown inFIG. 8A ) is formed on thematerial 41 by PVD or the like. A 1-2 μmthick Cu film 51 is formed on the seed Cu by plating. After that, annealing is provided so as to form a self-formingbarrier material 41. A low-C-concentration portion 32 is formed between the material 41 and theSiOC film 3, on a side and bottom of the trench. - In this state, annealing (a heat treatment) is performed within the temperature range of 200° C. to 300° C. If Mn atoms or Al atoms remain in the seed Cu alloy of the
Cu film 51, this annealing can form thesame barrier film 41 on the outer peripheral portions, i.e., the side portions, and bottom portion of theCu film 51. The MnOx(Siy) and Al2O3 barriers thus formed have adhesion to Cu higher than that of a normal diffusion barrier insulating film. This makes it possible to obtain good EM characteristics in addition to the effects of the first embodiment. - Subsequently, as shown in
FIG. 8B , theCu film 51 on theSiOC film 3 is polished by CMP and is formed in the trench. An upper edge of the low-C-concentration portion 32 is exposed. As shown inFIG. 8C , the low-C-concentration portion 32 on the side surfaces of thematerial 41 is dissolved away by a weak acid, thereby forming gaps 321 (hollows or air gaps) between theCu film 51 andSiOC film 3. - Then, as shown in
FIG. 8D , a 15-50 nm thickdiffusion barrier film 61 made of a silicon-containing material such as SiCx is deposited on theSiOC film 3 and Cu film (interconnection) 51 by coating or ALD. In this step, thediffusion barrier film 61 is filled in thegaps 321 to a depth of about ½ the thickness of theCu film 51. Note that the depth of filling can be freely determined in the same manner as in the first embodiment. - Note that when MnOx(Siy) as a self-forming barrier material is used as the barrier material of a Cu film by applying the structure of the fourth embodiment to the third embodiment, the barrier is exposed to the air gap portion, so large effects on the water penetration resistance and oxidation resistance can be expected.
- Since the semiconductor device according to each embodiment of the present invention is applied to a product that operates at a high speed, the multilayered interconnection is required to decrease the value of resistance (R)×capacitance (C). For this purpose, copper (Cu) is used as an interconnection material, and a low-k insulating film is used in an insulating film portion surrounding the interconnection material.
- Examples of an insulating film having a particularly low dielectric constant are SiOxCy, CxHy, SiOxCy and Cx Hy containing pores, and stacked structures of these materials.
- An SiOx Cy or Cx Hy film is formed using the plasma process that is used when forming an interconnection or a trench for a via. In this step, the film readily suffers plasma damage (C is easily released). This phenomenon occurs on the sidewall portion of the interconnection trench. In each of the above embodiments, this portion is removed by the WET processing after CMP, and a material such as SiCN or SiC having a high etching selectivity to SiOxCy or CxHy is filled as an etching stopper in the portion from which the low-C-concentration portion is removed.
- This makes it possible to prevent oxidation of the barrier film formed in the interconnection trench, and prevent the leak of Cu from the Cu interconnection. Accordingly, the reliability of the semiconductor device can be improved by suppressing deterioration of the transistor.
- Each embodiment of the present invention can provide a semiconductor device that prevents oxidation of a barrier film surrounding an interconnection layer and prevents the leak of Cu from a Cu interconnection, and a method of manufacturing the device.
- Also, the above-mentioned embodiments can be practiced not only singly but also in the form of an appropriate combination. Furthermore, the aforesaid embodiments include inventions in various stages, so inventions in various stages can also be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.
- Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims (9)
1. A semiconductor device manufacturing method comprising:
forming a first insulating film on a semiconductor substrate;
forming a trench in the first insulating film;
forming a first barrier film on side and bottom surfaces of the trench;
forming a first interconnection on the first barrier film in the trench; and
forming a first hollow portion between the first barrier film and the first insulating film by removing a low-carbon (C)-concentration portion of the first insulating film which exists near a side surface of the first barrier film.
2. The method according to claim 1 ,
further comprising forming a second insulating film on an upper surface of the first interconnection, and in the first hollow portion between the side surface of the first barrier film and the first insulating film, the second insulating film being formed from the upper surface of the first interconnection to a depth higher than a bottom surface of the first interconnection, the first hollow portion remaining below the second insulating film.
3. The method according to claim 2 , wherein
the first insulating film includes a lower film and an upper film formed on the lower film, the first hollow portion includes a lower hollow portion between the side surface of the first barrier film and the lower film, and an upper hollow portion between the side surface of the first barrier film and the upper film, and a width of the lower hollow portion is larger than that of the upper hollow portion, and
the second insulating film is formed in the lower hollow portion.
4. The method according to claim 1 , wherein the first insulating film is made of a film containing carbon (C), and a region having a carbon concentration lower than that of other portions of the first insulating film is formed in a bottom surface of the trench formed in the first insulating film.
5. The method according to claim 1 , wherein the first barrier film is a self-forming barrier film formed by annealing the first interconnection.
6. The method according to claim 1 , wherein the first barrier film and the second insulating film prevent diffusion of a material contained in the first interconnection.
7. The method according to claim 1 , wherein the first interconnection contains a Cu film.
8. The method according to claim 2 , further comprising:
forming a third insulating film on the second insulating film;
forming a second interconnection in a trench formed in the third insulating film;
forming a second barrier film between the second interconnection and the third insulating film; and
forming a fourth insulating film on an upper surface of the second interconnection, and in a second hollow portion between a side surface of the second barrier film and the third insulating film, the fourth insulating film being formed from the upper surface of the second interconnection to a depth higher than a bottom surface of the second interconnection, and the second hollow portion being formed below a bottom surface of the fourth insulating film.
9. The method according to claim 8 ,
further comprising forming a via contact hole in a trench formed in the third insulating film between the first interconnection and the second interconnection, the third insulating film being made of a film containing carbon (C), a region having a carbon concentration lower than that of other portions of the third insulating film being formed in a side surface of the trench formed in the third insulating film.
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US10157841B2 (en) * | 2017-04-17 | 2018-12-18 | Micron Technology, Inc. | Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally between a pair of structures |
CN110060955B (en) * | 2018-01-18 | 2021-11-30 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
CN110858578B (en) * | 2018-08-23 | 2021-07-13 | 联华电子股份有限公司 | Die seal ring and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6917109B2 (en) * | 2002-11-15 | 2005-07-12 | United Micorelectronics, Corp. | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
US7439172B2 (en) * | 2007-01-16 | 2008-10-21 | International Business Machines Corporation | Circuit structure with low dielectric constant regions and method of forming same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6452276B1 (en) * | 1998-04-30 | 2002-09-17 | International Business Machines Corporation | Ultra thin, single phase, diffusion barrier for metal conductors |
JP2000260861A (en) * | 1999-03-05 | 2000-09-22 | Toshiba Corp | Semiconductor device and manufacture of the semiconductor device |
JP2003163266A (en) * | 2001-11-28 | 2003-06-06 | Sony Corp | Semiconductor device and manufacturing method thereof |
JP4250006B2 (en) * | 2002-06-06 | 2009-04-08 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP3898669B2 (en) * | 2002-06-10 | 2007-03-28 | 株式会社東芝 | Manufacturing method of semiconductor device |
JP4864307B2 (en) * | 2003-09-30 | 2012-02-01 | アイメック | Method for selectively forming an air gap and apparatus obtained by the method |
JP4478038B2 (en) | 2004-02-27 | 2010-06-09 | 株式会社半導体理工学研究センター | Semiconductor device and manufacturing method thereof |
JP4383262B2 (en) | 2004-06-15 | 2009-12-16 | Necエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
KR100641362B1 (en) | 2005-01-13 | 2006-10-31 | 삼성전자주식회사 | Interconnection structure having double diffusion barrier layer and method of fabricating the same |
US7538434B2 (en) * | 2005-03-08 | 2009-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper interconnection with conductive polymer layer and method of forming the same |
JP2008066498A (en) * | 2006-09-07 | 2008-03-21 | Sony Corp | Method for manufacturing semiconductor device, and semiconductor device |
-
2007
- 2007-11-28 JP JP2007307745A patent/JP2009135139A/en active Pending
-
2008
- 2008-11-24 US US12/276,796 patent/US7944053B2/en not_active Expired - Fee Related
-
2011
- 2011-04-12 US US13/084,623 patent/US20110189850A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6917109B2 (en) * | 2002-11-15 | 2005-07-12 | United Micorelectronics, Corp. | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
US7439172B2 (en) * | 2007-01-16 | 2008-10-21 | International Business Machines Corporation | Circuit structure with low dielectric constant regions and method of forming same |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20240250184A1 (en) * | 2011-09-29 | 2024-07-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
DE102012111574B4 (en) | 2012-06-19 | 2022-04-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a dual damascene conductive contact structure and manufacturing method for a semiconductor device |
US8772934B2 (en) * | 2012-08-28 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Aluminum interconnection apparatus |
US9607891B2 (en) | 2012-08-28 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Aluminum interconnection apparatus |
US9455184B2 (en) | 2014-06-17 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Aluminum interconnection apparatus |
Also Published As
Publication number | Publication date |
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US20090134517A1 (en) | 2009-05-28 |
JP2009135139A (en) | 2009-06-18 |
US7944053B2 (en) | 2011-05-17 |
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