US20110169158A1 - Solder Pillars in Flip Chip Assembly - Google Patents
Solder Pillars in Flip Chip Assembly Download PDFInfo
- Publication number
- US20110169158A1 US20110169158A1 US12/687,268 US68726810A US2011169158A1 US 20110169158 A1 US20110169158 A1 US 20110169158A1 US 68726810 A US68726810 A US 68726810A US 2011169158 A1 US2011169158 A1 US 2011169158A1
- Authority
- US
- United States
- Prior art keywords
- solder
- semiconductor die
- solder material
- die
- pillar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 85
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000004891 communication Methods 0.000 claims description 9
- 239000004952 Polyamide Substances 0.000 claims description 2
- 238000005272 metallurgy Methods 0.000 claims description 2
- 229920002647 polyamide Polymers 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 230000008901 benefit Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 239000000374 eutectic mixture Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Definitions
- the present description generally relates to flip chip assembly and, more specifically, to the use of new shapes for portions of solder material.
- Flip chip assembly is a process in use today for integrated circuit (IC) packaging.
- a semiconductor die is created with metallized contact pads on a surface of the die.
- a mask is then laid down and solder is plated over the mask.
- the mask is removed and small solder balls are then formed on the metallized contact pads by reflowing the solder material.
- the die is then cut and flipped over so the solder balls align with metal contacts on a packaging substrate.
- the die is placed on the packaging substrate, and the solder is then reflowed to ensure that the solder makes sufficient electrical contact with the metal contacts on the packaging substrate. Insulating underfill is then applied to the package.
- the result is a semiconductor package where the inputs and outputs of the die are in electrical communication with the packaging substrate.
- An overall system may have other components thereon, such as processors, passive components, power components, and the like, which are then interfaced with the semiconductor die through, for example, traces on the package.
- FIG. 1 illustrates a conventional assembly technique employing solder balls.
- a semiconductor die 101 includes a metallized contact pad 102 , which is in contact with a solder ball 103 (also known as a “flip chip bump”).
- a package substrate 104 includes a copper contact 105 and the mask 106 .
- the mask 106 prevents the solder ball 103 from making electrical contact with the copper contact 105 , even after the solder ball 103 is reflowed.
- FIG. 1 illustrates a defect that happens from time to time during flip chip techniques that use solder balls. Such a lack of contact is sometimes caused by a shift in solder mask registration or other kind of misalignment.
- the assembly technique of FIG. 2 includes filling the solder mask opening of the package substrate 104 with the solder 107 to facilitate contact with the solder ball 103 .
- the assembly technique is known as solder on pad (SOP).
- SOP solder on pad
- the SOP technique has several disadvantages. SOP is relatively hard to control for both coplanarity and quality. SOP involves an additional thermal cycle, and precautions are necessary to maintain surface quality for good solder attachment. Furthermore, in practice, current SOP processes can only be used for pitches of 150 ⁇ m and larger.
- FIG. 3 shows a process that uses a copper post 301 and a solder cap 302 to make electrical contact between the copper contact 105 and the semiconductor die 101 .
- the copper post technique of FIG. 3 has several disadvantages, as well. For instance, the copper post technique is relatively expensive when compared to the technique of FIGS. 1 and 2 . Furthermore, copper is quite rigid, and some materials within the semiconductor die 101 are somewhat brittle, so that when stress is applied to the assembly, the semiconductor die 101 can be mechanically damaged.
- a semiconductor package system includes a semiconductor die and a solder pillar on a side of the semiconductor die extending outwardly from a side of the semiconductor die.
- a method for packaging a semiconductor die includes disposing photo resist upon a die, the die having a first metal contact, and the photo resist defining a volume that is substantially pillar-shaped and aligned with the first metal contact. The method also includes providing solder material within the volume, reflowing the solder material within the volume, and removing the photo resist to expose the solder material.
- a semiconductor die has multiple conductive pads, each of the conductive pads providing an interface to circuitry within the semiconductor die.
- the die also has means for facilitating electrical communication with contacts on a package substrate, each of the means for facilitating corresponding to, and in contact with, one of the conductive pads and having a pillar shape and being formed of solder material.
- FIG. 1 is a schematic illustrating a conventional assembly technique employing solder balls.
- FIG. 2 is a schematic illustrating a conventional SOP assembly technique employing solder balls.
- FIG. 3 is a schematic illustrating a conventional assembly technique employing copper posts.
- FIG. 4 is an illustration of an exemplary system adapted according to one embodiment of the disclosure.
- FIGS. 5A and 5B are illustrations of an exemplary technique, according to one embodiment of the disclosure, for creating a cylindrical solder bump and making preliminary contact with a package substrate.
- FIG. 6 is an illustration of three different basic shapes that can be used for solder pillars according to various embodiments.
- FIG. 7 is a schematic illustrating an exemplary wireless communication system in which an embodiment may be advantageously employed.
- FIG. 4 is an illustration of an exemplary system 400 adapted according to one embodiment.
- the system 400 includes a semiconductor die 401 and under bump metallurgy (UMB) 402 , which provides an electrical contact between the solder bump 403 and circuitry (not shown) within the die 401 . While not shown in FIG. 4 for simplicity, it is understood that the solder bump 403 is aligned and moved relative to a metal contact 405 so as to make electrical contact therewith.
- UMB under bump metallurgy
- the solder bump 403 is shaped substantially as a cylinder. That is, in this example, the solder bump 403 conforms to a basic cylinder shape but deviates from a true cylinder shape at the interface with the UBM 402 .
- the circumference of the cylinder shape can be smaller than that of the solder ball of FIG. 1 , while the elongated dimension allows for electrical contact to be made between the UBM 402 and the metal contact 405 of the package substrate 404 .
- the cylindrical shape of the solder bump 403 facilitates making preliminary contact with the metal contact 405 through the opening in the mask 406 .
- FIGS. 5A and 5B are illustrations of an exemplary technique 500 for creating a cylindrical solder bump and making preliminary contact with a package substrate.
- the UBM 402 is created on the semiconductor die 401 by, e.g., sputtering.
- the die pad may be coated with the UBM.
- the UBM 402 creates an electrical interface with circuitry inside of the semiconductor die 401 .
- photo resist is applied in a pattern to create a mask 550 .
- the view of the photo resist is a cut-away view, and it is understood that the photo resist creates a substantially cylindrical volume 551 .
- the technique uses the pattern of the mask 550 to provide the shape of the solder bump (as explained in more detail below). Any of a variety of materials, such as color photoresists, can be used to create the mask 550 .
- polyamide is used as a material for the mask 550 because its relatively high heat resistance allows for a reflow process to be performed before the mask 550 has been removed (as explained below with respect to the block 504 ).
- the solder material 552 is applied.
- the solder is plated as a eutectic mixture on the mask 550 .
- the mask 550 allows the solder material 552 into the volume 551 , thereby creating a cylindrical shape with a cap on top.
- the solder material 552 is reflowed.
- the structure can be heated beyond the melting point of the solder but not so high as to melt or char the mask 550 or the die 401 .
- Reflowing after plating is used in this embodiment to cause the different layers of solder material to coalesce.
- a reflow profile is used, wherein the structure is slowly heated up and cooled down.
- the solder material 552 is constrained by boundaries of the volume 551 , and the shape of the eventual solder bump is dictated, at least in part, by the shape of the volume 551 .
- the mask 550 is removed after the solder material 552 has returned to a solid state. Any of a variety of techniques can be used to remove the mask 550 , such as, for example, stripping the mask 550 with a solvent, e.g., acetone.
- a solvent e.g., acetone
- buffing is performed to make a distal surface 553 substantially flat.
- the shape of the solder bump 403 is defined by the mask pattern, the plating process, and the buffing process. Buffing can be used to achieve a greater degree of coplanarity than could be achieved otherwise.
- coplanarity refers to the property of the surface 553 as it relates spatially to similar surfaces of other solder bumps (not shown) on the die 401 .
- the distal surface 553 and similar surfaces of other solder bumps are substantially coplanar so that contact is made by all solder bumps to their respective package substrate contacts. For many applications, coplanarity on the order of a few microns is sufficient. Buffing, such as by chemical mechanical polishing, can be performed either before or after mask removal.
- the structure that includes the die 401 and the solder bump 403 is brought into proximity with the package substrate 404 and aligned with the metal contact 405 .
- some embodiments include flipping the structure that includes the die 401 and the solder bump 403 so that it is spatially located above the package substrate 404 . Preliminary contact is made between the solder bump 403 and the metal contact 405 , for example by solder reflow.
- the technique 500 is shown as a series of specific processes, various embodiments are not limited thereto. In fact, other embodiments may add, omit, modify, or rearrange various processes. For instance, after the block 506 , some embodiments perform an additional reflow process followed by an underfill process.
- the resulting package substrate assembly including the die 401 , can be used in further manufacturing processing, such as disposing other components onto the package substrate 404 and installing the package substrate assembly in a device (e.g., a mobile device or other processor-based device).
- a device e.g., a mobile device or other processor-based device.
- the technique is illustrated with respect to a single solder bump 403 , it is noted that many embodiments will perform the technique for a multitude of solder bumps on a die (e.g., 800 solder bumps).
- the embodiments above have been described with reference made to specific materials for the mask and the solder bump, it is noted that various embodiments may use any suitable solder or mask material.
- FIG. 6 is an illustration of three different basic shapes that can be used for solder pillars according to various embodiments, and FIG. 6 is intended to be non-exclusive.
- FIG. 6 includes a rectangular volume 601 , a triangular volume 602 , and a cylindrical volume 603 , though a variety of arbitrary shapes, such as octagonal volumes, are adaptable to various embodiments.
- some embodiments offer more control of the structure than was provided with solder balls.
- the diameter of the pillar can be adjusted to easily fit within the aperture provided by the mask on the package substrate.
- the diameter of the column can be adjusted to compensate for alignment tolerance, thereby helping to ensure contact with the metal pad.
- solder pillars offer the alignment benefits of copper posts while avoiding the rigidity of copper posts that can lead to damage to the semiconductor die when stress is applied to the structure.
- some embodiments offer better coplanarity than the SOP solution shown in FIG. 2 , especially when buffing or another shaping process is performed on the pillars.
- Coplanarity generally becomes a greater issue as the number of bumps and contacts increases, and greater coplanarity can help increase yield.
- FIG. 7 shows an exemplary wireless communication system 700 in which an embodiment of the invention may be advantageously employed.
- FIG. 7 shows three remote units 720 , 730 , and 740 and two base stations 750 , 760 .
- the remote units 720 , 730 , and 740 and the base stations 750 , 760 can include any of a variety of components, such as memory units, Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), processors, delta sigma data converters, and the like (and the components can be manufactured from semiconductor dies such as the die 401 of FIGS. 4 and 5 ).
- ADCs Analog to Digital Converters
- DACs Digital to Analog Converters
- processors such as the die 401 of FIGS. 4 and 5 .
- Embodiments can utilize package assemblies that include components wherein the components have been mounted on the package assemblies using solder pillar techniques described above.
- FIG. 7 shows forward link signals 780 from the base stations 750 , 760 to the remote units 720 , 730 , and 740 and the reverse link signals 790 from the remote units 720 , 730 , and 740 to the base stations 750 , 760 .
- remote units may include cell phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, fixed location data units such as meter reading equipment, and/or the like.
- the remote unit 720 is shown as a mobile telephone
- the remote unit 730 is shown as a portable computer
- the remote unit 740 is shown as a fixed location remote unit in a wireless local loop system.
- the base stations 750 , 760 can be any of a variety of wireless base stations, including, e.g., cellular telephone base stations, wireless network access points (e.g., IEEE 802.11 compliant access points), and the like.
- FIG. 7 illustrates remote units and base stations, the disclosure is not limited to these exemplary illustrated units.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US12/687,268 US20110169158A1 (en) | 2010-01-14 | 2010-01-14 | Solder Pillars in Flip Chip Assembly |
PCT/US2011/021386 WO2011088384A2 (fr) | 2010-01-14 | 2011-01-14 | Colonnes de soudure dans l'assemblage de puce retournée |
TW100101502A TW201135891A (en) | 2010-01-14 | 2011-01-14 | Solder pillars in flip chip assembly |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/687,268 US20110169158A1 (en) | 2010-01-14 | 2010-01-14 | Solder Pillars in Flip Chip Assembly |
Publications (1)
Publication Number | Publication Date |
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US20110169158A1 true US20110169158A1 (en) | 2011-07-14 |
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ID=44065080
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/687,268 Abandoned US20110169158A1 (en) | 2010-01-14 | 2010-01-14 | Solder Pillars in Flip Chip Assembly |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110169158A1 (fr) |
TW (1) | TW201135891A (fr) |
WO (1) | WO2011088384A2 (fr) |
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US9082832B2 (en) | 2011-09-21 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9105530B2 (en) | 2012-09-18 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive contacts having varying widths and method of manufacturing same |
US9142533B2 (en) | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US9159695B2 (en) | 2013-01-07 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Elongated bump structures in package structure |
US9299674B2 (en) | 2012-04-18 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US9425136B2 (en) * | 2012-04-17 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US9646923B2 (en) | 2012-04-17 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
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US20180226372A1 (en) * | 2017-02-08 | 2018-08-09 | Nanya Technology Corporation | Package structure and manufacturing method thereof |
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Also Published As
Publication number | Publication date |
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TW201135891A (en) | 2011-10-16 |
WO2011088384A2 (fr) | 2011-07-21 |
WO2011088384A3 (fr) | 2011-09-09 |
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