US20110133778A1 - Non-volatile logic circuits, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits - Google Patents
Non-volatile logic circuits, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits Download PDFInfo
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- US20110133778A1 US20110133778A1 US12/805,550 US80555010A US2011133778A1 US 20110133778 A1 US20110133778 A1 US 20110133778A1 US 80555010 A US80555010 A US 80555010A US 2011133778 A1 US2011133778 A1 US 2011133778A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
Definitions
- the present disclosure relates to non-volatile logic circuits, and more particularly, to non-volatile logic circuits including non-volatile memory devices, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits.
- next-generation memory devices that are not only non-volatile memory but also do not need to be refreshed.
- next-generation memory devices such as Phase Change Random Access Memory (PRAM), Nano Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), and Resistive RAM (RRAM). Accordingly, research has been actively conducted in order to apply such a next-generation memory device to a logic circuit.
- PRAM Phase Change Random Access Memory
- NFGM Nano Floating Gate Memory
- NFGM Nano Floating Gate Memory
- MoRAM Polymer RAM
- MRAM Magnetic RAM
- FeRAM Ferroelectric RAM
- RRAM Resistive RAM
- non-volatile logic circuits to which non-volatile memory devices are applied for shorter booting time and writing operations are performed with respect to the non-volatile memory devices for a reduced number of times in consideration of endurances of the non-volatile memory devices, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits.
- a non-volatile logic circuit includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells configured to receive first and second write voltages based on data of the pair of latch nodes and a write enable signal.
- the first and second write voltages are different from each other and logic values of data written to the respective non-volatile memory cells are different.
- the pair of latch nodes are configured to receive data stored in the pair of non-volatile memory cells based on a read enable signal. Furthermore, the pair of non-volatile memory cells may not be connected to the pair of latch nodes when the write enable signal based on the read enable signal.
- the non-volatile logic circuit may further include a normal operation selecting unit configured to control a connection between the pair of non-volatile memory cells and the pair of latch nodes based on a read enable signal and the write enable signal, a read operation selecting unit configured to provide data stored in the pair of non-volatile memory cells to the pair of latch nodes based on the read enable signal, and a write operation selecting unit configured to apply the first and second write voltages to the pair of non-volatile memory cells, respectively, based on data of the pair of latch nodes when the write enable signal is activated.
- a normal operation selecting unit configured to control a connection between the pair of non-volatile memory cells and the pair of latch nodes based on a read enable signal and the write enable signal
- a read operation selecting unit configured to provide data stored in the pair of non-volatile memory cells to the pair of latch nodes based on the read enable signal
- a write operation selecting unit configured to apply the first and second write voltages to the pair of non-volatile memory
- the non-volatile logic circuit may further include an equalization unit configured to connect the pair of latch nodes based on a pulse signal for equalizing data of the pair of latch nodes.
- the normal operation selecting unit may include a logic gate configured to output an activated output signal based on the read enable signal and the write enable signal, and first and second ground switches configured to connect the pair of latch nodes, respectively, to ground voltage terminals based on the activated output signal.
- the read operation selecting unit may include first and second read switches configured to connect the pair of latch nodes to the pair of non-volatile memory cells, respectively, based on the read enable signal.
- the write operation selecting unit may include first and second write voltage providing units configured to apply the first and second write voltages, respectively, based on the write enable signal, two first write switches configured to connect the first and second write voltage providing units to the pair of non-volatile memory cells, respectively, based on data of a first latch node of the pair of the latch nodes, and two second write switches configured to connect the first and second write voltage providing units to the pair of non-volatile memory cells, respectively, based on data of a second latch node of the pair of the latch nodes.
- a circuit block includes a master latch configured to latch input data and a slave latch configured to latch output data of the master latch.
- the slave latch includes a latch unit having a pair of latch nodes and a pair of latch nodes and a pair of non-volatile memory cells configured to receive first and second write voltages based on data of the pair of latch nodes and a write enable signal. The first and second write voltages are different from each other and logic values of data written to the respective non-volatile memory cells are different.
- an integrated circuit includes a plurality of circuit blocks having at least one logic circuit block and at least one non-volatile logic circuit, a power sensor configured to generate a sense signal if power supplied to at least one of the circuit blocks drops below a value, and a controller configured to generate a read enable signal or a write enable signal based on at least one of the sense signal and an externally provided command.
- the at least one non-volatile logic circuit includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells configured to receive first and second write voltages based on data of the pair of latch nodes and a write enable signal. The first and second write voltages are different from each other and logic values of data written to the respective non-volatile memory cells are different.
- a method of operating an integrated circuit including a plurality of circuit blocks having at least one logic circuit block and at least one non-volatile logic circuit, wherein the non-volatile logic circuit includes a latch unit having a pair of latch nodes and includes a pair of non-volatile memory cells
- the method includes first generating, by the IC, a sense signal if power supplied to at least one of the circuit blocks drops below a value, second generating, by the IC, a read enable signal or a write enable signal based on at least one of the sense signal and an externally provided command, and writing, by the IC, the pair of non-volatile memory cells by applying the first and second write voltages, which are different, to the pair of non-volatile memory cells, respectively, based on data of the pair of latch nodes.
- FIG. 1 is a schematic block diagram of an integrated circuit (IC) according to an example embodiment
- FIG. 2 is a timing diagram for describing operations of a power sensor and a controller of FIG. 1 ;
- FIG. 3 is a timing diagram for describing operations of the controller of FIG. 1 ;
- FIG. 4 is a circuit diagram showing an example of a latch circuit included in a flip-flop as shown in FIG. 1 ;
- FIG. 5 is a circuit diagram for describing a normal operation of the latch circuit shown in FIG. 4 ;
- FIG. 6 is a circuit diagram for describing a read operation of the latch circuit shown in FIG. 4 ;
- FIG. 7 is a circuit diagram for describing a write operation of the latch circuit shown in FIG. 4 ;
- FIG. 8 is a circuit diagram showing an example of a flip-flop shown in FIG. 1 ;
- FIG. 9 is a circuit diagram for describing a normal operation of the flip-flop of FIG. 8 ;
- FIG. 10 is a circuit diagram for describing a read operation of the flip-flop of FIG. 8 ;
- FIG. 11 is a timing diagram for describing a read operation of the flip-flop of FIG. 8 ;
- FIG. 12 is a circuit diagram for describing a write operation of the flip-flop shown in FIG. 8 ;
- FIG. 13 is a timing diagram for describing write operation of the flip-flop shown in FIG. 8 .
- FIG. 1 is a schematic block diagram of an integrated circuit (IC) 1 according to an example embodiment.
- the IC 1 may be embodied as a single chip within a single electronic system, and may include a plurality of circuit blocks 10 through 50 , a power sensor 60 , a controller 70 and/or a pulse generator 95 configured to output a pulse signal PS to at least circuit blocks 10 , 20 and 30 .
- the plurality of circuit blocks 10 through 50 may include first through third flip-flops 10 , 20 , and 30 and first and second logic circuit blocks 40 and 50 .
- FIG. 1 shows three flip-flops 10 , 20 , and 30 and two logic circuit blocks 40 and 50 for convenience of explanation, the IC 1 may include more flip-flops and/or more logic circuit blocks.
- the first through third flip-flops 10 , 20 , and 30 may be non-volatile flip-flops, each of which includes a pair of non-volatile memory cells.
- non-volatile flip-flops will be described in detail as an example of a non-volatile logic circuit.
- the first flip-flop 10 may receive, from an external data generator 90 , externally provided input data IN and latch the input data IN to be synchronized with a clock signal CLK.
- the first logic circuit block 40 may perform a predetermined logic operation with respect to data output by the first flip-flop 10 .
- the second flip-flop 20 may receive data output by the first logic circuit block 40 and latch the received data to be synchronized with a clock signal CLK.
- the second logic circuit block 50 may perform a predetermined logic operation with respect to data output by the second flip-flop 20 .
- the third flip-flop 30 may receive data output by the second logic circuit block 50 and latch the received data to be synchronized with a clock signal CLK. Accordingly, the first through third flip-flops 10 , 20 , and 30 perform normal latching operations, such that signals within the IC 1 are synchronized with a clock signal CLK.
- the first through third flip-flops 10 , 20 , and 30 may perform a write operation or a read operation with respect to the pairs of non-volatile memory cells included therein according to a write enable signal WEN or a read enable signal REN. Therefore, each of the flip-flops 10 , 20 , and 30 may perform the write operation or the read operation when the write enable signal WEN or the read enable signal REN is activated, and may perform a normal latching operation when the write enable signal WEN or the read enable signal REN is not activated. Detailed descriptions of operations of each of the flip-flops 10 , 20 , and 30 will be given below.
- the power sensor 60 may sense power applied to the IC 1 , and, when the power drops below a predetermined critical value, the power sensor 60 may generate a sense signal SS.
- the power sensor 60 may generate the sense signal SS by detecting power applied to at least one of the plurality of circuit blocks 10 through 50 in the IC 1 .
- the controller 70 may activate the read enable signal REN or the write enable signal WEN based on an externally input command CMD received from an external command generator 80 or the sense signal SS generated by the power sensor 60 .
- the externally input command CMD may be a write command W_CMD or a read command R_CMD, for example.
- a user may generate the write command W_CMD.
- the controller 70 may activate a write enable signal WEN according to the write command W_CMD.
- a user may generate the read command R_CMD.
- the controller 70 may activate the read enable signal REN according to the read command R_CMD.
- FIG. 2 is a timing diagram for describing operations of the power sensor 60 and the controller 70 of FIG. 1 .
- the power sensor 60 may generate a sense signal SS when power applied to the IC 1 drops below a predetermined critical value, and the controller 70 may activate a write enable signal WEN when a sense signal SS is generated.
- the write enable signal WEN activated by the controller 70 may be provided to the first through third flip-flops 10 , 20 , and 30 .
- Each of the flip-flops 10 , 20 , and 30 may perform a write operation with respect to the pair of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 based on the activated write enable signal WEN.
- FIG. 3 is a timing diagram for describing operations of the controller 70 of FIG.
- the controller 70 may activate a write enable signal WEN or a read enable signal REN.
- the write enable signal WEN and the read enable signal REN may be provided to the first through third flip-flops 10 , 20 , and 30 .
- Each of the flip-flops 10 , 20 , and 30 may perform a read operation with respect to the pair of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 based on the activated read enable signal REN.
- each of the flip-flops 10 , 20 , and 30 may perform a write operation with respect to the pair of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 based on the activated write enable signal WEN.
- the controller 70 may not activate the write enable signal WEN and the read enable signal REN, and thus each of the flip-flops 10 , 20 , and 30 may operate as a normal latch. Meanwhile, when a read command R_CMD is externally received, the controller 70 may activate the read enable signal REN, and each of the flip-flops 10 , 20 , and 30 may perform a read operation with respect to the pair of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 based on the activated read enable signal REN.
- the controller 70 may activate the write enable signal WEN, and each of the flip-flops 10 , 20 , and 30 may perform a write operation with respect to the pair of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 based on the activated write enable signal WEN.
- the power sensor 60 may generate the sense signal SS before the supply of the power is discontinued, and the controller 70 may activate the write enable signal WEN. Therefore, write operations may be performed with respect to the pairs of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 . As a result, the operation results of the logic circuit blocks 40 and 50 included in the IC 1 may be stored in each of the flip-flops 10 , 20 , and 30 before the supply of the power is discontinued.
- the controller 70 may activate a read enable signal REN. Therefore, read operations may be performed with respect to data stored in the pairs of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 , and thus boot codes may be loaded. As a result, when power is applied to the IC 1 again, a booting operation may be performed by loading data stored in the pairs of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 in the IC 1 without accessing an external read-only memory (ROM), and thus the time taken to perform a booting operation may be reduced.
- ROM read-only memory
- non-volatile memory cells When non-volatile memory cells are applied to a logic circuit, such as a flip-flop, it is necessary for the non-volatile memory cells to have excellent endurance. In other words, it is necessary for non-volatile memory cells to endure the infinite number of times write operations are performed. However, in reality, non-volatile memory cells may endure from about 10 5 to about 10 6 write operations. Therefore, in the case where a logic circuit includes a non-volatile memory cell, when write operations are always performed with respect to the non-volatile memory cell based on data input to the logic circuit, reliability of the logic circuit itself may not be guaranteed due to the limited endurance of the non-volatile memory cell.
- each of the flip-flops 10 , 20 , and 30 may perform a write operation with respect to the pair of non-volatile memory cells included in each of the flip-flops 10 , 20 , and 30 only when a write enable signal WEN is received and is activated. Therefore, despite of the limited endurances of each of the non-volatile memory cells, reliability of the flip-flops 10 , 20 , and 30 including the non-volatile memory cells may be significantly improved by reducing the number of times write operations are performed with respect to each of the non-volatile memory cells.
- FIG. 4 is a circuit diagram showing an example of a latch circuit 100 included in a flip-flop as shown in FIG. 1 .
- the latch circuit 100 includes a latch unit 11 , first and second non-volatile memory cells 12 and 13 , a normal operation selecting unit 14 , a read operation selecting unit 15 , a write operation selecting unit 16 , and an equalization unit 17 .
- the latch unit 11 includes first and second latch nodes LN 1 and LN 2 and two inverters that are cross-combined to each other.
- a first inverter includes a first p-type metal-oxide-semiconductor (PMOS) transistor P 1 , which is connected to a power voltage terminal Vcc, and a first n-type metal-oxide-semiconductor (NMOS) transistor N 1 , which is connected to the first PMOS transistor P 1 in series
- a second inverter includes a second PMOS transistor P 2 , which is connected to the power voltage terminal Vcc, and a second NMOS transistor N 2 , which is connected to the second PMOS transistor P 2 in series.
- the input terminal of the first inverter and the output terminal of the second inverter correspond to the first latch node LN 1
- the output terminal of the first inverter and the input terminal of the second inverter correspond to the second latch node LN 2 .
- the first and second non-volatile memory cells 12 and 13 are devices capable of retaining stored data even if power supplies thereto are interrupted.
- the first and second memory cells 12 and 13 may be resistive memory devices.
- the resistance values of the resistive memory devices may change according to a magnitude of a voltage or a current applied thereto and a direction in which a voltage or a current is applied thereto, thus, the resistive memory devices may have a reset state (a high resistance state) or a set state (a low resistance state). That is, the state of each of resistive memory devices changes to a high or low resistance state when a voltage or a current pulse is applied thereto.
- resistive memory devices may store information by using the high and low resistance states as bit information.
- first and second non-volatile memory cells 12 and 13 are not limited to resistive memory devices, and may be any of various types of memories; e.g. flash memories, phase change memories (PRAMs), ferroelectric RAMs (FeRAMs), or magnetoresistive RAMs (MRAMs).
- flash memories phase change memories (PRAMs), ferroelectric RAMs (FeRAMs), or magnetoresistive RAMs (MRAMs).
- PRAMs phase change memories
- FeRAMs ferroelectric RAMs
- MRAMs magnetoresistive RAMs
- the normal operation selecting unit 14 controls the first and second non-volatile memory cells 12 and 13 to be not connected to the latch unit 11 .
- the normal operation selecting unit 14 may include a logic gate 141 and first and second ground switches 142 and 143 that are turned on/off by an output signal of the logic gate 141 .
- the logic gate 141 activates an output signal in the case where the read enable signal REN and the write enable signal WEN are not activated.
- the logic gate 141 may be embodied as a NOR gate, and may perform a logic NOR operation with respect to a read enable signal REN and a write enable signal WEN.
- the first and second ground switches 142 and 143 are closed and respectively connect the source terminals of the first and second NMOS transistors N 1 and N 2 included in the latch unit 11 to ground voltage terminals. Accordingly, when the read enable signal REN and the write enable signal WEN are not activated, the latch circuit 100 may operate as a normal latch.
- the read operation selecting unit 15 When a read enable signal REN is activated, the read operation selecting unit 15 provides data stored in the first and second non-volatile memory cells 12 and 13 to the first and second latch nodes LN 1 and LN 2 by connecting the first and second non-volatile memory cells 12 and 13 to the first and second latch nodes LN 1 and LN 2 , respectively.
- the read operation selecting unit 15 may include first and second read switches 151 and 152 that are turned on/off by a read enable signal REN.
- the first and second read switches 151 and 152 When a read enable signal REN is activated, the first and second read switches 151 and 152 are closed and respectively connect the first and second non-volatile memory cells 12 and 13 to the first and second latch nodes LN 1 and LN 2 . Therefore, data stored in the first and second non-volatile memory cells 12 and 13 may be transmitted to the first and second latch nodes LN 1 and LN 2 , and thus a read operation may be performed.
- the write operation selecting unit 16 applies first and second write voltages V 1 and V 2 , which differ from each other according to data of the first and second latch nodes LN 1 and LN 2 , to the first and second non-volatile memory cells 12 and 13 , respectively.
- the first write voltage V 1 may be a voltage to be applied to set the first and second non-volatile memory cells 12 and 13
- the second write voltage V 2 may be a voltage to be applied to reset the first and second non-volatile memory cells 12 and 13 .
- the second write voltage V 2 may be greater than the first write voltage V 1 .
- the write operation selecting unit 16 includes first and second write voltage providing units 161 and 162 , first write switches 163 and 164 , and second write switches 165 and 166 .
- the first write voltage providing unit 161 may include a PMOS transistor having a source connected to a first write voltage V 1 terminal and having a gate, to which an inverted write enable signal nWEN is applied.
- the second write voltage providing unit 162 may include a PMOS transistor having a source connected to a second write voltage V 2 terminal and having a gate, to which the inverted write enable signal nWEN is applied. Therefore, when the write enable signal WEN is activated (that is, when the inverted write enable signal nWEN is logic low), the PMOS transistors included in the first and second write voltage providing units 161 and 162 may be turned on and may respectively output first and second write voltages V 1 and V 2 .
- the first write switches 163 and 164 are turned on/off by data of the first latch node LN 1 and connect the output terminals of the first and second write voltage providing units 161 and 162 to the first and second non-volatile memory cells 12 and 13 , respectively.
- the second write switches 165 and 166 are turned on/off by data of the second latch node LN 2 and connect the output terminals of the first and second write voltage providing units 161 and 162 to the first and second non-volatile memory cells 12 and 13 , respectively.
- the equalization unit 17 is interconnected between the first latch node LN 1 and the second latch node LN 2 , and, when a pulse signal PS having a pulse width is applied thereto, the equalization unit 17 transmits voltages of the first latch node LN 1 and the second latch node LN 2 .
- the equalization unit 17 may be embodied as an NMOS transistor having a gate to which a pulse signal PS is applied. Therefore, when the pulse signal PS is activated (logic high), the first latch node LN 1 and the second latch node LN 2 are connected to each other, and thus the voltage of the first latch node LN 1 becomes equal to the voltage of the second latch node LN 2 .
- the pulse signal PS is activated when a read operation is performed with respect to the first and second non-volatile memory cells 12 and 13 . Therefore, when the pulse signal PS is deactivated after the voltages of the first latch node LN 1 and the second latch node LN 2 are equalized during a period when the pulse signal PS is activated, data stored in the first and second non-volatile memory cells 12 and 13 may be read out by transmitting the data stored in the first and second non-volatile memory cells 12 and 13 to the first latch node LN 1 and the second latch node LN 2 .
- FIG. 5 is a circuit diagram for describing a normal operation of the latch circuit 100 shown in FIG. 4 .
- a read enable signal REN and a write enable signal WEN are not activated, and a pulse signal PS is also not activated. Therefore, an output signal of the logic gate 141 of the normal operation selecting unit 14 is activated, and thus the first and second ground switches 142 and 143 are closed (“on”). Meanwhile, the first and second read switches 151 and 152 are opened (“off”), and the first and second write voltage providing units 161 and 162 of the write operation selecting unit 16 and the equalization unit 17 are deactivated. Therefore, the latch unit 11 is not connected to the first and second non-volatile memory cells 12 and 13 , and thus the latch circuit 100 operates as a normal latch circuit.
- FIG. 6 is a circuit diagram for describing a read operation of the latch circuit 100 shown in FIG. 4 .
- the equalization unit 17 connects the first latch node LN 1 and the second latch node LN 2 first, and thus the voltages of the first latch node LN 1 and the second latch node LN 2 are equalized.
- an output signal of the logic gate 141 of the normal operation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the read operation selecting unit 15 are closed, and the first and second write voltage providing units 161 and 162 of the write operation selecting unit 16 are deactivated. Therefore, the first and second non-volatile memory cells 12 and 13 are connected to the first and second latch nodes LN 1 and LN 2 via the path indicated by an arrow in FIG. 6 , and thus data stored in the first and second non-volatile memory cells 12 and 13 are transmitted to the first and second latch nodes LN 1 and LN 2 , respectively.
- FIG. 7 is a circuit diagram for describing a write operation of the latch circuit 100 shown in FIG. 4 .
- a write enable signal WEN is activated, whereas a read enable signal REN and a pulse signal PS are not activated. Therefore, an output signal of the logic gate 141 of the normal operation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the read operation selecting unit 15 are opened, and the first and second write voltage providing units 161 and 162 of the write operation selecting unit 16 are activated.
- data of the first and second latch nodes LN 1 and LN 2 are provided to the first write switches 163 and 164 and the second write switches 165 and 166 via the path indicated by an arrow in FIG. 7 .
- data of the first latch node LN 1 and data of the second latch node LN 2 have opposite logic values, and thus the first write switches 163 and 164 or the second write switches 165 and 166 are selectively opened.
- the first write switches 163 and 164 are opened, and the second write switches 165 and 166 are closed. Therefore, the output terminal of the second write voltage providing unit 162 is connected to the first non-volatile memory cell 12 , whereas the output terminal of the first write voltage providing unit 161 is connected to the second non-volatile memory cell 13 . Therefore, a second write voltage V 2 , which is a reset voltage, is applied to the first non-volatile memory cell 12 , and a first write voltage V 1 , which is a set voltage, is applied to the second non-volatile memory cell 13 .
- the first write switches 163 and 164 are closed, and the second write switches 165 and 166 are opened. Therefore, the output terminal of the first write voltage providing unit 161 is connected to the first non-volatile memory cell 12 , whereas the output terminal of the second write voltage providing unit 162 is connected to the second non-volatile memory cell 13 . Therefore, a first write voltage V 1 , which is a set voltage, is applied to the first non-volatile memory cell 12 , and a second write voltage V 1 , which is a reset voltage, is applied to the second non-volatile memory cell 13 .
- FIG. 8 is a circuit diagram showing an example of a flip-flop 200 as shown in FIG. 1 .
- the first through third flip-flops 10 , 20 and 30 have the same structure of the flip-flop 200 , shown in FIG. 8 .
- the flip-flop 200 may be a master-slave flip-flop including a master latch ML and a slave latch SL.
- the flip-flop 200 may further include first and second transmission gates TG 1 and TG 2 .
- the first transmission gate TG 1 is turned on/off by a clock signal CLK and an inverted clock signal nCLK and may transmit input data Din to the master latch ML.
- the second transmission gate TG 2 is turned on/off by the clock signal CLK and the inverted clock signal nCLK and may transmit output data of the master latch ML to the slave latch SL.
- the master latch ML includes first and second inverters INV 1 and INV 2 that are cross-coupled with each other, and may further include a third transmission gate TG 3 .
- the third transmission gate TG 3 may be turned on/off by the clock signal CLK and the inverted clock signal nCLK and may transmit output data of the second inverter INV 2 to the first inverter INV 1 .
- the slave latch SL may include the latch circuit 100 of FIG. 4 . Therefore, the latch circuit 100 included in the slave latch SL is identical to the latch circuit 100 shown in FIG. 4 , and thus detailed descriptions thereof will be omitted. Furthermore, the slave latch SL may further include a third inverter INV 3 and a fourth transmission gate TG 4 .
- the third inverter INV 3 inverts output data of the second transmission gate TG 2 .
- the fourth transmission gate TG 4 may be turned on/off by the clock signal CLK and the inverted clock signal nCLK, and may transmit output data of the third inverter INV 3 to an output node Dout.
- the third inverter INV 3 may be connected to the output terminal of the master latch ML and may invert output data of the master latch ML.
- FIG. 9 is a circuit diagram for describing a normal operation of the flip-flop 200 of FIG. 8 .
- a read enable signal REN and a write enable signal WEN are not activated, and a pulse signal is also not activated. Therefore, an output signal of the logic gate 141 of the normal operation selecting unit 14 is activated, and thus the first and second ground switches 142 and 143 are closed. Meanwhile, the first and second read switches 151 and 152 are opened, and the first and second write voltage providing units 161 and 162 of the write operation selecting unit 16 and the equalization unit 17 are deactivated. Therefore, the latch unit 11 is not connected to the first and second non-volatile memory cells 12 and 13 , and thus the latch circuit 100 operates as a normal latch circuit. Therefore, the flip-flop 200 functions as a normal master slave flip-flop. Here, the flip-flop 200 may latch data at the rising edge of a clock signal CLK.
- FIG. 10 is a circuit diagram for describing a read operation of the flip-flop 200 of FIG. 8 .
- the equalization unit 17 connects the first latch node LN 1 and the second latch node LN 2 first, and thus the voltages of the first latch node LN 1 and the second latch node LN 2 are equalized.
- the pulse signal PS is deactivated, the voltages of the first latch node LN 1 and the second latch node LN 2 are changed by the read operation with respect to the first and second non-volatile memory cells 12 and 13 .
- an output signal of the logic gate 141 of the normal operation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the read operation selecting unit 15 are closed, and the first and second write voltage providing units 161 and 162 of the write operation selecting unit 16 are deactivated. Therefore, the first and second non-volatile memory cells 12 and 13 are connected to the first and second latch nodes LN 1 and LN 2 via the path indicated by an arrow in FIG. 10 , and thus data stored in the first and second non-volatile memory cells 12 and 13 are transmitted to the first and second latch nodes LN 1 and LN 2 , respectively.
- FIG. 11 is a timing diagram for describing a read operation of the flip-flop 200 of FIG. 8 .
- data Din input to the flip-flop 200 is transmitted to the slave latch SL after two cycles of a clock signal CLK.
- a pulse signal PS is activated, the first latch node LN 1 and the second latch node LN 2 of the slave latch SL are connected to each other, and thus the voltages of the first and second latch nodes LN 1 and LN 2 are equalized.
- the pulse signal PS is deactivated. In the case of performing the read operation, it is necessary to perform the equalization of the voltages of the first and second latch nodes LN 1 and LN 2 first for clearly sensing data of the first and second non-volatile memory cells 12 and 13 .
- the first and second non-volatile memory cells 12 and 13 are connected to the first and second latch nodes LN 1 and LN 2 , respectively. Therefore, data stored in the first and second non-volatile memory cells 12 and 13 is transmitted to the first and second latch nodes LN 1 and LN 2 , respectively. Accordingly, the read operation is performed with respect to the first and second non-volatile memory cells 12 and 13 .
- FIG. 12 is a circuit diagram for describing a write operation of the flip-flop 200 shown in FIG. 8 .
- a write enable signal WEN is activated, whereas a read enable signal REN and a pulse signal PS are not activated. Therefore, an output signal of the logic gate 141 of the normal operation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the read operation selecting unit 15 are opened, and the first and second write voltage providing units 161 and 162 of the write operation selecting unit 16 are activated.
- data of the first and second latch nodes LN 1 and LN 2 are connected to the first write switches 163 and 164 and the second write switches 165 and 166 via the path indicated by an arrow in FIG. 12 .
- data of the first latch node LN 1 and data of the second latch node LN 2 have opposite logic values, and thus the first write switches 163 and 164 or the second write switches 165 and 166 are selectively opened.
- FIG. 13 is a timing diagram for describing a write operation of the flip-flop 200 shown in FIG. 8 .
- data Din input to the flip-flop 200 is transmitted to the slave latch SL after two cycles of a clock signal CLK.
- a read enable signal WEN is activated
- the first latch node LN 1 and the second latch node LN 2 of the slave latch SL are connected to the first write switches 163 and 164 and the second write switches 165 and 166 , respectively. Therefore, the first write switches 163 and 164 and the second write switches 165 and 166 are turned on/off by data of the first and second latch nodes LN 1 and LN 2 , and the first and second write voltages V 1 and V 2 are selectively applied to the first and second non-volatile memory cells 12 and 13 . Accordingly, the write operation is performed with respect to the first and second non-volatile memory cells 12 and 13 .
- the first write switches 163 and 164 are opened, and the second write switches 165 and 166 are closed. Therefore, the output terminal of the second write voltage providing unit 162 is connected to the first non-volatile memory cell 12 , whereas the output terminal of the first write voltage providing unit 161 is connected to the second non-volatile memory cell 13 . Therefore, a second write voltage V 2 , which is a reset voltage, is applied to the first non-volatile memory cell 12 , and a first write voltage V 1 , which is a set voltage, is applied to the second non-volatile memory cell 13 .
- the first write switches 163 and 164 are closed, and the second write switches 165 and 166 are opened. Therefore, the output terminal of the first write voltage providing unit 161 is connected to the first non-volatile memory cell 12 , whereas the output terminal of the second write voltage providing unit 162 is connected to the second non-volatile memory cell 13 . Therefore, a first write voltage V 1 , which is a set voltage, is applied to the first non-volatile memory cell 12 , and a second write voltage V 1 , which is a reset voltage, is applied to the second non-volatile memory cell 13 .
- An IC according to example embodiments as described above may be included in an electronic device or in an electric system.
- an IC according to an example embodiment may be embodied as a single chip in an electronic device or in an electric system.
- logic circuits included in a plurality of chips included in an electronic device or in an electric system may include non-volatile memory cells. Therefore, data of the electronic device or in the electric system may be stored in non-volatile memory cells even in the case where power is suddenly removed, and the electronic device or the electric system may be booted quickly after power is restored.
- a non-volatile logic circuit includes a latch unit, which includes a pair of latch nodes, and a pair of non-volatile memory cells, and performs a write operation with respect to the pair of non-volatile memory cells only when a write enable signal is activated. Therefore, a non-volatile logic circuit may be stably operated despite the limited endurance of non-volatile memory cells.
- the non-volatile logic circuit transmits data stored in the non-volatile memory cells to the pair of latch nodes, respectively, when a read enable signal is activated.
- the data stored in the non-volatile memory cells before power is cut off may be quickly read from when power is supplied again. Accordingly, the non-volatile logic circuit may be booted in a simple manner and directly without having to access an external ROM, thereby greatly reducing a booting time.
- data stored in the non-volatile logic circuit may be written to the non-volatile memory cells by generating a sense signal and activating a write enable signal and the data may be read from the non-volatile memory cells when power is supplied again.
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Abstract
Description
- This non-provisional U.S. application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0121938, filed on Dec. 9, 2009, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.
- 1. Field
- The present disclosure relates to non-volatile logic circuits, and more particularly, to non-volatile logic circuits including non-volatile memory devices, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits.
- 2. Description of the Related Art
- A need for development of memory devices that have high storage capacity and consumes less power has triggered research into next-generation memory devices that are not only non-volatile memory but also do not need to be refreshed. Recently, much attention has been paid to next-generation memory devices, such as Phase Change Random Access Memory (PRAM), Nano Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), and Resistive RAM (RRAM). Accordingly, research has been actively conducted in order to apply such a next-generation memory device to a logic circuit.
- Provided are non-volatile logic circuits, to which non-volatile memory devices are applied for shorter booting time and writing operations are performed with respect to the non-volatile memory devices for a reduced number of times in consideration of endurances of the non-volatile memory devices, integrated circuits including the non-volatile logic circuits, and methods of operating the integrated circuits.
- Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of example embodiments.
- According to an example embodiment, a non-volatile logic circuit includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells configured to receive first and second write voltages based on data of the pair of latch nodes and a write enable signal. The first and second write voltages are different from each other and logic values of data written to the respective non-volatile memory cells are different.
- The pair of latch nodes are configured to receive data stored in the pair of non-volatile memory cells based on a read enable signal. Furthermore, the pair of non-volatile memory cells may not be connected to the pair of latch nodes when the write enable signal based on the read enable signal.
- The non-volatile logic circuit may further include a normal operation selecting unit configured to control a connection between the pair of non-volatile memory cells and the pair of latch nodes based on a read enable signal and the write enable signal, a read operation selecting unit configured to provide data stored in the pair of non-volatile memory cells to the pair of latch nodes based on the read enable signal, and a write operation selecting unit configured to apply the first and second write voltages to the pair of non-volatile memory cells, respectively, based on data of the pair of latch nodes when the write enable signal is activated.
- The non-volatile logic circuit may further include an equalization unit configured to connect the pair of latch nodes based on a pulse signal for equalizing data of the pair of latch nodes.
- The normal operation selecting unit may include a logic gate configured to output an activated output signal based on the read enable signal and the write enable signal, and first and second ground switches configured to connect the pair of latch nodes, respectively, to ground voltage terminals based on the activated output signal. The read operation selecting unit may include first and second read switches configured to connect the pair of latch nodes to the pair of non-volatile memory cells, respectively, based on the read enable signal. The write operation selecting unit may include first and second write voltage providing units configured to apply the first and second write voltages, respectively, based on the write enable signal, two first write switches configured to connect the first and second write voltage providing units to the pair of non-volatile memory cells, respectively, based on data of a first latch node of the pair of the latch nodes, and two second write switches configured to connect the first and second write voltage providing units to the pair of non-volatile memory cells, respectively, based on data of a second latch node of the pair of the latch nodes.
- According to another example embodiment, a circuit block includes a master latch configured to latch input data and a slave latch configured to latch output data of the master latch. The slave latch includes a latch unit having a pair of latch nodes and a pair of latch nodes and a pair of non-volatile memory cells configured to receive first and second write voltages based on data of the pair of latch nodes and a write enable signal. The first and second write voltages are different from each other and logic values of data written to the respective non-volatile memory cells are different.
- According to another example embodiment, an integrated circuit (IC) includes a plurality of circuit blocks having at least one logic circuit block and at least one non-volatile logic circuit, a power sensor configured to generate a sense signal if power supplied to at least one of the circuit blocks drops below a value, and a controller configured to generate a read enable signal or a write enable signal based on at least one of the sense signal and an externally provided command. The at least one non-volatile logic circuit includes a latch unit having a pair of latch nodes and a pair of non-volatile memory cells configured to receive first and second write voltages based on data of the pair of latch nodes and a write enable signal. The first and second write voltages are different from each other and logic values of data written to the respective non-volatile memory cells are different.
- According to another example embodiment, a method of operating an integrated circuit (IC) including a plurality of circuit blocks having at least one logic circuit block and at least one non-volatile logic circuit, wherein the non-volatile logic circuit includes a latch unit having a pair of latch nodes and includes a pair of non-volatile memory cells, the method includes first generating, by the IC, a sense signal if power supplied to at least one of the circuit blocks drops below a value, second generating, by the IC, a read enable signal or a write enable signal based on at least one of the sense signal and an externally provided command, and writing, by the IC, the pair of non-volatile memory cells by applying the first and second write voltages, which are different, to the pair of non-volatile memory cells, respectively, based on data of the pair of latch nodes.
- These and/or other aspects will become apparent and more readily appreciated from the following description of example embodiments, taken in conjunction with the accompanying drawings of which:
-
FIG. 1 is a schematic block diagram of an integrated circuit (IC) according to an example embodiment; -
FIG. 2 is a timing diagram for describing operations of a power sensor and a controller ofFIG. 1 ; -
FIG. 3 is a timing diagram for describing operations of the controller ofFIG. 1 ; -
FIG. 4 is a circuit diagram showing an example of a latch circuit included in a flip-flop as shown inFIG. 1 ; -
FIG. 5 is a circuit diagram for describing a normal operation of the latch circuit shown inFIG. 4 ; -
FIG. 6 is a circuit diagram for describing a read operation of the latch circuit shown inFIG. 4 ; -
FIG. 7 is a circuit diagram for describing a write operation of the latch circuit shown inFIG. 4 ; -
FIG. 8 is a circuit diagram showing an example of a flip-flop shown inFIG. 1 ; -
FIG. 9 is a circuit diagram for describing a normal operation of the flip-flop ofFIG. 8 ; -
FIG. 10 is a circuit diagram for describing a read operation of the flip-flop ofFIG. 8 ; -
FIG. 11 is a timing diagram for describing a read operation of the flip-flop ofFIG. 8 ; -
FIG. 12 is a circuit diagram for describing a write operation of the flip-flop shown inFIG. 8 ; and -
FIG. 13 is a timing diagram for describing write operation of the flip-flop shown inFIG. 8 . - Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. In the drawings, the sizes and relative sizes of elements may be exaggerated for clarity. Like numerals refer to like elements throughout.
- It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
- The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
-
FIG. 1 is a schematic block diagram of an integrated circuit (IC) 1 according to an example embodiment. - Referring to
FIG. 1 , theIC 1 may be embodied as a single chip within a single electronic system, and may include a plurality ofcircuit blocks 10 through 50, apower sensor 60, acontroller 70 and/or apulse generator 95 configured to output a pulse signal PS to at leastcircuit blocks flops FIG. 1 shows three flip-flops IC 1 may include more flip-flops and/or more logic circuit blocks. - According to an example embodiment, the first through third flip-
flops - The first flip-
flop 10 may receive, from anexternal data generator 90, externally provided input data IN and latch the input data IN to be synchronized with a clock signal CLK. The firstlogic circuit block 40 may perform a predetermined logic operation with respect to data output by the first flip-flop 10. The second flip-flop 20 may receive data output by the firstlogic circuit block 40 and latch the received data to be synchronized with a clock signal CLK. The secondlogic circuit block 50 may perform a predetermined logic operation with respect to data output by the second flip-flop 20. The third flip-flop 30 may receive data output by the secondlogic circuit block 50 and latch the received data to be synchronized with a clock signal CLK. Accordingly, the first through third flip-flops IC 1 are synchronized with a clock signal CLK. - Furthermore, the first through third flip-
flops flops flops - The
power sensor 60 may sense power applied to theIC 1, and, when the power drops below a predetermined critical value, thepower sensor 60 may generate a sense signal SS. In detail, thepower sensor 60 may generate the sense signal SS by detecting power applied to at least one of the plurality of circuit blocks 10 through 50 in theIC 1. - The
controller 70 may activate the read enable signal REN or the write enable signal WEN based on an externally input command CMD received from anexternal command generator 80 or the sense signal SS generated by thepower sensor 60. The externally input command CMD may be a write command W_CMD or a read command R_CMD, for example. For example, to update a boot code, a user may generate the write command W_CMD. At this point, thecontroller 70 may activate a write enable signal WEN according to the write command W_CMD. Furthermore, in the case where a booting operation is performed or power supplied to theIC 1 is turned on, a user may generate the read command R_CMD. At this point, thecontroller 70 may activate the read enable signal REN according to the read command R_CMD. -
FIG. 2 is a timing diagram for describing operations of thepower sensor 60 and thecontroller 70 ofFIG. 1 . - Referring to
FIGS. 1 and 2 , thepower sensor 60 may generate a sense signal SS when power applied to theIC 1 drops below a predetermined critical value, and thecontroller 70 may activate a write enable signal WEN when a sense signal SS is generated. Here, the write enable signal WEN activated by thecontroller 70 may be provided to the first through third flip-flops flops flops -
FIG. 3 is a timing diagram for describing operations of thecontroller 70 of FIG. Referring toFIGS. 1 and 3 , when a write command W_CMD or a read command R_CMD is externally input, thecontroller 70 may activate a write enable signal WEN or a read enable signal REN. At this point, the write enable signal WEN and the read enable signal REN may be provided to the first through third flip-flops flops flops flops flops - Hereinafter, referring back to
FIG. 1 , operations of each of the flip-flops - When the value of power supplied to the
IC 1 is maintained at a constant level or an additional command is not externally received, thecontroller 70 may not activate the write enable signal WEN and the read enable signal REN, and thus each of the flip-flops controller 70 may activate the read enable signal REN, and each of the flip-flops flops IC 1 drops below a predetermined critical value or a write command W_CMD is externally received, thecontroller 70 may activate the write enable signal WEN, and each of the flip-flops flops - Therefore, when the supply of the power to the
IC 1 is discontinued, thepower sensor 60 may generate the sense signal SS before the supply of the power is discontinued, and thecontroller 70 may activate the write enable signal WEN. Therefore, write operations may be performed with respect to the pairs of non-volatile memory cells included in each of the flip-flops IC 1 may be stored in each of the flip-flops - Furthermore, when power is applied to the
IC 1 again, thecontroller 70 may activate a read enable signal REN. Therefore, read operations may be performed with respect to data stored in the pairs of non-volatile memory cells included in each of the flip-flops IC 1 again, a booting operation may be performed by loading data stored in the pairs of non-volatile memory cells included in each of the flip-flops IC 1 without accessing an external read-only memory (ROM), and thus the time taken to perform a booting operation may be reduced. - When non-volatile memory cells are applied to a logic circuit, such as a flip-flop, it is necessary for the non-volatile memory cells to have excellent endurance. In other words, it is necessary for non-volatile memory cells to endure the infinite number of times write operations are performed. However, in reality, non-volatile memory cells may endure from about 105 to about 106 write operations. Therefore, in the case where a logic circuit includes a non-volatile memory cell, when write operations are always performed with respect to the non-volatile memory cell based on data input to the logic circuit, reliability of the logic circuit itself may not be guaranteed due to the limited endurance of the non-volatile memory cell.
- According to the present example embodiment, each of the flip-
flops flops flops -
FIG. 4 is a circuit diagram showing an example of alatch circuit 100 included in a flip-flop as shown inFIG. 1 . - Referring to
FIG. 4 , thelatch circuit 100 includes alatch unit 11, first and secondnon-volatile memory cells operation selecting unit 14, a readoperation selecting unit 15, a writeoperation selecting unit 16, and anequalization unit 17. - The
latch unit 11 includes first and second latch nodes LN1 and LN2 and two inverters that are cross-combined to each other. A first inverter includes a first p-type metal-oxide-semiconductor (PMOS) transistor P1, which is connected to a power voltage terminal Vcc, and a first n-type metal-oxide-semiconductor (NMOS) transistor N1, which is connected to the first PMOS transistor P1 in series, whereas a second inverter includes a second PMOS transistor P2, which is connected to the power voltage terminal Vcc, and a second NMOS transistor N2, which is connected to the second PMOS transistor P2 in series. The input terminal of the first inverter and the output terminal of the second inverter correspond to the first latch node LN1, whereas the output terminal of the first inverter and the input terminal of the second inverter correspond to the second latch node LN2. - The first and second
non-volatile memory cells second memory cells non-volatile memory cells - When the read enable signal REN and the write enable signal WEN are not activated, the normal
operation selecting unit 14 controls the first and secondnon-volatile memory cells latch unit 11. In detail, the normaloperation selecting unit 14 may include alogic gate 141 and first and second ground switches 142 and 143 that are turned on/off by an output signal of thelogic gate 141. - The
logic gate 141 activates an output signal in the case where the read enable signal REN and the write enable signal WEN are not activated. For example, thelogic gate 141 may be embodied as a NOR gate, and may perform a logic NOR operation with respect to a read enable signal REN and a write enable signal WEN. When an output signal of thelogic gate 141 is activated, the first and second ground switches 142 and 143 are closed and respectively connect the source terminals of the first and second NMOS transistors N1 and N2 included in thelatch unit 11 to ground voltage terminals. Accordingly, when the read enable signal REN and the write enable signal WEN are not activated, thelatch circuit 100 may operate as a normal latch. - When a read enable signal REN is activated, the read
operation selecting unit 15 provides data stored in the first and secondnon-volatile memory cells non-volatile memory cells operation selecting unit 15 may include first and second read switches 151 and 152 that are turned on/off by a read enable signal REN. - When a read enable signal REN is activated, the first and second read switches 151 and 152 are closed and respectively connect the first and second
non-volatile memory cells non-volatile memory cells - When a write enable signal WEN is activated, the write
operation selecting unit 16 applies first and second write voltages V1 and V2, which differ from each other according to data of the first and second latch nodes LN1 and LN2, to the first and secondnon-volatile memory cells non-volatile memory cells non-volatile memory cells operation selecting unit 16 includes first and second writevoltage providing units - The first write
voltage providing unit 161 may include a PMOS transistor having a source connected to a first write voltage V1 terminal and having a gate, to which an inverted write enable signal nWEN is applied. The second writevoltage providing unit 162 may include a PMOS transistor having a source connected to a second write voltage V2 terminal and having a gate, to which the inverted write enable signal nWEN is applied. Therefore, when the write enable signal WEN is activated (that is, when the inverted write enable signal nWEN is logic low), the PMOS transistors included in the first and second writevoltage providing units - The first write switches 163 and 164 are turned on/off by data of the first latch node LN1 and connect the output terminals of the first and second write
voltage providing units non-volatile memory cells voltage providing units non-volatile memory cells - The
equalization unit 17 is interconnected between the first latch node LN1 and the second latch node LN2, and, when a pulse signal PS having a pulse width is applied thereto, theequalization unit 17 transmits voltages of the first latch node LN1 and the second latch node LN2. In detail, theequalization unit 17 may be embodied as an NMOS transistor having a gate to which a pulse signal PS is applied. Therefore, when the pulse signal PS is activated (logic high), the first latch node LN1 and the second latch node LN2 are connected to each other, and thus the voltage of the first latch node LN1 becomes equal to the voltage of the second latch node LN2. - Here, the pulse signal PS is activated when a read operation is performed with respect to the first and second
non-volatile memory cells non-volatile memory cells non-volatile memory cells -
FIG. 5 is a circuit diagram for describing a normal operation of thelatch circuit 100 shown inFIG. 4 . - Referring to
FIG. 5 , when thelatch circuit 100 performs normal operations, a read enable signal REN and a write enable signal WEN are not activated, and a pulse signal PS is also not activated. Therefore, an output signal of thelogic gate 141 of the normaloperation selecting unit 14 is activated, and thus the first and second ground switches 142 and 143 are closed (“on”). Meanwhile, the first and second read switches 151 and 152 are opened (“off”), and the first and second writevoltage providing units operation selecting unit 16 and theequalization unit 17 are deactivated. Therefore, thelatch unit 11 is not connected to the first and secondnon-volatile memory cells latch circuit 100 operates as a normal latch circuit. -
FIG. 6 is a circuit diagram for describing a read operation of thelatch circuit 100 shown inFIG. 4 . - Referring to
FIG. 6 , in the case where thelatch circuit 100 performs the read operation, a read enable signal REN and a pulse signal PS are activated, whereas a write enable signal WEN is not activated. Here, a period when a pulse signal PS is activated is shorter than a period when a read enable signal REN is activated. Therefore, theequalization unit 17 connects the first latch node LN1 and the second latch node LN2 first, and thus the voltages of the first latch node LN1 and the second latch node LN2 are equalized. - Furthermore, an output signal of the
logic gate 141 of the normaloperation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the readoperation selecting unit 15 are closed, and the first and second writevoltage providing units operation selecting unit 16 are deactivated. Therefore, the first and secondnon-volatile memory cells FIG. 6 , and thus data stored in the first and secondnon-volatile memory cells -
FIG. 7 is a circuit diagram for describing a write operation of thelatch circuit 100 shown inFIG. 4 . - Referring to
FIG. 7 , in the case where thelatch circuit 100 performs the write operation, a write enable signal WEN is activated, whereas a read enable signal REN and a pulse signal PS are not activated. Therefore, an output signal of thelogic gate 141 of the normaloperation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the readoperation selecting unit 15 are opened, and the first and second writevoltage providing units operation selecting unit 16 are activated. - Therefore, data of the first and second latch nodes LN1 and LN2 are provided to the first write switches 163 and 164 and the second write switches 165 and 166 via the path indicated by an arrow in
FIG. 7 . Here, data of the first latch node LN1 and data of the second latch node LN2 have opposite logic values, and thus the first write switches 163 and 164 or the second write switches 165 and 166 are selectively opened. - In detail, when the data of the first latch node LN1 is logic high and the data of the second latch node LN2 is logic low, the first write switches 163 and 164 are opened, and the second write switches 165 and 166 are closed. Therefore, the output terminal of the second write
voltage providing unit 162 is connected to the firstnon-volatile memory cell 12, whereas the output terminal of the first writevoltage providing unit 161 is connected to the secondnon-volatile memory cell 13. Therefore, a second write voltage V2, which is a reset voltage, is applied to the firstnon-volatile memory cell 12, and a first write voltage V1, which is a set voltage, is applied to the secondnon-volatile memory cell 13. - Meanwhile, when the data of the first latch node LN1 is logic low and the data of the second latch node LN2 is logic high, the first write switches 163 and 164 are closed, and the second write switches 165 and 166 are opened. Therefore, the output terminal of the first write
voltage providing unit 161 is connected to the firstnon-volatile memory cell 12, whereas the output terminal of the second writevoltage providing unit 162 is connected to the secondnon-volatile memory cell 13. Therefore, a first write voltage V1, which is a set voltage, is applied to the firstnon-volatile memory cell 12, and a second write voltage V1, which is a reset voltage, is applied to the secondnon-volatile memory cell 13. -
FIG. 8 is a circuit diagram showing an example of a flip-flop 200 as shown inFIG. 1 . The first through third flip-flops flop 200, shown inFIG. 8 . - Referring to
FIG. 8 , the flip-flop 200 may be a master-slave flip-flop including a master latch ML and a slave latch SL. The flip-flop 200 may further include first and second transmission gates TG1 and TG2. The first transmission gate TG1 is turned on/off by a clock signal CLK and an inverted clock signal nCLK and may transmit input data Din to the master latch ML. The second transmission gate TG2 is turned on/off by the clock signal CLK and the inverted clock signal nCLK and may transmit output data of the master latch ML to the slave latch SL. - The master latch ML includes first and second inverters INV1 and INV2 that are cross-coupled with each other, and may further include a third transmission gate TG3. The third transmission gate TG3 may be turned on/off by the clock signal CLK and the inverted clock signal nCLK and may transmit output data of the second inverter INV2 to the first inverter INV1.
- The slave latch SL may include the
latch circuit 100 ofFIG. 4 . Therefore, thelatch circuit 100 included in the slave latch SL is identical to thelatch circuit 100 shown inFIG. 4 , and thus detailed descriptions thereof will be omitted. Furthermore, the slave latch SL may further include a third inverter INV3 and a fourth transmission gate TG4. The third inverter INV3 inverts output data of the second transmission gate TG2. The fourth transmission gate TG4 may be turned on/off by the clock signal CLK and the inverted clock signal nCLK, and may transmit output data of the third inverter INV3 to an output node Dout. According to another example embodiment, the third inverter INV3 may be connected to the output terminal of the master latch ML and may invert output data of the master latch ML. -
FIG. 9 is a circuit diagram for describing a normal operation of the flip-flop 200 ofFIG. 8 . - Referring to
FIG. 9 , in the case where the flip-flop 200 performs the normal operation, a read enable signal REN and a write enable signal WEN are not activated, and a pulse signal is also not activated. Therefore, an output signal of thelogic gate 141 of the normaloperation selecting unit 14 is activated, and thus the first and second ground switches 142 and 143 are closed. Meanwhile, the first and second read switches 151 and 152 are opened, and the first and second writevoltage providing units operation selecting unit 16 and theequalization unit 17 are deactivated. Therefore, thelatch unit 11 is not connected to the first and secondnon-volatile memory cells latch circuit 100 operates as a normal latch circuit. Therefore, the flip-flop 200 functions as a normal master slave flip-flop. Here, the flip-flop 200 may latch data at the rising edge of a clock signal CLK. -
FIG. 10 is a circuit diagram for describing a read operation of the flip-flop 200 ofFIG. 8 . - Referring to
FIG. 10 , in the case where the flip-flop 200 performs the read operation, a read enable signal REN and a pulse signal PS are activated, whereas a write enable signal WEN is not activated. Here, a period when the pulse signal PS is activated is shorter than a period when the read enable signal REN is activated. Therefore, theequalization unit 17 connects the first latch node LN1 and the second latch node LN2 first, and thus the voltages of the first latch node LN1 and the second latch node LN2 are equalized. Next, when the pulse signal PS is deactivated, the voltages of the first latch node LN1 and the second latch node LN2 are changed by the read operation with respect to the first and secondnon-volatile memory cells - Here, an output signal of the
logic gate 141 of the normaloperation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the readoperation selecting unit 15 are closed, and the first and second writevoltage providing units operation selecting unit 16 are deactivated. Therefore, the first and secondnon-volatile memory cells FIG. 10 , and thus data stored in the first and secondnon-volatile memory cells -
FIG. 11 is a timing diagram for describing a read operation of the flip-flop 200 ofFIG. 8 . - Referring to
FIGS. 10 and 11 , data Din input to the flip-flop 200 is transmitted to the slave latch SL after two cycles of a clock signal CLK. Next, when a pulse signal PS is activated, the first latch node LN1 and the second latch node LN2 of the slave latch SL are connected to each other, and thus the voltages of the first and second latch nodes LN1 and LN2 are equalized. When the voltages of the first and second latch nodes LN1 and LN2 are equalized, the pulse signal PS is deactivated. In the case of performing the read operation, it is necessary to perform the equalization of the voltages of the first and second latch nodes LN1 and LN2 first for clearly sensing data of the first and secondnon-volatile memory cells - Furthermore, when a read enable signal REN is activated, the first and second
non-volatile memory cells non-volatile memory cells non-volatile memory cells -
FIG. 12 is a circuit diagram for describing a write operation of the flip-flop 200 shown inFIG. 8 . - Referring to
FIG. 12 , in the case where the flip-flop 200 performs the write operation, a write enable signal WEN is activated, whereas a read enable signal REN and a pulse signal PS are not activated. Therefore, an output signal of thelogic gate 141 of the normaloperation selecting unit 14 is not activated, and thus the first and second ground switches 142 and 143 are opened. Meanwhile, the first and second read switches 151 and 152 of the readoperation selecting unit 15 are opened, and the first and second writevoltage providing units operation selecting unit 16 are activated. - Therefore, data of the first and second latch nodes LN1 and LN2 are connected to the first write switches 163 and 164 and the second write switches 165 and 166 via the path indicated by an arrow in
FIG. 12 . Here, data of the first latch node LN1 and data of the second latch node LN2 have opposite logic values, and thus the first write switches 163 and 164 or the second write switches 165 and 166 are selectively opened. -
FIG. 13 is a timing diagram for describing a write operation of the flip-flop 200 shown inFIG. 8 . - Referring to
FIGS. 12 and 13 , data Din input to the flip-flop 200 is transmitted to the slave latch SL after two cycles of a clock signal CLK. Next, when a read enable signal WEN is activated, the first latch node LN1 and the second latch node LN2 of the slave latch SL are connected to the first write switches 163 and 164 and the second write switches 165 and 166, respectively. Therefore, the first write switches 163 and 164 and the second write switches 165 and 166 are turned on/off by data of the first and second latch nodes LN1 and LN2, and the first and second write voltages V1 and V2 are selectively applied to the first and secondnon-volatile memory cells non-volatile memory cells - In detail, when the data of the first latch node LN1 is logic high and the data of the second latch node LN2 is logic low, the first write switches 163 and 164 are opened, and the second write switches 165 and 166 are closed. Therefore, the output terminal of the second write
voltage providing unit 162 is connected to the firstnon-volatile memory cell 12, whereas the output terminal of the first writevoltage providing unit 161 is connected to the secondnon-volatile memory cell 13. Therefore, a second write voltage V2, which is a reset voltage, is applied to the firstnon-volatile memory cell 12, and a first write voltage V1, which is a set voltage, is applied to the secondnon-volatile memory cell 13. - Meanwhile, when the data of the first latch node LN1 is logic low and the data of the second latch node LN2 is logic high, the first write switches 163 and 164 are closed, and the second write switches 165 and 166 are opened. Therefore, the output terminal of the first write
voltage providing unit 161 is connected to the firstnon-volatile memory cell 12, whereas the output terminal of the second writevoltage providing unit 162 is connected to the secondnon-volatile memory cell 13. Therefore, a first write voltage V1, which is a set voltage, is applied to the firstnon-volatile memory cell 12, and a second write voltage V1, which is a reset voltage, is applied to the secondnon-volatile memory cell 13. - An IC according to example embodiments as described above may be included in an electronic device or in an electric system. In detail, an IC according to an example embodiment may be embodied as a single chip in an electronic device or in an electric system. Accordingly, logic circuits included in a plurality of chips included in an electronic device or in an electric system may include non-volatile memory cells. Therefore, data of the electronic device or in the electric system may be stored in non-volatile memory cells even in the case where power is suddenly removed, and the electronic device or the electric system may be booted quickly after power is restored.
- As described above, according to one or more of the example embodiments, a non-volatile logic circuit includes a latch unit, which includes a pair of latch nodes, and a pair of non-volatile memory cells, and performs a write operation with respect to the pair of non-volatile memory cells only when a write enable signal is activated. Therefore, a non-volatile logic circuit may be stably operated despite the limited endurance of non-volatile memory cells.
- Furthermore, according to the one or more of example embodiments, the non-volatile logic circuit transmits data stored in the non-volatile memory cells to the pair of latch nodes, respectively, when a read enable signal is activated. Thus, the data stored in the non-volatile memory cells before power is cut off may be quickly read from when power is supplied again. Accordingly, the non-volatile logic circuit may be booted in a simple manner and directly without having to access an external ROM, thereby greatly reducing a booting time.
- Furthermore, according to the one or more example embodiments, even if power is cut off suddenly, data stored in the non-volatile logic circuit may be written to the non-volatile memory cells by generating a sense signal and activating a write enable signal and the data may be read from the non-volatile memory cells when power is supplied again.
- It should be understood that example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within example embodiments should typically be considered as available for other similar features or aspects in other example embodiments. It will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
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KR1020090121938A KR101611416B1 (en) | 2009-12-09 | 2009-12-09 | Nonvolatile logic circuit, Integrated circuit including the nonvolatile logic circuit and method of operating the integrated circuit |
KR10-2009-0121938 | 2009-12-09 |
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US7961005B1 (en) | 2011-06-14 |
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JP5707102B2 (en) | 2015-04-22 |
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