US20110057727A1 - Adaptive common mode bias for differential amplifier input circuits - Google Patents
Adaptive common mode bias for differential amplifier input circuits Download PDFInfo
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- US20110057727A1 US20110057727A1 US12/557,139 US55713909A US2011057727A1 US 20110057727 A1 US20110057727 A1 US 20110057727A1 US 55713909 A US55713909 A US 55713909A US 2011057727 A1 US2011057727 A1 US 2011057727A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45008—Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45078—Indexing scheme relating to differential amplifiers the common mode signal being taken or deducted from the one or more inputs of the differential amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45292—Indexing scheme relating to differential amplifiers the AAC comprising biasing means controlled by the signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45342—Indexing scheme relating to differential amplifiers the AAC comprising control means on a back gate of the AAC
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- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
Description
- 1. Field
- The disclosure relates generally to differential amplifiers and, more specifically, to body biasing circuitry for differential amplifiers.
- 2. Description of the Related Art
- As the demand for bandwidth and gain requirements in serial link receivers increases, complex problems continue to rise to the forefront. For example, input signals of varying ranges often lead to non-linear operation of differential amplifier stages. These non-linear responses are caused by limited common mode range of the differential amplifier. Design engineers continually seek to solve problems relating to common mode range of their devices.
- In a differential amplifier, the input common mode range refers to the range of differential input signals over which a differential amplifier maintains a linear response, including differential gain. In its simplest form, a differential amplifier has a pair of differential input transistors that receive a differential signal. Differential input signals have a common mode voltage that is the average of the differential voltage input signal received by the pair of transistors. Certain applications require a high common mode range. As common mode requirements go to extreme highs and lows, as compared to the power supply of the amplifier, biasing problems associated with the differential input transistors and current sources of the amplifier arise. These biasing problems lead to non-linear responses and inaccurate differential gain outputs of the differential amplifier.
- To solve the problem of lack of input common mode range, stages have often been added to amplifiers to shift the common mode range. One example of an added stage is an active level shifter. However, adding additional circuitry causes processing speed to decrease and the size of the devices to increase. Processing speed decreasing with device size increasing creates an even greater problem for applications having increased bandwidth and gain requirements. Further, level shifting does not extend common mode range. Level shifting only shifts a default common mode range to a desired level. Ultimately, design engineers have generally had to live with the common mode range present in the devices.
- Therefore, it would be advantageous to provide transistor biasing circuitry that can extend the input common mode range.
- The illustrative embodiments provide a method and apparatus for extending common mode range. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit, wherein coupling the pair of body terminals to the output node of the common mode voltage inversion circuit extends a common mode range of the differential amplifier.
- The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
-
FIG. 1 is a block diagram illustrating a circuit system in accordance with an illustrative embodiment; -
FIG. 2 is a circuit diagram illustrating a body biasing circuit in connection with a differential amplifier in accordance with an illustrative embodiment; -
FIG. 3 is a graph illustrating a relationship between body voltage and the common mode voltage of the circuitry in accordance with an illustrative embodiment; -
FIG. 4 is a graph illustrating a relationship between threshold voltage and body-to-source voltage of the circuitry in accordance with an illustrative embodiment; -
FIG. 5 is a graph illustrating a relationship between threshold voltage and common mode voltage of the circuitry in accordance with an illustrative embodiment; -
FIG. 6 is a graph illustrating a relationship between gate-to-source voltage and common mode voltage of the circuitry in accordance with an illustrative embodiment; -
FIG. 7 is a circuit diagram illustrating behavior of a differential amplifier for a given low common mode voltage in accordance with an illustrative embodiment; -
FIG. 8 is a circuit diagram illustrating behavior of a differential amplifier for a given high common mode voltage in accordance with an illustrative embodiment; -
FIG. 9 is a graph depicting simulation results for increased common mode range at low common mode in accordance with an illustrative embodiment; and -
FIG. 10 is a graph depicting simulation results for increased common mode range at high common mode in accordance with an illustrative embodiment. - With reference now to the figures, and particularly with reference to
FIG. 1 , a block diagram ofcircuit system 116 is depicted in accordance with an illustrative embodiment.Differential signal 100 is received by both commonmode detection circuit 102 anddifferential amplifier 110. Commonmode detection circuit 102 monitorsdifferential signal 100 to determinecommon mode voltage 104 ofdifferential signal 100.Common mode voltage 104 passes through commonmode inversion circuit 106 creatingbody voltage 108.Body voltage 108 bears an inverse relationship tocommon mode voltage 104, thereby extending the common mode range ofdifferential amplifier 110.Differential amplifier 110 producesoutput signal 114. Whilecircuit system 116 is comprised of commonmode detection circuit 102, commonmode inversion circuit 106, anddifferential amplifier 110 in this illustrative embodiment, additional circuitry may be added tocircuit system 116. - Turning now to
FIG. 2 , a circuit diagram illustrating a body biasing circuit connected with a differential amplifier is depicted in accordance with an illustrative embodiment.Differential amplifier 252 includesinput transistors input transistors Input transistors differential signal 200 and their source terminals tied to the drain terminal oftransistor 244. Tail current 248 passes throughtransistor 244. The body terminals ofinput transistors operational amplifier 212 represented bybody voltage 220.Differential amplifier 252 further includes supply voltage 242 (Vsupply),load resistors output nodes output signal 114 inFIG. 1 , is produced. While NMOS transistors are used in this example, PMOS transistors may also be used as input transistors fordifferential amplifier 252. -
Input transistors differential amplifier 252, and are critical to the common mode range and linear performance ofdifferential amplifier 252.Input transistors differential amplifier 252. The greater the range of input voltage signals that bothinput transistors differential amplifier 252. Saturation mode biasing of an NMOS transistor is determined by the voltage drop from the drain to the source of the transistor (VDS) staying higher than the voltage drop from the gate to the source minus the threshold voltage (VTH). For high common mode voltage ranges,differential amplifier 252 is biased better with a higher threshold voltage. For low common mode voltage ranges,differential amplifier 252 is biased better with lower threshold voltage. - The threshold voltage (VTH) of an NMOS transistor can be adjusted by the body effects of the transistor. The voltage drop from the body terminal of a transistor to the source terminal of the transistor (VBS) bears an inverse relationship to the threshold voltage of the transistor. Thus, as VBS decreases, VTH increases, and vice versa.
- The body effect is used to extend the common mode range in this illustrative example. In this embodiment,
body biasing circuit 250 is used to manipulate the VBS ofinput transistors Body biasing circuit 250 includesresistors differential signal 200 and connect to a common node withcapacitor 206 to form a detection circuit, such as commonmode detection circuit 102 inFIG. 1 . Common mode voltage 208 (Vcm) is detected asdifferential signal 200 is filtered byresistors capacitor 206.Common mode voltage 208 passes throughoperational amplifier 212 to produce body voltage 220 (Vbody).Resistors operational amplifier 212 into that of an inverting amplifier. Thus,body voltage 220 bears an inverse relationship tocommon mode voltage 208.Body voltage 220 is connected to the body terminals ofinput transistors body voltage 220 is created by invertingcommon mode voltage 208 and connected to the body terminals, Vcm and VTH bear a direct relationship. In other words, the threshold voltage will move up with high common mode and down with low common mode. This direct relationship between threshold voltage and common mode voltage allowsinput transistors body biasing circuit 250 anddifferential amplifier 252 are depicted inFIG. 2 as an example of circuitry used incircuit system 116 inFIG. 1 , additional circuitry may be added tocircuit system 116 without departing from the scope of the present invention. - Further, the circuitry of this illustrative embodiment may be optimized for a range of common mode voltages detected. Gain parameters for
operational amplifier 212 are controlled by input resistor 214 (R1), feedback resistor 215 (R2), and reference voltage 218 (Vref). Adjusting the parameters of these components may alter the relationship betweenbody voltage 220 andcommon mode voltage 208, allowing for a sharper or flatter response to changes in common mode voltage ranges detected. Adjustable responses to changes in common mode voltage ranges detected allows the circuitry to be tuned for different body effect parameters and create desired differential amplifier performance. - The inverting amplifier formed from
resistors operational amplifier 212 is used as an example of a circuit, such as commonmode inversion circuit 106 inFIG. 1 , to create the inverse relationship betweencommon mode voltage 208 andbody voltage 220. Other types of inversion circuitry may be used to create this relationship, such as, for example, a common source amplifier, inverter, or comparator. - Turning now to
FIGS. 3-6 , graphs illustrating voltage relationships between various nodes of the circuitry are depicted in accordance with an illustrative embodiment.Graph 300 inFIG. 3 shows the inverse relationship betweenbody voltage 302 andcommon mode voltage 304 for a reference voltage 306 (Vref). This inverse relationship can be created by passingcommon mode voltage 304 through common mode inversion circuitry, such asoperational amplifier 212 inFIG. 2 .Common mode voltage 304 can be a common mode detected from an input differential signal, such ascommon mode voltage 208 detected fromdifferential signal 200 inFIG. 2 . This inverse relationship is represented by the following body to common mode equation: -
- with the slope of the inverse relationship being equal to −R2/R1 for
reference voltage 306. -
Graph 400 inFIG. 4 shows the body effect betweenthreshold voltage 402 and body-to-source voltage 404 for an NMOS transistor, such asinput transistors FIG. 2 . The body effect creates an inverse relationship as well. Therefore, as body-to-source voltage 404 of a transistor increases,threshold voltage 402 decreases exponentially. This body effect is represented by the following body effect equation: -
V TH =V T0+γ(√{square root over (φ−V BS)}−√{square root over (φ)}) - where
V T0 406 is threshold voltage for VBS=0. γ is the body effect parameter, and φ is the surface potential of the transistor. -
Graph 500 inFIG. 5 shows the direct relationship betweenthreshold voltage 402 andcommon mode voltage 304 for a transistor, such asinput transistors FIG. 2 . Thus, as thecommon mode voltage 304 increases, thethreshold voltage 402 of a transistor is increased and the common mode range of the transistor is increased. These relationships are represented by the following equation: -
VTH≅VT0+γ(√{square root over (φ−Vbody 30 Vcm−VGS)}−√{square root over (φ)}) - which is the body effect equation substituting
common mode voltage 304 for body-to-source voltage 404 where VGS is the gate-to-source voltage of a transistor which is equal tocommon mode voltage 304 minus the source voltage for a transistor in circuitry in accordance with an illustrative embodiment, such asinput transistors FIG. 2 . Next, placing the previous equation in terms of R1, R2 and Vref, such as those ofbody biasing circuit 250 inFIG. 2 , result in the following equation: -
- This equation further provides for control over optimization of the circuitry such as the gain parameters described above. These equations are approximate because they ignore the slight effects of VGS dependence on VTH.
-
Graph 600 inFIG. 6 shows the direct relationship between gate-to-source voltage 602 andcommon mode voltage 304 for transistors, such asinput transistors FIG. 2 , for a constant drain-to-source current. This direct relationship is represented by the following equations: -
- where VDS represents the drain-to-source current across the transistors and β is a process parameter. As
threshold voltage 402 increases with increasing inputcommon mode voltage 304, as shown inFIG. 5 , the gate-to-source voltage 602 increases. Increasing the gate-to-source voltage 602 improves the biasing of the input transistors, such asinput transistors FIG. 2 , at high common mode because the drain-to-source voltage is increased. Conversely, at lowercommon mode voltage 304,threshold voltage 402 decreases which decreases gate-to-source voltage 602 ofinput transistors source voltage 602 improves the biasing of the current source, such astransistor 244 inFIG. 2 , at low common mode because the drain-to-source voltage of the current source is increased. These equations are also approximate because they ignore the slight effects of VGS dependence on VTH. - Turning now to
FIGS. 7 and 8 , circuit diagrams illustrating behavior of a differential amplifier for different given common mode voltages are depicted in accordance with an illustrative embodiment. The circuit diagrams illustratedifferential amplifier 700 performing at low common mode inFIG. 7 and at high common mode inFIG. 8 . Lowcommon mode 702 inFIG. 7 and highcommon mode 802 inFIG. 8 symbolize the common mode voltage of the differential signal input. - When the common mode input is low (low common mode 702),
body voltage 704 rises due to the inverse relationship created, such as bybody biasing circuit 250 inFIG. 2 . The body effect, represented by the body effect equation, lowers the threshold voltage oftransistors source voltage 706. The lowered gate-to-source voltage 706 results from the direct relationship created with common mode voltage, such as illustrated bygraph 600 inFIG. 6 . Lower gate-to-source voltage 706 allows for a higher drain-to-source voltage 708 (VDS3) acrosstransistor 744.Transistor 744 acts as a current source fordifferential amplifier 700, with tail current 710 representing the current. Higher drain-to-source voltage 708 acrosstransistor 744 allows it to remain biased in saturation mode despite lowcommon mode 702 input. The bias oftransistor 744 in saturation mode allowsdifferential amplifier 700 to perform properly at lowcommon mode 702, thereby extending the common mode range ofdifferential amplifier 700 for low common mode voltage ranges. - When the common mode input is high (high common mode 802) the inverse relationship created lowers
body voltage 804, such as bybody biasing circuit 250 inFIG. 2 . The body effect, represented by the body effect equation, raises the threshold voltage oftransistors transistors source voltage 806 rises as a result of the direct relationship created with common mode voltage, as illustrated bygraph 600 inFIG. 6 . Raising gate-to-source voltage 806 lowers drain-to-source voltage 808 acrosstransistor 744. The lower drain-to-source voltage 808 increases drain-to-source voltage 804 oftransistors transistors source source voltage 806 lowers drain-to-source voltage 808 acrosstransistor 744. At highcommon mode 802, bias oftransistor 744 is not much of an issue as drain-to-source voltage 808 is generally high for highcommon mode 802. Lowering drain-to-source voltage 808 allows for higher drain-to-source voltage 804 acrosstransistors source voltage 810 acrosstransistors transistors common mode 802 and the gain performance ofdifferential amplifier 700 increases. - Turning now to
FIGS. 9 and 10 , graphs illustrating simulation results for increased common mode range for given common mode voltages are depicted in accordance with an illustrative embodiment.FIG. 9 shows the DC gain 904 forcommon mode voltage 902 ofsignals Signal 906 illustrates a graph of a signal from a differential amplifier with body terminals connected to a body biasing circuit, such as illustrated byFIG. 2 .Signal 908 illustrates a signal from a differential amplifier that does not use a body biasing circuit. Rather, the body terminal is tied to ground, as commonly used in high common mode differential amplifier settings. For an application having maximum acceptable level of DC gain 910, the increase of the common mode range detected during the simulation at low common mode is over 50%. Likewise,FIG. 10 shows theDC gain 1004 forcommon mode voltage 1002 ofsignals Signal 1006 illustrates a graph of a signal from a differential amplifier with body terminals connected to a body biasing circuit, such as illustrated byFIG. 2 .Signal 1008 illustrates a signal form a differential amplifier that does not use a body biasing circuit. Rather, the body terminal is set to 600 mV, as commonly used in low common mode differential amplifier settings. For an application having minimum acceptable level ofDC gain 1010, the increase of the common mode range detected during the simulation at high common mode is over 25%. - There are several additional benefits to the described embodiments of the invention besides extending the common mode range of the differential amplifier. The differential amplifier performance improves because the input devices and current source devices are biased in a more ideal location. Thus, the DC gain accuracy of the amplifier improves, the AC response is flatter, and the jitter performance is improved. The common mode rejection of the differential amplifier is also improved because the current source impedance is higher with better saturation mode biasing across the input common mode range. There is an additional benefit to increasing the current source impedance from this body biasing approach. If source degeneration is implemented in the differential amplifier, the resulting DC gain of the differential amplifier is more accurate. This is especially true at very low DC gain applications where the source degeneration resistance is very high.
- The circuit, as described above, is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- The description of the present invention has been presented for purposes of illustration and description, and it is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (20)
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US12/557,139 US7893766B1 (en) | 2009-09-10 | 2009-09-10 | Adaptive common mode bias for differential amplifier input circuits |
KR1020100086664A KR20110027584A (en) | 2009-09-10 | 2010-09-03 | Adaptive common mode bias for differential amplifier input circuits |
JP2010199510A JP5443305B2 (en) | 2009-09-10 | 2010-09-07 | Adaptive common-mode bias for differential amplifier input circuits. |
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275094B1 (en) * | 1999-06-22 | 2001-08-14 | International Business Machines Corporation | CMOS device and circuit and method of operation dynamically controlling threshold voltage |
US6472939B2 (en) * | 1998-12-11 | 2002-10-29 | Micron Technology, Inc. | Low power supply CMOS differential amplifier topology |
US6509795B1 (en) * | 2001-09-26 | 2003-01-21 | Texas Instruments Incorporated | CMOS input stage with wide common-mode range |
US6590980B1 (en) * | 2001-09-24 | 2003-07-08 | Micrel, Incorporated | Low voltage, low power operational amplifier with rail to rail output |
US6642789B2 (en) * | 2002-03-08 | 2003-11-04 | Texas Instruments Incorporated | Operational amplifier input stage and method |
US20060066393A1 (en) * | 2004-09-30 | 2006-03-30 | Bradley Kendall Davis | High-speed, low-power, low-skew, low-voltage differential receiver |
US20070132500A1 (en) * | 2005-12-12 | 2007-06-14 | Sirific Wireless Corporation | System for reducing second order intermodulation products from differential circuits |
US20080191802A1 (en) * | 2004-09-20 | 2008-08-14 | Kinget Peter R | Low Voltage Operational Transconductance Amplifier Circuits |
US7579905B2 (en) * | 2007-03-05 | 2009-08-25 | Intel Corporation | Reduced jitter amplification methods and apparatuses |
US7714653B2 (en) * | 2007-10-01 | 2010-05-11 | Yamaha Corporation | Differential amplifier |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6281753B1 (en) * | 1998-12-18 | 2001-08-28 | Texas Instruments Incorporated | MOSFET single-pair differential amplifier having an adaptive biasing scheme for rail-to-rail input capability |
JP2004343277A (en) * | 2003-05-14 | 2004-12-02 | Mitsubishi Electric Corp | Input buffer circuit |
JP4829650B2 (en) * | 2006-03-15 | 2011-12-07 | 新日本無線株式会社 | Differential amplifier circuit |
-
2009
- 2009-09-10 US US12/557,139 patent/US7893766B1/en not_active Expired - Fee Related
-
2010
- 2010-09-03 KR KR1020100086664A patent/KR20110027584A/en not_active Application Discontinuation
- 2010-09-07 JP JP2010199510A patent/JP5443305B2/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6472939B2 (en) * | 1998-12-11 | 2002-10-29 | Micron Technology, Inc. | Low power supply CMOS differential amplifier topology |
US6275094B1 (en) * | 1999-06-22 | 2001-08-14 | International Business Machines Corporation | CMOS device and circuit and method of operation dynamically controlling threshold voltage |
US6590980B1 (en) * | 2001-09-24 | 2003-07-08 | Micrel, Incorporated | Low voltage, low power operational amplifier with rail to rail output |
US6509795B1 (en) * | 2001-09-26 | 2003-01-21 | Texas Instruments Incorporated | CMOS input stage with wide common-mode range |
US6642789B2 (en) * | 2002-03-08 | 2003-11-04 | Texas Instruments Incorporated | Operational amplifier input stage and method |
US20080191802A1 (en) * | 2004-09-20 | 2008-08-14 | Kinget Peter R | Low Voltage Operational Transconductance Amplifier Circuits |
US20060066393A1 (en) * | 2004-09-30 | 2006-03-30 | Bradley Kendall Davis | High-speed, low-power, low-skew, low-voltage differential receiver |
US20070132500A1 (en) * | 2005-12-12 | 2007-06-14 | Sirific Wireless Corporation | System for reducing second order intermodulation products from differential circuits |
US7579905B2 (en) * | 2007-03-05 | 2009-08-25 | Intel Corporation | Reduced jitter amplification methods and apparatuses |
US7714653B2 (en) * | 2007-10-01 | 2010-05-11 | Yamaha Corporation | Differential amplifier |
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JP5443305B2 (en) | 2014-03-19 |
US7893766B1 (en) | 2011-02-22 |
JP2011061789A (en) | 2011-03-24 |
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