JP4213146B2 - Differential amplifier - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a high-speed operation method of a differential amplifier including a current mirror circuit for passing an output to a load side with a current, for example, a differential amplifier used as a high-speed data transfer driver.

  Differential amplifiers are widely used. FIG. 24 shows a general configuration example of such a differential amplifier. This differential amplifier is a combination of a differential pair having a diode-connected load and a source follower circuit. A current mirror circuit is configured by the combination, and the output of the differential amplifier has a current on the load side. It is in the format passed by.

The circuit of the differential pair and the source follower constituting the differential amplifier is described in the following document.
B. Razavi, translated by Tadahiro Kuroda “Design of Analog CMOS Integrated Circuits”, Basics, p. 83, Maruzen B. Razavi, translated by Tadahiro Kuroda “Design of Analog CMOS Integrated Circuits” Application, p. 394, Maruzen

  In FIG. 24, a transistor 100 and a transistor 101 to which a non-inverting input and an inverting input are respectively applied are connected to the ground by a current source 102 and are connected to a power supply voltage VDD by transistors 103 and 105. The diode-connected transistors 103 and 105 constitute a current mirror circuit with the transistor 104 and the transistor 106, respectively. The transistor 104 and the transistor 106 through which a copy current flows in the current mirror circuit are connected to the load side resistors 107 and 108, respectively. The voltages applied to the resistors 107 and 108 are taken out as output voltages.

  In FIG. 24, when either the input signal VIN + or VIN− becomes H, the voltage of the node 1 or the node 2 starts to drop from the power supply voltage VDD. When the potential of the node 1 or the node 2 falls below the value obtained by subtracting the threshold voltage from the power supply voltage, a current starts to flow through the transistors 103 and 105, and this current flows to the output resistance side by the current mirror circuit to generate an output voltage.

  However, in the circuit of FIG. 24, there is a delay time from when the input signal is turned on, that is, when the input signal is H, until a current flows through the transistor 103 or 105. FIG. 25 is an explanatory diagram of this delay time. In the figure, the voltage of the node 1 or the node 2 starts to decrease from the time when the input signal is turned on, that is, H, but the transistor 103 until the value becomes equal to or less than the value obtained by subtracting the threshold voltage from the power supply voltage as described above. , Or 105, no current flows, so that the current on the copy side of the current mirror, that is, the start of the rise of the current flowing through the transistor 104 or transistor 106 is also delayed by that amount, and the output voltage has a similar delay. become.

  When the differential amplifier is used as a driver circuit for high-speed data transfer, such a delay time becomes a serious problem. In particular, in order to realize a transfer speed of 480 Mbps as in the USB (Universal Serial Bus) 2.0 standard, a delay time of about 100 ps becomes a problem. Furthermore, in order to satisfy the USB 2.0 stress test standard, it is difficult to use a low-breakdown-voltage high-speed transistor, and it is necessary to pass a large current, which increases the transistor size and the load capacity. There is also a problem that the delay time becomes large.

There are the following documents as conventional techniques related to such a differential amplifier.
Japanese Patent Laid-Open No. 10-209844 “Small Amplitude Signal Input Interface Circuit” Japanese Patent Laid-Open No. 11-127042 “Differential Amplifier” Japanese Patent Laid-Open No. 2001-251149 “Amplification Circuit”

  In Patent Document 1, the number of clocked inverters is reduced and the performance is improved in order to improve the operation speed in the normal operation mode other than the IDDQ test mode as a test method of the semiconductor integrated circuit and reduce the circuit area. An interface circuit is disclosed.

  Patent Document 2 discloses a differential amplifier that can reduce the average current consumption in the entire input range by making the output current variable according to the level of the non-inverting input voltage.

  Patent Document 3 discloses an amplifying circuit that has a constant transconductance that does not depend on changes in ambient temperature and variations in process conditions during manufacturing, and can maintain a constant amplification factor and output resistance.

  However, even in these prior arts, the transistors constituting the current mirror circuit in the differential amplifier having the current mirror circuit as shown in FIG. 24 are cut off when the corresponding input voltage is L, and the operation is delayed. The problem could not be solved.

  Further, for example, when a semiconductor device including a differential amplifier is used for USB standard data transfer, and data transfer is started when both of the two input signals VIN + and VIN− to the differential amplifier are in an L state, the operation is performed. There was also a problem that a delay occurred.

  In view of the above problems, the problem of the present invention is to prevent the transistors constituting the current mirror circuit from being cut off when the corresponding input voltage is L or when both of the two input voltages are L. It is to realize high speed operation of the differential amplifier.

  FIG. 1 is a principle configuration diagram of a differential amplifier according to the present invention. This figure shows the principle of the present invention in comparison with the conventional example of FIG. Compared to FIG. 24, the transistor 200 and the current source 10 are connected in series between the node 1 and the ground, and the transistor 201 and the current source 11 are connected in series between the node 2 and the ground. . Here, the two transistors 200 and 201 are transistors that are turned on when the input voltages VIN + and VIN− corresponding to the nodes 1 and 2, respectively, are L and turned off when the voltages are H.

  That is, in the differential amplifier of the present invention, a terminal of a transistor that constitutes a differential amplifier and can serve as an output point of the differential amplifier among the terminals of the transistors to which one of the two inputs to the differential amplifier is provided. Two transistors connected to each other, which are connected to each other and have a terminal that can serve as an output point, are turned on when the input is L, and are turned off when the input is H, and the two transistors and the ground And a current source connected to each other. Here, the current sources are not separate as shown in FIG. 1, and it is naturally possible to use a single current source.

  To describe the principle of the present invention more functionally, the differential amplifier of the present invention includes a transistor to which each one of the aforementioned inputs is provided, and a current mirror circuit for passing the output of the differential amplifier to the load side as a current. Cut-off prevention means for supplying a current that does not cut off the transistor through which the monitor current flows, only when the input corresponding to the transistor to which the monitor current flows and the input corresponding to the transistor to which the monitor current flows and the current mirror circuit is L Is provided.

  In FIG. 1, transistors 200 and 201 are both n-channel transistors, and the two to which an input signal is applied are connected to the gates of transistors 1 and 2 and the gates of transistors 200 and 201 by inverters 202 and 203, respectively. . This is for turning on the two transistors 200 and 201 when the values of the input signals VIN + and VIN− are L. If the transistors 200 and 201 are, for example, p-channel transistors, inverters 202 and 203 are used. Is unnecessary, and the gates of the transistor 1 and the transistor 200 and the gates of the transistor 2 and the transistor 201 are directly connected.

  As described above, according to the present invention, only when the input corresponding to the connection point between the transistor supplied with the input to the differential amplifier and the current mirror circuit for passing the output to the load is L, the current mirror An operation of flowing a current is performed so as not to cut off the transistor through which the monitor current of the circuit flows.

  According to the present invention, for example, in a differential amplifier including a current mirror circuit that delivers an output with a current to the load side, when the two input voltages to the differential amplifier are both L, the input voltage is L The high-speed operation of the differential amplifier can be achieved without cutting off the transistor through which the monitor current flows in the current mirror circuit. Further, by supplying the current for preventing the cut-off only when the input voltage is L, it is possible to reduce the power consumption as compared with the case where the current is supplied even when the input voltage is H.

  The differential amplifier targeted by the present invention is used in a driver circuit for data transfer when performing data transfer using a USB cable, for example. FIG. 2 is an overall configuration diagram of a connection system between a digital camera and a personal computer using such a USB cable. In the figure, a digital camera 15 and a personal computer 16 are connected by a USB cable 17. For example, image data is transferred from the digital camera 15 side to the personal computer 16 by a USB cable 17. A driver circuit for transferring the image data is provided inside the digital camera 15, and a differential amplifier is used as the driver circuit.

  FIG. 3 is an explanatory diagram of an LSI configuration and a data transfer method inside the digital camera of FIG. In the figure, the LSI in the digital camera is constituted by a microprocessor (MPU) 20 that controls the whole, a bus 21, a USB interface 22, a random access memory 23, and a peripheral circuit 24.

  The driver circuit 25 configured by the differential amplifier targeted by the present invention is a part of the USB interface 22, and sends image data, for example, to the personal computer 16 via the USB cable 17 under the control of the MPU 20.

  FIG. 4 is the most basic configuration diagram of the differential amplifier of the present invention. When this figure is compared with the principle configuration diagram of FIG. 1, the two transistors 200 and 201 and the two inverters 202 and 203 are omitted, the current source 10 is directly connected to the node 1, and the current source 11 is directly connected to the node 2. ing.

  That is, in FIG. 4, the current sources 10 and 11 are directly connected between the node 1 and the node 2 and the ground, whereby the input voltages VIN + and VIN− applied to the transistors 1 and 2 constituting the differential amplifier. Regardless of the value, in the current mirror circuit, by always passing a very small current through the transistors 4 and 6 through which the monitor current flows, the cutoff of these transistors can be prevented and the operation of the differential amplifier can be speeded up. It becomes possible.

  As described above, in the principle configuration of FIG. 1, by turning on the transistors 200 and 201 only when the corresponding input is L, the transistor 4 in which the monitor current of the current mirror circuit flows when the input voltage is both L. 6 can be speeded up even when the USB standard data transfer is started, for example, and when the corresponding input is H, a minute current not to cut off is not supplied. As a result, overall power consumption can be suppressed.

  In the following description, first, a current source is directly connected to node 1 and node 2 corresponding to FIG. 4, or a circuit element or the like is connected between node 1 and node 2. An embodiment in which a current for preventing the transistor through which the monitor current of the current mirror circuit flows is always allowed to flow will be described, and an embodiment directly corresponding to FIG. This will be described as ten examples.

  In FIG. 4, transistors 32 and 33 are connected between the transistor 5 through which the current copied in the current mirror circuit flows, and the transistor 7 and the resistors 8 and 9, respectively, and the connection point between the transistor 5 and the transistor 32, In other words, the current source Ie30 is connected to the node 3, and the connection point between the transistor 7 and the transistor 33, that is, the current source Id31 is connected to the node 4 is different. The resistors 8 and 9 have a role of a terminating resistor on the data transmission side in the driver circuit as shown in FIG.

  In FIG. 4, by connecting the current sources Ia10 and Ib11 to the node 1 and the node 2, respectively, even if the input is L, a very small current always flows through the transistors 4 and 6, so that these transistors are not cut off. It has become. However, since this minute current flows through the transistor 4 or the transistor 6, the current that flows through the current mirror circuit, that is, the transistor that flows through the current mirror circuit, that is, the transistor 5 and the transistor 7 also flows. There is a problem that.

  Therefore, by connecting the current sources Ie30 and Id31 to the node 3 and the node 4, respectively, the current flowing through the transistor 5 and the transistor 7 is allowed to flow to the current source side without flowing to the termination resistor 8 or 9. Even if the current flows to the current source side in this way, the voltages at the nodes 3 and 4 are not completely zero, and an output voltage is generated. Therefore, transistors 32 and 33 are inserted, and the gate voltage bias is input. The output voltage can be reduced to 0 by adjusting the potential to be lower than the potential of the node 3 or the node 4 by the threshold voltage so that these transistors are turned off in the state of L. When the input voltage becomes H and a relatively large current flows through the transistor 5 or 6, the potential of the node 3 or the node 4 rises, the Vgs in the transistor 32 or the transistor 33 increases, and the current becomes the termination resistor 8, Or it will flow to 9.

  FIG. 5 is an explanatory diagram of a current change in the basic configuration diagram of FIG. 4, for example. Before the input voltage VIN is turned on, the transistor 4 or the transistor 6 is not cut off even if the current flowing through the current source Ia10 or Ib11 is very small. 1 or the voltage of the node 2 decreases, and the current flowing through the transistor 4 or the transistor 6 increases. Note that the voltage at the node 1 or the node 2 is always lower than the power supply voltage by a threshold voltage or more.

  FIG. 6 is a time chart of input signals and output signals corresponding to the basic circuit of FIG. Compared to the uppermost input signal in the figure, in the conventional circuit as described in FIG. 24, there is a delay of about 100 ps from the time when the input signal rises to the time when the output signal rises. In the circuit of the present invention, the delay is about several ps, and problems such as cross-point shift and duty ratio difference are solved as in the conventional circuit.

  FIG. 7 is a block diagram of the first embodiment of the differential amplifier of the present invention. In the first embodiment, a current bias circuit in which mutual conductance and output resistance as basic physical parameters of a MOSFET can be easily expressed by using a current I is used as a bias circuit, and a current mirror is used to generate a current. For accurate copying, a bias circuit is a cascade type, and a low-voltage current mirror circuit that can lower the lower limit value of the output voltage of the current source circuit is used.

  This low-voltage current mirror circuit includes two reference current sources 37 and 38 and three transistors 39, 40, and 41 for determining bias voltages biasn1 and biasn2, and these bias voltages are two transistors 35, As a whole, the current source Ic12 of FIG.

  Further, the other four current sources in FIG. 4 are constituted by two transistors each having the two bias voltages applied to the gate. The current source Ia10 includes transistors 51 and 52, the current source Ib11 includes transistors 53 and 54, the current source Ie30 includes transistors 46 and 47, and the current source Id31 includes transistors 48 and 49.

  The bias voltage biasp applied to the gates of the transistors 32 and 33 connects the transistors 42 and 43 to which the two bias voltages biasn2 and biasn1 are respectively applied to the gates as shown in the lower right of FIG. By using the two transistors 44 and 45 in between, the transistor 32 or the transistor 33 is determined to be in an off state when the input voltage is L as described above. This determination will be further described later.

  FIG. 8 is a configuration diagram of a second embodiment of the differential amplifier. Comparing this figure with the first embodiment of FIG. 7, instead of the two transistors 51 and 52 and 53 and 54 respectively constituting the two current sources Ia10 and Ib11 of FIG. The difference is that a transistor 56 connecting two output points is provided. In the figure, for example, when the input voltage VIN + to the gate of the transistor 1 is H, a minute current flows through the transistor 6 through the transistor 56. Therefore, the transistor 6 which has been cut off in the circuit of the conventional example is not cut off, and a high-speed response is possible as in the first embodiment of FIG. The transistor 56 may be any element that can pass a minute current, and may be replaced with a resistor, for example.

  Next, determination of the bias voltage in these two embodiments will be further described with reference to FIGS. FIG. 9 is an explanatory diagram of specific current values in the circuit when the bias voltage biasp is determined in the first embodiment of FIG. That is, for example, in the first embodiment of FIG. 7, the value of the bias voltage biasp is determined by adjusting the transistor size of the p-channel transistors 44 and 45 connected in two stages and the current flowing therethrough. It is explanatory drawing of the electric current and voltage value at the time of the adjustment and determination of the transistor size of the transistors 32 and 33 which this bias voltage is given to a gate.

  In FIG. 9, assuming that the current flowing through the transistor 6 when the input voltage VIN− to the gate of the transistor 2 is L is 300 μA, the transistor 7 has a current of 1.8 mA which is six times according to the size ratio of the transistor in the current mirror. Flows. This current basically flows through the current source Id, that is, the transistors 48 and 49.

  At this time, if the connection point between the transistors 7 and 33, that is, the potential of the node 4 is 2.2V, the current starts to flow through the transistor 33 when the potential of the bias is lowered by a threshold voltage (about 0.6V). FIG. 10 is an explanatory diagram of the relationship between this current and the value of bias. Since it is difficult to accurately determine the value of bias when the current of Tr33 actually starts to flow, in this embodiment, the value of bias when the current is 100 μA is obtained by estimation from FIG.

  On the other hand, the connection point between the transistors 5 and 32, that is, the potential of the node 3 is high, and a current flows through the transistor 32 even when the bias is close to VDD. Therefore, as shown in FIG. 11, the size of the transistor 32 is determined so that a desired current (here, 18 mA) flows when the biasp is the estimated value.

Next, for example, determination of the bias voltages biasn1 and biasn2 applied to the gates of two transistors constituting the respective current sources in FIG. For example biasn1 applied to the gate of the transistor 36 has a size of the transistor 41, the value of the current Iref2 flowing therethrough, the following equation using a threshold voltage Vr, and the parameter beta ₁ that is proportional to the channel width and channel length of the transistor 41 Determined by.

次にトランジスタ３５のゲート電圧ｂｉａｓｎ２は、同様にトランジスタ３９のサイズ、およびパラメータβ_２と、電流Ｉｒｅｆ１とから次式によって決定される。

Then the gate voltage biasn2 of the transistor 35 are similarly sized transistor 39, and a parameter beta _2, is determined from the current Iref1 Prefecture by the following equation.

低電圧用カレントミラー回路においては、２つの参照電流の値を同一（Ｉｒｅｆ１＝Ｉｒｅｆ２）、トランジスタ４１とトランジスタ３９のサイズ比を４対１にすることによって、バイアス電圧ｂｉａｓｎ２の値は次式によって決定される。

In the low-voltage current mirror circuit, the values of the two reference currents are the same (Iref1 = Iref2), and the size ratio of the transistors 41 and 39 is set to 4 to 1, whereby the value of the bias voltage biasn2 is determined by the following equation: Is done.

図７、および図８の第１の実施例と第２の実施例では、低電圧用カレントミラー回路を用いることによって、カレントミラーの精度を上げることができ、また出力電圧を低下させてＣＭＯＳアナログ回路が利用できる電圧値範囲を広げることができる実施例について説明したが、本発明の差動増幅器ではこのような低電圧用カレントミラー回路に限定することなく、各種のカレントミラー回路を使用することが可能である。低電圧用カレントミラー回路を含む各種の低電圧用カレントミラー回路の詳細については次の文献に記載されている。
谷口健二 ＣＭＯＳアナログ回路入門−バイアス回路 Ｄｅｓｉｇｎ Ｗａｖｅ Ｍａｇａｚｉｎｅ２００２ Ａｕｇｕｓｔ，ｐ．１５３

In the first and second embodiments of FIG. 7 and FIG. 8, the accuracy of the current mirror can be increased by using the low-voltage current mirror circuit, and the output voltage is lowered to reduce the CMOS analog. Although the embodiment that can expand the voltage value range that can be used by the circuit has been described, the differential amplifier of the present invention is not limited to such a low-voltage current mirror circuit, and various current mirror circuits can be used. Is possible. Details of various low-voltage current mirror circuits including the low-voltage current mirror circuit are described in the following documents.
Kenji Taniguchi Introduction to CMOS Analog Circuit-Bias Circuit Design Wave Magazine 2002 August, p. 153

  FIG. 12 is a configuration diagram of a third embodiment of the differential amplifier using the most basic current mirror circuit. This figure shows a configuration example of a differential amplifier using a basic current mirror circuit composed of a reference current 60 and two transistors 61 and 62. In the third embodiment, the four current sources Ia10, Ib11, Ie30, and Id31 of FIG. 4 are also constituted by one transistor 68, 69, 66, and 67, respectively. A bias voltage biasn1 is applied from the gate of the transistor 61 to the gates of these transistors. Further, this voltage is also applied to the gate of the transistor 63. For example, the bias voltage biasp applied to the gates of the two transistors 32 and 33 is determined by the two-stage connection of the p-channel transistors 64 and 65 as in FIG. .

  In the basic current mirror circuit used in the third embodiment, the accuracy of the current mirror is slightly lowered. In particular, as the miniaturization process proceeds, the slope of the gate current Id vs. drain-source voltage Vds characteristics in the saturation region increases. For example, even if the transistor size ratio of the transistors 61 and 62 is 1: 1, the transistors 61 and 62 When the values of Vds are different, the currents flowing through the transistors 61 and 62 cannot be made equal.

  The performance of such a current source circuit is improved by increasing the output resistance of the current source circuit. A typical method for increasing the output resistance is a cascade circuit. That is, a current source circuit with a large output resistance can be made by combining a circuit for monitoring the reference current and a circuit for generating a copy current together in a cascade structure, that is, a structure in which a plurality of elements are stacked.

  FIG. 13 is a configuration diagram of a fourth embodiment of a differential amplifier using such a cascade current mirror circuit. In this fourth embodiment, the cascade current mirror is composed of a reference current 70, two-stage transistors 71 and 72 for monitoring the reference current, and two-stage transistors 35 and 36 for producing a copy current. The circuit for generating the four current sources Ia10, Ib11, Ie30, Id31 and the bias biasp is the same as that of the first embodiment in FIG. 7, and is denoted by the same reference numeral.

  The cascade current mirror circuit used in the fourth embodiment of FIG. 13 has a problem that the lower limit value of the output voltage of the current source circuit becomes large. That is, this current mirror circuit is composed of four MOSFETs operating in the saturation region, and a current flows between the gate and source of the MOSFET operating in such a saturation characteristic region in addition to the threshold voltage Vr. In addition, it is necessary to apply an overdrive voltage as a voltage to be additionally applied to the gate electrode. In the cascade current mirror circuit, the lower limit value of the output voltage is an addition value of the threshold voltage and twice the overdrive voltage, and the lower limit value of the output voltage is about 0.9V.

  FIG. 14 is a configuration diagram of a fifth embodiment of the differential amplifier using the modified cascade current mirror that can lower the lower limit value of the output voltage to about twice the overdrive voltage. In the figure, the modified cascade current mirror circuit includes two reference currents 75 and 76, two transistors 77 and 78 that monitor these reference currents, and two transistors 35 and 36 that generate a copy current. The other four current sources and the circuit for generating the bias voltage biasp are of the same type as those of the first embodiment of FIG. 7 as in the fourth embodiment of FIG.

  Even in the modified cascade current mirror circuit used in the fifth embodiment, an error occurs because the circuit through which the reference current Iref2 flows is not cascade-connected in the current monitoring circuit. In order to prevent this error, this portion is cascade-connected to the low-voltage current mirror circuit used in the first embodiment of FIG. That is, in the first embodiment and the second embodiment of FIG. 8, the low-voltage current mirror circuit that has high performance as a current mirror and can lower the lower limit of the output voltage is used for differential operation. An amplifier is configured.

  In the third to fifth embodiments, the first embodiment, that is, the embodiment using various current mirror circuits as compared with the case of using two current sources Ia10 and Ib11 as shown in FIG. However, it is of course possible to use various current mirror circuits corresponding to the second embodiment described with reference to FIG.

  Next, another embodiment of the present invention will be described. In the third to fifth embodiments, the first embodiment described with reference to FIG. 7 or the second embodiment described with reference to FIG. 8 has been described. In the present embodiment and the second embodiment, there is a possibility that the influence of fluctuations in the semiconductor manufacturing process may remain.

  As described with reference to FIG. 9, for example, in the first embodiment, VIN + is L and the current is 1.8 mA corresponding to 300 μA flowing through the transistor 4 constituting the current mirror circuit during the period when the transistor 1 is off. Current flows through the transistors 46 and 47 corresponding to the current source Ie30. However, depending on the semiconductor manufacturing process, the current flowing through the transistor 5 constituting the current mirror circuit becomes 1.8 mA + ΔIds. There is a possibility that the current of ΔIds may flow out of the output terminal as a leakage current.

  FIG. 15 is an explanatory diagram of the influence of the semiconductor manufacturing process conditions on the drain-source current Ids vs. drain-source voltage Vds characteristics. In the figure, saturation of the current Ids appears remarkably under the process manufacturing typical (TYP) condition, but under the power (POW) condition where the operation of the transistor becomes fast, the current Ids does not saturate so much and the Ids is fixed at, for example, 1.8 mA. Even if an attempt is made, the current becomes 1.8 mA + ΔIds depending on the value of Vds, and this current ΔIds may flow out as a leakage current from the output terminal.

  Next, in the first embodiment of FIG. 7, for example, when VIN + becomes H and the voltage across the resistor 8 is output as Vout +, first, current flows through the transistors 46 and 47, and the transistors 5 and 32 As a result, the potential of the node 3 that is the connection point of the transistor 32 rises, the drain-source voltage Vds of the transistor 32 is determined accordingly, and the potential of the output Vout + is finally determined. Here, the impedance of the constant current source Ie30 constituted by the transistors 46 and 47 is high, and it takes time until the potential of the node 3 is determined, which causes a problem of jitter of the output voltage Vout +. Further, since the currents of the transistors 46 and 47 vary due to the process variation, the jitter variation due to the process variation is large.

  FIG. 16 is a configuration diagram of a differential amplifier circuit according to a sixth embodiment of the present invention. Comparing this figure with FIG. 7 showing the first embodiment, the current source connected to the nodes 3 and 4 is two transistors 75 and 76 on the node 3 side, and two transistors corresponding to the current source. 81 and 82 and on the node 4 side, two transistors 77 and 78 and transistors 83 and 84 corresponding to current sources are different.

  For example, on the node 3 side, when the input signal VIN + is L and VIN− is H, the transistor 75 is turned on and 76 is turned off. Therefore, when the transistor 1 constituting the differential pair is off, the current flowing through the transistor 4, for example, the current 1.8 mA flowing through the transistor 5 corresponding to 300 μA, is supplied to the transistors 81 and 82 constituting the current source via the transistor 75. Will flow into. By setting the currents of the current sources of the two transistors 81 and 82 to a value larger than 1.8 mA, for example, 2 mA, the leakage current ΔIds can be reduced even if the current flowing through the transistor 5 becomes larger than 1.8 mA due to process variations. Absorption by the current of the current source constituted by the transistors 81 and 82 is possible without flowing to the transistor 32 side.

  The transistors 81 and 82 are supplied with biasn2 and biasn1 as bias voltages, respectively, as in the transistors 46 and 47 in FIG. Although it is assumed that the value is different from 8 mA, for example, 2 mA, for example, it is naturally possible to set the current source current to 2 mA by giving a voltage biasn3 different from the bias voltage for the transistor 47 to the transistor 82, for example. .

  FIG. 17 is a configuration diagram of a seventh embodiment of the differential amplifier. This figure corresponds to the second embodiment of FIG. 8 in which the current source connected to the node 3 and the current source connected to the node 4 are changed in the same manner as in FIG. Since it is basically the same as in the sixth embodiment of FIG. 16, its detailed description is omitted.

  FIG. 18 is a configuration diagram of an eighth embodiment of the differential amplifier of the present invention. In the eighth embodiment, as in the sixth and seventh embodiments, leakage current from the output terminal and variation in jitter due to process variations are prevented, and for example, 2 in the basic configuration diagram of FIG. In this embodiment, for example, an increase in power consumption due to a current of, for example, 300 μA flowing through each of the two current sources Ia10 and Ib11 can be prevented.

  18, the transistor 86 connected to the node 3, the transistor 87 connected to the node 4, and the transistor 88 as a current source to which these two transistors are connected make the two current sources Ie30 and Id31 of FIG. Composed. On the node 3 side, when VIN− is H and VIN + is L, the transistor 86 is turned on, and even if the current flowing through the transistor 5 exceeds 1.8 mA due to process variation, the increase is absorbed by 2 mA flowing through the transistor 88. , Leakage current is prevented from flowing out of the output terminal. At this time, on the node 4 side, the voltage across the resistor 9 is output as Vout−, but the transistor 87 is off, and the current flowing through the current source constituted by the transistor 88 is output by the output voltage Vout−. The current is not affected. The transistors 90 and 91 in FIG. 18 and the transistor 92 constituting the current source of 300 μA correspond to the two current sources Ia10 and Ib11 in FIG. However, the actual current source is only one transistor 92.

  In FIG. 18, when the input signal VIN + is H and VIN− is L, the transistor 90 is turned off and the transistor 91 is turned on, so that a current of 300 μA that should flow through the transistor 6 flows through the transistor 91. On the other hand, when VIN + is L and VIN− is H, the transistor 90 is turned on and 91 is turned off, so that a current of 300 μA that should flow through the transistor 4 flows through the transistor 90. As a result, only the transistor 92 is required as a current source, and power consumption can be reduced. It was found that the current consumption can be reduced by about 2.1 mA when viewed from the power source side.

  As described above, in the sixth to eighth embodiments, output leakage current due to process variation can be eliminated, jitter variation can be reduced, and in the eighth embodiment, it is possible to further reduce power consumption. In FIG. 18, it is naturally possible to use various current mirror circuits similar to those in the first to fifth embodiments for the transistor 93 constituting the current source of 3 mA.

  Further, for example, in the sixth embodiment of FIG. 16, transistors 90 to 92 corresponding to one current source may be used instead of the transistors 51 to 54 corresponding to two current sources. Of course, embodiments using various combinations are possible, such as changing the configuration from No. to 84 to the configuration using the transistors 86 to 88.

  In the above, as described in FIG. 3, for example, the speeding up of the differential amplifier at the time of data transfer using a USB cable has been described. However, the problem cannot be solved by the above embodiments at the start of data transfer. There is. 19 and 20 are explanatory diagrams of this problem.

  FIG. 19 is a time chart of data transfer at the start of transfer in USB 2.0 standard high-speed data transfer. In the USB 2.0 standard, a data plus signal DP and a data minus signal DM are transferred as data signals. During an idle period in which no data transfer is performed, the values of these signals are both L. However, at the start of data transfer, for example, the DM signal first becomes H, and thereafter the L and H sections are repeated. Thus, the DP signal is transferred as a waveform obtained by inverting the DM signal. The data plus signal DP corresponds to the input signal VIN + signal on the differential amplifier side, and the data minus signal DM corresponds to the VIN− signal.

  FIG. 20 is an explanatory diagram of an operation delay on the differential amplifier side. In the figure, the waveforms of the input signals VIN + and VIN− are the same as the data signals DP and DM in FIG. Thus, at the start of data transfer, since the two input signals VIN + and VIN− are both L until then, for example, in FIG. 18, both the transistors 4 and 6 through which the monitor current of the current mirror circuit flows are cut off. For this reason, even if VIN− becomes H at the start of data transfer, the rise of the corresponding output Vout− is delayed by about 100 ps, for example.

  In the eighth embodiment, not only the output voltage is delayed at the start of data transfer, but also the output voltage immediately after the start of transfer becomes unstable. FIG. 21 is an explanatory diagram of this problem. That is, in the eighth embodiment, the potential of the node 5 fluctuates at the start of data transfer, and as a result, the gate potential of the transistor 88, that is, the bias voltage changes. For example, the same bias voltage is used for the transistors 92 and 93. If so, the current flowing through the transistors 88, 92, and 93 constituting the current source changes, and as a result, the output voltage becomes unstable.

  This problem will be further described. In FIG. 18, when the input voltages VIN + and VIN− are both L, the transistors 1, 2, 86, 87, 90, 91 are all off, and no current flows through the transistors 88, 92, 93. On the other hand, a bias voltage is applied to the transistors 88, 92, and 93. These transistors are turned on, and the nodes 5, 6, and 7 are all at a potential close to 0V. Further, no current flows through the transistors 5 and 7, and the nodes 3 and 4 are in a high impedance state.

  Here, when one of the inputs at the start of data transfer, for example, VIN− becomes H, the transistors 86, 90, and 2 are turned on. At this time, the potential of the node 3 is once pulled to the potential of the node 5 by the transistor 86 being turned on and becomes a low value.

  On the other hand, when the transistor 90 is turned on and a minute current of 300 μA flows through the transistor 4, and as a result, a current of 1.8 mA starts flowing through the transistor 5, the potential of the node 3 rises slowly. The current does not flow through the transistor 86 until the potential of the node 3 becomes high, and the potential of the node 5 rises as the current starts to flow through the transistor 86.

  Such a change in the potential of the node 5 changes the gate potential of the transistor 88, that is, the bias voltage biasn via the coupling capacitance between the gate and drain of the transistor 88. If the transistors 92 and 93 use a bias circuit that generates the same bias voltage biasn, the value of the current flowing through the transistors 88, 92, and 93 changes, and as a result, the output voltage Vout− is shown at the bottom of FIG. Thus, a voltage in which triangular noise is superimposed on the H level becomes a voltage instability, which causes a problem at the start of data transfer together with a delay in rising of the output voltage Vout−.

  FIG. 22 is a configuration diagram of the ninth embodiment of the differential amplifier. In this embodiment, as in the eighth embodiment described with reference to FIG. 18, when the corresponding input value is H, the transistor constituting the current mirror circuit has a small current that does not cut off the transistor. In the implementation, the delay of the operation of the differential amplifier at the start of the data transfer described with reference to FIGS. 19 and 20 and the instability of the output voltage described with reference to FIG. 21 can be prevented without reducing power consumption. It is an example.

  When the configuration of the ninth embodiment is compared with that of the eighth embodiment of FIG. 18, the output of the inverter 95 for inverting the input signal VIN + is connected to the gates of the transistors 86 and 90. The difference is that the output of an inverter 96 for inverting the input signal VIN− is connected to the gate.

  In the ninth embodiment of FIG. 22, the first transistor in claim 3 of the present invention is the transistors 5 and 7, the second transistor is the transistors 32 and 33, and the third transistor is This corresponds to the transistors 86 and 87.

  In the ninth embodiment, when the input signals VIN + and VIN− are both L, the transistors 86, 87, 90 and 91 are all turned on, and when VIN + is H and VIN− is L, the transistors 86 and 90 are turned on. Are off and transistors 87 and 91 are on. Further, when VIN + is L and VIN− is H, the transistors 86 and 90 are turned on and the transistors 87 and 91 are turned off.

  As a result, the transistors 90 and 91 are both turned on before the start of data transfer, so that a minute current for preventing these transistors from being cut off flows through the transistors 4 and 6 through which the monitor current of the current mirror circuit flows. The delay of the operation of the differential amplifier at the start of data transfer is prevented, and after the start of the transfer operation, the transistor whose corresponding input becomes H out of the two transistors 90 and 91 is turned off to constitute a current source. It is also possible to reduce current flowing through the transistor 92 and reduce power consumption.

  In the ninth embodiment, the problem described with reference to FIG. 21, that is, in the eighth embodiment of FIG. 18, the transistors 86 and 87 are turned off before the start of data transfer. The problem that the output voltage becomes unstable as a result of being unstable is solved. That is, even when the input voltages VIN + and VIN− are both L, the transistors 86 and 87 are on, and the influence of the potential fluctuation at the node 5 on the bias voltage at the start of data transfer can be reduced. It is possible to prevent the output voltage from becoming unstable.

  FIG. 23 is a block diagram of the tenth embodiment of the differential amplifier. When this embodiment is compared with the ninth embodiment shown in FIG. 22, n-channel transistors 98 and 99 are used instead of the p-channel transistors 32 and 33, and all the transistors except the transistors 4 to 7 constituting the current mirror circuit are n-channel. The difference is that transistors are used. Note that the n-channel transistors 98 and 99 need to be off when the corresponding inputs VIN + and VIN− are L, similarly to the p-channel transistors 32 and 33, and the gate has a bias corresponding to such an operation. It is necessary to supply the voltage biasn4.

  Although the ninth and tenth embodiments of the present invention have been described above, the basic concept in the ninth and tenth embodiments, that is, two inputs VIN + and VIN + are input to the transistor through which the monitor current flows in the current mirror circuit. The concept that a very small current is allowed to flow even when both − are L is, for example, in the first embodiment of FIG. 7, between the connection point between the transistors 1 and 4 and the transistor 51 and between the transistors 2 and 6. By inserting a transistor that is turned on when the input voltages VIN + and VIN− are L respectively between the point and the transistor 53, the present invention can be applied in the same manner as in many other embodiments. In the ninth and tenth embodiments, each current source is constituted by one transistor, and the bias voltage for these transistors can be determined in the same manner as in the third embodiment of FIG. 12, for example. Of course, these current sources can be constituted by two-stage transistors as in the first embodiment.

  Circuits for determining the bias voltage for the transistors constituting these current sources include low voltage current mirror circuits, basic current mirror circuits, cascade current mirror circuits, modified cascade current mirror circuits, etc. Of course, various current mirror circuits can be used.

It is a figure which shows the principle structure of the differential amplifier of this invention. It is a figure which shows the example of the image data transfer system in which the differential amplifier of this invention is used. It is a figure which shows the structure of LSI in the digital camera in FIG. It is a figure which shows the most fundamental structure of the differential amplifier of this invention. FIG. 5 is a diagram showing a waveform of a current flowing through a transistor constituting the differential amplifier of FIG. It is a time chart which shows the relationship between the input signal and output signal in the differential amplifier of this invention. It is a figure which shows the structure of the 1st Example of a differential amplifier. It is a figure which shows the structure of the 2nd Example of a differential amplifier. It is a figure explaining the example of the electric current value at the time of the determination of the bias voltage in a 1st, 2nd Example. It is explanatory drawing of the determination method of bias voltage biasp. It is explanatory drawing of the determination method of transistor size. It is a figure which shows the structure of the 3rd Example of a differential amplifier. It is a figure which shows the structure of the 4th Example of a differential amplifier. It is a figure which shows the structure of the 5th Example of a differential amplifier. It is a figure explaining the leakage current by process variation. It is a figure which shows the structure of the 6th Example of a differential amplifier. It is a figure which shows the structure of the 7th Example of a differential amplifier. It is a figure which shows the structure of the 8th Example of a differential amplifier. It is a time chart of USB data transfer at the time of transfer start. It is explanatory drawing of the operation delay of the differential amplifier at the time of a data transfer start. It is explanatory drawing of the output instability of the differential amplifier at the time of a data transfer start. It is a figure which shows the structure of the 9th Example of a differential amplifier. It is a figure which shows the structure of the 10th Example of a differential amplifier. It is a figure which shows the structure of the prior art example of a differential amplifier. It is explanatory drawing of the current delay in the prior art example of FIG.

Explanation of symbols

1, 2 Transistors to which input voltage is applied 3 Current source Ic
4, 6 Transistors through which current mirror monitor current flows 5, 7 Transistors through which current mirror copy current flows 8, 9 Termination resistor 10 Current source Ia
11 Current source Ib
12 Current source Ic
15 Digital camera 16 Personal computer 17 USB cable 20 MPU
21 Bus 22 USB interface 23 RAM
24 peripheral circuit 25 driver circuit 30 current source Ie
31 Current source Id
200, 201 Transistor 202, 203 Inverter

Claims (8)

Two transistors that constitute a differential amplifier and are connected to each of the terminals that can be the output point of the differential amplifier among the terminals of each transistor to which one of two inputs to the differential amplifier is provided Two transistors that are turned on when the input given to the connected transistor having a terminal that can serve as an output point is L and turned off when the input is H;
A differential amplifier comprising a current source connected between the two transistors and ground.   The differential amplifier according to claim 1, wherein the input is supplied to a gate of each of the transistors, and an inverter is connected between the gate and the gates of the two transistors. In the differential amplifier,
A current mirror circuit for passing the output of the differential amplifier to the load side as a current; each transistor to which one of the inputs is applied is connected to a transistor through which a monitor current flows in the current mirror circuit;
A transistor connected between a first transistor in which a copy current flows in the current mirror circuit and a resistor as a load to which the output is passed, and which is provided with either one of the two inputs A second transistor that is turned off when the input to is L;
A third transistor connected to a connection point between the first transistor and the second transistor and turned on when an input to the transistor to which any one of the two inputs is applied is L;
3. The differential amplifier according to claim 1, further comprising a current source connected between the third transistor and ground. A current source connected between the two transistors and the ground and a current source connected between the third transistor and the ground are constituted by transistors, respectively.
4. The differential amplifier according to claim 3, wherein the transistor and a bias circuit section for applying a bias voltage to the transistor further constitute a current mirror circuit.   5. The differential amplifier according to claim 4, wherein the current mirror circuit is a cascade current mirror circuit in which an output resistance of a current source is large.   5. The differential amplifier according to claim 4, wherein the current mirror circuit is a modified cascade current mirror circuit in which a lower limit of an output voltage of a current source is low.   5. The low-voltage mirror circuit according to claim 4, wherein the current mirror circuit is a low-voltage mirror circuit that uses two reference currents and cascades a transistor through which a copy current flows and a transistor through which one reference current flows. Differential amplifier.   A monitor current of a current mirror circuit that constitutes a differential amplifier and that is supplied with each one of two inputs to the differential amplifier and a current mirror circuit for passing the output of the differential amplifier to the load side flows. A differential comprising: a cutoff prevention means for flowing a current that does not cut off the transistor through which the monitor current flows only when the input to the transistor to which the input is applied is L, connected to a connection point with the transistor amplifier.

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