US20110004718A1 - System, method, and computer program product for ordering a plurality of write commands associated with a storage device - Google Patents
System, method, and computer program product for ordering a plurality of write commands associated with a storage device Download PDFInfo
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- US20110004718A1 US20110004718A1 US12/497,327 US49732709A US2011004718A1 US 20110004718 A1 US20110004718 A1 US 20110004718A1 US 49732709 A US49732709 A US 49732709A US 2011004718 A1 US2011004718 A1 US 2011004718A1
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- storage device
- write commands
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- write
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1097—Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
Definitions
- the present invention relates to storage devices, and more particularly to ordering write commands associated with such storage devices.
- Storage systems may include many devices including storage device and other devices connected to and/or in communication with the storage devices. These devices in communication with the storage devices often need to access commands and/or data associated with the storage devices. In many different types of storage systems, commands are queued and the commands are executed in a random order.
- Serial ATA computer bus is one storage-interface for connecting host bus adapters to storage devices such as hard disk drives and optical drives, etc.
- SATA Serial ATA
- commands are queued and the order that the commands are executed is random.
- a device connected to a SATA drive does not have any knowledge as to the order the write commands will be executed.
- the device attached to a SATA drive may not pre-fetch write data unless it has enough resources to pre-fetch write data for all of the commands.
- Pre-fetching for all commands is very costly because pre-fetching all commands requires the use of a large portion of memory. Additionally, this pre-fetching may not add performance because the command being executed may not necessarily be the command for which data has been pre-fetched. There is thus a need for addressing these and/or other issues associated with the prior art.
- a system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device.
- a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.
- FIG. 1 shows a method for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
- FIG. 2 shows a system for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
- FIG. 3 shows a method for ordering a plurality of write commands associated with a storage device, in accordance with another embodiment.
- FIG. 4 illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.
- FIG. 1 shows a method 100 for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment. As shown, a plurality of write commands associated with a storage device to be sent to a device are identified. See operation 102 .
- a storage device refers to any device capable of storing data.
- the storage device may include, but is not limited to, a Serial ATA (SATA) drive, a Serial Attached SCSI (SAS) drive, a Fibre Channel (FC) drive, or a Universal Serial Bus (USB) drive, and/or any other storage device.
- the storage device may include a Peripheral Component Interconnect (PCI) or PCI Express based plug in card configured to appear as a storage device, or a PCI or PCI Express interface configured to appear as a storage device.
- PCI or PCI Express interface may be used to access the storage device.
- the write commands may be sent to any type of device capable of receiving commands.
- the device may include a host system, an SAS/SATA bridge (e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB to SATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.), a PCI or PCI Express based plug in card (e.g. configured to appear as a storage device, etc.), a PCI or PCI Express interface, an interface used to access at least one storage device or system, or any device capable of having a plurality of commands outstanding at one time.
- an SAS/SATA bridge e.g. an SAS to SATA bridge, etc.
- a USB/SATA bridge e.g. a USB to SATA bridge, etc.
- an FC/SATA bridge e.g. an FC to SATA bridge, etc.
- PCI or PCI Express based plug in card e.g. configured to appear as a
- an order of the plurality of write commands is determined, the determined order being known by the device. See operation 104 .
- the determined order may be a predetermined order known by the device.
- the order may be determined based on an order in which the write commands are identified (e.g. a first come first served based approach, etc.). For example, as commands are generated and/or received, the commands may be queued. As another option, the order may include a predetermined order known by the device.
- the order may include any order known by the device.
- a controller may inform the device of the order.
- the order may be determined by the storage device in real time or near real time.
- the plurality of write commands are ordered in the determined order. See operation 106 .
- the storage device may order the plurality of write commands in the determined order.
- the device may be permitted to pre-fetch data associated with the plurality of write commands.
- the device may be permitted to pre-fetch the data before an associated write command is executed. This may be accomplished because the device knows the order of the write commands.
- read commands associated with the storage device may also be identified.
- the plurality of read commands associated with the storage device may be ordered randomly or in a determined order.
- the read commands may be intermixed with the write commands, where the write commands maintain their determined order relative to one another.
- FIG. 2 shows a system 200 for ordering a plurality of write commands associated with a storage device, in accordance with one embodiment.
- the present system 200 may be implemented to carry out the method 100 of FIG. 2 .
- the system 200 may be implemented in any desired environment. It should also be noted that the aforementioned definitions may apply during the present description.
- the system 200 includes a storage device 202 .
- one or more devices 204 are in communication with and/or connected to the storage device 202 . This communication and/or connection may be accomplished utilizing any type of bus, etc.
- the storage device 202 may represent any number of storage devices.
- the storage device 202 may represent a SATA drive, an SAS drive, an FC drive, a USB drive, a PCI or PCI Express based plug in card configured to appear as a storage device, and/or any other storage device.
- the one or more devices 204 may include any device capable of receiving commands.
- the devices 204 may include an SAS/SATA bridge, a USB/SATA bridge, an FC/SATA bridge, a PCI or PCI Express based plug in card, an expander, and initiator, and/or any other device.
- the storage device 202 may identify write commands associated with the storage device 202 to be sent to one or more of the devices 204 .
- the storage device 202 may then determine an order. In various embodiments, this determination may be made in real time or near real time, or may be a predetermined order.
- the storage device 202 may then order the write commands in a determined order, where the determined order is known by the devices 204 .
- the storage device 202 may order the write commands by placing the write commands in a queue in the order.
- the storage device 202 may order the write commands by assigning an order to the write commands.
- the identifying, determining, and ordering may be performed based on a mode of the storage device 202 .
- a mode may indicate that a particular ordering is to be performed and/or utilized.
- the identifying, determining, and ordering may be performed as a standard function.
- a plurality of read commands associated with the storage device 202 may also be identified.
- the plurality of read commands associated with the storage device 202 may be ordered randomly. Further, the plurality of read commands ordered randomly may be intermixed with the plurality of write commands in the determined order.
- the devices 204 may be permitted to pre-fetch data associated with the write commands.
- the devices 204 may be permitted to pre-fetch the data before an associated write command is executed. This may be accomplished because the devices 204 know the order of the write commands.
- a device e.g. a host/bridge, etc.
- a SATA drive may not know the order of the write commands.
- the drive can not pre-fetch write data unless it has enough resources to pre-fetch write data for all the commands.
- pre-fetching for all commands may be very costly since this costs a large portion of memory.
- a hard disk drive may reorder the commands to reduce the number of rotations of the media needed to fetch all the data.
- a solid-state drive (SSD) may reorder the commands based on the internal architectures to optimize for the drive.
- the host/bridge attached to the drive that needs to fetch write data may be a bottle neck.
- the drive may order the commands in a deterministic fashion which is known by the host and/or bridge. In one embodiment, this may be implemented as a first come first served approach. Thus, the host will know the order of the write commands and it may pre-fetch write data before the command is executed. In various embodiments, the drive may always perform this ordering, or the ordering may be based on a mode. As an option, there may be more than one mode.
- ordering may be implemented for any protocol or mode within a protocol that does not have a deterministic technique of ordering the commands relative to one another. It should be noted that the order of the read commands may or may not be deterministic relative to the order of the write commands.
- a memory controller e.g. an SSD controller, etc. may pass information about the order of write commands to the device attached to the drive to allow for efficient pre-fetching.
- FIG. 3 shows a method 300 for ordering a plurality of write commands associated with a storage device, in accordance with another embodiment.
- the present method 300 may be implemented in the context of the functionality and architecture of FIGS. 1-2 .
- the method 300 may be carried out in any desired environment. Again, the aforementioned definitions may apply during the present description.
- a command is identified. See operation 302 . If a command is identified, it is determined whether the command is a read command. See operation 304 .
- the read command is queued in a random order. See operation 306 . If the command is not a read command, it is determined if the command is a write command. See operation 308 .
- the command is queued in an order known to a receiving device. See operation 310 .
- the write command may be queued in an order and then the receiving device may be informed as to the order.
- the write command may be queued in a predetermined order already known by the receiving device.
- a SATA drive may execute write commands in the same order that a host, bridge, or attached device sends the commands.
- the host, bridge, or attached device may then pre-fetch data based on knowing the order the write commands will be executed. Thus, all available write data storage may be used for the next data.
- an SSD controller may pass information about the order of write commands to the device attached to allow for efficient pre-fetching.
- FIG. 4 illustrates an exemplary system 400 in which the various architecture and/or functionality of the various previous embodiments may be implemented.
- a system 400 is provided including at least one host processor 401 which is connected to a communication bus 402 .
- the system 400 also includes a main memory 404 .
- Control logic (software) and data are stored in the main memory 404 which may take the form of random access memory (RAM).
- RAM random access memory
- the system 400 also includes a graphics processor 406 and a display 408 , i.e. a computer monitor.
- the graphics processor 406 may include a plurality of shader modules, a rasterization module, etc. Each of the foregoing modules may even be situated on a single semiconductor platform to form a graphics processing unit (GPU).
- GPU graphics processing unit
- a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (CPU) and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.
- CPU central processing unit
- the system 400 may also include a secondary storage 410 .
- the secondary storage 410 includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, etc.
- the removable storage drive reads from and/or writes to a removable storage unit in a well known manner.
- Computer programs, or computer control logic algorithms may be stored in the main memory 404 and/or the secondary storage 410 . Such computer programs, when executed, enable the system 400 to perform various functions. Memory 404 , storage 410 and/or any other storage are possible examples of computer-readable media.
- the architecture and/or functionality of the various previous figures may be implemented in the context of the host processor graphics processor 406 , an integrated circuit (not shown) that is capable of at least a portion of the capabilities of both the host processor 401 and the graphics processor 406 , a chipset (i.e. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.), and/or any other integrated circuit for that matter.
- an integrated circuit not shown
- a chipset i.e. a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.
- the architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system.
- the system 400 may take the form of a desktop computer, lap-top computer, and/or any other type of logic.
- the system 400 may take the form of various other devices including, but not limited to, a personal digital assistant (PDA) device, a mobile phone device, a television, etc.
- PDA personal digital assistant
- system 400 may be coupled to a network [e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.] for communication purposes.
- a network e.g. a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, etc.
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Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/497,327 US20110004718A1 (en) | 2009-07-02 | 2009-07-02 | System, method, and computer program product for ordering a plurality of write commands associated with a storage device |
| TW99121910A TWI470436B (zh) | 2009-07-02 | 2010-07-02 | 用於排序關聯於儲存裝置之複數個寫入命令之系統、方法、及電腦程式產品 |
| CN201080030032.6A CN102473087B (zh) | 2009-07-02 | 2010-07-02 | 对与存储装置关联的多个写命令进行排序 |
| JP2012519610A JP5957634B2 (ja) | 2009-07-02 | 2010-07-02 | ストレージデバイスに関連付けられた複数の書き込みコマンドの順序付け |
| KR1020167011543A KR101718128B1 (ko) | 2009-07-02 | 2010-07-02 | 스토리지 디바이스와 연관된 복수의 기록 커맨드들의 오더링 |
| KR1020127002875A KR101712504B1 (ko) | 2009-07-02 | 2010-07-02 | 스토리지 디바이스와 연관된 복수의 기록 커맨드들의 오더링 |
| US13/379,607 US8930606B2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
| PCT/US2010/040855 WO2011003050A2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
| US14/576,078 US9582195B2 (en) | 2009-07-02 | 2014-12-18 | Ordering a plurality of write commands associated with a storage device |
| US15/409,190 US10019200B2 (en) | 2009-07-02 | 2017-01-18 | Ordering a plurality of write commands associated with a storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/497,327 US20110004718A1 (en) | 2009-07-02 | 2009-07-02 | System, method, and computer program product for ordering a plurality of write commands associated with a storage device |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2010/040855 Continuation-In-Part WO2011003050A2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
| US13/379,607 Continuation-In-Part US8930606B2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
| US13/379,607 Continuation US8930606B2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20110004718A1 true US20110004718A1 (en) | 2011-01-06 |
Family
ID=43411771
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/497,327 Abandoned US20110004718A1 (en) | 2009-07-02 | 2009-07-02 | System, method, and computer program product for ordering a plurality of write commands associated with a storage device |
| US13/379,607 Active 2030-03-18 US8930606B2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
| US14/576,078 Active 2029-12-15 US9582195B2 (en) | 2009-07-02 | 2014-12-18 | Ordering a plurality of write commands associated with a storage device |
| US15/409,190 Active US10019200B2 (en) | 2009-07-02 | 2017-01-18 | Ordering a plurality of write commands associated with a storage device |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US13/379,607 Active 2030-03-18 US8930606B2 (en) | 2009-07-02 | 2010-07-02 | Ordering a plurality of write commands associated with a storage device |
| US14/576,078 Active 2029-12-15 US9582195B2 (en) | 2009-07-02 | 2014-12-18 | Ordering a plurality of write commands associated with a storage device |
| US15/409,190 Active US10019200B2 (en) | 2009-07-02 | 2017-01-18 | Ordering a plurality of write commands associated with a storage device |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US20110004718A1 (enExample) |
| JP (1) | JP5957634B2 (enExample) |
| KR (2) | KR101718128B1 (enExample) |
| CN (1) | CN102473087B (enExample) |
| TW (1) | TWI470436B (enExample) |
| WO (1) | WO2011003050A2 (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100251009A1 (en) * | 2009-03-27 | 2010-09-30 | Ross John Stenfort | System, method, and computer program product for converting logical block address de-allocation information in a first format to a second format |
| US20100250830A1 (en) * | 2009-03-27 | 2010-09-30 | Ross John Stenfort | System, method, and computer program product for hardening data stored on a solid state disk |
| US8930606B2 (en) | 2009-07-02 | 2015-01-06 | Lsi Corporation | Ordering a plurality of write commands associated with a storage device |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8671258B2 (en) | 2009-03-27 | 2014-03-11 | Lsi Corporation | Storage system logical block address de-allocation management |
| US9792074B2 (en) | 2009-07-06 | 2017-10-17 | Seagate Technology Llc | System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips |
| JP5920496B2 (ja) | 2014-02-18 | 2016-05-18 | 住友化学株式会社 | 積層多孔質フィルムおよび非水電解液二次電池 |
| WO2017131724A1 (en) * | 2016-01-29 | 2017-08-03 | Hewlett Packard Enterprise Development Lp | Host devices and non-volatile memory subsystem controllers |
| CN106339326A (zh) * | 2016-08-26 | 2017-01-18 | 记忆科技(深圳)有限公司 | 一种提升固态硬盘顺序读性能的方法 |
| US10466904B2 (en) * | 2017-03-24 | 2019-11-05 | Western Digital Technologies, Inc. | System and method for processing and arbitrating submission and completion queues |
| KR102549545B1 (ko) | 2018-03-22 | 2023-06-29 | 삼성전자주식회사 | 스토리지 장치 및 스토리지 장치의 동작 방법 |
| CN114995882B (zh) * | 2022-07-19 | 2022-11-04 | 沐曦集成电路(上海)有限公司 | 一种异构结构系统包处理的方法 |
| TWI822386B (zh) | 2022-10-11 | 2023-11-11 | 慧榮科技股份有限公司 | 橋接控制晶片與相關的訊號處理方法 |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2012532397A (ja) | 2012-12-13 |
| WO2011003050A2 (en) | 2011-01-06 |
| US20170123734A1 (en) | 2017-05-04 |
| US8930606B2 (en) | 2015-01-06 |
| KR101712504B1 (ko) | 2017-03-06 |
| US20120102287A1 (en) | 2012-04-26 |
| US10019200B2 (en) | 2018-07-10 |
| WO2011003050A3 (en) | 2011-04-07 |
| TWI470436B (zh) | 2015-01-21 |
| CN102473087B (zh) | 2018-08-21 |
| US20150106546A1 (en) | 2015-04-16 |
| KR101718128B1 (ko) | 2017-03-20 |
| KR20120103555A (ko) | 2012-09-19 |
| KR20160054628A (ko) | 2016-05-16 |
| JP5957634B2 (ja) | 2016-08-10 |
| TW201115352A (en) | 2011-05-01 |
| CN102473087A (zh) | 2012-05-23 |
| US9582195B2 (en) | 2017-02-28 |
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