US20100309341A1 - Black Level Compensation Circuit - Google Patents
Black Level Compensation Circuit Download PDFInfo
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- US20100309341A1 US20100309341A1 US12/477,899 US47789909A US2010309341A1 US 20100309341 A1 US20100309341 A1 US 20100309341A1 US 47789909 A US47789909 A US 47789909A US 2010309341 A1 US2010309341 A1 US 2010309341A1
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- amplifier
- blc
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- output
- compensation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/68—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
Definitions
- the present invention generally relates to black level compensation (BLC) for an image sensor, and more particularly to an analog BLC circuit for an image sensor.
- BLC black level compensation
- CCDs charge-coupled devices
- CMOS complementary metal-oxide-semiconductor
- signals optical black signals
- PGA programmable gain amplifier
- FIG. 1 shows a conventional black level compensation (BLC) system, which includes a digital loop made of an analog-to-digital converter (ADC) 1 , a digital circuit 2 and a digital-to-analog converter (DAC) 3 .
- ADC analog-to-digital converter
- DAC digital-to-analog converter
- compensation for optical black signals of the image sensor begins with the ADC 1 receiving optical black signals from the PGA 4 , and accordingly outputting their digital equivalents.
- the digitized optical black signals are then compared and averaged by the digital circuit 2 to generate an averaged signal.
- the averaged signal is then converted back to its analog equivalent, which is then used to compensate the PGA 4 .
- the ADC 1 and the digital circuit 2 incur latency, and the DAC 3 is subject to quantization errors, thus attenuating the speed and accuracy of the conventional BLC system.
- an object of the present invention is to provide an analog black level compensation (BLC) circuit for quickly and accurately performing BLC. It is another object of the present invention to substantially save chip area and power consumption.
- BLC black level compensation
- the BLC circuit includes a switched-capacitor (SC) integrator configured to compensate (e.g., with a compensation voltage) a readout amplifier of an image sensor.
- the SC integrator includes a compensation amplifier (e.g., a differential amplifier), a feedback capacitor, an input capacitor and a plurality of phase-1/phase-2 switches.
- the input of the compensation amplifier is connected to an output of the readout amplifier.
- the feedback capacitor is connected between an input and an output of the compensation amplifier, and the input capacitor is controllably connected between an input of the BLC circuit and the input of the compensation amplifier.
- the phase-1/phase-2 switches are configured in a manner such that charge difference due to a reference voltage and due to the output of the readout amplifier is integrated.
- Another output of the compensation amplifier provides the compensation voltage to compensate the readout amplifier. As a result, the output of the readout amplifier is clamped to the reference voltage at which a black level of the image sensor is defined.
- a bad pixel detector is used to detect a bad (or hot) pixel or pixels of optically black pixels, which are being or have been read.
- the detected bad pixels are blocked from being integrated into/by the SC integrator.
- FIG. 1 shows a conventional black level compensation (BLC) system
- FIG. 2 shows a BLC circuit coupled to a readout amplifier according to a first embodiment of the present invention
- FIG. 3 shows a timing diagram illustrating non-overlapping phase signals P 1 and P 2 ;
- FIG. 4 shows a BLC circuit according to a second embodiment of the present invention
- FIG. 5 shows a modified version of the second embodiment depicted in FIG. 4 ;
- FIG. 6 shows another modified version of the second embodiment depicted in FIG. 4 ;
- FIG. 7 shows an exemplary bad pixel detector according to an aspect of the present invention.
- FIG. 2 shows a black level compensation (BLC) circuit, which is configured as a switched-capacitor (SC) integrator 10 and which is coupled to a readout amplifier according to a first embodiment of the present invention.
- the BLC circuit 10 is used to compensate the readout amplifier, which comprises, for example, a programmable gain amplifier (PGA) 12 that amplifies signals obtained from an image sensor (not shown).
- PGA programmable gain amplifier
- ADC analog-to-digital converter
- the output OUTP of the PGA 12 is connected to the input of the BLC circuit 10 , and the (positive) output DACN of the BLC circuit 10 is controllably connected to charge a feedback capacitor CF 1 or an input capacitor CS 1 of the PGA 12 , thereby forming a BLC loop, which is an analog loop rather than the digital loop used by the conventional BLC system ( FIG. 1 ).
- the SC integrator 10 includes a compensation amplifier (e.g., a fully differential amplifier, which is referred to not by way of limitation as a compensation amplifier) A 2 , a feedback capacitor CF 2 , an input capacitor CS 2 , and phase 1/phase 2 switches P 1 /P 2 .
- the feedback capacitor CF 2 is connected between the positive input and the negative output of the compensation amplifier A 2 .
- the input capacitor CS 2 is connected, via switches P 1 /P 2 , between the input of the BLC circuit 10 and the positive input of the compensation amplifier A 2 .
- the positive output of the compensation amplifier A 2 provides the compensation voltage DACN to the PGA 12 .
- FIG. 3 is a timing diagram illustrating non-overlapping phase signals P 1 /P 2 and signals from the implementation of FIG. 2 .
- the first phase P 1 charge is stored on the input capacitor CS 2 due to the negative reference voltage REFN, which is the zero level of the ADC 14 at which a black level of the image sensor is defined.
- REFN negative reference voltage
- the second phase P 2 charge is stored on the input capacitor CS 2 due to the output voltage OUTP of the PGA 12 .
- the charge difference due to REFN and OUTP is then transferred to the feedback capacitor CF 2 , or, in other words, the difference between OUTP and REFN is integrated by the SC integrator 10 .
- the output voltage OUTP of the PGA 12 is clamped to the negative reference voltage REFN, thus completing the BLC. It is appreciated that, in another embodiment, the output voltage OUTP of the PGA 12 may be clamped to a non-zero defined black level. For example, the output voltage OUTP of the PGA 12 may be clamped to the 90% REFN if the optical black level is defined at the level of the ADC 14 .
- the capacitance of the feedback capacitor CF 2 is designed to be substantially the same as the capacitance of the input capacitor CS 2 , such that the BLC loop can settle fast (usually in only a few clock cycles) while reading optical black signals (corresponding to optically black or light-shielded pixels) with the closing of switch ACT of the SC integrator 10 .
- the capacitance of the feedback capacitor CF 2 substantially increases ( FIG. 3 ) by controllably coupling another capacitor (CF 2 increase) in parallel with CF 2 .
- the increased feedback capacitance makes the BLC circuit 10 more resistant to bad (unwanted or hot) pixels. Accordingly, an accurate and high-speed BLC circuit 10 can be attained.
- the switch ACT is then opened after completion of the BLC.
- the switch ACT may be opened when one or more bad pixels are detected, thereby eliminating any adverse effects which may be caused by the bad pixels.
- the embodiment of the present invention utilizes an analog feedback loop to realize BLC, and therefore the digital circuit 2 ( FIG. 1 ) and the DAC 3 ( FIG. 1 ) are no longer needed, thereby eliminating the incurred latency and quantization error. Furthermore, substantial chip area and associated power consumption are saved.
- FIG. 4 shows a BLC circuit 10 A/ 10 B according to a second embodiment of the present invention.
- a multi-stage (for example, two-stage) PGA 12 A/ 12 B is applied.
- the BLC circuit 10 A is used to clamp the output of the PGA 12 A
- the BLC circuit 10 B is used to clamp the output of the PGA 12 B.
- only the final PGA stage is clamped while other stage or stages are ignored.
- the output voltage OUTP 3 of the second-stage PGA 12 B is clamped to the negative reference voltage REFN
- the target clamp voltage of each stage is scaled down with the ratio of the gain in the following PGA. For example, as shown in FIG. 4 , the PGA gain A 3 in the second stage is equal to CS 3 /CF 3 , and the target clamp voltage of the first stage is thus equal to REFN/A 3 .
- the phase switches P 1 /P 2 are alternated between the neighboring stages.
- the neighboring stages may accordingly share one amplifier.
- this embodiment can be a modified version of the second embodiment ( FIG. 4 ), thereby saving more chip area than that of FIG. 4 .
- the compensation amplifier A 2 is configured to be connected to the first-stage BLC circuit 10 A during the first phase P 1
- the same compensation amplifier A 2 is configured to be connected to the second-stage BLC circuit 10 B during the second phase P 2
- the compensation amplifier Al is connected to the second-stage PGA 12 B during the first phase P 1
- the same compensation amplifier A 1 is connected to the first-stage PGA 12 A during the second phase P 2 .
- FIG. 6 shows another modified version of the second embodiment ( FIG. 4 ).
- two-stage PGA is applied, while only one stage of BLC circuit 10 B is used, thereby saving more chip area and associated power consumption than that in FIG. 4 .
- the single-stage BLC circuit 10 B is arranged in an inverting configuration, in which the negative output DACN of the single-stage BLC circuit 10 B is connected to compensate the first-stage PGA 12 A, while the output OUTP 3 of the second-stage PGA 12 B is connected to the input of the single-stage BLC circuit 10 .
- FIG. 7 shows an exemplary bad pixel detector according to one aspect of the present invention.
- An inverter CMP 1 and a capacitor C 1 serve as a comparator to compare the output OUTP level of the PGA 12 (e.g., in FIG. 2 ) with a defined bad-pixel reference BAD_REFP.
- the comparator's output Pixel_OK becomes “0” and the detector output ACT becomes “0,” which is then used to bypass the bad-pixel information.
- the detector as disclosed may be modified or substituted by other circuits having equivalent function.
Abstract
Description
- 1. Field of the Invention
- The present invention generally relates to black level compensation (BLC) for an image sensor, and more particularly to an analog BLC circuit for an image sensor.
- 2. Description of the Prior Art
- Semiconductor based image sensors such as charge-coupled devices (CCDs) or complementary metal-oxide-semiconductor (CMOS) sensors are widely used, for example, in cameras and camcorders, to convert images of visible light into electronic signals that can be stored, transmitted or displayed.
- Due to imperfections in electronic circuitry, leakage current exists even when no light is received by the image sensor. In order to overcome this problem, signals (optical black signals) from rows of optically black (or light-shielded) pixels are read from a programmable gain amplifier (PGA) and then averaged as a base reference for the black color to facilitate compensation of the optical black signals. This base reference, however, may vary due to different gain settings in the PGA.
-
FIG. 1 shows a conventional black level compensation (BLC) system, which includes a digital loop made of an analog-to-digital converter (ADC) 1, adigital circuit 2 and a digital-to-analog converter (DAC) 3. Specifically, compensation for optical black signals of the image sensor begins with theADC 1 receiving optical black signals from thePGA 4, and accordingly outputting their digital equivalents. The digitized optical black signals are then compared and averaged by thedigital circuit 2 to generate an averaged signal. The averaged signal is then converted back to its analog equivalent, which is then used to compensate thePGA 4. TheADC 1 and thedigital circuit 2 incur latency, and theDAC 3 is subject to quantization errors, thus attenuating the speed and accuracy of the conventional BLC system. - For the reason that a conventional BLC system, particularly a digital-loop BLC such as described above, cannot speedily and accurately compensate the black level for the image sensor, a need has arisen to propose a novel scheme for rapidly and accurately performing BLC.
- In view of the foregoing, an object of the present invention is to provide an analog black level compensation (BLC) circuit for quickly and accurately performing BLC. It is another object of the present invention to substantially save chip area and power consumption.
- According to one embodiment, the BLC circuit includes a switched-capacitor (SC) integrator configured to compensate (e.g., with a compensation voltage) a readout amplifier of an image sensor. The SC integrator includes a compensation amplifier (e.g., a differential amplifier), a feedback capacitor, an input capacitor and a plurality of phase-1/phase-2 switches.
- Specifically, the input of the compensation amplifier is connected to an output of the readout amplifier. The feedback capacitor is connected between an input and an output of the compensation amplifier, and the input capacitor is controllably connected between an input of the BLC circuit and the input of the compensation amplifier. The phase-1/phase-2 switches are configured in a manner such that charge difference due to a reference voltage and due to the output of the readout amplifier is integrated. Another output of the compensation amplifier provides the compensation voltage to compensate the readout amplifier. As a result, the output of the readout amplifier is clamped to the reference voltage at which a black level of the image sensor is defined.
- According to an aspect of the present invention a bad pixel detector is used to detect a bad (or hot) pixel or pixels of optically black pixels, which are being or have been read. The detected bad pixels are blocked from being integrated into/by the SC integrator.
-
FIG. 1 shows a conventional black level compensation (BLC) system; -
FIG. 2 shows a BLC circuit coupled to a readout amplifier according to a first embodiment of the present invention; -
FIG. 3 shows a timing diagram illustrating non-overlapping phase signals P1 and P2; -
FIG. 4 shows a BLC circuit according to a second embodiment of the present invention; -
FIG. 5 shows a modified version of the second embodiment depicted inFIG. 4 ; -
FIG. 6 shows another modified version of the second embodiment depicted inFIG. 4 ; and -
FIG. 7 shows an exemplary bad pixel detector according to an aspect of the present invention. -
FIG. 2 shows a black level compensation (BLC) circuit, which is configured as a switched-capacitor (SC)integrator 10 and which is coupled to a readout amplifier according to a first embodiment of the present invention. TheBLC circuit 10 is used to compensate the readout amplifier, which comprises, for example, a programmable gain amplifier (PGA) 12 that amplifies signals obtained from an image sensor (not shown). An (open-loop) analog-to-digital converter (ADC) 14 receives the output of thePGA 12. In the embodiment, the output OUTP of thePGA 12 is connected to the input of theBLC circuit 10, and the (positive) output DACN of theBLC circuit 10 is controllably connected to charge a feedback capacitor CF1 or an input capacitor CS1 of thePGA 12, thereby forming a BLC loop, which is an analog loop rather than the digital loop used by the conventional BLC system (FIG. 1 ). - In the embodiment, the
SC integrator 10 includes a compensation amplifier (e.g., a fully differential amplifier, which is referred to not by way of limitation as a compensation amplifier) A2, a feedback capacitor CF2, an input capacitor CS2, andphase 1/phase 2 switches P1/P2. The feedback capacitor CF2 is connected between the positive input and the negative output of the compensation amplifier A2. The input capacitor CS2 is connected, via switches P1/P2, between the input of theBLC circuit 10 and the positive input of the compensation amplifier A2. The positive output of the compensation amplifier A2 provides the compensation voltage DACN to thePGA 12. -
FIG. 3 is a timing diagram illustrating non-overlapping phase signals P1/P2 and signals from the implementation ofFIG. 2 . During the first phase P1, charge is stored on the input capacitor CS2 due to the negative reference voltage REFN, which is the zero level of theADC 14 at which a black level of the image sensor is defined. During the second phase P2, charge is stored on the input capacitor CS2 due to the output voltage OUTP of thePGA 12. The charge difference due to REFN and OUTP is then transferred to the feedback capacitor CF2, or, in other words, the difference between OUTP and REFN is integrated by theSC integrator 10. As a result, the output voltage OUTP of thePGA 12 is clamped to the negative reference voltage REFN, thus completing the BLC. It is appreciated that, in another embodiment, the output voltage OUTP of thePGA 12 may be clamped to a non-zero defined black level. For example, the output voltage OUTP of thePGA 12 may be clamped to the 90% REFN if the optical black level is defined at the level of theADC 14. - In practice, the capacitance of the feedback capacitor CF2 is designed to be substantially the same as the capacitance of the input capacitor CS2, such that the BLC loop can settle fast (usually in only a few clock cycles) while reading optical black signals (corresponding to optically black or light-shielded pixels) with the closing of switch ACT of the
SC integrator 10. Subsequently, the capacitance of the feedback capacitor CF2 substantially increases (FIG. 3 ) by controllably coupling another capacitor (CF2 increase) in parallel with CF2. The increased feedback capacitance makes theBLC circuit 10 more resistant to bad (unwanted or hot) pixels. Accordingly, an accurate and high-speed BLC circuit 10 can be attained. The switch ACT is then opened after completion of the BLC. The switch ACT may be opened when one or more bad pixels are detected, thereby eliminating any adverse effects which may be caused by the bad pixels. - Compared to the conventional BLC system of
FIG. 1 , the embodiment of the present invention utilizes an analog feedback loop to realize BLC, and therefore the digital circuit 2 (FIG. 1 ) and the DAC 3 (FIG. 1 ) are no longer needed, thereby eliminating the incurred latency and quantization error. Furthermore, substantial chip area and associated power consumption are saved. -
FIG. 4 shows aBLC circuit 10A/10B according to a second embodiment of the present invention. In the embodiment, a multi-stage (for example, two-stage)PGA 12A/12B is applied. There is one BLC circuit corresponding to each PGA stage. For example, in one exemplary embodiment, theBLC circuit 10A is used to clamp the output of thePGA 12A, and theBLC circuit 10B is used to clamp the output of thePGA 12B. In another exemplary embodiment, however, only the final PGA stage is clamped while other stage or stages are ignored. - In the second embodiment (
FIG. 4 ), the output voltage OUTP3 of the second-stage PGA 12B is clamped to the negative reference voltage REFN, and the output voltage OUTP of the first-stage PGA 12A is clamped to the voltage REFN/A3 (where A3=CS3/CF3). Generally speaking, the target clamp voltage of each stage is scaled down with the ratio of the gain in the following PGA. For example, as shown inFIG. 4 , the PGA gain A3 in the second stage is equal to CS3/CF3, and the target clamp voltage of the first stage is thus equal to REFN/A3. - It is noted that, in the multi-stage embodiment of
FIG. 4 , the phase switches P1/P2 are alternated between the neighboring stages. As each amplifier (A2 or A4) works only half of the time, the neighboring stages may accordingly share one amplifier. As shown inFIG. 5 , this embodiment can be a modified version of the second embodiment (FIG. 4 ), thereby saving more chip area than that ofFIG. 4 . According to theFIG. 5 , the compensation amplifier A2 is configured to be connected to the first-stage BLC circuit 10A during the first phase P1, and the same compensation amplifier A2 is configured to be connected to the second-stage BLC circuit 10B during the second phase P2. Similarly, for thePGA 12A/12B, the compensation amplifier Al is connected to the second-stage PGA 12B during the first phase P1, and the same compensation amplifier A1 is connected to the first-stage PGA 12A during the second phase P2. -
FIG. 6 shows another modified version of the second embodiment (FIG. 4 ). In this modified embodiment, two-stage PGA is applied, while only one stage ofBLC circuit 10B is used, thereby saving more chip area and associated power consumption than that inFIG. 4 . The single-stage BLC circuit 10B is arranged in an inverting configuration, in which the negative output DACN of the single-stage BLC circuit 10B is connected to compensate the first-stage PGA 12A, while the output OUTP3 of the second-stage PGA 12B is connected to the input of the single-stage BLC circuit 10. - During integration of the optical black signals, a number of bad-pixel signals may occur due to non-ideal manufacturing. Therefore a bad pixel detector may be applied to control the switch ACT in the BLC circuit to bypass this bad pixel information by disconnecting the BLC loop.
FIG. 7 shows an exemplary bad pixel detector according to one aspect of the present invention. An inverter CMP1 and a capacitor C1 serve as a comparator to compare the output OUTP level of the PGA 12 (e.g., inFIG. 2 ) with a defined bad-pixel reference BAD_REFP. When the output OUTP is greater than the bad pixel reference BAD_REFP, the comparator's output Pixel_OK becomes “0” and the detector output ACT becomes “0,” which is then used to bypass the bad-pixel information. The detector as disclosed may be modified or substituted by other circuits having equivalent function. - Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.
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US12/477,899 US8130290B2 (en) | 2009-06-03 | 2009-06-03 | Black level compensation circuit |
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Cited By (2)
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US20130271628A1 (en) * | 2012-04-17 | 2013-10-17 | Skybox Imaging, Inc. | Sensor dark pixel offset estimation |
TWI422224B (en) * | 2011-05-13 | 2014-01-01 | Himax Imaging Inc | Black level compensation circuit, image sensor and associated method |
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