US20100045113A1 - Power source device and magnetic resonance imaging apparatus using the same - Google Patents
Power source device and magnetic resonance imaging apparatus using the same Download PDFInfo
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- US20100045113A1 US20100045113A1 US11/993,818 US99381806A US2010045113A1 US 20100045113 A1 US20100045113 A1 US 20100045113A1 US 99381806 A US99381806 A US 99381806A US 2010045113 A1 US2010045113 A1 US 2010045113A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
- G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
- G01R33/32—Excitation or detection systems, e.g. using radio frequency signals
- G01R33/36—Electrical details, e.g. matching or coupling of the coil to the receiver
- G01R33/3614—RF power amplifiers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
- G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
- G01R33/38—Systems for generation, homogenisation or stabilisation of the main or gradient magnetic field
- G01R33/383—Systems for generation, homogenisation or stabilisation of the main or gradient magnetic field using permanent magnets
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
- G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
- G01R33/38—Systems for generation, homogenisation or stabilisation of the main or gradient magnetic field
- G01R33/385—Systems for generation, homogenisation or stabilisation of the main or gradient magnetic field using gradient magnetic field coils
- G01R33/3852—Gradient amplifiers; means for controlling the application of a gradient magnetic field to the sample, e.g. a gradient signal synthesizer
Definitions
- FIG. 3 is a diagram for explaining an operation of the phase shift inverter circuit as shown in FIG. 2 according to a first control method
- the negative current component in the current Ie of the semiconductor switch 7 f and in the current If of the semiconductor switch 7 f as shown in FIG. 3 is the current flowing through the diodes 7 g and 7 h connected respectively in antiparallel to the semiconductor switches 7 e and 7 f and only positive current flows through the semiconductor switches 7 e and 7 f.
- the semiconductor switch 7 a in the arm 1 is rendered nonconductive prior to the semiconductor switch 7 j in the arm 3 , the current flowing through the load is commutated to the diode 7 d connected in antiparallel to the semiconductor switch 7 b in the arm 1 and continues to flow through a circuit of the semiconductor switch 7 j in the arm 3 —the insulating transformer 9 —the diode 7 d connected in anti parallel to the semiconductor switch 7 b in the arm 1 , and the current gradually decreases even after a gate signal is inputted to the semiconductor switch 7 b in the arm 1 until the semiconductor switch 7 i in the arm 3 is rendered conductive and is rendered to zero before the semiconductor switch 7 i is rendered conductive.
- 18 i ⁇ 18 p are respectively circuits for driving the respective semiconductor switches 18 a and 18 b in arms 24 ⁇ 27 in the multi level PWM inverter circuit 18 after amplifying switching control signals outputted from the switching control device 18 q to predetermined values.
- the diode 18 e is connected as shown in the drawing, between the connection point of the semiconductor switches 18 a and 18 b in the arms 25 and the connection point of the second smoothing capacitor 12 and the third smoothing capacitor 13 , the diode 18 f is connected, between the connection point of the semiconductor switches 18 a and 18 b in the arms 26 and the connection point of the second smoothing capacitor 12 and the third smoothing capacitor 13 , the diode 18 g is connected and between the connection point of the semiconductor switches 18 a and 18 b in the arms 27 and the connection point of the second smoothing capacitor 12 and the third smoothing capacitor 13 , the diode 18 h is connected.
- FIG. 6 is a circuit constitution diagram of a gradient magnetic field power source device for an MRI apparatus representing a second embodiment of a power source device according to the present invention.
- the fourth AC-DC converter 80 can meet the phases of phase current with the phase voltage of the AC power source by performing the pulse width modulation control on the semiconductor switches 80 a ⁇ 80 f in response to a phase difference between the phase current and the phase voltage of the AC power source and an error between the output voltage of the smoothing capacitor 80 p and the set value 22 a (the first voltage command value), thereby, such advantages can be obtained that the power factor is increased and the apparent power is decreased, thus, the current required to be flown through the fourth AC-DC converter 80 can be reduced as well as the capacity of the three phase AC power source installation can also be reduced.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Magnetic Resonance Imaging Apparatus (AREA)
Abstract
Description
- The present invention relates to a power source device and in particular relates to a power source device that is suitable for varieties of power sources necessary for generating static magnetic fields, gradient magnetic fields and high frequency magnetic fields for a magnetic resonance imaging apparatus (herein below will be called as an MRI apparatus) requiring a high voltage and a large current, and an MRI apparatus using the same.
- An MRI apparatus is one that which pulse like high frequency magnetic fields are applied to an inspection object which is placed in static magnetic fields, detects nuclear magnetic resonance signals generated from the inspection object and forms such as spectra and images based on the detected signals.
- The MRI apparatus is provided with, as its magnetic fields generating coils, super-conducting coils for generating static magnetic fields, gradient magnetic field coils for generating the gradient magnetic fields being superposed on the static magnetic fields and further high frequency coils for generating the high frequency magnetic fields.
- For these magnetic field generating coils, respective power source devices of which magnitude and timing of current to be fed thereto are controllable are provided in order to generate magnetic fields of predetermined intensities.
- In such MRI apparatus, the magnetic field intensity of such as the static magnetic fields, the gradient magnetic fields and the high frequency magnetic fields greatly affects such as on noises in finally obtained images and on image taking time.
- Further, in order to obtain images useful for diagnosis in a short time, as power sources for the magnetic fields in the MRI apparatus, a highly stable and highly accurate power source device is required of which current flowing through the magnetic coils for generating the magnetic fields shows a short rise and fall time and shows free of such as ripples and variation after the rising.
- In particular, in these days, it is required to devise shortening the image taking time by accelerating the image taking, and in order to accelerate the image taking from a view point of the gradient magnetic fields, the intensity of the pulse like gradient magnetic fields has to be increased further than the conventional one and the rise and fall time has to be further shortened.
- For these purposes, since a large current is required to be fed to the gradient magnetic coils with a short rise and fall time, as a power source for the gradient magnetic coils, a large current and high voltage power source of roughly 300 [A]˜400 [A] and of about 2000 [V] is required.
- For example, JP-A-7-313489 discloses a power source device for gradient magnetic fields in an MRI apparatus that is capable of outputting a large current and high voltage to meet these requirements. The power source device for gradient magnetic fields is constituted by DC voltage power sources each having an output voltage different from each other that are serially connected in multi stages and a multi level diode clamped type PWM inverter connected to these DC voltage power sources, and to the output side of the multi level diode clamped type PWM inverter, is connected a series connection of gradient magnetic field coils in the MRI apparatus and a linear amplifier that linearly amplifies a command signal of a current to be fed to the gradient magnetic field coils outputted from a sequencer in the MRI apparatus to form a coil current and is capable of feeding the current to the gradient magnetic field coils.
- However, JP-A-7-313489 absolutely nowhere refers to any circuit configurations of the respective DC voltage power sources serially connected in multi stages that constitute the power source device for the gradient magnetic fields.
- Further, in order to constitute the DC voltage power sources serially connected in multi stages, for example, when a full bridge inverter circuit as disclosed, for example, in JP-A-5-159893 is used, a problem arose that the circuit scale thereof enlarges because not less than eight sets of transistors and diodes are necessitated.
- An object of the present invention is to provide a small sized and highly accurate high voltage and large current power source device in which DC voltage power sources serially connected in multi stages necessary for a multi level diode clamped type PWM inverter to which output terminal such as gradient magnetic field coils in an MRI apparatus are connected as a load are constituted with a comparatively simple circuit and further while suppressing loss in the power sources, and an MRI apparatus using the same.
- The above object is achieved by the following measures.
- (1) In a power source device provided with a DC voltage power source means constituted by connecting in series plural DC voltage sources, a current amplifying means of a multi level inverter using DC voltage of the DC voltage power source means as a power source, at the output of the current amplifying means a load is connected and a current control means that controls the current amplifying means so that a current flowing through the load assumes a current command value, the DC voltage power source means comprises an AC-DC converting and voltage stepping up means that converts a commercial AC power source voltage to a DC voltage and steps up the converted DC voltage, a DC-AC converting means that converts the DC voltage stepped up by the previous means to an AC voltage and plural insulating transformers which step up the AC voltage converted by the converting means while insulating each other, and is constituted by connecting in series DC voltages that are obtained by converting the output voltages of the transformers to DC and smoothing the same.
- In the power source device constituted in the above manner, with the AC-DC converting and voltage stepping up means, the voltage obtained through full wave rectification of the commercial AC power source voltage is stepped up to a higher voltage, the stepped up DC voltage is converted to AC voltages by the DC-AC converting means, these AC voltages are stepped up by the transformers while insulating each other and after smoothing the same and connecting the DC voltages in series, the DC voltage power source is obtained and constituted, thus, if an operating frequency of the AC-DC converting and voltage stepping up means and the DC-AC converting means, which use semiconductor switches is shifted to a high frequency side to about 20 kHz, the sizes of the insulating transformers and smoothing means are reduced extremely, thereby, the size and cost of the DC voltage power source means, which is insulated from the commercial AC power source can be reduced.
- (2) The DC-AC converting means is provided with not less than two sets of full bridge inverter circuits in which an arm is constituted by connecting in series two switch means each is constituted by a semiconductor switch and a diode connected in antiparallel to the semiconductor switch and at least three arms are connected in parallel and which are constituted by at least one common arm among the plural arms and the remaining arms and a phase difference control means which controls respective semiconductor switches in the common arm of the respective full bridge inverter circuits by providing a conduction phase different from that of the corresponding semiconductor switches in the remaining arms, and with the phase difference control means, the conduction phase of the semiconductor switches in the remaining arms is controlled in a delayed phase and/or in an advanced phase with respect to the conduction phase of the semiconductor switches in the common arm.
- In the DC-AC converting means (which corresponds to a phase
shift inverter circuit - (3) The phase difference control means (which corresponds to second
switching control devices voltage command value 22 b and a thirdvoltage command value 22 d in embodiments) assumes zero. - Thereby, the DC voltage of the DC power source means shows a stable power source voltage without variation and a stable current with a short rise time can be fed to a load by the multi level inverter using the DC power source.
- (4) The AC-DC converting and voltage stepping up means is constituted by being provided with means for converting the commercial AC power source voltage to a DC, a step up voltage type chopper circuit (which corresponds to a step up voltage
type chopper circuit 6 in embodiments) that steps up the DC voltage converted by the previous means and a conduction rate control means that controls a conduction rate of the semiconductor switches in the chopper circuit. - By switching controlling the conduction rate (ratio of conductive period and non-conductive period of a semiconductor switch) of the semiconductor switches in the step up voltage type chopper circuit the output voltage thereof can be stepped up to any desired voltages.
- Further, the conduction rate control means is further provided with means for detecting an output voltage of the step up voltage type chopper circuit and the conduction rate of the semiconductor switches can be feed back controlled so that a difference between a detection value detected by the previous means and a second target voltage command value (which corresponds to a first
voltage command value 22 a in embodiments) assumes zero. - Through controlling in this manner, a variation in the output voltage of the chopper circuit is prevented and the input DC power source voltage to the DC-AC converting means can be kept at a constant voltage which can otherwise vary due to such as a variation of the commercial AC power source voltage and others, thereby, the DC-AC converting means can be operated stably.
- (5) Further, another embodiment of the AC-DC converting and voltage stepping up means is constituted by being provided with a bridge circuit in which plural pairs of semiconductor switches are connected in parallel, diodes connected in antiparallel to the respective semiconductor switches in the plural pairs, reactors connected between AC terminals of the bridge circuit and the commercial AC power source and a pulse width modulation control means that performs pulse width modulation control on the semiconductor switches (which corresponds to a fourth AC-
DC converter 80 in an embodiment and the pulse width modulation control means therein corresponds to a fourthswitching control device 80 r). - The pulse width modulation control means is further provided with means for detecting an output voltage of the AC-DC converting and voltage stepping up means and the conduction pulse width of the semiconductor switches can be feed back controlled so that a difference between a detection value detected by the previous means and a third target voltage command value (which corresponds to a first
voltage command value 22 a in embodiments) assumes zero. - In addition, the pulse width modulation control means is further provided with means for detecting a phase voltage and a phase current of the commercial AC power source and controls the phases of the phase voltage and the phase current to meet each other.
- Through the use of such AC-DC converting and voltage stepping up means, the output voltage can be stepped up to a same voltage as of the AC-DC converting and voltage stepping up means as explained in (4) and further the number of the elements constituting the circuit is reduced. Further, the power factor is improved to lessen the apparent power and the amount of current flowing through the semiconductor switches is permitted to be small as well as the capacity of the commercial AC power source installation can be reduced.
- (6) In an MRI apparatus using a power source device provided with a DC voltage power source means constituted by connecting in series plural DC voltage sources, a current amplifying means of a multi level inverter using DC voltage of the DC voltage power source means as a power source, at the output of the current amplifying means a load is connected and a current control means that controls the current amplifying means so that a current flowing through the load assumes a current command value, the load is coils for generating magnetic fields in the MRI apparatus and as the power source device for the MRI apparatus, any one of the devices as indicated in (1)˜(5) is used.
- With thus constituted power source device for the coils for generating the magnetic fields, a highly accurate high voltage and large current can be obtained while being insulated from the commercial AC power source, thereby, the intensity of the pulse like gradient magnetic fields can be increased and the magnetic fields having a short rise and fall time can be obtained, accordingly, the image taking speed by the MRI apparatus can be accelerated and the image taking time can be shortened.
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FIG. 1 is a circuit configuration diagram of a power source device representing a first embodiment according to the present invention, which is applied to gradient magnetic field coils, as a load thereof, of an MRI apparatus; -
FIG. 2 is a detailed diagram of a phase shift inverter circuit of the power source device representing the first embodiment as shown inFIG. 1 ; -
FIG. 3 is a diagram for explaining an operation of the phase shift inverter circuit as shown inFIG. 2 according to a first control method; -
FIG. 4 is a diagram for explaining an operation of the phase shift inverter circuit as shown inFIG. 2 according to a second control method; -
FIG. 5 is a diagram for explaining an operation of the phase shift inverter circuit as shown inFIG. 2 according to a third control method; -
FIG. 6 is a circuit configuration diagram of a major part of a power source device representing a second embodiment according to the present invention, which is applied to gradient magnetic field coils, as a load thereof, of an MRI apparatus; -
FIG. 7 is a circuit configuration diagram of a major part of a power source device representing a third embodiment according to the present invention, which is applied to gradient magnetic field coils, as a load thereof, of an MRI apparatus; and -
FIG. 8 is a circuit configuration diagram of a major part of a power source device representing a fourth embodiment according to the present invention, which is applied to gradient magnetic field coils, as a load thereof, of an MRI apparatus. - Preferable embodiments of a power source device and an MRI apparatus using the same according to the present invention will be explained in detail with reference to the drawings as attached.
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FIG. 1 is a circuit configuration diagram of a power source device for gradient magnetic fields in an MRI apparatus representing a first embodiment for a power source device according to the present invention. - A gradient magnetic field
power source device 2 is constituted to receive an electric power supply from a three phaseAC power source 3 and to feed an electric current to a gradientmagnetic field coil 1 serving as a load, and is constituted by being provided with a first AC-DC converter 4 that is connected to the three phaseAC power source 3 and converts a three phase AC voltage to a DC voltage, afirst smoothing capacitor 5 that is connected to the output side of the AC-DC converter 4 and smoothes the DC voltage, a DC-DC converter (herein below will be called as a voltage step up type chopper circuit) 6 that is connected to thefirst smoothing capacitor 5 and steps up the smoothed DC voltage to a predetermined DC voltage, a DC-AC converter (herein below will be called as a phase shift inverter circuit) 7 that is constituted by three arms, is connected to the output side of the voltage step uptype chopper circuit 6 and converts the stepped up DC voltage into two single phase AC voltages, an AC-DC stepping up and converting unit (which produces two DC voltages Vdc1 and Vdc2) 14, which is constituted by twoinsulating transformers shift inverter circuit 7 and insulate the respective two single phase AC voltages each other, a second AC-DC converter 10 and a third AC-DC converter 11 that are connected respectively to the secondary side of thetransformers second smoothing capacitor 12 and athird smoothing capacitor 13 which smooth these converted DC voltages, andcurrent amplifiers unit 14 and is constituted by a multi level PWM (Pulse Width Modulation, herein below will be abbreviated as PWM)inverter circuit 18 of three levels and is connected to one of anX axis coil 15, aY axis coil 16 and aZ axis coil 17 for the gradientmagnetic coil 1. - The voltage step up
type chopper circuit 6 is what is for stepping up to a voltage higher than the voltage obtained by converting the three phase AC voltage of the three phaseAC power source 3 into a DC voltage by the first AC-DC converter 4 and is constituted by areactor 6 a, asemiconductor switch 6 b using an insulated gate type bipolar transistor (Insulated Gate Bipolar Transistor, herein below will be abbreviated as IGBT), adiode 6 c connected in antiparallel to thesemiconductor switch 6 b, afourth smoothing capacitor 6 d, afirst voltage detector 6 e for detecting a voltage Vdcc at thesmoothing capacitor 6 d and a firstswitching control device 6 f that performs a switching control of thesemiconductor switch 6 b so that a firstvoltage command value 22 a outputted from asequencer 22 of an MRI apparatus meets with the voltage Vdcc detected by thefirst voltage detector 6 e as shown in the drawing. - Further, 6 g is a circuit for driving the
semiconductor switch 6 b after amplifying a switching control signal outputted from aswitching control device 6 f to a predetermined value. - The voltage step up
type chopper circuit 6 thus constituted is what causes thesemiconductor switch 6 b to be conductive and non-conductive in a predetermined period and steps up the DC voltage smoothed by thefirst smoothing capacitor 5, and when thesemiconductor switch 6 b is rendered conductive, a circuit of thefirst smoothing capacitor 5—thereactor 6 a—thesemiconductor switch 6 b is formed and causes to flow a current through thereactor 6 a to store electromagnetic energy in thereactor 6 a. - When the
semiconductor switch 6 b is rendered non-conductive under this condition, the electromagnetic energy stored in thereactor 6 a charges thefourth smoothing capacitor 6 d through adiode 6 h. - Through this operation, namely, through switching control of the
semiconductor switch 6 b between conductive and non-conductive in a predetermined period, the voltage of thefourth smoothing capacitor 6 d can be stepped up more than the voltage of thefirst smoothing capacitor 5, namely, the voltage obtained when the voltage of the threephase power source 3 is full wave rectified, and the firstswitching control device 6 f switching controls thesemiconductor switch 6 b so that the detection value detected by thefirst voltage detector 6 e meets the firstvoltage command value 22 a outputted from thesequencer 22 of the MRI apparatus. - In this manner, the voltage of the
fourth smoothing capacitor 6 d corresponding to the output voltage of the voltage step uptype chopper 6, namely, the DC source voltage Vdcc inputted to the phaseshift inverter circuit 7 can be stepped up to any voltages through the switching control of thesemiconductor switch 6 b between conductive and non-conductive in a predetermined period as referred to above. - The phase
shift inverter circuit 7 is constituted by anarm 1 formed bysemiconductor switches diodes 7 c and 7 d connected in antiparallel thereto, anarm 2 formed bysemiconductor switches diodes arm 3 formed bysemiconductor switches switching control device 7 m that switching controls these semiconductor switches, and with thearm 1 andarm 2, a first full bridge circuit is constituted and with thearm 1 andarm 3, a second full bridge circuit is constituted. - Namely, the
arm 1 is used in common for the first and second full bridge inverter circuits, thereby, the number of arms for constituting these full bridge inverter circuits is reduced from four to three and the number of the semiconductor switches can be devised to decrease. Further 7 n˜7 s respectively are circuits for driving thesemiconductor switches switching control device 7 m to a predetermined value. - For the control of the output AC voltage of the first and second full bridge inverter circuits, by making use of a phase difference control technology through the phase shift PWM (Pulse Width Modulation) control as disclosed in JP-A-63-190556, the first AC output voltage Vac1 is controlled through the phase difference control of the
arms arms -
FIG. 2 shows a block constitutional diagram of the secondswitching control device 7 m in the phaseshift inverter circuit 7 inFIG. 1 together with thearms 1˜3, thedrive circuits 7 n˜7 s and the AC-DC stepping up and convertingunit 14, and the control operation of thephase shift inverter 7, which is one of major parts of the present invention will be explained in detail with reference to relationships between the operation timing of thesemiconductor switches FIGS. 3 , 4 and 5. - In
FIG. 2 , the secondswitching control device 7 m is constituted by a phase difference PWM controlsignal producing unit 7m 1 that produces a control signal for controlling the DC high voltages Vdc1 and Vdc2 corresponding to the output voltage of the AC-DC voltage step up and convertingunit 14, which will be explained later, to meet the secondvoltage command value 22 b from thesequencer 22 in the MRI apparatus, a firstphase shift unit 7m 2 that causes the conductive phase of thesemiconductor switches arm 2 in a delayed phase with respect to the conductive phase of thesemiconductor switches arm 1 and a secondphase shift unit 7m 3 that causes the conductive phase of thesemiconductor switches arm 3 in a delayed phase or an advanced phase with respect to the conductive phase of thesemiconductor switches arm 1. -
FIG. 3 is a control timing diagram of the phaseshift inverter circuit 7 according to a first control method, wherein gate signals for the respective semiconductor switches, voltages applied to the semiconductor switches, currents flowing through the semiconductor switches and output voltages Vac1 and Vac2 from the phaseshift inverter circuit 7 are shown. - In the instant first control method, the output voltage is controlled in a manner that with respect to the conductive phase of the
semiconductor switches arm 1 common for the first and second full bridge inverter circuits, the conductive phases of thesemiconductor switches arm 2 and thesemiconductor switches arm 3 are set indelayed phase differences signal generating unit 7m 1 in the secondswitching control device 7 m as shown inFIG. 2 is shifted in the delayed phase difference φ1 by the firstphase shift unit 7m 2 and with this control signal thesemiconductor switches arm 2 are conduction controlled, and the control signal produced in the phase difference PWM controlsignal generating unit 7m 1 is shifted in the delayed phase difference φ2 by the secondphase shift unit 7m 3 and with this control signal thesemiconductor switches arm 3 are conduction controlled, thereby, the two AC output voltages Vac1 and Vac2 are respectively controlled independently. - Namely, with respect to the
semiconductor switch 7 a in thearm 1 constituting the first full bridge inverter circuit, the conductive phase of thesemiconductor switch 7 f in thearm 2 is delayed by φ1 and with respect to thesemiconductor switch 7 b in thearm 1 of which phase is delayed by 180° from that of thesemiconductor switch 7 a in thearm 1, the conductive phase of thesemiconductor switch 7 e in thearm 2 is delayed by φ1, and by varying the delayed phase difference φ1 from 0° to 180° in an electrical angle, the first AC output voltage Vac1 can be varied to any AC voltages between 0 to the maximum voltage. - Further, when the
semiconductor switch 7 f is rendered non-conductive, because of the inductance of the load, the current flowing through a circuit of the DC power source Vdcc—the semiconductor switch 7 a in thearm 1—theinsulating transformer 8—the semiconductor switch 7 f in thearm 2 until now moves to thediode 7 g connected in antiparallel to thesemiconductor switch 7 e in the arm 2 (which will be called as commutation herein after), and the current flowing through the load continues to flow through a circuit of thediode 7 g connected in antiparallel to thesemiconductor switch 7 e in thearm 2—thesemiconductor switch 7 a in thearm 1 and theinsulating transformer 8 and the current becomes 0 at the timing when the semiconductor switch 7 b in thearm 1 is rendered conductive and thesemiconductor switch 7 a thereof is rendered nonconductive. - Further, when the semiconductor switch 7 e in the
arm 2 is rendered nonconductive, the current flowing through a circuit of the DC power source Vdcc—thesemiconductor switch 7 e in thearm 2—theinsulating transformer 8—thesemiconductor switch 7 b in thearm 1 is commutated to thediode 7 h connected in antiparallel to thesemiconductor switch 7 f in thearm 2 and the current flowing through the load continues to flow through a circuit of thediode 7 h connected in antiparallel to thesemiconductor switch 7 f in thearm 2—theinsulating transformer 8 and thesemiconductor switch 7 b in thearm 1 and the current becomes zero at the timing when the semiconductor switch 7 a in thearm 1 is rendered conductive and thesemiconductor switch 7 b thereof is rendered nonconductive. - In such a way, the negative current component in the current Ie of the
semiconductor switch 7 f and in the current If of the semiconductor switch 7 f as shown inFIG. 3 is the current flowing through thediodes semiconductor switches semiconductor switches - In the like manner as above, with respect to the
semiconductor switch 7 a in thearm 1 constituting the second full bridge inverter circuit, the conductive phase of thesemiconductor switch 7 j in thearm 3 is delayed by φ2 and with respect to thesemiconductor switch 7 b in thearm 1 of which phase is delayed by 180° from that of thesemiconductor switch 7 a in thearm 1, the conductive phase of thesemiconductor switch 7 i in thearm 3 is delayed by φ2, and by varying the delayedphase difference 42 from 0° to 180° in an electrical angle, the second AC output voltage Vac2 can be varied to any AC voltages between 0 to the maximum voltage. - Further, like the first full bridge inverter circuit constituted by the
arms semiconductor switch 7 i and in the current Ij of thesemiconductor switch 7 j as shown inFIG. 3 is the current flowing through the diodes 7 k and 7 l connected respectively in antiparallel to the semiconductor switches 7 i and 7 j and only positive current flows through the semiconductor switches 7 i and 7 j. - As has been explained above, in the first control method, current Ia, which is a sum current of the current flowing through the
semiconductor switch 7 f in thearm 2, the current flowing through thesemiconductor switch 7 j in thearm 3, the current flowing through thediode 7 g connected in antiparallel to thesemiconductor switch 7 e in thearm 2 and the current flowing through thediode 7 h connected in antiparallel to thesemiconductor switch 7 i in thearm 3, flows through thesemiconductor switch 7 a in thearm 1, and current Ib, which is also a sum current of the current flowing through thesemiconductor switch 7 e in thearm 2 and through thesemiconductor switch 7 i in thearm 3 and the current flowing through thediode 7 h connected in antiparallel to thesemiconductor switch 7 f in thearm 2 and through the diode 7 l connected in antiparallel to thesemiconductor switch 7 j in thearm 3, flows through thesemiconductor switch 7 b in thearm 1. - In this manner, although the sum currents of the current flowing through the semiconductor switches 7 e and 7 f in the
arm 2 and the semiconductor switches 7 i and 7 j in thearm 3 and the current flowing through thediodes arm 1, at the time of switching of the semiconductor switches 7 a and 7 b in thearm 1, the respective currents Ia and Ib flowing through the semiconductor switches 7 a and 7 b and the voltages thereat are nearly zero as shown in the drawing, for this reason, almost no switching loss is generated in the semiconductor switches 7 a and 7 b. - Accordingly, although a large current flows through the semiconductor switches 7 a and 7 b in the
arm 1 in comparison with the semiconductor switches in other arms, since the switching loss is dominant among the losses in the semiconductor switches performing the PWM control with high frequency, it is sufficient only if the conduction loss is taken into account for the semiconductor switches 7 a and 7 b in thearm 1. - On the other hand, although a switching loss is caused in the semiconductor switches in the
arms - As a result, in the first control method, the losses caused in the semiconductor switches in the
arm 1 and in the semiconductor switches in the other arms are distributed. - Namely, it is sufficient if the inverter circuit is installed while putting weight on the conduction loss for the semiconductor switches in the
arm 1 and weight on the switching loss for the semiconductor switches in the other arms. - Further, although not illustrated, each of the semiconductor switches are generally provided with a surge voltage suppressing means constituted by such as a capacitor and a resistor for suppressing a surge voltage caused during switching, however, in the first control method, such surge voltage suppressing means is provided only for the semiconductor switches in the
arms arm 1 in which almost no switching loss is caused, thereby, the circuit installation is simplified. - Further, in view of the characteristics of losses caused in the semiconductor switches in the respective arms, for example, when high speed semiconductor switches are selected for the semiconductor switches in the
arms arm 1, the loss and heating in the semiconductor switches are effectively suppressed and the installation of the phase shift inverter circuit can be simplified while reducing the size thereof. -
FIG. 4 is a control timing diagram of the phaseshift inverter circuit 7 according to a second control method, wherein gate signals for the respective semiconductor switches, voltages applied to the semiconductor switches, currents flowing through the semiconductor switches and output voltages Vac1 and Vac2 from the phaseshift inverter circuit 7 are shown. - In the instant second control method, the output voltage is controlled in a manner that with respect to the conductive phase of the semiconductor switches 7 a and 7 b in the
arm 1 common for the first and second full bridge inverter circuits, the conductive phases of the semiconductor switches 7 e and 7 f in thearm 2 are set in a delayed phase difference φ1, and those of the semiconductor switches 7 i and 7 j in thearm 3 are set in an advanced phase difference φ2, in that a control signal produced in the phase difference PWM controlsignal generating unit 7m 1 in the secondswitching control device 7 m as shown inFIG. 2 is shifted in the delayed phase difference φ1 by the firstphase shift unit 7m 2 and with this control signal the semiconductor switches 7 e and 7 f in thearm 2 are conduction controlled, and the control signal produced in the phase difference PWM controlsignal generating unit 7m 1 is shifted in the advanced phase difference φ2 by the secondphase shift unit 7m 3 and with this control signal the semiconductor switches 7 i and 7 j in thearm 3 are conduction controlled, thereby, the two AC output voltages Vac1 and Vac2 are respectively controlled independently. - Namely, with respect to the
semiconductor switch 7 a in thearm 1 constituting the first full bridge inverter circuit, the conductive phase of thesemiconductor switch 7 f in thearm 2 is delayed by φ1 and with respect to thesemiconductor switch 7 b in thearm 1 of which phase is delayed by 180° from that of thesemiconductor switch 7 a in thearm 1, the conductive phase of thesemiconductor switch 7 e in thearm 2 is delayed by φ1, and by varying the delayed phase difference φ1 from 0° to 180° in an electrical angle, the first AC output voltage Vac1 can be varied to any AC voltages between 0 to the maximum voltage. - Further, when the
semiconductor switch 7 f is rendered non-conductive, because of the inductance of the transformer, the current flowing through a circuit of the DC power source Vdcc—thesemiconductor switch 7 a in thearm 1—the insulatingtransformer 8—thesemiconductor switch 7 f in thearm 2 until now commutates to thediode 7 g connected in antiparallel to thesemiconductor switch 7 e in thearm 2, and the current flowing through the load continues to flow through a circuit of thediode 7 g connected in antiparallel to thesemiconductor switch 7 e in thearm 2—thesemiconductor switch 7 a in thearm 1 and the insulatingtransformer 8 and the current becomes 0 at the timing when thesemiconductor switch 7 b in thearm 1 is rendered conductive and thesemiconductor switch 7 a thereof is rendered nonconductive. - Further, when the
semiconductor switch 7 e in thearm 2 is rendered nonconductive, the current flowing through a circuit of the DC power source Vdcc—thesemiconductor switch 7 e in thearm 2—the insulatingtransformer 8—thesemiconductor switch 7 b in thearm 1 is commutated to thediode 7 h connected in antiparallel to thesemiconductor switch 7 f in thearm 2 and the current flowing through the load continues to flow through a circuit of thediode 7 h connected in antiparallel to thesemiconductor switch 7 f in thearm 2—the insulatingtransformer 8—thesemiconductor switch 7 b in thearm 1 and the current becomes zero at the timing when thesemiconductor switch 7 a in thearm 1 is rendered conductive and thesemiconductor switch 7 b thereof is rendered nonconductive. - In such a way, the negative current component in the current Ie of the
semiconductor switch 7 e and in the current If of thesemiconductor switch 7 f as shown inFIG. 4 is the current flowing through thediodes - On the other hand, with respect to the
semiconductor switch 7 a in thearm 1 constituting the second full bridge inverter circuit, the conductive phase of thesemiconductor switch 7 j in thearm 3 is advanced by φ2 and with respect to thesemiconductor switch 7 b in thearm 1 of which phase is delayed by 180° from that of thesemiconductor switch 7 a in thearm 1, the conductive phase of thesemiconductor switch 7 i in thearm 3 is advanced by φ2, and by varying the delayed phase difference φ2 from 0° to 180° in an electrical angle, the second AC output voltage Vac2 can be varied to any AC voltages between 0 to the maximum voltage. - In the second full bridge inverter circuit operating in the above manner, different from the first control method, since the
semiconductor switch 7 a in thearm 1 is rendered nonconductive prior to thesemiconductor switch 7 j in thearm 3, the current flowing through the load is commutated to thediode 7 d connected in antiparallel to thesemiconductor switch 7 b in thearm 1 and continues to flow through a circuit of thesemiconductor switch 7 j in thearm 3—the insulatingtransformer 9—thediode 7 d connected in anti parallel to thesemiconductor switch 7 b in thearm 1, and the current gradually decreases even after a gate signal is inputted to thesemiconductor switch 7 b in thearm 1 until thesemiconductor switch 7 i in thearm 3 is rendered conductive and is rendered to zero before thesemiconductor switch 7 i is rendered conductive. - With regard to the current flowing through the
semiconductor switch 7 j in thearm 3 in the second full bridge inverter circuit, the same is applied as above, in that since thesemiconductor switch 7 b in thearm 1 is rendered nonconductive prior to thesemiconductor switch 7 i in thearm 3, the current flowing through the load is commutated to the diode 7 c connected in antiparallel to thesemiconductor switch 7 a in thearm 1 and continues to flow through a circuit of thesemiconductor switch 7 i in thearm 3—the insulatingtransformer 9—the diode 7 c connected in anti parallel to thesemiconductor switch 7 a in thearm 1, and the current gradually decreases even after a gate signal is inputted to thesemiconductor switch 7 a in thearm 1 until thesemiconductor switch 7 j in thearm 3 is rendered conductive and is rendered to zero before thesemiconductor switch 7 j is rendered conductive. - In such a manner, when the conduction phase of the semiconductor switches in the
arm 3 is set in an advanced phase with respect to the conduction phase of the semiconductor switches in thearm 1, a period when current flows through thediodes 7 c and 7 d connected respectively in antiparallel to the semiconductor switches 7 a and 7 b in thearm 1 appears, however, no period when current flows through the diodes 7 k and 7 l connected respectively in antiparallel to the semiconductor switches 7 i and 7 j in thearm 3 appears and the current flows through the respective semiconductor switches as shown inFIG. 4 . - The loss in the
arm 2 according to the instant second control method is the same as that of the first control method, however, the switching loss in thearm 1 according to the second control method is large in comparison with that of the first control method and the conduction loss therein is small. Further, in thearm 3 no switching loss is caused with the same current as in the first control method, therefore, in total the second control method is a control method with small loss. -
FIG. 5 is a control timing diagram of the phaseshift inverter circuit 7 according to a third control method, wherein gate signals for the respective semiconductor switches, voltages applied to the semiconductor switches, currents flowing through the semiconductor switches and output voltages Vac1 and Vac2 from the phaseshift inverter circuit 7 are shown. - In the instant third control method, the output voltage is controlled in a manner that with respect to the conductive phase of the semiconductor switches 7 a and 7 b in the
arm 1 common for the first and second full bridge inverter circuits, the conductive phases of the semiconductor switches 7 e and 7 f in thearm 2 are set in an advanced phase difference φ1, and those of the semiconductor switches 7 i and 7 j in thearm 3 are also set in an advanced phase difference φ2, in that a control signal produced in the phase difference PWM controlsignal generating unit 7m 1 in the secondswitching control device 7 m as shown inFIG. 2 is shifted in the advanced phase difference φ1 by the firstphase shift unit 7m 2 and with this control signal the semiconductor switches 7 e and 7 f in thearm 2 are conduction controlled, and the control signal produced in the phase difference PWM controlsignal generating unit 7m 1 is shifted in the advanced phase difference φ2 by the secondphase shift unit 7m 3 and with this control signal the semiconductor switches 7 i and 7 j in thearm 3 are conduction controlled, thereby, the two AC output voltages Vac1 and Vac2 are respectively controlled independently. - Namely, with respect to the
semiconductor switch 7 a in thearm 1 constituting the first full bridge inverter circuit, the conductive phase of thesemiconductor switch 7 f in thearm 2 is advanced by φ1 and with respect to thesemiconductor switch 7 b in thearm 1 of which phase is delayed by 180° from that of thesemiconductor switch 7 a in thearm 1, the conductive phase of thesemiconductor switch 7 e in thearm 2 is advanced by φ1, and by varying the advanced phase difference φ1 from 0° to 180° in an electrical angle, the first AC output voltage Vac1 can be varied to any AC voltages between 0 to the maximum voltage. - In the first full bridge inverter circuit operating in the above manner, different from the first and second control methods, since the
semiconductor switch 7 a in thearm 1 is rendered nonconductive prior to thesemiconductor switch 7 f in thearm 2, the current flowing through the load is commutated to thediode 7 d connected in antiparallel to thesemiconductor switch 7 b in thearm 1 and continues to flow through a circuit of thesemiconductor switch 7 f in thearm 2—thediode 7 d connected in antiparallel to thesemiconductor switch 7 b in thearm 1—the insulatingtransformer 8 and the current gradually decreases even after a gate signal is inputted to thesemiconductor switch 7 b in thearm 1 until thesemiconductor switch 7 e in thearm 3 is rendered conductive and is rendered to zero before thesemiconductor switch 7 e is rendered conductive. - In the like manner, since the
semiconductor switch 7 b in thearm 1 is rendered nonconductive prior to thesemiconductor switch 7 e in thearm 2, the current flowing through the load is commutated to the diode 7 c connected in antiparallel to thesemiconductor switch 7 a in thearm 1 and continues to flow through a circuit of the diode 7 c connected in anti parallel to thesemiconductor switch 7 a in thearm 1—thesemiconductor switch 7 e in thearm 2—the insulatingtransformer 8 and the current gradually decreases even after a gate signal is inputted to thesemiconductor switch 7 a in thearm 1 until thesemiconductor switch 7 f in thearm 2 is rendered conductive and is rendered to zero before thesemiconductor switch 7 f is rendered conductive. - The
arms FIG. 5 . - In such a manner, when the conduction phase of the
diodes semiconductor switch arm 2 and the semiconductor switches in thearm 3 is set in an advanced phase with respect to the conduction phase of the semiconductor switches in thearm 1, a period when current flows through thediodes 7 c and 7 d connected respectively in antiparallel to the semiconductor switches 7 a and 7 b in thearm 1 appears, however, no period when current flows through thearm 2 and the diodes 7 k and 7 l connected respectively in antiparallel to the semiconductor switches 7 i and 7 j in thearm 3 appears. - Therefore, a switching loss is caused in the
arm 1 and the current therein is large. In contrast, the current in thearms arm 1. - As has been explained hitherto, through constituting the two full bridge inverter circuits with three arms, the number of semiconductor switches is reduced as well as the number of circuits for driving the semiconductor switches and of the wirings therefor can also be reduced.
- Further, since the losses in the semiconductor switches consisting of the switching loss and the conduction loss are different from arm to arm and for the arms with no switching loss, no surge voltage suppressing means for the semiconductor switches are necessary, through heat radiating installation (an installation such as heat sinks, fins and air cooling fans for cooling the semiconductor switches) in view of the losses caused in every semiconductor switches in the respective arms such as selection of semiconductor switches having a small conduction loss for the semiconductor switches in the arms showing a large conduction loss, minimization of surge voltage suppressing means and proper selection of semiconductor switches, a small sized and inexpensive inverter circuit can be realized.
- In the AC-DC stepping up and converting
unit 14, the two single phase AC voltages Vac1 and Vac2 converted by the phaseshift inverter circuit 7 are inputted to the insulatingtransformers transformers third smoothing capacitors current amplifiers unit 14 is insulated from the three phaseAC power source 3. - The two DC power source voltages Vdc1 and Vdc2 are connected in series to form a DC high voltage power source for the multi level
PWM inverter circuit 18, which will be explained later, therefore, Vdc1 and Vdc2 have to be a same value. - For this reason, insulating
voltage detectors 12 a and 12 b are provided which are capable of detecting the Vdc1 and Vdc2 while insulating each other and the secondswitching control device 7 m performs a switching control for the semiconductor switches 7 a, 7 b, 7 e, 7 f, 7 i and 7 j in the phaseshift inverter circuit 7 so that the detection values detected by these detectors meet with the secondvoltage command value 22 b outputted from thesequencer 22 in the MRI apparatus. - In addition, when the operating frequency of the phase
shift inverter circuit 7 is increased to (about 20 kHz), the size and cost of the insulatingtransformers unit 14 can be reduced. - The
current amplifiers PWM inverter circuit 18 of 3 levels and the currents from the multi levelPWM inverter circuits 18 are fed respectively to theX axis coil 15, theY axis coil 16 and theZ axis coil 17 in the gradient magnetic field coils 1 representing the load. - 3 level voltages of 0 level, ½ E level and E of maximum level using the DC power source voltages Vdc1 and Vdc2 as the power source (Vdc1=Vdc2=E/2) are applied from the multi level
PWM inverter circuits 18 to theX axis coil 15, theY axis coil 16 and theZ axis coil 17 in the gradient magnetic field coils 1 representing the load while being changed over by the current command values 22c 1, 22 c 2 and 22 c 3 from thesequencer 22 of the MRI apparatus. - The
current amplifier 19 is constituted by being provided with the multi levelPWM inverter circuit 18 connected in parallel with the second smoothing capacitor (voltage Vdc1) 12 and the third smoothing capacitor (voltage Vdc2) 13 which are respectively connected in series and serve as an input DC voltage source therefor, wherein to the output side of the multi levelPWM inverter circuit 18 theX axis coil 15 is connected, acurrent detector 23 for detecting an output current (current flowing through the gradient magnetic field coil 15) of thecurrent amplifier 19 and aswitching control device 18 q which receives the current command value 22 c 1 from thesequencer 22 in the MRI apparatus and the current detection value outputted from thecurrent detector 23 and drive controls the multi levelPWM inverter circuit 18 so that the difference of both values assumes zero. - Further, 18 i˜18 p are respectively circuits for driving the respective semiconductor switches 18 a and 18 b in
arms 24˜27 in the multi levelPWM inverter circuit 18 after amplifying switching control signals outputted from the switchingcontrol device 18 q to predetermined values. - The
current amplifier 20 is also constituted in the same manner as above, wherein to the output side of the multi levelPWM inverter circuit 18 theY axis coil 16 is connected, and is constituted by being provided with acurrent detector 23 for detecting an output current of thecurrent amplifier 20 and aswitching control device 18 q which receives the current command value 22 c 2 and the current detection value outputted of thecurrent detector 23 and drive controls the multi levelPWM inverter circuit 18 so that the difference of both values assumes zero. - Further, the
current amplifier 21 is also constituted in the same manner as above, wherein to the output side of the multi levelPWM inverter circuit 18 theZ axis coil 17 is connected, and is constituted by being provided with acurrent detector 23 for detecting an output current of thecurrent amplifier 21 and aswitching control device 18 q which receives the current command value 22 c 3 and the current detection value outputted of thecurrent detector 23 and drive controls the multi levelPWM inverter circuit 18 so that the difference of both values assumes zero. - The multi level
PWM inverter circuit 18 of 3 levels is constituted in such a manner that to the inputs thereof DC voltage sources E (voltage=Vdc1+Vdc2) and E0 are connected and any voltage waveforms are outputted at output terminals A and B. - Further, the 3 level
PWM inverter circuit 18 divides the DC voltage E-E0 between the DC voltage sources into two (E/2) and includes four sets ofarms 24˜27 constituted by connecting in series two pairs of semiconductor switches 18 a and 18 b of IGBTs anddiodes - Then, between the connection point (potential at level 2) of the
second smoothing capacitor 12 and thethird smoothing capacitor 13 and the respective connection points of the semiconductor switches in therespective arms 24˜27 in the full bridge structure,diodes - Namely, between the connection point of the semiconductor switches 18 a and 18 b in the
arms 24 and the connection point of thesecond smoothing capacitor 12 and thethird smoothing capacitor 13, thediode 18 e is connected as shown in the drawing, between the connection point of the semiconductor switches 18 a and 18 b in thearms 25 and the connection point of thesecond smoothing capacitor 12 and thethird smoothing capacitor 13, thediode 18 f is connected, between the connection point of the semiconductor switches 18 a and 18 b in thearms 26 and the connection point of thesecond smoothing capacitor 12 and thethird smoothing capacitor 13, thediode 18 g is connected and between the connection point of the semiconductor switches 18 a and 18 b in thearms 27 and the connection point of thesecond smoothing capacitor 12 and thethird smoothing capacitor 13, thediode 18 h is connected. - Herein, when the semiconductor switches 18 a and 18 b in the
arm 24 are rendered conductive, voltage +E is outputted at the output terminal A, when thesemiconductor switch 18 b in thearm 24 and thesemiconductor switch 18 a in thearm 25 are rendered conductive, voltage +E/2 is outputted at the output terminal A, further, when the semiconductor switches 18 a and 18 b in thearm 25 are rendered conductive, voltage 0 is outputted at the output terminal A, in this manner, voltages of three levels can be outputted at the output terminal A. - Further, the above is true with regard to the output terminal B, resultantly, five voltages from −E to +E (−E, −E/2, 0, +E/2 and E) are outputted as voltages between the output terminals A and B.
- Further, through performing the PWM control thereon any desired voltages from −E to +E can be outputted.
- Since 3 level
PWM inverter circuit 18 divides the DC voltage source into Vdc1 and Vdc2, therespective arms 24˜27 likely divide the same with the semiconductor switches 18 a and 18 b and the respective connection points thereof are connected via thediodes - Further, since the
current amplifiers 19˜21 respectively use the multi levelPWM inverter circuit 18 and with which PWM control is performed, current ripples can be reduced in comparison with when other inverters are used. - In the multi level PWM inverter circuit, for example, in the case of the 3 level
PWM inverter circuit 18, when a difference appears between the divided two DC power source voltages Vdc1 and Vdc2, a difference also appears in positive and negative output voltages which causes to increase ripples in the current flowing through the load. Accordingly, in order to equalize the two DC power source voltages Vdc1 and Vdc2 and to stabilize the same, the respective output voltages from the step upchopper circuit 6 and the phaseshift inverter circuit 7 are feed back controlled so as to meet with the first and second voltage command values 22 a and 22 b outputted from thesequencer 22 in the MRI apparatus. - As shown in
FIG. 1 , the voltage Vdc1 at thesecond smoothing capacitor 12 and the voltage Vdc2 at thethird smoothing capacitor 13 are detected by the insulatingvoltage detectors 12 a and 12 b and the phase difference in the phaseshift inverter circuit 7 is controlled so that the difference between these detected values and the secondvoltage command value 22 b outputted from thesequencer 22 in the MRI apparatus assumes zero, thereby, the two DC power source voltages Vdc1 and Vdc2 can be stabilized at a same voltage. - Likely, with regard to the input DC power source voltage Vdcc to the phase
shift inverter circuit 7, namely, the output voltage Vdcc of the step upchopper circuit 6, the rate of conduction and non-conduction of the semiconductor switch in the step upchopper circuit 6 is controlled so that the difference between the value detected by thevoltage detector 6 e and the firstvoltage command value 22 a outputted from thesequencer 22 in the MRI apparatus assumes zero, thereby, the input DC power source voltage Vdcc to the phaseshift inverter circuit 7 can be stabilized. - Further, since the DC power source voltages Vdc1 and Vdc2 of the multi level
PWM inverter circuit 18 are feed back controlled by the phaseshift inverter circuit 7 to stabilize the same, the output voltage of the step upchopper circuit 6 is sometimes unnecessary to be feed back controlled. - Although the sum of the DC power source voltages Vdc1 and Vdc2 is required to be a high DC voltage of about 2000 [V], according to the first embodiment of the present invention, since two elements of the step up
chopper circuit 6 and the insulatingtransformers - For example, a commercial power source voltage of 200 [V] is converted to a DC by the first AC-
DC converter 4, a voltage of about 282[V] (200×√{square root over (2)}) obtained by smoothing the converted DC voltage is stepped up three times to 864 [V] by the step up chopper circuit 6 (in view of the withstanding voltage of the semiconductor switches of IGBT) and when the stepped up voltage is further stepped up to about 2.5 times by the insulatingtransformers - In this instance, as has been explained above, when the frequency of the input voltage to the insulating
transformers shift inverter circuit 7, the size of the insulatingtransformers - In this manner, since the step up ratio by the step up
chopper circuit 6 and the transformation ratio of theinsulation transformers shift inverter circuit 7 is inputted to the insulatingtransformers shift inverter circuit 7 is constituted by the two sets of full bridge inverter circuits including three arms, the size and cost of the DC high voltage power source for the multi levelPWM inverter circuit 18 can be reduced. -
FIG. 6 is a circuit constitution diagram of a gradient magnetic field power source device for an MRI apparatus representing a second embodiment of a power source device according to the present invention. - Among the constitutional elements for generating a high DC voltage, since the constitution up to the step up
chopper circuit 6 is the same as that in the first embodiment as shown inFIG. 1 , inFIG. 6 , only a phaseshift inverter circuit 60 and an AC-DC step up and convertingunit 50 are illustrated, and as the multi level PWM inverter circuit receiving the output of the AC-DC step up and convertingunit 50, a multi levelPWM inverter circuit 30 of 5 levels is used and to which output side theX axis coil 15 is connected as the load thereof. Further, the semiconductor switching control device for thecircuit 30 and a circuit for driving the semiconductor switches in the multi levelPWM inverter circuit 30 after amplifying the output signal from the device above are omitted. - Still further, although like multi level
PWM inverter circuit 30 of 5 levels is used for theY axis coil 16 and theZ axis coil 17, herein, only the case in connection with theX axis coil 15 will be explained. - In the multi level
PWM inverter circuit 30 of 5 levels, a DC voltage power source of 5 levels from 0 level, 1/4 level, 2/4 level (=1/2 level), 3/4 level and the maximum level of 4/4 level is required as the DC power sources. - In the second embodiment, in order to obtain these four same DC voltages, the output voltage Vdcc (voltage at the
fourth smoothing capacitor 6 d) from the step uptype chopper circuit 6 as shown inFIG. 1 is converted into four AC voltages by the phaseshift inverter circuit 60, and the AC voltages are converted into DC by the AC-DC step up and convertingunit 50. - The phase
shift inverter circuit 60 is constituted by being provided with five arms of anarm 1 includingsemiconductor 60 a and 60 b, anarm 2 includingsemiconductor arm 3 includingsemiconductor arm 4 includingsemiconductor arm 5 includingsemiconductor arms arms arms arms switching control device 60 k for performing switching control of the semiconductor switches in these full bridge inverter circuits and adrive circuit 60 g for driving the semiconductor switches after amplifying the output from the thirdswitching control device 60 k. - Further, a diode is connected in antiparallel to the respective semiconductor switches 60 a˜60 j.
- The third
switching control device 60 k is constituted by a phase difference PWM control signal producing unit 60 l which produces a control signal for meeting the DC power source voltage to the multi levelPWM inverter circuit 30 of 5 levels with the thirdvoltage command value 22 d outputted from thesequencer 22 in the MRI apparatus and a third phase shift unit 60 m, a fourth phase shift unit 60 n, a fifth phase shift unit 60 o and a third phase shift unit 60 p each shifts the phase of the signal produced by the phase difference PWM controlsignal producing unit 60 i in a delayed phase or an advanced phase. - With the four full bridge inverter circuits in which the
arm 1 is in common for all of the full bridge inverter circuits, the conduction control of the semiconductor switches is performed by making use of one of the first, second and third control methods which are explained in connection with the first embodiment as shown inFIG. 1 to obtain four AC voltages of a same value. - Namely, with respect to the conduction phase of the semiconductor switches in the
arm 1, the corresponding semiconductor switches in thearms 2˜5 are conduction controlled in a delayed phase or in an advance phase, thereby, the input DC voltage Vdcc is converted to an AC voltage Vac3 by the first full bridge inverter circuit constituted by thearms arms arms arms transformers unit 50. - In the AC-DC step up and converting
unit 50, the four AC voltages Vac3˜Vac6 converted by the phaseshift inverter circuit 60 are stepped up by the insulatingtransformers capacitors PWM inverter circuit 30 of 5 levels. - In order to keep these four DC voltages Vdc3, Vdc4, Vdc5 and Vdc6 at a stable voltage of a same value with no variation, the voltages Vdc3, Vdc4, Vdc5 and Vdc6 are detected by insulating
voltage detectors switching control device 60 k so as to meet the DC voltages Vdc3, Vdc4, Vdc5 and Vdc6 with the thirdvoltage command value 22 d as explained previously. - Such full bridge inverter circuits for controlling the four AC voltages independently require 16 pieces of semiconductor switches conventionally, however, 10 pieces of semiconductor switches are enough for the second embodiment of the present invention, therefore, the number of the semiconductor switches and of the circuits for driving these semiconductor switches are reduced.
- Further, as has been explained in connection with the first embodiment, by making use of any one of the first, second and third control methods for the conduction control of the semiconductor switches, the heat radiating installation in view of the losses caused in the semiconductor switches in the respective arms is optimized, the surge voltage suppressing means is minimized and proper semiconductor switches are selected, thereby, a small sized and inexpensive inverter circuit can be realized.
- The multi level
PWM inverter circuit 30 of 5 levels is constituted in such a manner that to the inputs thereof DC voltage sources E and E0 (voltage=Vdc3+Vdc4+Vdc5+Vdc6) are connected and any voltage waveforms are outputted at output terminals A and B, and further includes four sets ofarms 31˜34 constituted by connecting in series four pairs of semiconductor switches 30 a, 30 b, 30 c and 30 d anddiodes - Between the connection point of the smoothing
capacitor 33 a and the smoothingcapacitor 33 b and the respective connection points of the semiconductor switches 30 a and 30 b in therespective arms 31˜34 in the full bridge structure,diodes 35˜38 are respectively connected, further, between the connection point of the smoothingcapacitor 33 b and the smoothingcapacitor 33 c and the respective connection points of the semiconductor switches 30 b and 30 c in therespective arms 31˜34,diodes 39˜42 are respectively connected, and likely between the connection point of the smoothingcapacitor 33 c and the smoothingcapacitor 33 d and the respective connection points of the semiconductor switches 30 c and 30 d in therespective arms 31˜34, diodes 43˜46 are respectively connected. - Herein, when the semiconductor switches 30 a˜30 d in the
arm 31 are rendered conductive, voltage +E is outputted at the output terminal A, when the semiconductor switches 30 b˜30 d in thearm 31 and thesemiconductor switch 30 a in thearm 32 are rendered conductive, voltage +E 3/4 is outputted at the output terminal A, when the semiconductor switches 30 c and 30 d in thearm 31 and the semiconductor switches 30 a and 30 b in thearm 32 are rendered conductive, voltage +E 1/2 is outputted at the output terminal A, when thesemiconductor switch 30 d in thearm 31 and thesemiconductor switch 30 a˜30 c in thearm 32 are rendered conductive, voltage +E 1/4 is outputted at the output terminal A, further, when the semiconductor switches 30 a˜30 d in thearm 32 are rendered conductive, voltage 0 is outputted at the output terminal A, in this manner, voltages of five levels can be outputted at the output terminal A. - Further, the above is true with regard to the output terminal B, resultantly, nine voltages from −E to +E are outputted as voltages between the output terminals A and B.
- Further, through performing the PWM control thereon any desired voltages from −E to +E can be outputted.
- Since 5 level
PWM inverter circuit 30 divides the DC voltage source between E˜E0 into four voltages Vdc3, Vdc4, Vdc5 and Vdc6, therespective arms 31˜34 likely divide the same with the foursemiconductor switches 30 a˜30 d and the respective connection points thereof are connected via thediodes 35˜46, thereby, only the divided DC voltage component is applied to therespective semiconductor switches 30˜30 d, accordingly, even when semiconductor switches having a low withstand voltage are used, a large output can be obtained. -
FIG. 7 is a circuit constitution diagram of a gradient magnetic field power source device for an MRI apparatus representing a third embodiment of a power source device according to the present invention. - In the third embodiment, since only a major portion of a phase
shift inverter circuit 70 is different from that of the second embodiment as shown inFIG. 6 and the others thereof are the same as those in the second embodiment, herein, only the constitution of the phaseshift inverter circuit 70 will be explained. - The phase
shift inverter circuit 70 inFIG. 7 uses two sets of phaseshift inverter circuits 7 in the first embodiment as shown inFIG. 1 and converts the output voltage Vdcc from the step upchopper circuit 6 into four voltages Vdc3, Vdc4, Vdc5 and Vdc6. - Namely, with the
arm 1 formed bysemiconductor switches arm 2 formed bysemiconductor switches arm 3 formed bysemiconductor switches arm 4 formed bysemiconductor switches arm 5 formed bysemiconductor switches arm 6 formed bysemiconductor switches 70 k and 70 l, two sets of full bridge inverter circuits are constituted. - In the two sets of full bridge inverter circuits constituted by the
arms 1˜3, a first full bridge inverter circuit is constituted by thearms arms arm 1 is used in common for the first and second full bridge inverter circuits. - Likely, in the two sets of full bridge inverter circuit constituted by the
arms 4˜6, a third full bridge inverter circuit is constituted by thearms arms arm 4 is used in common for the third and fourth full bridge inverter circuits. - With the four full bridge inverter circuits, the conduction control of the semiconductor switches is performed by making use of one of the first, second and third control methods which are explained in connection with the first embodiment as shown in
FIG. 1 to obtain four AC voltages of a same value. - Namely, with respect to the conduction phase of the semiconductor switches in the
arm 1, the corresponding semiconductor switches in thearms arms arms - Likely, with respect to the conduction phase of the semiconductor switches in the
arm 4, the corresponding semiconductor switches in thearms arms arms - Such full bridge inverter circuit for controlling the four AC voltages independently requires 16 pieces of semiconductor switches conventionally, however, 12 pieces of semiconductor switches are enough for the third embodiment of the present invention, therefore, the number of the semiconductor switches and of the circuits for driving these semiconductor switches are reduced.
- Further, by making use of any one of the first, second and third control methods for the conduction control of the semiconductor switches, the heat radiating installation in view of the losses caused in the semiconductor switches in the respective arms is optimized, the surge voltage suppressing means is minimized and proper semiconductor switches are selected, thereby, a small sized and inexpensive inverter circuit can be realized.
-
FIG. 8 is a fourth embodiment of a power source device according to the present invention in which the step uptype chopper circuit 6 in the DC high voltage power source for the multi level PWM inverter circuit of 3 levels for the first embodiment and 5 levels for the second and third embodiments is improved and shows a circuit constitutional diagram of a fourth AC-DC converter 80 which has a function of converting the AC voltage from the commercial three phaseAC voltage source 3 as well as full wave rectifying the three phase AC power source voltage and stepping up to a higher voltage than that obtained when smoothing the rectified voltage, and the DC voltage stepped up by theconverter 80 is applied as the DC power source for the phaseshift inverter circuits - The fourth AC-
DC converter 80 as shown inFIG. 8 is constituted by a three phase full wave rectifying circuit formed by self extinguishable semiconductor switches 80 a˜80 f of IGBTs anddiodes 80 g˜80 l connected in antiparallel thereto,reactors AC power source 3, a smoothingcapacitor 80 p for smoothing the output voltage from the three phase full wave rectifying circuit, avoltage detector 80 q for detection the voltage at the smoothingcapacitor 80 q, a fourthswitching control device 80 r which performs switching control of the semiconductor switches so that the detection value of thevoltage detector 80 q meets with the firstvoltage command value 22 a from thesequencer 22 in the MRI apparatus and acircuit 80 s which amplifies a switching control signal outputted from the switchingcontrol device 80 r to a predetermined value and drives the semiconductor switches 80 a˜80 f. - As disclosed in JP-A-7-65987, the fourth AC-
DC converter 80 performs pulse width modulation control (PWM control) on the semiconductor switches 80 a˜80 f so that the detection value of thevoltage detector 80 q meets with the firstvoltage command value 22 a from thesequencer 22 in the MRI apparatus, stores the electro magnetic energy in thereactors capacitor 80 p charges the smoothingcapacitor 80 p at a voltage higher than that of the AC power source. - Namely, the voltage is stepped up to a voltage, for example, about 846 [V] as stepped up by the step up
type chopper circuit 6 in the first embodiment. - Further, through provision of a phase current and
phase voltage detector 80 t for detecting the phase current and the phase voltage of the three phaseAC power source 3, the fourth AC-DC converter 80 can meet the phases of phase current with the phase voltage of the AC power source by performing the pulse width modulation control on the semiconductor switches 80 a˜80 f in response to a phase difference between the phase current and the phase voltage of the AC power source and an error between the output voltage of the smoothingcapacitor 80 p and theset value 22 a (the first voltage command value), thereby, such advantages can be obtained that the power factor is increased and the apparent power is decreased, thus, the current required to be flown through the fourth AC-DC converter 80 can be reduced as well as the capacity of the three phase AC power source installation can also be reduced. - As has been explained above, according to the fourth embodiment of the present invention, such advantages are obtained that the size and cost of the DC high voltage power source for the gradient magnetic field power source device making use of the multi level PWM inverter circuit can be reduced as well as the capacity of the three phase AC power source installation can also be reduced.
- Further, in the above embodiments, an example is explained in which the stabilization is performed by the feed back controlling (to the phase
shift inverter circuits type chopper circuit 6 and the fourth AC-DC converter 80) the DC power source voltage to the multi level PWM converter circuit, however, since the control measure for meeting the current flowing through the gradient magnetic field coil representing the load with the current command values 22c 1, 22 c 2 and 22 c 3 is provided, when the variation of the DC power source caused due to voltage variation of the commercial AC power source and others is in a predetermined range, the feed back control can be dispensed with. - Accordingly, the feed back control of the DC power source voltage to the multi level PWM inverter circuit can be applied depending on the necessity.
- Further, in the above embodiments, an example is explained in which as the semiconductor switches the IGBTs are used for the fourth AC-
DC converter 80, the step uptype chopper circuit 6, the phaseshift inverter circuit - Still further, in the above embodiments, as the current amplifier, examples of the multi level PWM inverter circuits of 3 levels and 5 levels are explained, however, the present invention is not limited thereto, and a multi level PWM inverter circuit of more than 5 levels can be used to which a DC power source constituted according to the idea of the above embodiments is applied.
- Still further, in the above embodiments, an example is explained in which as the load the gradient magnetic field coil in the MRI apparatus is connected to the power source device according to the present invention, the coil for generating the static magnetic field and the high frequency magnetic field can be connected and used as the load.
- Still further, in the above embodiments, an example is illustrated in which number of DC voltages produced by the AC-DC step up and converting unit is an even number, however, DC voltages of odd number can be produced thereby.
Claims (16)
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JP2005-193317 | 2005-07-01 | ||
JP2005193317 | 2005-07-01 | ||
PCT/JP2006/313102 WO2007004565A1 (en) | 2005-07-01 | 2006-06-30 | Power source device, and magnetic resonance imaging apparatus using the device |
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US20100045113A1 true US20100045113A1 (en) | 2010-02-25 |
US7928600B2 US7928600B2 (en) | 2011-04-19 |
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US11/993,818 Expired - Fee Related US7928600B2 (en) | 2005-07-01 | 2006-06-30 | Power source device and magnetic resonance imaging apparatus using the same |
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Also Published As
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JP5020077B2 (en) | 2012-09-05 |
US7928600B2 (en) | 2011-04-19 |
JPWO2007004565A1 (en) | 2009-01-29 |
WO2007004565A1 (en) | 2007-01-11 |
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