US20100019354A1 - Semiconductor chip shape alteration - Google Patents
Semiconductor chip shape alteration Download PDFInfo
- Publication number
- US20100019354A1 US20100019354A1 US12/573,364 US57336409A US2010019354A1 US 20100019354 A1 US20100019354 A1 US 20100019354A1 US 57336409 A US57336409 A US 57336409A US 2010019354 A1 US2010019354 A1 US 2010019354A1
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- US
- United States
- Prior art keywords
- semiconductor chip
- semiconductor
- chip
- wafer
- corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 230000004075 alteration Effects 0.000 title description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 230000000977 initiatory effect Effects 0.000 abstract description 4
- 230000032798 delamination Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000009623 Bosch process Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates generally to semiconductor devices, and more particularly to a semiconductor chip shape alteration.
- the shape of a semiconductor chip is important to semiconductor technology.
- the shape of a semiconductor chip can cause physical stress on the semiconductor chip. Stress on the semiconductor chip causes delamination, which is the fracture of a semiconductor chip's Back End of the Line (“BEOL”) materials, which in turn leads to semiconductor chip failure.
- BEOL Back End of the Line
- Prior art semiconductor chips are limited to square and rectangular shapes, which introduce the most stress on the semiconductor chip, because of the ninety degree corners inherent in such shapes.
- FIGS. 1 a - 1 b depict a prior art semiconductor wafer 100 and chip 110 . Note the perpendicular dicing channels 102 in the prior art semiconductor wafer 100 . Once diced, singulated die, also known as semiconductor chips, are separated from the semiconductor wafer 100 . Once separated, the semiconductor chips 110 have a square or rectangular shape. FIG. 1 b highlights the problem associated with prior art semiconductor chips 110 . More specifically, a semiconductor chip 110 diced from the prior art semiconductor wafer 100 results in a square or rectangular semiconductor chip 110 .
- Prior art square and rectangular semiconductor chip 110 shapes introduce stress on the semiconductor chip 110 , and particularly at the corners 108 . Such stress causes delamination, which is a problem in prior art semiconductor chips 110 . Often delamination begins in the triangular zone 106 and travels toward the active area 112 of the semiconductor chip 110 . Once delamination reaches the active area 112 , the semiconductor chip 110 fails. While prior art semiconductor chips 110 include a crackstop, which functions to prevent delamination into the active area 112 , crackstops 112 are largely ineffective as semiconductor technology evolves because low-k dielectric is more frequently used. Low k dielectric material is particularly susceptible to delamination.
- the invention is directed to a method for creating a semiconductor chip.
- the method comprises a creating and dicing step.
- the creating step comprises creating a hole in a semiconductor wafer comprising semiconductor chips separated by dicing channels.
- the hole is created at an intersection of the dicing channels.
- the dicing step comprises dicing through the dicing channels and a portion of the semiconductor chip at the intersection of the dicing channels.
- the invention solves the problem of delamination by creation of a semiconductor chip without any ninety degree corners.
- the absence of ninety degree corners reduces physical stress on the semiconductor chip, which in turn mitigates against delamination.
- Prior art methods for semiconductor chip creation focus on dicing efficiency and manufacturing cost minimization.
- Prior art methods specify neither the alteration of semiconductor chip shape nor the influence of chip shape on stress to the semiconductor chip.
- the invention solves the aforementioned problems associated with prior art semiconductor chips.
- the invention improves semiconductor technology.
- FIG. 1 a depicts a prior art semiconductor wafer 100 ;
- FIG. 1 b depicts a prior art semiconductor chip diced from the semiconductor wafer 100 of FIG. 1 a;
- FIG. 2 a depicts a semiconductor wafer 200 of a first embodiment of the invention
- FIG. 2 b depicts a semiconductor chip 210 diced from the semiconductor wafer 200 of FIG. 2 a;
- FIG. 3 depicts a semiconductor wafer 300 of a second embodiment of the invention.
- FIG. 4 depicts a semiconductor wafer 400 of a third embodiment of the invention.
- the invention is directed to a method for creating a semiconductor chip absent any ninety degree angles.
- the semiconductor chip originates from a semiconductor wafer with dicing channels that separate semiconductor chips and holes at each intersection of the dicing channels. Once diced, semiconductor chips are created without any ninety degree angles.
- the semiconductor wafer 200 includes holes 220 at the intersection of the dicing channels 102 .
- the holes 220 can be created by laser drilling, Bosch process deep drilling, photolithography followed by reactive ion etching, or ion milling.
- semiconductor chips 210 as shown in FIG. 2 a are created.
- the semiconductor wafer 200 can be diced by mechanical saw blade dicing or laser dicing.
- FIG. 2 b further depicts the semiconductor chip 210 diced from the semiconductor wafer 200 of FIG. 2 a.
- the semiconductor chip 210 does not have a corner with a ninety degree angle 220 . Therefore, the semiconductor chip 210 has a reduced underfill to hard passivation layer (triangular zone 106 ).
- the triangular zone 106 is substantially reduced in the embodiment, while maintaining the crackstop 104 .
- the substantially reduced triangular zone 106 reduces the initiation, and therefore the propagation of cracks in the semiconductor chip 210 .
- FIG. 2 a depicts holes 220 with a circle shape
- FIGS. 3-4 depict holes 220 of another shape.
- FIG. 3 depicts a semiconductor wafer 300 of a further embodiment of the invention. More specifically, FIG. 3 depicts holes 220 with a diamond shape. Similar to the holes 220 with a circle shape shown in FIG. 2 a, the holes 220 with a diamond shape in FIG. 3 , substantially reduces the triangular zone 106 (not shown), which in turn reduces the initiation and propagation of cracks in the semiconductor chip 210 .
- the semiconductor chip 310 in FIG. 3 similar to the semiconductor chip in FIG. 2 b, has the advantage of corners without ninety degree corners.
- the exploded view 310 a of a corner of the semiconductor chip shown in FIG. 3 As shown in the exploded view 310 a , the corner of the semiconductor chip does not have a ninety degree corner.
- FIG. 4 depicts a semiconductor wafer 400 of a third embodiment of the invention. Similar to the semiconductor chips in FIGS. 2 b and 3 , the semiconductor chip 410 in FIG. 4 does not have a ninety degree corner. The corner in the semiconductor chip 410 of FIG. 4 has a concave shape. As shown in the exploded view 410 a of the semiconductor chip 410 the corner has a concave shape, which necessarily requires that the corner does not have a ninety degree corner. Similar to FIGS. 1-3 , the semiconductor wafer 400 has dicing channels 102 . Further, similar to FIGS. 2 a and 3 , the semiconductor wafer 400 has holes 220 . The shape of the holes 220 in the semiconductor wafer 400 of FIG. 4 creates a corner in the semiconductor chip 410 with a concave shape.
- FIGS. 2 a - 4 reduce delamination initiation and propagation by eliminating semiconductor chips with corners having ninety degree angles.
- the invention solves the aforementioned problems associated with prior art semiconductor chips. More specifically, the invention eliminates any corner with a ninety degree angle in a semiconductor chip.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Dicing (AREA)
Abstract
Description
- This application is a divisional of currently co-pending U.S. patent application Ser. No. 11/615,236 filed Dec. 22, 2006.
- 1. Field of the Invention
- The invention relates generally to semiconductor devices, and more particularly to a semiconductor chip shape alteration.
- 2. Description of the Related Art
- The shape of a semiconductor chip is important to semiconductor technology. The shape of a semiconductor chip can cause physical stress on the semiconductor chip. Stress on the semiconductor chip causes delamination, which is the fracture of a semiconductor chip's Back End of the Line (“BEOL”) materials, which in turn leads to semiconductor chip failure. Prior art semiconductor chips are limited to square and rectangular shapes, which introduce the most stress on the semiconductor chip, because of the ninety degree corners inherent in such shapes.
-
FIGS. 1 a-1 b depict a priorart semiconductor wafer 100 andchip 110. Note theperpendicular dicing channels 102 in the priorart semiconductor wafer 100. Once diced, singulated die, also known as semiconductor chips, are separated from thesemiconductor wafer 100. Once separated, thesemiconductor chips 110 have a square or rectangular shape.FIG. 1 b highlights the problem associated with priorart semiconductor chips 110. More specifically, asemiconductor chip 110 diced from the prior art semiconductor wafer 100 results in a square orrectangular semiconductor chip 110. - Prior art square and
rectangular semiconductor chip 110 shapes introduce stress on thesemiconductor chip 110, and particularly at thecorners 108. Such stress causes delamination, which is a problem in priorart semiconductor chips 110. Often delamination begins in thetriangular zone 106 and travels toward the active area 112 of thesemiconductor chip 110. Once delamination reaches the active area 112, thesemiconductor chip 110 fails. While priorart semiconductor chips 110 include a crackstop, which functions to prevent delamination into the active area 112, crackstops 112 are largely ineffective as semiconductor technology evolves because low-k dielectric is more frequently used. Low k dielectric material is particularly susceptible to delamination. - What is needed in the art is an improved semiconductor chip shape that reduces delamination.
- The invention is directed to a method for creating a semiconductor chip. The method comprises a creating and dicing step. The creating step comprises creating a hole in a semiconductor wafer comprising semiconductor chips separated by dicing channels. The hole is created at an intersection of the dicing channels. The dicing step comprises dicing through the dicing channels and a portion of the semiconductor chip at the intersection of the dicing channels.
- The invention solves the problem of delamination by creation of a semiconductor chip without any ninety degree corners. The absence of ninety degree corners reduces physical stress on the semiconductor chip, which in turn mitigates against delamination.
- Prior art methods for semiconductor chip creation focus on dicing efficiency and manufacturing cost minimization. Prior art methods specify neither the alteration of semiconductor chip shape nor the influence of chip shape on stress to the semiconductor chip. Even were prior art methods to focus on alteration of semiconductor chip shape, which prior art methods have not, prior art methods would not focus on the increased propensity of certain semiconductors materials to cause delamination within the semiconductor chips. More specifically, as semiconductor technology evolves, low k dielectric materials are more frequently utilized, which are prone to delamination.
- The invention solves the aforementioned problems associated with prior art semiconductor chips.
- For at least the foregoing reasons, the invention improves semiconductor technology.
- The features and the element characteristics of the invention are set forth with particularity in the appended claims. The figures are for illustrative purposes only and are not drawn to scale. Furthermore, like numbers represent like features in the drawings. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows, taken in conjunction with the accompanying figures, in which:
-
FIG. 1 a depicts a priorart semiconductor wafer 100; -
FIG. 1 b depicts a prior art semiconductor chip diced from thesemiconductor wafer 100 ofFIG. 1 a; -
FIG. 2 a depicts asemiconductor wafer 200 of a first embodiment of the invention; -
FIG. 2 b depicts asemiconductor chip 210 diced from thesemiconductor wafer 200 ofFIG. 2 a; -
FIG. 3 depicts asemiconductor wafer 300 of a second embodiment of the invention; and, -
FIG. 4 depicts asemiconductor wafer 400 of a third embodiment of the invention. - The invention will now be described with reference to the accompanying figures. In the figures, various aspects of the structures have been depicted and schematically represented in a simplified manner to more clearly describe and illustrate the invention.
- By way of overview and introduction, the invention is directed to a method for creating a semiconductor chip absent any ninety degree angles. The semiconductor chip originates from a semiconductor wafer with dicing channels that separate semiconductor chips and holes at each intersection of the dicing channels. Once diced, semiconductor chips are created without any ninety degree angles.
- An embodiment of the
invention 200 will be described with reference to theFIG. 2 a. As shown thesemiconductor wafer 200 includesholes 220 at the intersection of thedicing channels 102. Theholes 220 can be created by laser drilling, Bosch process deep drilling, photolithography followed by reactive ion etching, or ion milling. Once thesemiconductor wafer 200 is diced,semiconductor chips 210 as shown inFIG. 2 a are created. Thesemiconductor wafer 200 can be diced by mechanical saw blade dicing or laser dicing. -
FIG. 2 b further depicts thesemiconductor chip 210 diced from thesemiconductor wafer 200 ofFIG. 2 a. As shown, thesemiconductor chip 210 does not have a corner with a ninetydegree angle 220. Therefore, thesemiconductor chip 210 has a reduced underfill to hard passivation layer (triangular zone 106). Note that thetriangular zone 106 is substantially reduced in the embodiment, while maintaining thecrackstop 104. The substantially reducedtriangular zone 106 reduces the initiation, and therefore the propagation of cracks in thesemiconductor chip 210. WhileFIG. 2 a, depictsholes 220 with a circle shape,FIGS. 3-4 depictholes 220 of another shape. -
FIG. 3 depicts asemiconductor wafer 300 of a further embodiment of the invention. More specifically,FIG. 3 depictsholes 220 with a diamond shape. Similar to theholes 220 with a circle shape shown inFIG. 2 a, theholes 220 with a diamond shape inFIG. 3 , substantially reduces the triangular zone 106 (not shown), which in turn reduces the initiation and propagation of cracks in thesemiconductor chip 210. Note that thesemiconductor chip 310 inFIG. 3 , similar to the semiconductor chip inFIG. 2 b, has the advantage of corners without ninety degree corners. Note the explodedview 310 a of a corner of the semiconductor chip shown inFIG. 3 . As shown in the explodedview 310 a, the corner of the semiconductor chip does not have a ninety degree corner. -
FIG. 4 depicts asemiconductor wafer 400 of a third embodiment of the invention. Similar to the semiconductor chips inFIGS. 2 b and 3, thesemiconductor chip 410 inFIG. 4 does not have a ninety degree corner. The corner in thesemiconductor chip 410 ofFIG. 4 has a concave shape. As shown in the explodedview 410 a of thesemiconductor chip 410 the corner has a concave shape, which necessarily requires that the corner does not have a ninety degree corner. Similar toFIGS. 1-3 , thesemiconductor wafer 400 has dicingchannels 102. Further, similar toFIGS. 2 a and 3, thesemiconductor wafer 400 hasholes 220. The shape of theholes 220 in thesemiconductor wafer 400 ofFIG. 4 creates a corner in thesemiconductor chip 410 with a concave shape. - Unlike the prior art depicted in
FIGS. 1 a-b, the embodiments depicted inFIGS. 2 a-4 reduce delamination initiation and propagation by eliminating semiconductor chips with corners having ninety degree angles. - The invention solves the aforementioned problems associated with prior art semiconductor chips. More specifically, the invention eliminates any corner with a ninety degree angle in a semiconductor chip.
- While the invention has been particularly described in conjunction with a specific preferred embodiment and other alternative embodiments, it is evident that numerous alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore intended that the appended claims embrace all such alternatives, modifications and variations as falling within the true scope and spirit of the invention.
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/573,364 US20100019354A1 (en) | 2006-12-22 | 2009-10-05 | Semiconductor chip shape alteration |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/615,236 US7648891B2 (en) | 2006-12-22 | 2006-12-22 | Semiconductor chip shape alteration |
US12/573,364 US20100019354A1 (en) | 2006-12-22 | 2009-10-05 | Semiconductor chip shape alteration |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/615,236 Division US7648891B2 (en) | 2006-12-22 | 2006-12-22 | Semiconductor chip shape alteration |
Publications (1)
Publication Number | Publication Date |
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US20100019354A1 true US20100019354A1 (en) | 2010-01-28 |
Family
ID=39541640
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US11/615,236 Expired - Fee Related US7648891B2 (en) | 2006-12-22 | 2006-12-22 | Semiconductor chip shape alteration |
US12/573,364 Abandoned US20100019354A1 (en) | 2006-12-22 | 2009-10-05 | Semiconductor chip shape alteration |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/615,236 Expired - Fee Related US7648891B2 (en) | 2006-12-22 | 2006-12-22 | Semiconductor chip shape alteration |
Country Status (6)
Country | Link |
---|---|
US (2) | US7648891B2 (en) |
EP (1) | EP2095419A4 (en) |
JP (1) | JP2010514223A (en) |
KR (1) | KR20090101915A (en) |
CN (1) | CN101584042A (en) |
WO (1) | WO2008079662A1 (en) |
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US20110227201A1 (en) * | 2010-03-22 | 2011-09-22 | Too Seah S | Semiconductor chip with a rounded corner |
US8916980B2 (en) * | 2012-02-16 | 2014-12-23 | Omnivision Technologies, Inc. | Pad and circuit layout for semiconductor devices |
US20150069576A1 (en) * | 2013-09-12 | 2015-03-12 | Infineon Technologies Ag | Semiconductor Device and Method for Manufacturing a Semiconductor Device |
US9728518B2 (en) | 2014-04-01 | 2017-08-08 | Ati Technologies Ulc | Interconnect etch with polymer layer edge protection |
US20190140207A1 (en) * | 2017-04-20 | 2019-05-09 | Boe Technology Group Co., Ltd. | Method for fabricating display panel, display panel and display apparatus |
US10340306B1 (en) * | 2018-02-08 | 2019-07-02 | Semiconductor Components Industries, Llc | Semiconductor package with chamfered corners and related methods |
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2006
- 2006-12-22 US US11/615,236 patent/US7648891B2/en not_active Expired - Fee Related
-
2007
- 2007-12-11 WO PCT/US2007/087082 patent/WO2008079662A1/en active Application Filing
- 2007-12-11 CN CNA2007800465609A patent/CN101584042A/en active Pending
- 2007-12-11 JP JP2009543064A patent/JP2010514223A/en active Pending
- 2007-12-11 KR KR1020097013802A patent/KR20090101915A/en not_active Application Discontinuation
- 2007-12-11 EP EP07865500A patent/EP2095419A4/en not_active Withdrawn
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- 2009-10-05 US US12/573,364 patent/US20100019354A1/en not_active Abandoned
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US8916980B2 (en) * | 2012-02-16 | 2014-12-23 | Omnivision Technologies, Inc. | Pad and circuit layout for semiconductor devices |
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US9356092B2 (en) * | 2013-09-12 | 2016-05-31 | Infineon Technologies Ag | Semiconductor device and method for manufacturing a semiconductor device |
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US10608042B2 (en) * | 2018-02-08 | 2020-03-31 | Semiconductor Components Industries, Llc | Semiconductor package with chamfered corners and related methods |
US10340306B1 (en) * | 2018-02-08 | 2019-07-02 | Semiconductor Components Industries, Llc | Semiconductor package with chamfered corners and related methods |
US11676913B2 (en) | 2020-05-12 | 2023-06-13 | Samsung Electronics Co., Ltd. | Semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
US20080150087A1 (en) | 2008-06-26 |
US7648891B2 (en) | 2010-01-19 |
JP2010514223A (en) | 2010-04-30 |
WO2008079662A1 (en) | 2008-07-03 |
EP2095419A4 (en) | 2011-03-16 |
KR20090101915A (en) | 2009-09-29 |
CN101584042A (en) | 2009-11-18 |
EP2095419A1 (en) | 2009-09-02 |
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