US20090206315A1 - Integrated circuit including u-shaped access device - Google Patents
Integrated circuit including u-shaped access device Download PDFInfo
- Publication number
- US20090206315A1 US20090206315A1 US12/033,519 US3351908A US2009206315A1 US 20090206315 A1 US20090206315 A1 US 20090206315A1 US 3351908 A US3351908 A US 3351908A US 2009206315 A1 US2009206315 A1 US 2009206315A1
- Authority
- US
- United States
- Prior art keywords
- region
- layer
- substrate
- access device
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
- This application is related to U.S. patent application Ser. No. ______, Attorney Docket Number Q600.128.101, entitled “INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE,” filed on the same date as the present application, which is incorporated herein by reference.
- One type of memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic “1” data bit value and a memory element programmed to have a low resistance value may represent a logic “0” data bit value. Typically, the resistance value of the memory element is switched electrically by applying a voltage pulse or a pattern of voltage pulses or a current pulse or a pattern of current pulses to the memory element.
- One type of resistive memory is phase change memory. Phase change memory uses a phase change material in the resistive memory element. The phase change material exhibits at least two different states. The states of the phase change material may be referred to as the amorphous state and the crystalline state, where the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered lattice. The amorphous state usually exhibits higher resistivity than the crystalline state. Also, some phase change materials exhibit multiple crystalline states, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state, which have different resistivities and may be used to store bits of data. In the following description, the amorphous state generally refers to the state having the higher resistivity and the crystalline state generally refers to the state having the lower resistivity.
- Phase changes in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state—“set”—and from the crystalline state to the amorphous state—“reset”—in response to temperature changes. The temperature changes of the phase change material may be achieved by driving current through the phase change material itself or by driving current through a resistive heater adjacent the phase change material. With both of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material.
- A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse or a pattern of pulses that is applied to the phase change material. The temperature in the phase change material in each memory cell generally corresponds to the applied level of current and/or voltage to achieve the heating.
- To achieve higher density phase change memories, a phase change memory cell can store multiple bits of data. Multi-bit storage in a phase change memory cell can be achieved by programming the phase change material to have intermediate resistance values or states, where the multi-bit or multilevel phase change memory cell can be written to more than two states. If the phase change memory cell is programmed to one of three different resistance levels, 1.5 bits of data per cell can be stored. If the phase change memory cell is programmed to one of four different resistance levels, two bits of data per cell can be stored, and so on. To program a phase change memory cell to an intermediate resistance value, the amount of crystalline material coexisting with amorphous material and hence the cell resistance is controlled via a suitable write strategy.
- Higher density phase change memories can also be achieved by reducing the physical size of each memory cell. Increasing the density of a phase change memory increases the amount of data that can be stored within the memory while at the same time typically reducing the cost of the memory. A relatively high current is used to reset a phase change memory cell. The access device used to access a phase change memory cell has to be capable of providing the high current. The high current can most efficiently (i.e., with the smallest memory cell size) be provided by a bipolar device such as a diode. Diodes are typically fabricated after transistor formation using a selective epitaxy process, which requires an ultra-high vacuum chemical vapor deposition (UHV-CVD) tool to meet the temperature budget requirements.
- For these and other reasons, there is a need for the present invention.
- One embodiment provides an integrated circuit. The integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
- The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
-
FIG. 1 is a block diagram illustrating one embodiment of a system. -
FIG. 2 is a diagram illustrating one embodiment of a memory device. -
FIG. 3 illustrates a cross-sectional view of one embodiment of a U-shaped diode access device. -
FIG. 4 illustrates a cross-sectional view of one embodiment of a bipolar transistor access device. -
FIG. 5 illustrates a cross-sectional view of one embodiment of an array of diode access devices. -
FIG. 6 illustrates a cross-sectional view of another embodiment of an array of diode access devices. -
FIG. 7 illustrates a cross-sectional view of one embodiment of an array of bipolar transistor access devices. -
FIG. 8 illustrates a cross-sectional view of another embodiment of an array of bipolar transistor access devices. -
FIG. 9A illustrates a top view of one embodiment of a substrate. -
FIG. 9B illustrates a cross-sectional view of one embodiment of the substrate. -
FIG. 9C illustrates another cross-sectional view of one embodiment of the substrate perpendicular to the view illustrated inFIG. 9B . -
FIG. 10A illustrates a cross-sectional view of one embodiment of the substrate after doping. -
FIG. 10B illustrates a cross-sectional view of one embodiment of the substrate after doping including optional co-implants. -
FIG. 11 illustrates a cross-sectional view of one embodiment of the substrate, a doped polysilicon layer, a word line material layer, and a nitride layer. -
FIG. 12 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, word lines, and the nitride layer after etching. -
FIG. 13 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, and an optional nitride layer. -
FIG. 14 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, and a polysilicon layer. -
FIG. 15 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and an oxide layer. -
FIG. 16 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, a polysilicon layer, and the oxide layer after etching. -
FIG. 17 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and the oxide layer after oxidation. -
FIG. 18 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and oxide. -
FIG. 19 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the oxide, and a doped polysilicon layer. -
FIG. 20 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, the nitride layer, and the oxide after annealing. -
FIG. 21 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, the nitride layer, the oxide, and a contact material layer. -
FIG. 22 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, a nitride layer, the oxide, the contact material layer, and a bottom electrode material layer. -
FIG. 23A illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, a nitride layer, the oxide, the contact material layer, the bottom electrode material layer, a phase change material layer, and a top electrode material layer. -
FIG. 23B illustrates another cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, the nitride layer, the oxide, the contact material layer, the bottom electrode material layer, the phase change material layer, and the top electrode material layer. -
FIG. 23C illustrates another cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, the nitride layer, the oxide, the contact material layer, the bottom electrode material layer, the phase change material layer, and the top electrode material layer. -
FIG. 24A illustrates a top view of one embodiment of the substrate, the doped polysilicon layers, the word lines, a nitride layer, the oxide, a contact, a bottom electrode, a phase change element, and a bit line after etching. -
FIG. 24B illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, the nitride layer, the oxide, the contact, the phase change element, and the bit line after etching. -
FIG. 24C illustrates another cross-sectional view of one embodiment of the substrate, the doped polysilicon layers, the word lines, the nitride layer, the oxide, the contact, the phase change element, and the bit line after etching. -
FIG. 25A illustrates a top view of another embodiment of a substrate. -
FIG. 25B illustrates a cross-sectional view of one embodiment of the substrate. -
FIG. 25C illustrates another cross-sectional view of one embodiment of the substrate perpendicular to the view illustrated inFIG. 25B . -
FIG. 26A illustrates a cross-sectional view of one embodiment of the substrate after doping. -
FIG. 26B illustrates a cross-sectional view of one embodiment of the substrate after doping including optional co-implants. -
FIG. 27 illustrates a cross-sectional view of one embodiment of the substrate, a doped polysilicon layer, a word line material layer, and a nitride layer. -
FIG. 28 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, word lines, and the nitride layer after etching. -
FIG. 29 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, and an optional nitride layer. -
FIG. 30 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, and a polysilicon layer. -
FIG. 31 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and an oxide layer. -
FIG. 32 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, the oxide layer, and a mask layer. -
FIG. 33 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and the oxide layer after etching a first opening. -
FIG. 34 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and the oxide layer after etching a second opening. -
FIG. 35 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and the oxide layer after oxidation. -
FIG. 36 illustrates a cross-sectional view of one embodiment of the substrate, the doped polysilicon layer, the word lines, the nitride layer, the polysilicon layer, and oxide. - In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
-
FIG. 1 is a block diagram illustrating one embodiment of asystem 90.System 90 includes ahost 92 and amemory device 100.Host 92 is communicatively coupled tomemory device 100 throughcommunication link 94.Host 92 includes a microprocessor, computer (e.g., desktop, laptop, handheld), portable electronic device (e.g., cellular phone, personal digital assistant (PDA), MP3 player, video player, digital camera), or any other suitable device that uses memory.Memory device 100 provides memory forhost 92. In one embodiment,memory device 100 provides embedded memory forhost 92 andhost 92 andmemory device 100 are included on a single integrated circuit or circuit board. In one embodiment,memory device 100 includes a phase change memory device or other suitable resistive or resistivity changing material memory device. -
FIG. 2 is a diagram illustrating one embodiment ofmemory device 100.Memory device 100 includes awrite circuit 124, acontroller 120, amemory array 102, and asense circuit 126.Memory array 102 includes a plurality of resistive memory cells 104 a-104 d (collectively referred to as resistive memory cells 104), a plurality of bit lines (BLs) 112 a-112 b (collectively referred to as bit lines 112), and a plurality of word lines (WLs) 110 a-110 b (collectively referred to as word lines 110). In one embodiment, resistive memory cells 104 are phase change memory cells. In other embodiments, resistive memory cells 104 are another suitable type of resistive memory cells or resistivity changing memory cells. - Each memory cell 104 includes a phase change element 106 and a diode 108. Diodes 108 are U-shaped and formed in a silicon on insulator (SOI) substrate or local SOI structures between isolation regions. As used herein, the term “U-shaped” includes any substantially U, J, or backward J shape. In another embodiment, diodes 108 are replaced by bipolar transistors. The bipolar transistors are U-shaped and formed in a substrate having a common potential, such as ground. The bipolar transistors are formed between isolations regions such that one side of each bipolar transistor is coupled to common or ground. Therefore, the bipolar transistors function similarly to diodes. Diodes 108 are fabricated without selective epitaxy, which requires the use of an ultra-high vacuum chemical vapor deposition (UHV-CVD) tool to meet the temperature budget requirements.
- As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements.
-
Memory array 102 is electrically coupled to writecircuit 124 throughsignal path 125, tocontroller 120 through signal path 121, and tosense circuit 126 throughsignal path 127.Controller 120 is electrically coupled to writecircuit 124 throughsignal path 128 and to sensecircuit 126 throughsignal path 130. Each phase change memory cell 104 is electrically coupled to a word line 110 and a bit line 112. Phasechange memory cell 104 a is electrically coupled tobit line 112 a andword line 110 a, and phasechange memory cell 104 b is electrically coupled tobit line 112 a andword line 110 b. Phase change memory cell 104 c is electrically coupled tobit line 112 b andword line 110 a, and phasechange memory cell 104 d is electrically coupled tobit line 112 b andword line 110 b. - Each phase change memory cell 104 includes a phase change element 106 and a diode 108. Phase
change memory cell 104 a includesphase change element 106 a anddiode 108 a. One side ofphase change element 106 a is electrically coupled tobit line 112 a, and the other side ofphase change element 106 a is electrically coupled to one side ofdiode 108 a. The other side ofdiode 108 a is electrically coupled toword line 110 a. In another embodiment, the polarity ofdiode 108 a is reversed. - Phase
change memory cell 104 b includesphase change element 106 b anddiode 108 b. One side ofphase change element 106 b is electrically coupled tobit line 112 a, and the other side ofphase change element 106 b is electrically coupled to one side ofdiode 108 b. The other side ofdiode 108 b is electrically coupled toword line 110 b. - Phase change memory cell 104 c includes
phase change element 106 c anddiode 108 c. One side ofphase change element 106 c is electrically coupled tobit line 112 b and the other side ofphase change element 106 c is electrically coupled to one side ofdiode 108 c. The other side ofdiode 108 c is electrically coupled toword line 110 a. - Phase
change memory cell 104 d includesphase change element 106 d anddiode 108 d. One side ofphase change element 106 d is electrically coupled tobit line 112 b and the other side ofphase change element 106 d is electrically coupled to one side ofdiode 108 d. The other side ofdiode 108 d is electrically coupled toword line 110 b. - In another embodiment, each phase change element 106 is electrically coupled to a word line 110 and each diode 108 is electrically coupled to a bit line 112. For example, for phase
change memory cell 104 a, one side ofphase change element 106 a is electrically coupled toword line 110 a. The other side ofphase change element 106 a is electrically coupled to one side ofdiode 108 a. The other side ofdiode 108 a is electrically coupled tobit line 112 a. - In one embodiment, each phase change element 106 comprises a phase change material that may be made up of a variety of materials. Generally, chalcogenide alloys that contain one or more elements from Group VI of the periodic table are useful as such materials. In one embodiment, the phase change material is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe, or AgInSbTe. In another embodiment, the phase change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S.
- Each phase change element 106 may be changed from an amorphous state to a crystalline state or from a crystalline state to an amorphous state under the influence of temperature change. The amount of crystalline material coexisting with amorphous material in the phase change material of one of the phase change elements thereby defines two or more states for storing data within
memory device 100. In the amorphous state, a phase change material exhibits significantly higher resistivity than in the crystalline state. Therefore, the two or more states of the phase change elements differ in their electrical resistance. In one embodiment, the two or more states are two states and a binary system is used, wherein the two states are assigned bit values of “0” and “1”. In another embodiment, the two or more states are three states and a ternary system is used, wherein the three states are assigned bit values of “0”, “1”, and “2”. In another embodiment, the two or more states are four states that are assigned multi-bit values, such as “00”, “01”, “10”, and “11”. In other embodiments, the two or more states can be any suitable number of states in the phase change material of a phase change element. -
Controller 120 includes a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation ofmemory device 100.Controller 120 controls read and write operations ofmemory device 100 including the application of control and data signals tomemory array 102 throughwrite circuit 124 andsense circuit 126. In one embodiment, writecircuit 124 provides voltage pulses throughsignal path 125 and bit lines 112 to memory cells 104 to program the memory cells. In other embodiments, writecircuit 124 provides current pulses throughsignal path 125 and bit lines 112 to memory cells 104 to program the memory cells. -
Sense circuit 126 reads each of the two or more states of memory cells 104 through bit lines 112 andsignal path 127. In one embodiment, to read the resistance of one of the memory cells 104,sense circuit 126 provides current that flows through one of the memory cells 104.Sense circuit 126 then reads the voltage across that one of the memory cells 104. In another embodiment,sense circuit 126 provides voltage across one of the memory cells 104 and reads the current that flows through that one of the memory cells 104. In another embodiment, writecircuit 124 provides voltage across one of the memory cells 104 andsense circuit 126 reads the current that flows through that one of the memory cells 104. In another embodiment, writecircuit 124 provides current that flows through one of the memory cells 104 andsense circuit 126 reads the voltage across that one of the memory cells 104. - In one embodiment, during a set operation of phase
change memory cell 104 a, one or more set current or voltage pulses are selectively enabled bywrite circuit 124 and sent throughbit line 112 a to phasechange element 106 a, thereby heatingphase change element 106 a above its crystallization temperature (but usually below its melting temperature). In this way,phase change element 106 a reaches its crystalline state or a partially crystalline and partially amorphous state during this set operation. - During a reset operation of phase
change memory cell 104 a, a reset current or voltage pulse is selectively enabled bywrite circuit 124 and sent throughbit line 112 a to phasechange element 106 a. The reset current or voltage quickly heatsphase change element 106 a above its melting temperature. After the current or voltage pulse is turned off,phase change element 106 a quickly quench cools into the amorphous state or a partially amorphous and partially crystalline state. - Phase
change memory cells 104 b-104 d and other phase change memory cells 104 inmemory array 102 are set and reset similarly to phasechange memory cell 104 a using similar current or voltage pulses. In other embodiments, for other types of resistive memory cells, writecircuit 124 provides suitable programming pulses to program the resistive memory cells 104 to the desired state. -
FIG. 3 illustrates a cross-sectional view of one embodiment of a U-shapeddiode access device 200. In one embodiment, a U-shapeddiode access device 200 is used for each diode 108 previously described and illustrated with reference toFIG. 2 . U-shapeddiode access device 200 includes a silicon on insulator (SOI) substrate orlocal SOI structure 204, polysilicon layers orcontacts lines substrate 204, which includesinsulation material 202 andsilicon regions - The diode includes a lightly doped (n−)
region 206, a heavily doped (n+)region 208, and a heavily doped (p+)region 210. The top of n− dopedregion 206 contacts the bottom of n+doped region 208 and the bottom of p+doped region 210. In one embodiment, n+doped region 208 is in the same horizontal plane as p+doped region 210 and is isolated from p+doped region 210 bydielectric material 218, thereby giving the diode a U-shape. In another embodiment, n+doped region 208 is not in the same horizontal plane as p+doped region 210, but n+ dopedregion 208 is still isolated from p+doped region 210 bydielectric material 218, thereby maintaining the U-shape of the diode. In another embodiment, the polarity of the diode is reversed, such thatregion 206 is p− doped,region 208 is p+ doped, andregion 210 is n+ doped. - The top of n+ doped
region 208 contacts the bottom of n+doped polysilicon layer 212. The top of n+ dopedpolysilicon layer 212 contacts the bottom of contact orline 216. The top of p+ dopedregion 210 contacts the bottom of p+doped polysilicon layer 214. The top of p+ dopedpolysilicon layer 214 contacts the bottom of contact orline 220. The n+ dopedpolysilicon layer 212 is in the same horizontal plane as p+doped polysilicon layer 214, and contact orline 216 is in the same horizontal plane as contact orline 220. The n+ dopedpolysilicon layer 212 and contact orline 216 are separated from p+doped polysilicon layer 214 and contact orline 220 bydielectric material 218. In another embodiment, where the polarity of the diode is reversed,polysilicon layer 212 is p+ doped andpolysilicon layer 214 is n+ doped. - In one embodiment,
dielectric material 218 is self-aligned between contacts orlines Insulation material 202 anddielectric material 218 includes SiO2, SiOx, SixNy, fluorinated silica glass (FSG), boro-phosphorous silicate glass (BPSG), boro-silicate glass (BSG), or other suitable dielectric material. In one embodiment, contact orline 216 is a word line and contact orline 220 is a contact for coupling to a phase change element. Contacts orlines -
FIG. 4 illustrates a cross-sectional view of one embodiment of a bipolartransistor access device 230. In one embodiment, a U-shaped bipolartransistor access device 230 is used in place of each diode 108 previously described and illustrated with reference toFIG. 2 . U-shaped bipolartransistor access device 230 includes asilicon substrate 232, polysilicon layers orcontacts lines substrate 232, which includessilicon regions - The bipolar transistor includes a p doped
region 234, an n− dopedregion 206, an n+ dopedregion 208, and a p+ dopedregion 210. In one embodiment, p dopedregion 234 is electrically coupled to common or ground such that the emitter-base path of the bipolar transistor acts as a diode. The top of p dopedregion 234 contacts the bottom of n− dopedregion 206. The top of n− dopedregion 206 contacts the bottom of n+doped region 208 and the bottom of p+doped region 210. In one embodiment, n+doped region 208 is in the same horizontal plane as p+doped region 210 and is isolated from p+doped region 210 bydielectric material 218, thereby giving the bipolar transistor a U-shape. In another embodiment, n+doped region 208 is not in the same horizontal plane as p+doped region 210, but n+ dopedregion 208 is still isolated from p+doped region 210 bydielectric material 218, thereby maintaining the U-shape of the bipolar transistor. In another embodiment, the polarity of the bipolar transistor is reversed, such thatregion 234 is n doped,region 206 is p− doped,region 208 is p+ doped, andregion 210 is n+ doped. - The top of n+ doped
region 208 contacts the bottom of n+doped polysilicon layer 212. The top of n+ dopedpolysilicon layer 212 contacts the bottom of contact orline 216. The top of p+ dopedregion 210 contacts the bottom of p+doped polysilicon layer 214. The top of p+ dopedpolysilicon layer 214 contacts the bottom of contact orline 220. The n+polysilicon layer 212 is in the same horizontal plane as p+doped polysilicon layer 214, and contact orline 216 is in the same horizontal plane as contact orline 220. The n+ dopedpolysilicon layer 212 and contact orline 216 are separated from p+doped polysilicon layer 214 and contact orline 220 bydielectric material 218. In another embodiment, where the polarity of the bipolar transistor is reversed,polysilicon layer 212 is p+ doped andpolysilicon layer 214 is n+ doped. - In one embodiment,
dielectric material 218 is self-aligned between contacts orlines Dielectric material 218 includes SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. In one embodiment, contact orline 216 is a word line and contact orline 220 is a contact for coupling to a phase change element. Contacts orlines -
FIG. 5 illustrates a cross-sectional view of one embodiment of anarray 240 ofdiode access devices 200. In one embodiment,array 240 is used to provide diodes 108 ofmemory array 102 previously described and illustrated with reference toFIG. 2 . Eachdiode access device 200 is similar todiode access device 200 previously described and illustrated with reference toFIG. 3 . Eachdiode access device 200 includesdielectric material 218, which is self-aligned between each contact orline 216 and each contact orline 220 of eachdiode access device 200. Adjacentdiode access devices 200 are isolated from each other byinsulation material 242, which is processed separately.Insulation material dielectric material 218 include SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. -
FIG. 6 illustrates a cross-sectional view of another embodiment of anarray 250 ofdiode access devices 200. In one embodiment,array 250 is used to provide diodes 108 ofmemory array 102 previously described and illustrated with reference toFIG. 2 . Eachdiode access device 200 is similar todiode access device 200 previously described and illustrated with reference toFIG. 3 . Eachdiode access device 200 includesdielectric material 218, which is self-aligned between each contact orline 216 and each contact orline 220 of eachdiode access device 200. Adjacentdiode access devices 200 are isolated from each other byinsulation material 252, which is self-aligned between a contact orline 216 of onediode access device 200 and a contact orline 220 of an adjacentdiode access device 200.Insulation material dielectric material 218 include SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. -
FIG. 7 illustrates a cross-sectional view of one embodiment of anarray 260 of bipolartransistor access devices 230. In one embodiment,array 260 is used to provide diodes 108 ofmemory array 102 previously described and illustrated with reference toFIG. 2 . Each bipolartransistor access device 230 is similar to bipolartransistor access device 230 previously described and illustrated with reference toFIG. 4 . Each bipolartransistor access device 230 includesdielectric material 218, which is self-aligned between each contact orline 216 and each contact orline 220 of each bipolartransistor access device 230. Adjacent bipolartransistor access devices 230 are isolated from each other byinsulation material 262, which is processed separately.Insulation material 262 anddielectric material 218 include SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. -
FIG. 8 illustrates a cross-sectional view of another embodiment of anarray 270 of bipolartransistor access devices 230. In one embodiment,array 270 is used to provide diodes 108 ofmemory array 102 previously described and illustrated with reference toFIG. 2 . Each bipolartransistor access device 230 is similar to bipolartransistor access device 230 previously described and illustrated with reference toFIG. 4 . Each bipolartransistor access device 230 includesdielectric material 218, which is self-aligned between each contact orline 216 and each contact orline 220 of each bipolartransistor access device 230. Adjacent bipolartransistor access devices 230 are isolated from each other byinsulation material 272, which is self-aligned between a contact orline 216 of one bipolartransistor access device 230 and a contact orline 220 of an adjacent bipolartransistor access device 230.Insulation material 272 anddielectric material 218 include SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. - The following
FIGS. 9A-36 illustrate embodiments for a fabricating a phase change memory cell, such as a phase change memory cell 104 previously described and illustrated with reference toFIG. 2 . Although the followingFIGS. 9A-36 illustrate embodiments of a process for fabricating a phase change memory cell including a grounded bipolar transistor access device formed in a silicon substrate as previously described and illustrated with reference toFIG. 4 , the illustrated process is also applicable to a phase change memory cell including a diode access device formed in a SOI structure or substrate as previously described and illustrated with reference toFIG. 3 . -
FIG. 9A illustrates a top view andFIGS. 9B and 9C illustrate cross-sectional views of one embodiment of asubstrate 300.Substrate 300 includesinsulation material 302 and anactive area 304. In one embodiment,insulation material 302 includes isolation trenches and/or shallow trench isolation.Insulation material 302 laterally surrounds the top portion ofactive area 304.Insulation material 302 includes SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. -
FIG. 10A illustrates a cross-sectional view of one embodiment ofsubstrate 300 after doping.Active area 304 ofsubstrate 300 is doped to provide p dopedregion 234 and n− dopedregion 308. The top of p dopedregion 234 contacts the bottom of n− dopedregion 308.Insulation material 302 laterally surrounds n− dopedregion 308.Active area 304 is doped using ion implantation or another suitable technique. -
FIG. 10B illustrates a cross-sectional view of one embodiment ofsubstrate 300 after doping includingoptional co-implants 3 10. This optional embodiment is similar to the embodiment previously described and illustrated with reference toFIG. 10A , except that in this embodiment co-implants 310 are included for controlling doping diffusion.Co-implants 310 are implanted near the surface of n− dopedregion 308. Co-implants 310 include sulfur, carbon, or other suitable material. While the followingFIGS. 11-24C illustratesubstrate 300 withoutco-implants 310,substrate 300 withco-implants 310 may also be used. -
FIG. 11 illustrates a cross-sectional view of one embodiment ofsubstrate 300, a dopedpolysilicon layer 312 a, a wordline material layer 314, and anitride layer 316 a. An n+ doped polysilicon is deposited oversubstrate 300 to provide n+ dopedpolysilicon layer 312 a.Polysilicon layer 312 a is deposited using chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), high density plasma-chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), jet vapor deposition (JVD), or other suitable deposition technique. - An electrically conductive material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, CoSi, NiSi, NiPtSi, WSi, a combination thereof, or other suitable word line material is deposited over n+
doped polysilicon layer 312 a to provide wordline material layer 314. Wordline material layer 314 is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. A nitride, such as SixNy or another suitable dielectric material is deposited over wordline material layer 314 to providenitride layer 316 a.Nitride layer 316 a is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. -
FIG. 12 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 312 b, word lines 216, andnitride layer 316 b after etching.Nitride layer 316 a, wordline material layer 314, and n+ dopedpolysilicon layer 312 a are etched to provide opening ortrench 318 and n+ dopedpolysilicon layer 312 b, word lines 216, andnitride layer 316 b.Trench 318 is defined using a suitable lithography process such thattrench 318 is above a portion of n− dopedregion 308 and a portion ofinsulation material 302. -
FIG. 13 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 312 b, word lines 216, and anoptional nitride layer 320. A nitride, such as SixNy or another suitable dielectric material is deposited over exposed portions ofnitride layer 316 b, word lines 216, and n+ dopedpolysilicon layer 312 b. The nitride layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The nitride layer is then spacer etched to expose a portion of n+doped polysilicon layer 312 b and to providenitride layer 320, which includesnitride layer 316 b.Nitride layer 320 encapsulatesword lines 216 to protectword lines 216 from oxidation during subsequent processing. In other embodiments, where a non-oxidizing material is used forword lines 216, word lines 216 are not encapsulated. -
FIG. 14 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 312 b, word lines 216,nitride layer 320, and apolysilicon layer 322. Polysilicon is deposited over exposed portions ofnitride layer 320 and n+ dopedpolysilicon layer 312 b to providepolysilicon layer 322.Polysilicon layer 322 is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. In one embodiment,polysilicon layer 322 is in situ p doped or p doped using ion implantation. In another embodiment,polysilicon layer 322 is replaced with an amorphous silicon layer. -
FIG. 15 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 312 b, word lines 216,nitride layer 320,polysilicon layer 322, and anoxide layer 324. An oxide, such as SiO2 or other suitable oxide is deposited overpolysilicon layer 322 to provide an oxide layer. The oxide layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The oxide layer is then back-etched to provideoxide layer 324 and to expose portions ofpolysilicon layer 322. -
FIG. 16 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 212, word lines 216,nitride layer 320, apolysilicon layer 330, andoxide layer 324 after etching. The exposed portions ofpolysilicon layer 322 and the underlying portions of n+ dopedpolysilicon layer 312 b are selectively etched to exposenitride layer 320, a portion of n− dopedregion 308, and a portion ofinsulation material 302. The etching provides n+ dopedpolysilicon layer 212 andpolysilicon layer 330, which includes portions of n+ dopedpolysilicon layer 312 b andpolysilicon layer 322. The exposed portion of n− dopedregion 308 is etched to provide opening ortrench 326. The exposed portion ofinsulation material 302 is etched to provide opening ortrench 328. In one embodiment, the depth ofopening 326 is greater than the depth ofopening 328. -
FIG. 17 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 212, word lines 216,nitride layer 320,polysilicon layer 330, andoxide layer 324 after oxidation. The exposed portions ofpolysilicon layers region 308 are oxidized to provideoxide 334. In one embodiment, where word lines 216 are not encapsulated bynitride layer 320, the exposed portions ofpolysilicon layers region 308 are selectively oxidized to provideoxide 334. -
FIG. 18 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 212, word lines 216,nitride layer 320,polysilicon layer 330, andoxide 336. In one embodiment, a nitride is used in place ofoxide 336. An oxide or nitride, such as SiO2, SixNy, or other suitable dielectric material is deposited overnitride layer 320,oxide layer 324, andoxide 324 to provide an oxide or nitride layer. The oxide or nitride layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The oxide or nitride layer andoxide layer 324 are then back-etched to provideoxide 336 and to exposenitride layer 320 andpolysilicon layer 330. -
FIG. 19 illustrates a cross-sectional view of one embodiment ofsubstrate 300, dopedpolysilicon layer 212, word lines 216,nitride layer 320,oxide 336, and a dopedpolysilicon layer 214 a. In one embodiment,polysilicon layer 330 is doped and/or counter doped to provide p+ dopedpolysilicon layer 214 a. In another embodiment,polysilicon layer 330 is back-etched and a p+ doped polysilicon layer is then deposited to provide p+ dopedpolysilicon layer 214 a. In another embodiment,polysilicon layer 330 is back-etched and an undoped polysilicon layer is then deposited. The undoped polysilicon layer is then doped using ion implantation or another suitable technique to provide p+ dopedpolysilicon layer 214 a. -
FIG. 20 illustrates a cross-sectional view of one embodiment ofsubstrate 232, dopedpolysilicon layers nitride layer 320, andoxide 336 after annealing.Substrate 300 and dopedpolysilicon layers substrate 232. During annealing, dopants from n+ dopedpolysilicon layer 212 diffuse into the underlying n− dopedregion 308 and dopants from p+ dopedpolysilicon layer 214 a diffuse into the underlying n− dopedregion 308. The diffusion of dopants from n+ dopedpolysilicon layer 212 into n− dopedregion 308 provides n+ dopedregion 208. The diffusion of dopants from p+ dopedpolysilicon layer 214 a into n− dopedregion 308 provides p+ dopedregion 210. The bottom of n+doped region 208 and the bottom of p+doped region 210 contact the top of n− dopedregion 206. The n+ dopedregion 208 is in the same horizontal plane as p+doped region 210 and is separated from p+doped region 210 byoxide 336. Therefore, a U-shaped bipolar transistor is formed insubstrate 232. -
FIG. 21 illustrates a cross-sectional view of one embodiment ofsubstrate 232, dopedpolysilicon layers nitride layer 320,oxide 336, and acontact material layer 338 a. An electrically conductive material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, CoSi, NiSi, NiPtSi, WSi, a combination thereof, or other suitable contact material is deposited over exposed portions ofnitride layer 320,oxide 336, and p+ dopedpolysilicon layer 214 a to provide a contact material layer. The contact material layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The contact material layer is then planarized to exposenitride layer 320 and to providecontact material layer 338 a. The contact material layer is planarized using chemical mechanical planarization (CMP) or another suitable planarization technique. -
FIG. 22 illustrates a cross-sectional view of one embodiment ofsubstrate 232, dopedpolysilicon layers nitride layer 342 a,oxide 336, acontact material layer 338 b, and a bottomelectrode material layer 340 a.Contact material layer 338 a is recess etched to providecontact material layer 338 b. A nitride, such as SixNy or other suitable dielectric material is deposited overnitride layer 320 andcontact material layer 338 b to provide a nitride layer. The nitride layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The nitride layer is then spacer etched to expose a portion ofcontact material layer 338 b and to providenitride layer 342 a, which includesnitride layer 320. - An electrically conductive material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, CoSi, NiSi, NiPtSi, WSi, a combination thereof, or other suitable electrode material is deposited over exposed portions of
nitride layer 342 a andcontact material layer 338 b to provide an electrode material layer. The electrode material layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The electrode material layer is then planarized to exposenitride layer 342 a and to provide bottomelectrode material layer 340 a. The electrode material layer is planarized using CMP or another suitable planarization technique. In one embodiment, bottomelectrode material layer 340 a has tapered sidewalls. In other embodiments, bottomelectrode material layer 340 a has another suitable shape. -
FIG. 23A illustrates a cross-sectional view of one embodiment ofsubstrate 232, dopedpolysilicon layers nitride layer 342 b,oxide 336,contact material layer 338 b, bottomelectrode material layer 340 a, a phasechange material layer 344 a, and a topelectrode material layer 346 a.FIG. 23B illustrates another cross-sectional view through n+ dopedpolysilicon layer 212 and perpendicular to the view illustrated in FIG. 23A.FIG. 23C illustrates another cross-sectional view through p+ dopedpolysilicon layer 214 a and perpendicular to the view illustrated inFIG. 23A . - A nitride, such as SixNy or other suitable dielectric material is deposited over
nitride layer 342 a andelectrode material layer 340 a to provide a nitride layer. The nitride layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The nitride layer is then etched to form a trench exposing a portion ofelectrode material layer 340 a and to providenitride layer 342 b, which includesnitride layer 342 a. - A phase change material, such as a chalcogenide compound material or other suitable phase change material is deposited over exposed portions of
nitride layer 342 b and bottomelectrode material layer 340 a to provide phasechange material layer 344 a. Phasechange material layer 344 a is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. An electrically conductive material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, CoSi, NiSi, NiPtSi, WSi, a combination thereof, or other suitable electrode material is deposited over phasechange material layer 344 a to provide topelectrode material layer 346 a. Topelectrode material layer 346 a is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. -
FIG. 24A illustrates a top view andFIGS. 24B and 24C illustrate cross-sectional views of one embodiment ofsubstrate 232, dopedpolysilicon layers nitride layer 342,oxide 336, acontact 220, abottom electrode 340, aphase change element 344, and abit line 346 after etching. Topelectrode material layer 346 a, phasechange material layer 344 a,nitride layer 342 b, bottomelectrode material layer 340 a,contact material layer 338 b, and p+ dopedpolysilicon layer 214 a are etched to exposeinsulation material 302 and to provide p+ dopedpolysilicon layer 214, contact 220,bottom electrode 340,nitride layer 342,phase change element 344, and bitline 346. In this way, p+ dopedpolysilicon layer 214, contact 220,bottom electrode 340, and phase change element 244 are self-aligned to bitline 346. - Insulation material, such SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material is deposited over exposed portions of
insulation material 302, p+doped polysilicon layer 214, contact 220,bottom electrode 340,nitride layer 342,phase change element 344, and bitline 346 to provide an insulation material layer (not shown). The insulation material layer is then planarized to exposebit line 346. The insulation material layer is planarized using CMP or another suitable planarization technique. In other embodiments,bottom electrode 340,nitride layer 342, andphase change element 344 are fabricated to provide any suitably shapedbottom electrode 340 andphase change element 344. - The following
FIGS. 25A-36 illustrate another embodiment for fabricating a phase change memory cell, such as a phase change memory cell 104 previously described and illustrated with reference toFIG. 2 . -
FIG. 25A illustrates a top view andFIGS. 25B and 25C illustrate cross-sectional views of another embodiment of asubstrate 400.Substrate 400 includesinsulation material 402 and anactive area 404. In one embodiment,insulation material 402 includes isolation trenches.Active area 404 is betweeninsulation material 402.Insulation material 402 includes SiO2, SiOx, SixNy, FSG, BPSG, BSG, or other suitable dielectric material. -
FIG. 26A illustrates a cross-sectional view of one embodiment ofsubstrate 400 after doping.Active area 404 ofsubstrate 400 is doped to provide p dopedregion 234 and n− dopedregion 408. The top of p dopedregion 234 contacts the bottom of n− dopedregion 408.Active area 404 is doped using ion implantation or another suitable technique. -
FIG. 26B illustrates a cross-sectional view of one embodiment ofsubstrate 400 after doping includingoptional co-implants 410. This optional embodiment is similar to the embodiment previously described and illustrated with reference toFIG. 26A , except that in this embodiment co-implants 410 are included for controlling doping diffusion.Co-implants 410 are implanted near the surface of n− dopedregion 408. Co-implants 410 include sulfur, carbon, or other suitable material. While the followingFIGS. 27-36 illustratesubstrate 400 withoutco-implants 410,substrate 400 withco-implants 410 may also be used. -
FIG. 27 illustrates a cross-sectional view of one embodiment ofsubstrate 400, a dopedpolysilicon layer 312 a, a wordline material layer 314, and anitride layer 316 a. An n+ doped polysilicon is deposited oversubstrate 400 to provide n+ dopedpolysilicon layer 312 a.Polysilicon layer 312 a is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. - An electrically conductive material, such as TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN, TiAlN, TaAlN, Cu, WN, CoSi, NiSi, NiPtSi, WSi, a combination thereof, or other suitable word line material is deposited over n+
doped polysilicon layer 312 a to provide wordline material layer 314. Wordline material layer 314 is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. A nitride, such as SixNy or another suitable dielectric material is deposited over wordline material layer 314 to providenitride layer 316 a.Nitride layer 316 a is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. -
FIG. 28 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 312 b, word lines 216, andnitride layer 316 b after etching.Nitride layer 316 a, wordline material layer 314, and n+ dopedpolysilicon layer 312 a are etched to provide opening ortrench 318 and n+ dopedpolysilicon layer 312 b, word lines 216, andnitride layer 316 b.Trench 318 is defined using a suitable lithography process. -
FIG. 29 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 312 b, word lines 216, and anoptional nitride layer 320. A nitride, such as SixNy or another suitable dielectric material is deposited over exposed portions ofnitride layer 316 b, word lines 216, and n+ dopedpolysilicon layer 312 b. The nitride layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The nitride layer is then spacer etched to expose a portion of n+doped polysilicon layer 312 b and to providenitride layer 320, which includesnitride layer 316 b.Nitride layer 320 encapsulatesword lines 216 to protectword lines 216 from oxidation during subsequent processing. In other embodiments, where a non-oxidizing material is used forword lines 216, word lines 216 are not encapsulated. -
FIG. 30 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 312 b, word lines 216,nitride layer 320, and apolysilicon layer 322. Polysilicon is deposited over exposed portions ofnitride layer 320 and n+ dopedpolysilicon layer 312 b to providepolysilicon layer 322.Polysilicon layer 322 is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. In one embodiment,polysilicon layer 322 is in situ p doped or p doped using ion implantation. -
FIG. 31 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 312 b, word lines 216,nitride layer 320,polysilicon layer 322, and anoxide layer 324. An oxide, such as SiO2 or other suitable oxide is deposited overpolysilicon layer 322 to provide an oxide layer. The oxide layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The oxide layer is then back-etched to provideoxide layer 324 and to expose portions ofpolysilicon layer 322. -
FIG. 32 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 312 b, word lines 216,nitride layer 320,polysilicon layer 322,oxide layer 324, and amask layer 410.Mask layer 410, such as a hardmask or other suitable mask is formed over a portion ofpolysilicon layer 322 andoxide layer 324. -
FIG. 33 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 312 c, word lines 216,nitride layer 320, apolysilicon layer 412, andoxide layer 324 after etching afirst opening 414 a. The exposed portions ofpolysilicon layer 322 are selectively etched to providepolysilicon layer 412 and to expose portions ofnitride layer 320 and portions of n+ dopedpolysilicon layer 312 b. The exposed portions of n+ dopedpolysilicon layer 312 b are then etched to provide n+polysilicon layer 312 c and to expose a portion ofactive area 404 ofsubstrate 400. The exposed portion ofactive area 404 ofsubstrate 400 is etched to provide first opening or trench 414 a.Mask layer 410 is then removed. -
FIG. 34 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 212, word lines 216,nitride layer 320,polysilicon layer 330, andoxide layer 324 after etching asecond opening 416. The exposed portions ofpolysilicon layer 412 and the underlying portion of n+dopedpolysilicon layer 312 c are selectively etched to exposenitride layer 320 and a portion ofactive area 404 ofsubstrate 400. The etching provides n+ dopedpolysilicon layer 212 andpolysilicon layer 330, which includes portions of n+dopedpolysilicon layer 312 c andpolysilicon layer 412. The exposed portion ofactive area 404 ofsubstrate 400 is etched to provide second opening ortrench 416 and to expandfirst opening 414 a to providefirst opening 414. In one embodiment, the depth ofsecond opening 416 is less than the depth offirst opening 414. -
FIG. 35 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 212, word lines 216,nitride layer 320,polysilicon layer 330, andoxide layer 324 after oxidation. The exposed portions ofpolysilicon layers active area 404 ofsubstrate 400 are oxidized to provideoxide 418. In one embodiment, where word lines 216 are not encapsulated bynitride layer 320, the exposed portions ofpolysilicon layers active area 404 ofsubstrate 400 are selectively oxidized to provideoxide 418. -
FIG. 36 illustrates a cross-sectional view of one embodiment ofsubstrate 400, dopedpolysilicon layer 212, word lines 216,nitride layer 320,polysilicon layer 330, andoxide 336. In one embodiment, a nitride is used in place ofoxide 336. An oxide or nitride, such as SiO2, SixNy, or other suitable dielectric material is deposited overnitride layer 320,oxide layer 324, andoxide 418 to provide an oxide or nitride layer. The oxide or nitride layer is deposited using CVD, LPCVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitable deposition technique. The oxide or nitride layer andoxide layer 324 are then back-etched to provideoxide 336 and to exposenitride layer 320 andpolysilicon layer 330. A process similar to the process previously described and illustrated with reference toFIGS. 19-24C is then performed to complete the fabrication of the phase change memory cell. - Embodiments provide U-shaped diodes or bipolar transistors for accessing resistive memory cells. Contact to the U-shaped diodes or bipolar transistors is made from the top of the access devices through polysilicon layers, which provide large metal to silicon transition areas. An array of the U-shaped access devices does not include buried metal lines thereby avoiding large series resistances. In addition, the self-alignment of the memory cells reduces area consumption to provide smaller memory cells compared to typical memory cells.
- While the specific embodiments described herein substantially focused on using phase change memory elements, the embodiments can be applied to any suitable type of resistive or resistivity changing memory elements.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (25)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/033,519 US7829879B2 (en) | 2008-02-19 | 2008-02-19 | Integrated circuit including U-shaped access device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/033,519 US7829879B2 (en) | 2008-02-19 | 2008-02-19 | Integrated circuit including U-shaped access device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090206315A1 true US20090206315A1 (en) | 2009-08-20 |
US7829879B2 US7829879B2 (en) | 2010-11-09 |
Family
ID=40954253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/033,519 Expired - Fee Related US7829879B2 (en) | 2008-02-19 | 2008-02-19 | Integrated circuit including U-shaped access device |
Country Status (1)
Country | Link |
---|---|
US (1) | US7829879B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080308860A1 (en) * | 2007-06-18 | 2008-12-18 | Samsung Electronics Co., Ltd. | Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same |
US20090206316A1 (en) * | 2008-02-19 | 2009-08-20 | Qimonda Ag | Integrated circuit including u-shaped access device |
US20090218556A1 (en) * | 2008-02-28 | 2009-09-03 | Shoaib Zaidi | Integrated circuit fabricated using an oxidized polysilicon mask |
US8476085B1 (en) * | 2010-09-21 | 2013-07-02 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Method of fabricating dual trench isolated epitaxial diode array |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020001223A1 (en) * | 2000-06-30 | 2002-01-03 | Yoshiaki Saito | Solid-state magnetic memory |
US20040057280A1 (en) * | 2002-09-19 | 2004-03-25 | Mitsubishi Denki Kabushiki Kaisha | Current drive circuit avoiding effect of voltage drop caused by load and semiconductor memory device equipped therewith |
US20050067630A1 (en) * | 2003-09-25 | 2005-03-31 | Zhao Jian H. | Vertical junction field effect power transistor |
US20050167744A1 (en) * | 2004-02-02 | 2005-08-04 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
US6995446B2 (en) * | 2002-12-13 | 2006-02-07 | Ovonyx, Inc. | Isolating phase change memories with schottky diodes and guard rings |
US7247876B2 (en) * | 2000-06-30 | 2007-07-24 | Intel Corporation | Three dimensional programmable device and method for fabricating the same |
US7283383B2 (en) * | 2003-12-13 | 2007-10-16 | Hynix Semiconductor Inc. | Phase change resistor cell, nonvolatile memory device and control method using the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100663358B1 (en) | 2005-02-24 | 2007-01-02 | 삼성전자주식회사 | Phase change memory devices employing cell diodes and methods of fabricating the same |
KR100689831B1 (en) | 2005-06-20 | 2007-03-08 | 삼성전자주식회사 | Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same |
US20070218665A1 (en) | 2006-03-15 | 2007-09-20 | Marvell International Ltd. | Cross-point memory array |
-
2008
- 2008-02-19 US US12/033,519 patent/US7829879B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020001223A1 (en) * | 2000-06-30 | 2002-01-03 | Yoshiaki Saito | Solid-state magnetic memory |
US7247876B2 (en) * | 2000-06-30 | 2007-07-24 | Intel Corporation | Three dimensional programmable device and method for fabricating the same |
US20040057280A1 (en) * | 2002-09-19 | 2004-03-25 | Mitsubishi Denki Kabushiki Kaisha | Current drive circuit avoiding effect of voltage drop caused by load and semiconductor memory device equipped therewith |
US6995446B2 (en) * | 2002-12-13 | 2006-02-07 | Ovonyx, Inc. | Isolating phase change memories with schottky diodes and guard rings |
US20050067630A1 (en) * | 2003-09-25 | 2005-03-31 | Zhao Jian H. | Vertical junction field effect power transistor |
US7283383B2 (en) * | 2003-12-13 | 2007-10-16 | Hynix Semiconductor Inc. | Phase change resistor cell, nonvolatile memory device and control method using the same |
US20050167744A1 (en) * | 2004-02-02 | 2005-08-04 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080308860A1 (en) * | 2007-06-18 | 2008-12-18 | Samsung Electronics Co., Ltd. | Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same |
US8158480B2 (en) * | 2007-06-18 | 2012-04-17 | Samsung Electronics Co., Ltd. | Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same |
US20090206316A1 (en) * | 2008-02-19 | 2009-08-20 | Qimonda Ag | Integrated circuit including u-shaped access device |
US7994536B2 (en) * | 2008-02-19 | 2011-08-09 | Qimonda Ag | Integrated circuit including U-shaped access device |
US20090218556A1 (en) * | 2008-02-28 | 2009-09-03 | Shoaib Zaidi | Integrated circuit fabricated using an oxidized polysilicon mask |
US7718464B2 (en) * | 2008-02-28 | 2010-05-18 | Qimonda North America Corp. | Integrated circuit fabricated using an oxidized polysilicon mask |
US8476085B1 (en) * | 2010-09-21 | 2013-07-02 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Method of fabricating dual trench isolated epitaxial diode array |
US20130189799A1 (en) * | 2010-09-21 | 2013-07-25 | Chao Zhang | Method of fabricating dual trench isolated epitaxial diode array |
Also Published As
Publication number | Publication date |
---|---|
US7829879B2 (en) | 2010-11-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7800093B2 (en) | Resistive memory including buried word lines | |
US7362608B2 (en) | Phase change memory fabricated using self-aligned processing | |
US7786464B2 (en) | Integrated circuit having dielectric layer including nanocrystals | |
US7875492B2 (en) | Integrated circuit including a memory fabricated using self-aligned processing | |
US7545668B2 (en) | Mushroom phase change memory having a multilayer electrode | |
US9064794B2 (en) | Integrated circuit including vertical diode | |
US7838860B2 (en) | Integrated circuit including vertical diode | |
US8284596B2 (en) | Integrated circuit including an array of diodes coupled to a layer of resistance changing material | |
US7495946B2 (en) | Phase change memory fabricated using self-aligned processing | |
US7869257B2 (en) | Integrated circuit including diode memory cells | |
US20090185411A1 (en) | Integrated circuit including diode memory cells | |
US7863610B2 (en) | Integrated circuit including silicide region to inhibit parasitic currents | |
US7671354B2 (en) | Integrated circuit including spacer defined electrode | |
US8039299B2 (en) | Method for fabricating an integrated circuit including resistivity changing material having a planarized surface | |
US7745812B2 (en) | Integrated circuit including vertical diode | |
US7829879B2 (en) | Integrated circuit including U-shaped access device | |
US8084759B2 (en) | Integrated circuit including doped semiconductor line having conductive cladding | |
US7671353B2 (en) | Integrated circuit having contact including material between sidewalls | |
US8254166B2 (en) | Integrated circuit including doped semiconductor line having conductive cladding | |
US20080315171A1 (en) | Integrated circuit including vertical diode | |
US7994536B2 (en) | Integrated circuit including U-shaped access device | |
US7679074B2 (en) | Integrated circuit having multilayer electrode |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WEIS, ROLF;HAPP, THOMAS;REEL/FRAME:020528/0120 Effective date: 20080219 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
|
AS | Assignment |
Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036575/0670 Effective date: 20150708 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.) |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20181109 |