US20090191676A1 - Flash memory having a high-permittivity tunnel dielectric - Google Patents

Flash memory having a high-permittivity tunnel dielectric Download PDF

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US20090191676A1
US20090191676A1 US12419469 US41946909A US2009191676A1 US 20090191676 A1 US20090191676 A1 US 20090191676A1 US 12419469 US12419469 US 12419469 US 41946909 A US41946909 A US 41946909A US 2009191676 A1 US2009191676 A1 US 2009191676A1
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memory
gate
dielectric
substrate
high
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Leonard Forbes
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Abstract

A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator.

Description

    RELATED APPLICATION
  • [0001]
    This Application is a Divisional of U.S. application Ser. No. 11/209,128, titled “FLASH MEMORY HAVING A HIGH-PERMITTIVITY TUNNEL DIELECTRIC,” filed Aug. 22, 2005 (Allowed), which is a Divisional of U.S. application Ser. No. 10/739,253, filed Dec. 18, 2003, now U.S. Pat. No. 7,157,769 issued on Jan. 2, 2007, which are commonly assigned and incorporated herein by reference.
  • TECHNICAL FIELD
  • [0002]
    The present invention relates generally to memory devices and in particular the present invention relates to flash memory device architecture.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. One type of flash memory is a nitride read only memory (NROM). NROM has some of the characteristics of flash memory but does not require the special fabrication processes of flash memory. NROM integrated circuits can be implemented using a standard CMOS process.
  • [0004]
    Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
  • [0005]
    The performance of flash memory transistors needs to increase as the performance of computer systems increases. To accomplish a performance increase, the transistors can be reduced in size. This has the effect of increased speed with decreased power requirements.
  • [0006]
    However, a problem with decreased flash memory size is that flash memory cell technologies have some scaling limitations. For example, stress induced leakage typically requires a tunnel oxide above 60 Å. This thickness results in a scaling limit on the gate length. Additionally, this gate oxide thickness limits the read current and may require large gate widths.
  • [0007]
    For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable, higher performance flash memory transistor.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    FIG. 1 shows a cross-sectional view of a flash memory cell transistor of the present invention.
  • [0009]
    FIG. 2 shows an energy-band diagram in accordance with a write operation to the transistor structure of FIG. 1.
  • [0010]
    FIG. 3 shows an energy-band diagram in accordance with an erase operation from the transistor structure of FIG. 1.
  • [0011]
    FIG. 4 shows a plot of tunneling current dependence on barrier height for various electric fields in accordance with the transistor structure of FIG. 1.
  • [0012]
    FIG. 5 shows a block diagram of an electronic system of the present invention.
  • DETAILED DESCRIPTION
  • [0013]
    In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.
  • [0014]
    FIG. 1 illustrates a cross-sectional view of a flash memory cell transistor of the present invention. The transistor is comprised of two source/drain regions 101 and 102 in a silicon substrate 111. Which region 101 or 102 functions as source and which functions as drain is determined by the direction of operation of the transistor.
  • [0015]
    In one embodiment, the source/drain regions 101 and 102 are n+ doped regions in a p-type substrate 111. An alternate embodiment may use p+ doped source/drain regions in an n-type substrate. The present invention is not limited to any one conductivity type for the source/drain regions or the substrate.
  • [0016]
    A high-permittivity (high-k) tunnel gate dielectric 103 is formed on top of the substrate 111 between the source/drain regions 101 and 102. A polysilicon floating gate layer 105 is formed on top of the tunnel gate dielectric layer 103. An interpoly oxide insulator layer 107 is formed on top of the floating gate 105. A polysilicon control gate 109 is formed on top of the oxide insulator 107.
  • [0017]
    In one embodiment, a high dielectric constant is considered to be a dielectric constant that is greater than that of SiO2. In one embodiment, LaAlO is used as the high-k tunneling gate dielectric 103 instead of the prior art SiO2 tunneling gate dielectric. Alternate embodiments use other dielectrics having other dielectric constants. These dielectric materials include Si3N4, Al2O3, Y2O3, La2O3, Ta2O3, TiO2, HfO2, ZrO2, or other high dielectric constant materials. The characteristics of these materials are well known to those skilled in the art and are not discussed further.
  • [0018]
    The LaAlO dielectric material is a high-k tunneling dielectric that has a band gap of 6.6 eV and a conduction band offset of 2.1 eV. Both of these are smaller than the prior art SiO2. Even though the barrier height of the LaAlO dielectric is less than that of SiO2 (i.e., 3.2 eV), the leakage current resulting from tunneling is still low enough to meet the requirements of intrinsic storage of non-volatile memory.
  • [0019]
    The lower tunneling barrier height of high-k dielectric gate insulators provides larger tunneling current into the floating gate 105 with a smaller gate voltage. Additionally, larger tunneling current out of the floating gate is accomplished with smaller control gate 109 voltages.
  • [0020]
    Another advantage of high-k gate insulators is that smaller write and erase voltages are necessary due to the reduced thickness of the SiO2 layer 107 between the control gate 109 and the floating gate 105. This layer can be made less than 15 Å thick. Additional advantages include increased cell current with respect to prior art flash memory cells, transistors can be scaled below 50 nm, drain turn-on, short-channel effects, and punchthrough are substantially eliminated.
  • [0021]
    In one embodiment, the high-k gate dielectric layer 103 of FIG. 1 is fabricated using atomic layer deposition (ALD). As is well known in the art, ALD is based on the sequential deposition of individual monolayers or fractions of a monolayer in a well controlled manner. Gaseous precursors are introduced one at a time to the substrate surface and between the pulses the reactor is purged with an inert gas or evacuated.
  • [0022]
    In the first reaction step, the precursor is saturatively chemisorbed at the substrate surface and during subsequent purging the precursor is removed from the reactor. In the second step, another precursor is introduced on the substrate and the desired films growth reaction takes place. After that reaction, byproducts and the precursor excess are purged from the reactor. When the precursor chemistry is favorable, one ALD cycle can be performed in less than one second in a properly designed flow-type reactor.
  • [0023]
    ALD is well suited for deposition of high-k dielectrics such as AlOx, LaAlO3, HfAlO3, Pr2O3, Lanthanide-doped TiOX, HfSiON, Zr—Sn—Ti—O films using TiCl4 or TiI4, ZrON, HfO2/Hf, ZrAlxOy, CrTiO3, and ZrTiO4.
  • [0024]
    The most commonly used oxygen source materials for ALD are water, hydrogen peroxide, and ozone. Alcohols, oxygen and nitrous oxide have also been used. Of these, oxygen reacts poorly at temperatures below 600° C. but the other oxygen sources are highly reactive with most of the metal compounds listed above.
  • [0025]
    Source materials for the above-listed metals include: zirconium tetrachloride (ZrCl4) for the Zr film, titanium tetraisopropoxide (Ti(OCH(CH3)2)4) for the Ti film, trimethyl aluminum (Al(CH3)3) for the Al film, chromyl chromide (CrO2Cl2) for the Cr film, praseodymium chloride (PrCl3) for the Pr film, and hafnium chloride (HfCl4) for the Hf film. Alternate embodiments use other source materials.
  • [0026]
    Thin oxide films are deposited at a temperature that is high enough such that, when it is adsorbed to the substrate surface, the vaporized source material reacts with a molecular layer of a second source material or that the vaporized source material becomes absorbed and reacts with the second source material directed to the substrate surface in the subsequent step. On the other hand, the temperature should be low enough such that thermal breakdown of the source material does not occur or that its significance in terms of the total growth rate of the film is very small. Regarding the above-listed metals, the ALD process may be carried out at a temperature range of approximately 200-600° C. Alternate embodiments use other temperature ranges.
  • [0027]
    In another embodiment of the flash memory transistor of the present invention illustrated in FIG. 1, the high-k dielectric layer 103 can be fabricated using evaporation techniques. Various evaporation techniques are subsequently described for the high dielectric constant materials listed above.
  • [0028]
    Very thin films of TiO2 can be fabricated with electron-gun evaporation from a high purity TiO2 slug (e.g., 99.9999%) in a vacuum evaporator in the presence of an ion beam. In one embodiment, an electron gun is centrally located toward the bottom of the chamber. A heat reflector and a heater surround the substrate holder. Under the substrate holder is an ozonizer ring with many small holes directed to the wafer for uniform distribution of ozone that is needed to compensate for the loss of oxygen in the evaporated TiO2 film. An ion gun with a fairly large diameter (3-4 in. in diameter) is located above the electron gun and argon gas is used to generate Ar ions to bombard the substrate surface uniformly during the film deposition to compact the growing TiO2 film.
  • [0029]
    A two-step process is used in fabricating a high purity HfO2 film. This method avoids the damage to the silicon surface by Ar ion bombardment, such as that encountered during Hf metal deposition using dc sputtering. A thin Hf film is deposited by simple thermal evaporation. In one embodiment, this is by electron-beam evaporation using a high purity Hf metal slug (e.g., 99.9999%) at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma and ion bombardment of the substrate (as in the case of sputtering), the original atomically smooth surface of the silicon substrate is maintained. The second step is oxidation to form the desired HfO2.
  • [0030]
    The first step in the deposition of CoTi alloy film is by thermal evaporation. The second step is the low temperature oxidation of the CoTi film at 400° C. Electron beam deposition of the CoTi layer minimizes the effect of contamination during deposition. The CoTi films prepared from an electron gun possess the highest purity because of the high-purity starting material. The purity of zone-refined starting metals can be as high as 99.999%. Higher purity can be obtained in deposited films because of further purification during evaporation.
  • [0031]
    A two step process in fabricating a high-purity ZrO2 film avoids the damage to the silicon surface by Ar ion bombardment. A thin Zr film is deposited by simple thermal evaporation. In one embodiment, this is accomplished by electron beam evaporation using an ultra-high purity Zr metal slug (e.g., 99.9999%) at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma and ion bombardment of the substrate, the original atomically smooth surface of the silicon substrate is maintained. The second step is the oxidation to form the desired ZrO2.
  • [0032]
    The fabrication of Y2O3 and Gd2O3 films may be accomplished with a two step process. In one embodiment, an electron gun provides evaporation of high purity (e.g., 99.9999%) Y or Gd metal followed by low-temperature oxidation technology by microwave excitation in a Kr/O2 mixed high-density plasma at 400° C. The method of the present invention avoids damage to the silicon surface by Ar ion bombardment such as that encountered during Y or Gd metal deposition sputtering. A thin film of Y or Gd is deposited by thermal evaporation. In one embodiment, an electron-beam evaporation technique is used with an ultra-high purity Y or Gd metal slug at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma or ion bombardment of the substrate, the original atomically smooth surface of the silicon substrate is maintained. The second step is the oxidation to form the desired Y2O3 or Gd2O3.
  • [0033]
    The desired high purity of a PrO2 film can be accomplished by depositing a thin film by simple thermal evaporation. In one embodiment, this is accomplished by an electron-beam evaporation technique using an ultra-high purity Pr metal slug at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma and ion bombardment of the substrate, the original atomically smooth surface of the silicon substrate is maintained. The second step includes the oxidation to form the desired PrO2.
  • [0034]
    The nitridation of the ZrO2 samples comes after the low-temperature oxygen radical generated in high-density Krypton plasma. The next step is the nitridation of the samples at temperatures >700° C. in a rapid thermal annealing setup. Typical heating time of several minutes may be necessary, depending on the sample geometry.
  • [0035]
    The formation of a Y—Si—O film may be accomplished in one step by co-evaporation of the metal (Y) and silicon dioxide (SiO2) without consuming the substrate Si. Under a suitable substrate and two-source arrangement, yttrium is evaporated from one source, and SiO2 is from another source. A small oxygen leak may help reduce the oxygen deficiency in the film. The evaporation pressure ratio rates can be adjusted easily to adjust the Y—Si—O ratio.
  • [0036]
    The prior art fabrication of lanthanum aluminate (LaAlO3) films has been achieved by evaporating single crystal pellets on Si substrates in a vacuum using an electron-beam gun. The evaporation technique of the present invention uses a less expensive form of dry pellets of Al2O3 and La2O3 using two electron guns with two rate monitors. Each of the two rate monitors is set to control the composition. The composition of the film, however, can be shifted toward the Al2O3 or La2O3 side depending upon the choice of dielectric constant. After deposition, the wafer is annealed ex situ in an electric furnace at 700° C. for ten minutes in N2 ambience. In an alternate embodiment, the wafer is annealed at 800°-900° C. in RTA for ten to fifteen seconds in N2 ambience.
  • [0037]
    FIG. 2 illustrates an energy-band diagram in accordance with a write operation in the transistor structure of FIG. 1 while FIG. 3 is the energy-band diagram for an erase operation. The diagrams show the conduction band edge, EC, and the valence band edge, EV. Between EC and EV is the band gap where there are no states for electrons. The energy barrier, Φ, is the discontinuity in the conduction bands.
  • [0038]
    The high-k tunnel gate dielectric of the present invention reduces the barriers between the substrate and gate insulator and/or between the floating gate and the gate insulator. FIG. 4 illustrates a plot of tunneling current dependence on barrier height for various electric fields in accordance with the transistor structure of FIG. 1. This plot shows that the tunneling current at a fixed electric field can be increased by orders of magnitude as a result of reducing the barriers.
  • [0039]
    In the specific case of Fowler-Nordheim tunneling, the expression that describes the conduction in the insulator is J=AE2exp(−B/E) where J is the current density in amps/cm2, E is the electric field in the insulator in volts/cm and A and B are constants for a particular insulator. The constants depend on the effective mass and the electron barrier energy of the insulator and are scaled with the barrier energy, Φ, as A∝(1/Φ) and B∝(Φ)3/2.
  • [0040]
    For the case of the commonly used gate insulator, SiO2, the equation above renders A(SiO2—Si)=5.5×10−16 amps/volt2 and B(SiO2—Si)=7.07×107 V/cm. If a new barrier of <)=1.08 eV is utilized, likely values for A and B can be extrapolated from the above equations. In this case, A(Φ=1.08 eV)=1.76×10−15 amps/volt2 and B(Φ=1.08 eV)=1.24×107 V/cm.
  • [0041]
    Curves of J versus the barrier energy, F, are shown in FIG. 4 for several values of E. For a given tunneling current, lower barriers require lower electric fields. As an example, an SiO2 barrier of 3.2 eV has an electric field of 6×106 V/cm while for the same tunneling current, a high-k dielectric with a 1.08 eV barrier requires only an electric field of 7×105 V/cm. If the thicknesses of the two dielectrics are the same then the voltage required will be about 8.6 times less for the same current. If the high-k dielectric has a dielectric constant of 28, then the equivalent oxide thickness (EOT) will be 7 times less than the actual thickness of the high-k dielectric.
  • [0042]
    The flash memory transistors of the present invention can thus be designed with very small equivalent oxide thicknesses and scaled into the 50 nm dimensions without drain turn-on problems, short-channel effects, and punchthrough. Additionally, retention times will decrease due to more thermal excitation and emission of electrons over the smaller barriers.
  • [0043]
    FIG. 5 illustrates a functional block diagram of a memory device 500 that can incorporate the flash memory cells of the present invention. The memory device 500 is coupled to a processor 510. The processor 510 may be a microprocessor or some other type of controlling circuitry. The memory device 500 and the processor 510 form part of an electronic system 520. The memory device 500 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
  • [0044]
    The memory device includes an array of flash memory cells 530 that can be floating gate flash memory cells. The memory array 530 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a wordline while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connection of the cells to the bitlines depends on whether the array is a NAND architecture or a NOR architecture.
  • [0045]
    An address buffer circuit 540 is provided to latch address signals provided on address input connections A0-Ax 542. Address signals are received and decoded by a row decoder 544 and a column decoder 546 to access the memory array 530. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 530. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
  • [0046]
    The memory device 500 reads data in the memory array 530 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 550. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 530. Data input and output buffer circuitry 560 is included for bi-directional data communication over a plurality of data connections 562 with the controller 510). Write circuitry 555 is provided to write data to the memory array.
  • [0047]
    Control circuitry 570 decodes signals provided on control connections 572 from the processor 510. These signals are used to control the operations on the memory array 530, including data read, data write, and erase operations. The control circuitry 570 may be a state machine, a sequencer, or some other type of controller.
  • [0048]
    The flash memory device illustrated in FIG. 5 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.
  • CONCLUSION
  • [0049]
    In summary, the flash memory transistors of the present invention use a high-k tunnel gate dielectric to enable the transistor to be reduced in size without performance problems. The high-k dielectric enables smaller write and erase voltages to be used and eliminates drain turn-on problems, short-channel effects, and punchthrough. The high-k dielectric can be deposited either with an evaporation process or an atomic layer deposition process.
  • [0050]
    The flash memory cells of the present invention may be NAND-type cells, NOR-type cells, or any other type of flash memory array architecture.
  • [0051]
    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Claims (20)

  1. 1. A method for fabricating a flash memory cell, the method comprising:
    creating a plurality of source/drain regions by doping portions of a substrate;
    forming an atomic layer deposition (ALD) tunnel dielectric layer with an atomic layer deposition technique on the substrate substantially between the plurality of source/drain regions, the ALD tunnel dielectric layer having a dielectric constant that is higher than silicon dioxide;
    depositing a floating gate on the evaporated tunnel dielectric layer;
    depositing an oxide insulator material on the floating gate; and
    forming a control gate on the oxide insulator material.
  2. 2. The method of claim 1 wherein forming an ALD tunnel gate insulator comprises depositing one of AlOX, LaAlO3, HfAlO3, Pr2O3, Lanthanide-doped TiOx, HfSiON, Zr—Sn—Ti—O films using TiCl4 or TiI4, ZrON, HfO2/Hf, ZrAlXOy, CrTiO3, or ZrTiO4.
  3. 3. A method for fabricating a memory device on a substrate, the memory device having a plurality of memory cells, the method comprising:
    doping a source region and a drain region into the substrate for each memory cell;
    forming a tunnel dielectric layer over the substrate substantially between each pair of source and drain regions, each tunnel dielectric layer having a barrier height that is less than silicon dioxide;
    forming a floating gate over each tunnel dielectric layer;
    forming a gate insulator over each floating gate; and
    forming a gate over each gate insulator.
  4. 4. The method of claim 3 wherein the tunnel dielectric layer comprises a high permittivity gate dielectric.
  5. 5. The method of claim 4 wherein the tunnel dielectric layer has a band gap of 6.6 eV and a conduction band offset of 2.1 eV.
  6. 6. The method of claim 3 wherein the tunnel dielectric layer is formed using atomic layer deposition using sequential deposition of individual monolayers or fractions of a monolayer where gaseous precursors are introduced one at a time to the substrate.
  7. 7. The method of claim 3 wherein the floating gate comprises a polysilicon layer.
  8. 8. The method of claim 3 wherein the gate insulator comprises an interpoly oxide insulator layer.
  9. 9. The method of claim 3 wherein the tunnel dielectric layer is less than 15 Å thick.
  10. 10. A method for fabricating a memory device, the method comprising:
    forming a pair of source/drain regions in the substrate for each memory cell of the memory device;
    forming a tunnel dielectric with atomic layer deposition, using an oxygen source of one of hydrogen peroxide, ozone, or nitrous oxide, over the substrate and substantially between each pair of source/drain regions, each tunnel dielectric layer having a barrier height that is less than silicon dioxide and is comprised of a metal compound;
    forming a floating gate over each tunnel dielectric;
    forming a gate insulator over each floating gate; and
    forming a gate over each gate insulator.
  11. 11. The method of claim 10 wherein the tunnel dielectric is formed by a plurality of reaction steps, including a first precursor that is saturatively chemisorbed at the substrate surface, in a flow-type reactor.
  12. 12. The method of claim 11 and further including purging the first precursor and introducing a second precursor that is introduced on the substrate for films growth reaction.
  13. 13. The method of claim 12 and further including purging byproducts and the second precursor.
  14. 14. The method of claim 10 wherein the tunnel dielectric is formed from one of source materials: zirconium tetrachloride (ZrCl4) for a Zr film, titanium tetraisopropoxide (Ti(OCH(CH3)2)4) for a Ti film, trimethyl aluminum (Al(CH3)3) for an Al film, chromyl chromide (CrO2Cl2) for a Cr film, praseodymium chloride (PrCl3) for a Pr film, and hafnium chloride (HfCl4) for an Hf film.
  15. 15. The method of claim 14 wherein thin oxide films are deposited on the substrate at a temperature that is high enough such that it is absorbed to the substrate surface.
  16. 16. The method of claim 15 wherein vaporized source material reacts with a molecular layer of a second source material.
  17. 17. The method of claim 16 wherein the vaporized source material becomes absorbed and reacts with the second source material directed to the substrate surface in a subsequent fabrication step.
  18. 18. The method of claim 10 wherein each memory cell is scaled below 50 nm.
  19. 19. The method of claim 10 wherein the oxygen sources further comprise water and alcohols.
  20. 20. The method of claim 10 wherein tunnel dielectric materials include one of Si3N4, Al2O3, Y2O3, La2O3, Ta2O3, TiO2, HfO2, ZrO2.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157186A1 (en) * 2006-12-29 2008-07-03 Samsung Electronics Co., Ltd. Non-volatile memory device including metal-insulator transition material
US20080274625A1 (en) * 2002-12-04 2008-11-06 Micron Technology, Inc. METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
US20110227142A1 (en) * 2010-03-22 2011-09-22 Micron Technology, Inc. Fortification of charge-storing material in high-k dielectric environments and resulting appratuses
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8445952B2 (en) 2002-12-04 2013-05-21 Micron Technology, Inc. Zr-Sn-Ti-O films

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7045430B2 (en) * 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7205218B2 (en) 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US7221017B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US6921702B2 (en) * 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US7199023B2 (en) * 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US7183186B2 (en) 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
US7154779B2 (en) * 2004-01-21 2006-12-26 Sandisk Corporation Non-volatile memory cell using high-k material inter-gate programming
US20050242387A1 (en) * 2004-04-29 2005-11-03 Micron Technology, Inc. Flash memory device having a graded composition, high dielectric constant gate insulator
US20050259467A1 (en) * 2004-05-18 2005-11-24 Micron Technology, Inc. Split gate flash memory cell with ballistic injection
KR100587686B1 (en) * 2004-07-15 2006-06-08 삼성전자주식회사 Method for forming TiN and method for manufacturing capacitor used the same
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7494939B2 (en) 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
US7271052B1 (en) 2004-09-02 2007-09-18 Micron Technology, Inc. Long retention time single transistor vertical memory gain cell
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7315474B2 (en) * 2005-01-03 2008-01-01 Macronix International Co., Ltd Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7374964B2 (en) 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7390756B2 (en) 2005-04-28 2008-06-24 Micron Technology, Inc. Atomic layer deposited zirconium silicon oxide films
US7572695B2 (en) 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
US7538389B2 (en) 2005-06-08 2009-05-26 Micron Technology, Inc. Capacitorless DRAM on bulk silicon
US7372098B2 (en) * 2005-06-16 2008-05-13 Micron Technology, Inc. Low power flash memory devices
US7829938B2 (en) * 2005-07-14 2010-11-09 Micron Technology, Inc. High density NAND non-volatile memory device
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8071476B2 (en) 2005-08-31 2011-12-06 Micron Technology, Inc. Cobalt titanium oxide dielectric films
US7473589B2 (en) * 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7907450B2 (en) * 2006-05-08 2011-03-15 Macronix International Co., Ltd. Methods and apparatus for implementing bit-by-bit erase of a flash memory device
US20070281105A1 (en) * 2006-06-02 2007-12-06 Nima Mokhlesi Atomic Layer Deposition of Oxides Using Krypton as an Ion Generating Feeding Gas
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films
US8772858B2 (en) * 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US7811890B2 (en) 2006-10-11 2010-10-12 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US7619926B2 (en) * 2007-03-29 2009-11-17 Sandisk Corporation NAND flash memory with fixed charge
US7732275B2 (en) * 2007-03-29 2010-06-08 Sandisk Corporation Methods of forming NAND flash memory with fixed charge
JP5221065B2 (en) * 2007-06-22 2013-06-26 株式会社東芝 Non-volatile semiconductor memory device
US7737488B2 (en) * 2007-08-09 2010-06-15 Macronix International Co., Ltd. Blocking dielectric engineered charge trapping memory cell with high speed erase
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US8208300B2 (en) * 2008-01-08 2012-06-26 Spansion Israel Ltd Non-volatile memory cell with injector
JP5349903B2 (en) * 2008-02-28 2013-11-20 ルネサスエレクトロニクス株式会社 Method of manufacturing a semiconductor device
CN101866931A (en) * 2010-05-19 2010-10-20 中国科学院微电子研究所 And a method of forming a semiconductor structure
US9240405B2 (en) 2011-04-19 2016-01-19 Macronix International Co., Ltd. Memory with off-chip controller
US9318336B2 (en) 2011-10-27 2016-04-19 Globalfoundries U.S. 2 Llc Non-volatile memory structure employing high-k gate dielectric and metal gate
US9978772B1 (en) 2017-03-14 2018-05-22 Micron Technology, Inc. Memory cells and integrated structures

Citations (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392930B1 (en) *
US4184207A (en) * 1978-01-27 1980-01-15 Texas Instruments Incorporated High density floating gate electrically programmable ROM
US4420504A (en) * 1980-12-22 1983-12-13 Raytheon Company Programmable read only memory
US4755864A (en) * 1984-12-25 1988-07-05 Kabushiki Kaisha Toshiba Semiconductor read only memory device with selectively present mask layer
US4881114A (en) * 1986-05-16 1989-11-14 Actel Corporation Selectively formable vertical diode circuit element
US5241496A (en) * 1991-08-19 1993-08-31 Micron Technology, Inc. Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells
US5330930A (en) * 1992-12-31 1994-07-19 Chartered Semiconductor Manufacturing Pte Ltd. Formation of vertical polysilicon resistor having a nitride sidewall for small static RAM cell
US5379253A (en) * 1992-06-01 1995-01-03 National Semiconductor Corporation High density EEPROM cell array with novel programming scheme and method of manufacture
US5378647A (en) * 1993-10-25 1995-01-03 United Microelectronics Corporation Method of making a bottom gate mask ROM device
US5397725A (en) * 1993-10-28 1995-03-14 National Semiconductor Corporation Method of controlling oxide thinning in an EPROM or flash memory array
US5467305A (en) * 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5576236A (en) * 1995-06-28 1996-11-19 United Microelectronics Corporation Process for coding and code marking read-only memory
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US5792697A (en) * 1997-01-07 1998-08-11 United Microelectronics Corporation Method for fabricating a multi-stage ROM
US5858841A (en) * 1997-01-20 1999-01-12 United Microelectronics Corporation ROM device having memory units arranged in three dimensions, and a method of making the same
US5911106A (en) * 1996-08-29 1999-06-08 Nec Corporation Semiconductor memory device and fabrication thereof
US5946558A (en) * 1997-02-05 1999-08-31 United Microelectronics Corp. Method of making ROM components
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US5994745A (en) * 1994-04-08 1999-11-30 United Microelectronics Corp. ROM device having shaped gate electrodes and corresponding code implants
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6028342A (en) * 1996-11-22 2000-02-22 United Microelectronics Corp. ROM diode and a method of making the same
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6081456A (en) * 1999-02-04 2000-06-27 Tower Semiconductor Ltd. Bit line control circuit for a memory array using 2-bit non-volatile memory cells
US6108240A (en) * 1999-02-04 2000-08-22 Tower Semiconductor Ltd. Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions
US6133102A (en) * 1998-06-19 2000-10-17 Wu; Shye-Lin Method of fabricating double poly-gate high density multi-state flat mask ROM cells
US6134156A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays
US6147904A (en) * 1999-02-04 2000-11-14 Tower Semiconductor Ltd. Redundancy method and structure for 2-bit non-volatile memory cells
US6157570A (en) * 1999-02-04 2000-12-05 Tower Semiconductor Ltd. Program/erase endurance of EEPROM memory cells
US6172396B1 (en) * 1998-02-03 2001-01-09 Worldwide Semiconductor Manufacturing Corp. ROM structure and method of manufacture
US6175523B1 (en) * 1999-10-25 2001-01-16 Advanced Micro Devices, Inc Precharging mechanism and method for NAND-based flash memory devices
US6174758B1 (en) * 1999-03-03 2001-01-16 Tower Semiconductor Ltd. Semiconductor chip having fieldless array with salicide gates and methods for making same
US6181597B1 (en) * 1999-02-04 2001-01-30 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells with serial read operations
US6184089B1 (en) * 1999-01-27 2001-02-06 United Microelectronics Corp. Method of fabricating one-time programmable read only memory
US6201737B1 (en) * 2000-01-28 2001-03-13 Advanced Micro Devices, Inc. Apparatus and method to characterize the threshold distribution in an NROM virtual ground array
US6204529B1 (en) * 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
US6207504B1 (en) * 1998-07-29 2001-03-27 United Semiconductor Corp. Method of fabricating flash erasable programmable read only memory
US6208557B1 (en) * 1999-05-21 2001-03-27 National Semiconductor Corporation EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6218695B1 (en) * 1999-06-28 2001-04-17 Tower Semiconductor Ltd. Area efficient column select circuitry for 2-bit non-volatile memory cells
US6222768B1 (en) * 2000-01-28 2001-04-24 Advanced Micro Devices, Inc. Auto adjusting window placement scheme for an NROM virtual ground array
US20010001075A1 (en) * 1997-03-25 2001-05-10 Vantis Corporation Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
US6240020B1 (en) * 1999-10-25 2001-05-29 Advanced Micro Devices Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices
US6243300B1 (en) * 2000-02-16 2001-06-05 Advanced Micro Devices, Inc. Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
US20010004332A1 (en) * 1998-05-20 2001-06-21 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6251731B1 (en) * 1998-08-10 2001-06-26 Acer Semiconductor Manufacturing, Inc. Method for fabricating high-density and high-speed nand-type mask roms
US6256231B1 (en) * 1999-02-04 2001-07-03 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells and method of implementing same
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6266281B1 (en) * 2000-02-16 2001-07-24 Advanced Micro Devices, Inc. Method of erasing non-volatile memory cells
US6269023B1 (en) * 2000-05-19 2001-07-31 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a current limiter
US6272043B1 (en) * 2000-01-28 2001-08-07 Advanced Micro Devices, Inc. Apparatus and method of direct current sensing from source side in a virtual ground array
US6275414B1 (en) * 2000-05-16 2001-08-14 Advanced Micro Devices, Inc. Uniform bitline strapping of a non-volatile memory cell
US6282118B1 (en) * 2000-10-06 2001-08-28 Macronix International Co. Ltd. Nonvolatile semiconductor memory device
US6291854B1 (en) * 1999-12-30 2001-09-18 United Microelectronics Corp. Electrically erasable and programmable read only memory device and manufacturing therefor
US6297096B1 (en) * 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US6303436B1 (en) * 1999-09-21 2001-10-16 Mosel Vitelic, Inc. Method for fabricating a type of trench mask ROM cell
US6348711B1 (en) * 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US6392930B2 (en) * 2000-02-14 2002-05-21 United Microelectronics Corp. Method of manufacturing mask read-only memory cell
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US20020086548A1 (en) * 2000-12-14 2002-07-04 Chang Kent Kuohua Method for forming gate dielectric layer in NROM
US6417053B1 (en) * 2001-11-20 2002-07-09 Macronix International Co., Ltd. Fabrication method for a silicon nitride read-only memory
US6421275B1 (en) * 2002-01-22 2002-07-16 Macronix International Co. Ltd. Method for adjusting a reference current of a flash nitride read only memory (NROM) and device thereof
US6429063B1 (en) * 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6432778B1 (en) * 2001-08-07 2002-08-13 Macronix International Co. Ltd. Method of forming a system on chip (SOC) with nitride read only memory (NROM)
US20020111001A1 (en) * 2001-02-09 2002-08-15 Micron Technology, Inc. Formation of metal oxide gate dielectric
US6451641B1 (en) * 2002-02-27 2002-09-17 Advanced Micro Devices, Inc. Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material
US6455890B1 (en) * 2001-09-05 2002-09-24 Macronix International Co., Ltd. Structure of fabricating high gate performance for NROM technology
US6461949B1 (en) * 2001-03-29 2002-10-08 Macronix International Co. Ltd. Method for fabricating a nitride read-only-memory (NROM)
US20020146885A1 (en) * 2001-04-04 2002-10-10 Chia-Hsing Chen Method of fabricating a nitride read only memory cell
US20020151138A1 (en) * 2001-04-13 2002-10-17 Chien-Hung Liu Method for fabricating an NROM
US6469342B1 (en) * 2001-10-29 2002-10-22 Macronix International Co., Ltd. Silicon nitride read only memory that prevents antenna effect
US6468864B1 (en) * 2001-06-21 2002-10-22 Macronix International Co., Ltd. Method of fabricating silicon nitride read only memory
US6486028B1 (en) * 2001-11-20 2002-11-26 Macronix International Co., Ltd. Method of fabricating a nitride read-only-memory cell vertical structure
US6487050B1 (en) * 1999-02-22 2002-11-26 Seagate Technology Llc Disc drive with wear-resistant ramp coating of carbon nitride or metal nitride
US20020177275A1 (en) * 2001-05-28 2002-11-28 Chien-Hung Liu Fabrication method for a silicon nitride read-only memory
US6514831B1 (en) * 2001-11-14 2003-02-04 Macronix International Co., Ltd. Nitride read only memory cell
US6531887B2 (en) * 2001-06-01 2003-03-11 Macronix International Co., Ltd. One cell programmable switch using non-volatile cell
US20030057491A1 (en) * 2001-09-19 2003-03-27 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6541079B1 (en) * 1999-10-25 2003-04-01 International Business Machines Corporation Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique
US6545309B1 (en) * 2002-03-11 2003-04-08 Macronix International Co., Ltd. Nitride read-only memory with protective diode and operating method thereof
US20030067807A1 (en) * 2001-09-28 2003-04-10 Hung-Sui Lin Erasing method for p-channel NROM
US6552387B1 (en) * 1997-07-30 2003-04-22 Saifun Semiconductors Ltd. Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6559013B1 (en) * 2002-06-20 2003-05-06 Macronix International Co., Ltd. Method for fabricating mask ROM device
US6576511B2 (en) * 2001-05-02 2003-06-10 Macronix International Co., Ltd. Method for forming nitride read only memory
US6580135B2 (en) * 2001-06-18 2003-06-17 Macronix International Co., Ltd. Silicon nitride read only memory structure and method of programming and erasure
US6580630B1 (en) * 2002-04-02 2003-06-17 Macronix International Co., Ltd. Initialization method of P-type silicon nitride read only memory
US20030117861A1 (en) * 2001-12-20 2003-06-26 Eduardo Maayan NROM NOR array
US6607957B1 (en) * 2002-07-31 2003-08-19 Macronix International Co., Ltd. Method for fabricating nitride read only memory
US6610586B1 (en) * 2002-09-04 2003-08-26 Macronix International Co., Ltd. Method for fabricating nitride read-only memory
US6617204B2 (en) * 2001-08-13 2003-09-09 Macronix International Co., Ltd. Method of forming the protective film to prevent nitride read only memory cell charging
US6630383B1 (en) * 2002-09-23 2003-10-07 Advanced Micro Devices, Inc. Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer
US6790782B1 (en) * 2001-12-28 2004-09-14 Advanced Micro Devices, Inc. Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
US20050158973A1 (en) * 2001-12-20 2005-07-21 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US142569A (en) * 1873-09-09 Improvement in cut-offs for cisterns
US57997A (en) * 1866-09-11 Improvement in malt-ksln floors
US117861A (en) * 1871-08-08 Improvement in fog-alarms
US57432A (en) * 1866-08-21 Improvement in gates
US62567A (en) * 1867-03-05 La forest rollins
US182829A (en) * 1876-10-03 Improvement in wheel-plows
US67807A (en) * 1867-08-13 Petkj
US11755A (en) * 1854-10-03 Self-acting mule
US177275A (en) * 1876-05-09 Improvement in volta-electric apparatus
US146885A (en) * 1874-01-27 Improvement in boring-machines
US151138A (en) * 1874-05-19 Improvement in axle-spindles for vehicles
US4513494A (en) 1983-07-19 1985-04-30 American Microsystems, Incorporated Late mask process for programming read only memories
JP2509706B2 (en) 1989-08-18 1996-06-26 株式会社東芝 Method of manufacturing a mask rom
US5416042A (en) * 1994-06-09 1995-05-16 International Business Machines Corporation Method of fabricating storage capacitors using high dielectric constant materials
US6335238B1 (en) * 1997-05-08 2002-01-01 Texas Instruments Incorporated Integrated dielectric and method
US6124164A (en) * 1998-09-17 2000-09-26 Micron Technology, Inc. Method of making integrated capacitor incorporating high K dielectric
US6911707B2 (en) 1998-12-09 2005-06-28 Advanced Micro Devices, Inc. Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance
FR2799570B1 (en) * 1999-10-08 2001-11-16 Itt Mfg Enterprises Inc Electrical Switch has perfected tactile several ways and single triggering device
US6544906B2 (en) * 2000-12-21 2003-04-08 Texas Instruments Incorporated Annealing of high-k dielectric materials
EP1263051A1 (en) 2001-05-30 2002-12-04 Infineon Technologies AG Bitline contacts in a memory cell array
US20020182829A1 (en) 2001-05-31 2002-12-05 Chia-Hsing Chen Method for forming nitride read only memory with indium pocket region
US6642131B2 (en) * 2001-06-21 2003-11-04 Matsushita Electric Industrial Co., Ltd. Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film
US20030062567A1 (en) 2001-09-28 2003-04-03 Wei Zheng Non volatile dielectric memory cell structure with high dielectric constant capacitive coupling layer
JP2003258242A (en) * 2002-03-07 2003-09-12 Fujitsu Ltd Semiconductor device and its manufacturing method
US6498377B1 (en) 2002-03-21 2002-12-24 Macronix International, Co., Ltd. SONOS component having high dielectric property
US6750066B1 (en) * 2002-04-08 2004-06-15 Advanced Micro Devices, Inc. Precision high-K intergate dielectric layer
US7135421B2 (en) * 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US6894931B2 (en) * 2002-06-20 2005-05-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US6791125B2 (en) * 2002-09-30 2004-09-14 Freescale Semiconductor, Inc. Semiconductor device structures which utilize metal sulfides

Patent Citations (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392930B1 (en) *
US6172396B2 (en) *
US6181597B2 (en) *
US4184207A (en) * 1978-01-27 1980-01-15 Texas Instruments Incorporated High density floating gate electrically programmable ROM
US4420504A (en) * 1980-12-22 1983-12-13 Raytheon Company Programmable read only memory
US4755864A (en) * 1984-12-25 1988-07-05 Kabushiki Kaisha Toshiba Semiconductor read only memory device with selectively present mask layer
US4881114A (en) * 1986-05-16 1989-11-14 Actel Corporation Selectively formable vertical diode circuit element
US5241496A (en) * 1991-08-19 1993-08-31 Micron Technology, Inc. Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells
US5467305A (en) * 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5379253A (en) * 1992-06-01 1995-01-03 National Semiconductor Corporation High density EEPROM cell array with novel programming scheme and method of manufacture
US5330930A (en) * 1992-12-31 1994-07-19 Chartered Semiconductor Manufacturing Pte Ltd. Formation of vertical polysilicon resistor having a nitride sidewall for small static RAM cell
US5378647A (en) * 1993-10-25 1995-01-03 United Microelectronics Corporation Method of making a bottom gate mask ROM device
US5397725A (en) * 1993-10-28 1995-03-14 National Semiconductor Corporation Method of controlling oxide thinning in an EPROM or flash memory array
US5994745A (en) * 1994-04-08 1999-11-30 United Microelectronics Corp. ROM device having shaped gate electrodes and corresponding code implants
US5576236A (en) * 1995-06-28 1996-11-19 United Microelectronics Corporation Process for coding and code marking read-only memory
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US5911106A (en) * 1996-08-29 1999-06-08 Nec Corporation Semiconductor memory device and fabrication thereof
US20010011755A1 (en) * 1996-08-29 2001-08-09 Kazuhiro Tasaka Semiconductor memory device and fabrication thereof
US6028342A (en) * 1996-11-22 2000-02-22 United Microelectronics Corp. ROM diode and a method of making the same
US5792697A (en) * 1997-01-07 1998-08-11 United Microelectronics Corporation Method for fabricating a multi-stage ROM
US5858841A (en) * 1997-01-20 1999-01-12 United Microelectronics Corporation ROM device having memory units arranged in three dimensions, and a method of making the same
US5946558A (en) * 1997-02-05 1999-08-31 United Microelectronics Corp. Method of making ROM components
US20010001075A1 (en) * 1997-03-25 2001-05-10 Vantis Corporation Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
US6297096B1 (en) * 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US6552387B1 (en) * 1997-07-30 2003-04-22 Saifun Semiconductors Ltd. Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6172396B1 (en) * 1998-02-03 2001-01-09 Worldwide Semiconductor Manufacturing Corp. ROM structure and method of manufacture
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
US6201282B1 (en) * 1998-05-05 2001-03-13 Saifun Semiconductors Ltd. Two bit ROM cell and process for producing same
US6477084B2 (en) * 1998-05-20 2002-11-05 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6348711B1 (en) * 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US20010004332A1 (en) * 1998-05-20 2001-06-21 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6133102A (en) * 1998-06-19 2000-10-17 Wu; Shye-Lin Method of fabricating double poly-gate high density multi-state flat mask ROM cells
US6207504B1 (en) * 1998-07-29 2001-03-27 United Semiconductor Corp. Method of fabricating flash erasable programmable read only memory
US6251731B1 (en) * 1998-08-10 2001-06-26 Acer Semiconductor Manufacturing, Inc. Method for fabricating high-density and high-speed nand-type mask roms
US6184089B1 (en) * 1999-01-27 2001-02-06 United Microelectronics Corp. Method of fabricating one-time programmable read only memory
US6157570A (en) * 1999-02-04 2000-12-05 Tower Semiconductor Ltd. Program/erase endurance of EEPROM memory cells
US6134156A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays
US6147904A (en) * 1999-02-04 2000-11-14 Tower Semiconductor Ltd. Redundancy method and structure for 2-bit non-volatile memory cells
US6081456A (en) * 1999-02-04 2000-06-27 Tower Semiconductor Ltd. Bit line control circuit for a memory array using 2-bit non-volatile memory cells
US6108240A (en) * 1999-02-04 2000-08-22 Tower Semiconductor Ltd. Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions
US6181597B1 (en) * 1999-02-04 2001-01-30 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells with serial read operations
US6256231B1 (en) * 1999-02-04 2001-07-03 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells and method of implementing same
US6487050B1 (en) * 1999-02-22 2002-11-26 Seagate Technology Llc Disc drive with wear-resistant ramp coating of carbon nitride or metal nitride
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6174758B1 (en) * 1999-03-03 2001-01-16 Tower Semiconductor Ltd. Semiconductor chip having fieldless array with salicide gates and methods for making same
US6208557B1 (en) * 1999-05-21 2001-03-27 National Semiconductor Corporation EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming
US6218695B1 (en) * 1999-06-28 2001-04-17 Tower Semiconductor Ltd. Area efficient column select circuitry for 2-bit non-volatile memory cells
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6204529B1 (en) * 1999-08-27 2001-03-20 Hsing Lan Lung 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate
US6303436B1 (en) * 1999-09-21 2001-10-16 Mosel Vitelic, Inc. Method for fabricating a type of trench mask ROM cell
US6240020B1 (en) * 1999-10-25 2001-05-29 Advanced Micro Devices Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices
US6175523B1 (en) * 1999-10-25 2001-01-16 Advanced Micro Devices, Inc Precharging mechanism and method for NAND-based flash memory devices
US6541079B1 (en) * 1999-10-25 2003-04-01 International Business Machines Corporation Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique
US6429063B1 (en) * 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6291854B1 (en) * 1999-12-30 2001-09-18 United Microelectronics Corp. Electrically erasable and programmable read only memory device and manufacturing therefor
US6272043B1 (en) * 2000-01-28 2001-08-07 Advanced Micro Devices, Inc. Apparatus and method of direct current sensing from source side in a virtual ground array
US6222768B1 (en) * 2000-01-28 2001-04-24 Advanced Micro Devices, Inc. Auto adjusting window placement scheme for an NROM virtual ground array
US6201737B1 (en) * 2000-01-28 2001-03-13 Advanced Micro Devices, Inc. Apparatus and method to characterize the threshold distribution in an NROM virtual ground array
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US6392930B2 (en) * 2000-02-14 2002-05-21 United Microelectronics Corp. Method of manufacturing mask read-only memory cell
US6243300B1 (en) * 2000-02-16 2001-06-05 Advanced Micro Devices, Inc. Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6266281B1 (en) * 2000-02-16 2001-07-24 Advanced Micro Devices, Inc. Method of erasing non-volatile memory cells
US6275414B1 (en) * 2000-05-16 2001-08-14 Advanced Micro Devices, Inc. Uniform bitline strapping of a non-volatile memory cell
US6269023B1 (en) * 2000-05-19 2001-07-31 Advanced Micro Devices, Inc. Method of programming a non-volatile memory cell using a current limiter
US6282118B1 (en) * 2000-10-06 2001-08-28 Macronix International Co. Ltd. Nonvolatile semiconductor memory device
US20020086548A1 (en) * 2000-12-14 2002-07-04 Chang Kent Kuohua Method for forming gate dielectric layer in NROM
US6602805B2 (en) * 2000-12-14 2003-08-05 Macronix International Co., Ltd. Method for forming gate dielectric layer in NROM
US20020111001A1 (en) * 2001-02-09 2002-08-15 Micron Technology, Inc. Formation of metal oxide gate dielectric
US6461949B1 (en) * 2001-03-29 2002-10-08 Macronix International Co. Ltd. Method for fabricating a nitride read-only-memory (NROM)
US20020146885A1 (en) * 2001-04-04 2002-10-10 Chia-Hsing Chen Method of fabricating a nitride read only memory cell
US20020151138A1 (en) * 2001-04-13 2002-10-17 Chien-Hung Liu Method for fabricating an NROM
US6576511B2 (en) * 2001-05-02 2003-06-10 Macronix International Co., Ltd. Method for forming nitride read only memory
US20020177275A1 (en) * 2001-05-28 2002-11-28 Chien-Hung Liu Fabrication method for a silicon nitride read-only memory
US6613632B2 (en) * 2001-05-28 2003-09-02 Macronix International Co., Ltd. Fabrication method for a silicon nitride read-only memory
US6531887B2 (en) * 2001-06-01 2003-03-11 Macronix International Co., Ltd. One cell programmable switch using non-volatile cell
US20030057997A1 (en) * 2001-06-01 2003-03-27 Macronix International Co., Ltd. One cell programmable switch using non-volatile cell
US6580135B2 (en) * 2001-06-18 2003-06-17 Macronix International Co., Ltd. Silicon nitride read only memory structure and method of programming and erasure
US6468864B1 (en) * 2001-06-21 2002-10-22 Macronix International Co., Ltd. Method of fabricating silicon nitride read only memory
US6432778B1 (en) * 2001-08-07 2002-08-13 Macronix International Co. Ltd. Method of forming a system on chip (SOC) with nitride read only memory (NROM)
US6617204B2 (en) * 2001-08-13 2003-09-09 Macronix International Co., Ltd. Method of forming the protective film to prevent nitride read only memory cell charging
US6455890B1 (en) * 2001-09-05 2002-09-24 Macronix International Co., Ltd. Structure of fabricating high gate performance for NROM technology
US20030057491A1 (en) * 2001-09-19 2003-03-27 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20030067807A1 (en) * 2001-09-28 2003-04-10 Hung-Sui Lin Erasing method for p-channel NROM
US6469342B1 (en) * 2001-10-29 2002-10-22 Macronix International Co., Ltd. Silicon nitride read only memory that prevents antenna effect
US6514831B1 (en) * 2001-11-14 2003-02-04 Macronix International Co., Ltd. Nitride read only memory cell
US6417053B1 (en) * 2001-11-20 2002-07-09 Macronix International Co., Ltd. Fabrication method for a silicon nitride read-only memory
US6486028B1 (en) * 2001-11-20 2002-11-26 Macronix International Co., Ltd. Method of fabricating a nitride read-only-memory cell vertical structure
US6953730B2 (en) * 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US20030117861A1 (en) * 2001-12-20 2003-06-26 Eduardo Maayan NROM NOR array
US20050158973A1 (en) * 2001-12-20 2005-07-21 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US6790782B1 (en) * 2001-12-28 2004-09-14 Advanced Micro Devices, Inc. Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
US6421275B1 (en) * 2002-01-22 2002-07-16 Macronix International Co. Ltd. Method for adjusting a reference current of a flash nitride read only memory (NROM) and device thereof
US6451641B1 (en) * 2002-02-27 2002-09-17 Advanced Micro Devices, Inc. Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material
US6545309B1 (en) * 2002-03-11 2003-04-08 Macronix International Co., Ltd. Nitride read-only memory with protective diode and operating method thereof
US6580630B1 (en) * 2002-04-02 2003-06-17 Macronix International Co., Ltd. Initialization method of P-type silicon nitride read only memory
US6559013B1 (en) * 2002-06-20 2003-05-06 Macronix International Co., Ltd. Method for fabricating mask ROM device
US6607957B1 (en) * 2002-07-31 2003-08-19 Macronix International Co., Ltd. Method for fabricating nitride read only memory
US6610586B1 (en) * 2002-09-04 2003-08-26 Macronix International Co., Ltd. Method for fabricating nitride read-only memory
US6630383B1 (en) * 2002-09-23 2003-10-07 Advanced Micro Devices, Inc. Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8445952B2 (en) 2002-12-04 2013-05-21 Micron Technology, Inc. Zr-Sn-Ti-O films
US20080274625A1 (en) * 2002-12-04 2008-11-06 Micron Technology, Inc. METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS
US7923381B2 (en) 2002-12-04 2011-04-12 Micron Technology, Inc. Methods of forming electronic devices containing Zr-Sn-Ti-O films
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8541276B2 (en) 2004-08-31 2013-09-24 Micron Technology, Inc. Methods of forming an insulating metal oxide
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
US9129961B2 (en) 2006-01-10 2015-09-08 Micron Technology, Inc. Gallium lathanide oxide films
US9583334B2 (en) 2006-01-10 2017-02-28 Micron Technology, Inc. Gallium lanthanide oxide films
US20080157186A1 (en) * 2006-12-29 2008-07-03 Samsung Electronics Co., Ltd. Non-volatile memory device including metal-insulator transition material
US8237214B2 (en) * 2006-12-29 2012-08-07 Samsung Electronics Co., Ltd. Non-volatile memory device including metal-insulator transition material
US8987806B2 (en) 2010-03-22 2015-03-24 Micron Technology, Inc. Fortification of charge storing material in high K dielectric environments and resulting apparatuses
US20110227142A1 (en) * 2010-03-22 2011-09-22 Micron Technology, Inc. Fortification of charge-storing material in high-k dielectric environments and resulting appratuses
US9576805B2 (en) 2010-03-22 2017-02-21 Micron Technology, Inc. Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
US8288811B2 (en) 2010-03-22 2012-10-16 Micron Technology, Inc. Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses

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US20050138262A1 (en) 2005-06-23 application
US7157769B2 (en) 2007-01-02 grant
US7528037B2 (en) 2009-05-05 grant

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