US20090102514A1 - Duty cycle detecting circuit for pulse width modulation - Google Patents
Duty cycle detecting circuit for pulse width modulation Download PDFInfo
- Publication number
- US20090102514A1 US20090102514A1 US11/987,685 US98768507A US2009102514A1 US 20090102514 A1 US20090102514 A1 US 20090102514A1 US 98768507 A US98768507 A US 98768507A US 2009102514 A1 US2009102514 A1 US 2009102514A1
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- United States
- Prior art keywords
- electric potential
- count
- duty cycle
- sampling
- potential states
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
Definitions
- the present invention relates to a duty cycle detecting circuit for pulse width modulation (PWM), and more particularly to a detecting circuit that samples a PWM signal based on a clock frequency and calculates the duty cycle of the pulse width modulation signal based on the sampling results.
- PWM pulse width modulation
- Pulse Width Modulation has been used extensively in electronic circuits including motor control circuits and power supply devices.
- a pulse signal with a fixed frequency is used for controlling the ON and OFF states of a transistor.
- a change of pulse width is used for determining the time interval of being active or cut-off for the transistor to achieve the control effect.
- the duty cycle of the PWM signal indicates a proportion of the active time (or high electric potential) of the pulse signal and plays an important role in the pulse width modulation system.
- the duty cycle is very sensitive to many factors including an operating frequency, an operating temperature, a power voltage, and a circuit design. Therefore, it is an important subject to detect an actual duty cycle of a pulse signal in a pulse width modulation system under different operating conditions.
- the present invention provides a duty cycle detecting circuit for pulse width modulation that is applied for detecting a duty cycle of a PWM signal
- the duty cycle detecting circuit comprises: a clock generating circuit for generating a clock signal; a sampling circuit for receiving the PWM signal and the clock signal and sampling the PWM signal based on the clock signal to generate a sampling signal; and a calculation circuit for calculating the duty cycle of the PWM signal based on the sampling signal.
- the sampling signal includes a high electric potential state and a low electric potential state.
- the calculation circuit accumulates the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively, and divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle.
- the calculation circuit accumulates the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively, and divides the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
- the clock generating circuit is an oscillator
- the sampling circuit is a flip-flop.
- the calculation circuit comprises a microprocessor unit for processing an operation required for calculating the duty cycle, and a memory unit for storing a computer code required for calculating the duty cycle.
- the calculation circuit further comprises a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively.
- the calculation circuit further includes a division circuit for dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
- the calculation circuit further includes a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.
- the calculation circuit includes a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and a number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively.
- the calculation circuit further includes a division circuit for dividing the count of high electric potential states by the total number of times of sampling.
- the calculation circuit further includes a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.
- FIG. 1 illustrates a block diagram of a duty cycle detecting circuit for pulse width modulation in accordance with the present invention
- FIG. 2 illustrates a duty cycle detecting circuit for pulse width modulation in accordance with a first preferred embodiment of the present invention
- FIG. 3 illustrates a duty cycle detecting circuit for pulse width modulation in accordance with a second preferred embodiment of the present invention.
- FIG. 4 illustrates a relation of a PWM signal, a clock signal and a sampling signal in accordance with the present invention.
- the duty cycle detecting circuit is applied for detecting a duty cycle of a PWM signal
- the duty cycle detecting circuit comprises: a clock generating circuit 11 for generating a clock signal; a sampling circuit 13 for receiving the PWM signal and the clock signal, and sampling the PWM signal based on the clock signal to generate a sampling signal; and a calculation circuit 15 for calculating the duty cycle of the PWM signal based on the sampling signal.
- the higher the frequency of the clock signal the higher is the sampling frequency.
- the higher the sampling frequency the higher is the accuracy of the detecting result.
- the frequency of a clock signal can be selected based on the frequency of the PWM signal. For example, a clock equals to ten times of the frequency of the pulse width modulation signal as the frequency of the clock signal.
- the sampling signal includes a high electric potential state and a low electric potential state.
- the calculation circuit accumulates the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively and divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle.
- the calculation circuit accumulates the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively, and dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
- the cycle of a single PWM signal is used as a unit time for the sampling to obtain the duty cycle of the single PWM signal; or the cycle of several PWM signals is used as a unit time for the sampling to obtain an average duty cycle.
- the clock generating circuit is an oscillator 21 ;
- the calculation circuit 25 comprises a microprocessor unit 251 , for processing the operation required for calculating the duty cycle; and a memory unit 252 , for storing a computer code required for calculating the duty cycle.
- the computer code drives the microprocessor unit 251 to accumulate the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively, and dividing the count of high electric potential states by the total number of times of sampling to obtain the duty cycle, or accumulating the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively, and dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
- the cycle of the single PWM signal is used as a unit time for the sampling to obtain the duty cycle of the single PWM signal; or the cycle of several PWM signals is used as a unit time for the sample to obtain an average duty cycle.
- the clock generating circuit is an oscillator 31 ;
- the sampling circuit is an flip-flop 33 ;
- the calculation circuit 35 comprises a counter 351 for receiving the sampling signal, and accumulating the sampling signal as s count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively.
- the calculation circuit 35 further includes a divider 355 for dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
- the calculation circuit 35 further includes a reset circuit 353 for resetting the counter 351 after a predetermined number of times of sampling, so that the counter 351 starts accumulating the count of high electric potential states and the count of low electric potential states again.
- the counter 351 accumulates the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively.
- the divider 355 divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Dc-Dc Converters (AREA)
- Analogue/Digital Conversion (AREA)
- Measuring Frequencies, Analyzing Spectra (AREA)
Abstract
A duty cycle detecting circuit for pulse width modulation (PWM) is disclosed. The circuit comprises a clock generating circuit, a sampling circuit and a calculation circuit. The clock generating circuit is for generating a clock signal. The sampling circuit receives a PWM signal and the clock signal, samples the PWM signal based on the clock signal, and generates a sampling signal. The calculation circuit is for calculating the duty cycle of the PWM signal based on the sampling signal.
Description
- 1. Field of the Invention
- The present invention relates to a duty cycle detecting circuit for pulse width modulation (PWM), and more particularly to a detecting circuit that samples a PWM signal based on a clock frequency and calculates the duty cycle of the pulse width modulation signal based on the sampling results.
- 2. Description of the Related Art
- Pulse Width Modulation (PWM) has been used extensively in electronic circuits including motor control circuits and power supply devices. In general, a pulse signal with a fixed frequency is used for controlling the ON and OFF states of a transistor. In a pulse width modulation system, a change of pulse width is used for determining the time interval of being active or cut-off for the transistor to achieve the control effect. In other words, the duty cycle of the PWM signal indicates a proportion of the active time (or high electric potential) of the pulse signal and plays an important role in the pulse width modulation system.
- However, the duty cycle is very sensitive to many factors including an operating frequency, an operating temperature, a power voltage, and a circuit design. Therefore, it is an important subject to detect an actual duty cycle of a pulse signal in a pulse width modulation system under different operating conditions.
- To achieve the foregoing objective, the present invention provides a duty cycle detecting circuit for pulse width modulation that is applied for detecting a duty cycle of a PWM signal, and the duty cycle detecting circuit comprises: a clock generating circuit for generating a clock signal; a sampling circuit for receiving the PWM signal and the clock signal and sampling the PWM signal based on the clock signal to generate a sampling signal; and a calculation circuit for calculating the duty cycle of the PWM signal based on the sampling signal.
- In the duty cycle detecting circuit for pulse width modulation, the sampling signal includes a high electric potential state and a low electric potential state. The calculation circuit accumulates the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively, and divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle.
- In the duty cycle detecting circuit for pulse width modulation, the calculation circuit accumulates the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively, and divides the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
- In the duty cycle detecting circuit for pulse width modulation, the clock generating circuit is an oscillator, and the sampling circuit is a flip-flop. The calculation circuit comprises a microprocessor unit for processing an operation required for calculating the duty cycle, and a memory unit for storing a computer code required for calculating the duty cycle.
- In the duty cycle detecting circuit for pulse width modulation, the calculation circuit further comprises a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively. The calculation circuit further includes a division circuit for dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle. The calculation circuit further includes a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.
- In the duty cycle detecting circuit for pulse width modulation, the calculation circuit includes a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and a number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively. The calculation circuit further includes a division circuit for dividing the count of high electric potential states by the total number of times of sampling. The calculation circuit further includes a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.
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FIG. 1 illustrates a block diagram of a duty cycle detecting circuit for pulse width modulation in accordance with the present invention; -
FIG. 2 illustrates a duty cycle detecting circuit for pulse width modulation in accordance with a first preferred embodiment of the present invention; -
FIG. 3 illustrates a duty cycle detecting circuit for pulse width modulation in accordance with a second preferred embodiment of the present invention; and -
FIG. 4 illustrates a relation of a PWM signal, a clock signal and a sampling signal in accordance with the present invention. - To make it easier for our examiner to understand the objective of the invention, its structure, innovative features, and performance, we use preferred embodiments together with the attached drawings for the detailed description of the invention.
- Referring to
FIG. 1 for a block diagram 10 of a duty cycle detecting circuit for pulse width modulation in accordance with the present invention, the duty cycle detecting circuit is applied for detecting a duty cycle of a PWM signal, and the duty cycle detecting circuit comprises: aclock generating circuit 11 for generating a clock signal; asampling circuit 13 for receiving the PWM signal and the clock signal, and sampling the PWM signal based on the clock signal to generate a sampling signal; and acalculation circuit 15 for calculating the duty cycle of the PWM signal based on the sampling signal. The higher the frequency of the clock signal, the higher is the sampling frequency. The higher the sampling frequency, the higher is the accuracy of the detecting result. The frequency of a clock signal can be selected based on the frequency of the PWM signal. For example, a clock equals to ten times of the frequency of the pulse width modulation signal as the frequency of the clock signal. - In the duty cycle detecting circuit for pulse width modulation as shown in
FIG. 4 , the sampling signal includes a high electric potential state and a low electric potential state. In a preferred embodiment, the calculation circuit accumulates the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively and divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle. - In the duty cycle detecting circuit for pulse width modulation in accordance with another preferred embodiment, the calculation circuit accumulates the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively, and dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle. When the sampling is performed, the cycle of a single PWM signal is used as a unit time for the sampling to obtain the duty cycle of the single PWM signal; or the cycle of several PWM signals is used as a unit time for the sampling to obtain an average duty cycle.
- Referring to
FIG. 2 for a duty cycle detecting circuit for pulse width modulation in accordance with a firstpreferred embodiment 20, the clock generating circuit is anoscillator 21; thecalculation circuit 25 comprises amicroprocessor unit 251, for processing the operation required for calculating the duty cycle; and amemory unit 252, for storing a computer code required for calculating the duty cycle. The computer code drives themicroprocessor unit 251 to accumulate the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively, and dividing the count of high electric potential states by the total number of times of sampling to obtain the duty cycle, or accumulating the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively, and dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle. When the sampling is performed, the cycle of the single PWM signal is used as a unit time for the sampling to obtain the duty cycle of the single PWM signal; or the cycle of several PWM signals is used as a unit time for the sample to obtain an average duty cycle. - Referring to
FIG. 3 for a duty cycle detecting circuit for pulse width modulation in accordance with a second preferredembodiment 30, the clock generating circuit is anoscillator 31; the sampling circuit is an flip-flop 33; and thecalculation circuit 35 comprises acounter 351 for receiving the sampling signal, and accumulating the sampling signal as s count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively. Thecalculation circuit 35 further includes adivider 355 for dividing the count of high electric potential states by the sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle. Thecalculation circuit 35 further includes areset circuit 353 for resetting thecounter 351 after a predetermined number of times of sampling, so that thecounter 351 starts accumulating the count of high electric potential states and the count of low electric potential states again. - In a duty cycle detecting circuit for pulse width modulation in accordance with a second embodiment, the
counter 351 accumulates the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively. Thedivider 355 divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle. - While the duty cycle detecting circuit for pulse width modulation in accordance with the invention has been described by means of specific embodiments, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope and spirit of the invention set forth in the claims.
Claims (15)
1. A duty cycle detecting circuit for pulse width modulation, applied for detecting a duty cycle of a PWM signal, comprising:
a clock generating circuit, for generating a clock signal;
a sampling circuit, for receiving the PWM signal and the clock signal, and sampling the PWM signal based on the clock signal to generate a sampling signal; and
a calculation circuit, for calculating the duty cycle of the PWM signal based on the sampling signal.
2. The duty cycle detecting circuit for pulse width modulation of claim 1 , wherein the sampling signal comprises a high electric potential state and a low electric potential state.
3. The duty cycle detecting circuit for pulse width modulation of claim 2 , wherein the calculation circuit accumulates the sampling signal into a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively.
4. The duty cycle detecting circuit for pulse width modulation of claim 3 , wherein the calculation circuit divides the count of high electric potential states by the total number of times of sampling to obtain the duty cycle.
5. The duty cycle detecting circuit for pulse width modulation of claim 2 , wherein the calculation circuit accumulates the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential states to obtain a count of high electric potential states and a count of low electric potential states respectively.
6. The duty cycle detecting circuit for pulse width modulation of claim 5 , wherein the calculation circuit divides the count of high electric potential states by a sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
7. The duty cycle detecting circuit for pulse width modulation of claim 1 , wherein the clock generating circuit is an oscillator.
8. The duty cycle detecting circuit for pulse width modulation of claim 1 , wherein the calculation circuit comprises:
a microprocessor unit, for processing an operation required to calculate the duty cycle; and
a memory unit, for storing a computer code required to calculate the duty cycle.
9. The duty cycle detecting circuit for pulse width modulation of claim 1 , wherein the sampling circuit is a flip-flop.
10. The duty cycle detecting circuit for pulse width modulation of claim 9 , wherein the calculation circuit comprises a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and the sampling signal as a count of low electric potential state to obtain a count of high electric potential states and a count of low electric potential states respectively.
11. The duty cycle detecting circuit for pulse width modulation of claim 10 , wherein the calculation circuit further comprises a divider for dividing the count of high electric potential states by a sum of the count of high electric potential states and the count of low electric potential states to obtain the duty cycle.
12. The duty cycle detecting circuit for pulse width modulation of claim 10 or 11 , wherein the calculation circuit further comprises a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.
13. The duty cycle detecting circuit for pulse width modulation of claim 9 , wherein the calculation circuit further includes a counter for receiving the sampling signal, and accumulating the sampling signal as a count of high electric potential states and a total number of times of sampling to obtain a count of high electric potential states and a total number of times of sampling respectively.
14. The duty cycle detecting circuit for pulse width modulation of claim 13 , wherein the calculation circuit further comprises a divider for dividing the count of high electric potential states by the total number of times of sampling to obtain the duty cycle.
15. The duty cycle detecting circuit for pulse width modulation of claim 13 or 14 , wherein the calculation circuit further comprises a reset circuit for resetting the counter after a predetermined number of times of sampling, so that the counter restarts accumulating the count of high electric potential states and the count of low electric potential states again.
Priority Applications (1)
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US14/101,641 US9354261B2 (en) | 2007-10-17 | 2013-12-10 | Duty cycle detecting circuit for pulse width modulation |
Applications Claiming Priority (2)
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TW096138938 | 2007-10-17 | ||
TW096138938A TWI394373B (en) | 2007-10-17 | 2007-10-17 | Duty cycle detecting circuit for pulse width modulation |
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US14/101,641 Division US9354261B2 (en) | 2007-10-17 | 2013-12-10 | Duty cycle detecting circuit for pulse width modulation |
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US11/987,685 Abandoned US20090102514A1 (en) | 2007-10-17 | 2007-12-04 | Duty cycle detecting circuit for pulse width modulation |
US14/101,641 Expired - Fee Related US9354261B2 (en) | 2007-10-17 | 2013-12-10 | Duty cycle detecting circuit for pulse width modulation |
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US14/101,641 Expired - Fee Related US9354261B2 (en) | 2007-10-17 | 2013-12-10 | Duty cycle detecting circuit for pulse width modulation |
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US (2) | US20090102514A1 (en) |
KR (1) | KR101375523B1 (en) |
TW (1) | TWI394373B (en) |
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CN102103168A (en) * | 2009-12-22 | 2011-06-22 | 比亚迪股份有限公司 | PWM (Pulse-Width Modulation) wave detecting method and device |
CN102478610A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | Duty ratio measuring system and method |
CN102933003A (en) * | 2012-11-20 | 2013-02-13 | 无锡中星微电子有限公司 | Dimming circuit |
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CN103347332A (en) * | 2013-06-25 | 2013-10-09 | 矽力杰半导体技术(杭州)有限公司 | Signal processing method and circuit and LED dimming circuit with circuit |
US9541591B2 (en) | 2014-08-11 | 2017-01-10 | Synopsys, Inc. | Periodic signal measurement using statistical sampling |
EP3151022A1 (en) * | 2015-10-01 | 2017-04-05 | Hamilton Sundstrand Corporation | Duty cycle-based bit interface system |
EP3177492A1 (en) * | 2014-08-05 | 2017-06-14 | WABCO GmbH | Method for determining the duty factor of a pulse-width-modulated signal by means of a vehicle control unit, and vehicle control unit |
WO2018197646A1 (en) * | 2017-04-28 | 2018-11-01 | Technische Universität Darmstadt | Circuit arrangement and method for determining an offset between two signal edges |
US10530351B2 (en) * | 2018-05-24 | 2020-01-07 | Thine Electronics, Inc. | Duty compensation device |
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US10050632B2 (en) * | 2016-12-30 | 2018-08-14 | Texas Instruments Incorporated | Counter-based SYSREF implementation |
KR102644538B1 (en) * | 2018-05-17 | 2024-03-06 | 현대자동차주식회사 | System monitoring computational procedure of pwm duty for controlling motor |
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Also Published As
Publication number | Publication date |
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KR20090039574A (en) | 2009-04-22 |
US9354261B2 (en) | 2016-05-31 |
TW200919967A (en) | 2009-05-01 |
US20140097825A1 (en) | 2014-04-10 |
TWI394373B (en) | 2013-04-21 |
KR101375523B1 (en) | 2014-03-25 |
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