CN115235649A

CN115235649A - Digital temperature sensor

Info

Publication number: CN115235649A
Application number: CN202110450037.4A
Authority: CN
Inventors: 高云; 杨运福; 蒲宇; 周明忠; 刘昂立; 石欢
Original assignee: Pingtouge Shanghai Semiconductor Co Ltd
Current assignee: Pingtouge Shanghai Semiconductor Co Ltd
Priority date: 2021-04-25
Filing date: 2021-04-25
Publication date: 2022-10-25

Abstract

The embodiment of the application provides a digital temperature sensor, includes: the temperature sensing circuit, the temperature determining circuit and the voltage processing circuit are composed of voltage-driven analog devices. The voltage processing circuit is electrically connected with a power supply end of the digital temperature sensor, can stabilize the power supply voltage by using the volt-ampere characteristic of the analog device, and provides the voltage-stabilized power supply voltage for the temperature sensing circuit and the temperature sensing circuit; the temperature sensing circuit can generate a signal to be detected corresponding to the temperature of the device to be detected; the temperature determining circuit can determine the temperature of the device to be tested according to the signal to be tested, and the temperature of the device to be tested is measured. The embodiment of the application adopts the analog circuit to design the voltage processing circuit suitable for the digital voltage domain, can reduce the power supply voltage fluctuation of the digital temperature sensor, and is favorable for reducing the influence of the power supply voltage fluctuation on the temperature measurement precision of the digital temperature sensor, thereby being favorable for improving the temperature measurement precision of the digital temperature sensor.

Description

Digital temperature sensor

Technical Field

The application relates to the technical field of integrated circuits, in particular to a digital temperature sensor.

Background

With the rapid development of integrated circuit technology, temperature sensors are widely used in medical treatment, environmental monitoring, and temperature monitoring of machines and even chips. Although the analog temperature sensor has high temperature measurement precision, the analog temperature sensor has a complex circuit structure and high power consumption. The digital temperature sensor is widely applied to temperature measurement of the chip due to simple circuit structure and low power consumption.

The temperature measurement accuracy is an important index for measuring the performance of the temperature sensor, and how to improve the temperature measurement accuracy of the digital temperature sensor becomes a problem of continuous research of technicians in the field.

Disclosure of Invention

Aspects of the present application provide a digital temperature sensor for improving temperature measurement accuracy of the digital temperature sensor.

The embodiment of the application provides a digital temperature sensor, includes: the temperature sensing circuit, the temperature determining circuit and the voltage processing circuit are composed of voltage-driven analog devices;

the voltage processing circuit is electrically connected with a power supply end for supplying power to the digital temperature sensor and the temperature sensing circuit, and is used for stabilizing the power supply voltage and supplying the voltage-stabilized power supply voltage to the temperature sensing circuit;

the temperature sensing circuit is electrically connected with the temperature determining circuit and used for sensing the temperature of a tested device, generating a signal to be tested carrying temperature information of the tested device and outputting the signal to be tested to the temperature determining circuit;

and the temperature determining circuit is used for determining the temperature of the device to be tested according to the corresponding relation between the signal to be tested and the temperature and the pre-calibrated detection signal.

The embodiment of the application provides a digital temperature sensor, includes: the temperature sensing circuit, the temperature determining circuit and the voltage processing circuit are composed of voltage-driven analog devices. The voltage processing circuit is electrically connected between a power supply end for supplying power to the digital temperature sensor and the temperature sensing circuit, can stabilize the power supply voltage by utilizing the volt-ampere characteristic of the analog device, and provides the voltage-stabilized power supply voltage for the temperature sensing circuit and the temperature determining circuit; the temperature sensing circuit can sense the temperature of the tested device and generate a to-be-tested signal carrying temperature information of the tested device; the temperature determining circuit can determine the temperature of the device to be tested according to the corresponding relation between the signal to be tested and the pre-calibrated detection signal and the temperature, and the temperature of the device to be tested is measured. This application embodiment adopts analog circuit to design and is fit for digital voltage domain voltage processing circuit, and the volt-ampere characteristic of usable its analog device carries out the steady voltage to mains voltage, reduces digital temperature sensor's supply voltage fluctuation, helps reducing the influence of mains voltage fluctuation to digital temperature sensor's temperature measurement precision, and then helps improving digital temperature sensor's temperature measurement precision.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1a and fig. 1b are schematic diagrams of working scenarios of a digital temperature sensor provided in an embodiment of the present application;

fig. 1c and fig. 2 are schematic structural diagrams of a voltage processing circuit according to an embodiment of the present application;

3-5 are schematic circuit diagrams of a voltage processing circuit according to an embodiment of the present application;

6-8 are schematic circuit diagrams of another voltage processing circuit provided by an embodiment of the present application;

fig. 9 and 10 are schematic structural diagrams of a digital temperature sensor provided in an embodiment of the present application;

fig. 11 is a schematic structural diagram of a temperature correction circuit and a temperature determination circuit provided in an embodiment of the present application;

fig. 12 is a schematic structural diagram of a temperature sensing circuit according to an embodiment of the present disclosure;

FIG. 13 is a schematic structural diagram of a ring oscillator according to an embodiment of the present application;

fig. 14 is a schematic diagram of the operating waveforms of the ring oscillator provided in fig. 13.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Although the analog temperature sensor has high temperature measurement precision, the analog temperature sensor has a complex circuit structure and high power consumption. If the analog temperature sensor is applied to the temperature measurement of the chip, the volume and the power consumption of the chip are undoubtedly increased. The digital temperature sensor is widely applied to temperature measurement of the chip due to simple circuit structure and low power consumption.

For a temperature sensor, temperature measurement accuracy is an important index for measuring the performance of the temperature sensor, and how to improve the temperature measurement accuracy of the digital temperature sensor becomes a problem of continuous research of technicians in the field.

In order to provide temperature measurement accuracy of the temperature sensor, the embodiment of the application provides a novel temperature sensor. The temperature sensor includes: the temperature sensing circuit, the temperature determining circuit and the voltage processing circuit are composed of voltage-driven analog devices. The voltage processing circuit is electrically connected with a power supply end for supplying power to the digital temperature sensor, the temperature sensing circuit and the temperature determining circuit, can stabilize the power supply voltage by using the volt-ampere characteristic of the analog device, and provides the voltage after voltage stabilization processing for the temperature sensing circuit and the temperature determining circuit; the temperature sensing circuit can generate a signal to be detected corresponding to the temperature of the device to be detected; the temperature determining circuit can determine the temperature of the device to be tested according to the signal to be tested, and the temperature of the device to be tested is measured. The temperature sensor that this application embodiment provided adopts analog circuit to design out and is fit for digital voltage domain voltage treatment circuit, and the volt-ampere characteristic of usable analog device carries out the steady voltage to mains voltage, and reducible digital temperature sensor's supply voltage is undulant, helps reducing the influence of mains voltage fluctuation to digital temperature sensor's temperature measurement precision, and then helps improving temperature sensor's temperature measurement precision.

On the other hand, the voltage processing circuit is composed of voltage-driven analog devices, the requirements of wide working range and low power voltage of the power voltage of a digital voltage domain can be met by adopting the analog devices with different threshold voltages, and the analog voltage processing circuit meeting the voltage domain requirement of the digital temperature sensor is realized.

The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be noted that: like reference numerals refer to like objects in the following figures and embodiments, and thus, once an object is defined in one figure or embodiment, further discussion thereof is not required in subsequent figures and embodiments.

Fig. 1a and fig. 1b are schematic structural diagrams of a working scenario of a digital temperature sensor according to an embodiment of the present application. As shown in fig. 1a, the digital temperature sensor TS may measure the temperature of the device S1 under test. As shown in FIG. 1a, a digital temperature sensor TS can be coupled into a device under test S1, integrated on the same chip as the device under test S1; the digital temperature sensor TS is a different chip than the device under test S1 as shown in fig. 1b. The chip may be a chip that can implement any function, for example, the chip may be a processor chip, a memory chip, or the like. The processor chip may be a processor chip of any electronic device. For example, it may be a processor chip of an internet of things (IOT) device, a processor chip of a server, or a data center processor chip, etc.

For the embodiment where the digital temperature sensor TS and the device under test S1 are different chips, the digital temperature sensor TS does not limit the distance between the digital temperature sensor TS and the device under test S1 when measuring the temperature of the device under test S1. The spacing distance between the digital temperature sensor TS and the tested device S1 can be flexibly set according to the sensitivity of the digital temperature sensor TS to temperature and the requirement of an actual application scene on temperature measurement precision, and is limited by a processing technology to a certain extent.

For the processor S11 in the chip, a digital temperature sensor TS can be electrically connected with the processor S11, the digital temperature sensor TS can measure the temperature of the device S1 under test and provide the temperature of the device S1 under test to the processor S11; the processor S11 can perform a set operation based on the temperature of the device S1 under test. For example, the processor may adjust the operating mode of the device under test based on the temperature of the device under test; for another example, the processor may monitor whether the temperature of the device under test exceeds a set temperature threshold; and if the temperature of the tested device exceeds the set temperature threshold value, limiting the tested device to work in a high-frequency mode, and the like.

As shown in fig. 1a and 1b, the voltage processing circuit 10 may be electrically connected between a power source terminal Vin for supplying power to a power receiver and the power receiver. Fig. 1a and 1b only illustrate the temperature sensing module S2 in the digital temperature sensor TS as an example, but do not limit the implementation form and function of the power receiving device.

The voltage processing circuit 10 provided in this embodiment is composed of a voltage-driven analog device, and performs voltage stabilization processing on the power supply voltage output by the power supply terminal Vin by using the volt-ampere characteristic of the analog device to obtain a power supply voltage Vout; and the power supply voltage Vout is output to the current-receiving device, so that the power supply voltage subjected to voltage stabilization can be provided for the current-receiving device, the stability of the power supply voltage is improved, and the influence of power supply voltage fluctuation on the current-receiving device is reduced.

In this embodiment, the power receiving device may be any device requiring power supply, and the voltage processing circuit 10 is configured to provide a stable power supply voltage to the power receiving device. For example, the power-receiving device may be a power-receiving device with a supply voltage operating in a digital voltage domain, such as the temperature sensing module S2 in the digital temperature sensor TS shown in fig. 1a and 1b. In fig. 1a and 1b, the voltage processing circuit 10 is used to provide a stable power supply voltage to the temperature sensing module S2, and the temperature sensing module S2 can measure the temperature of the device under test S1.

The voltage processing circuit provided by the embodiment of the application is composed of voltage-driven analog devices, and can adapt to different digital domain voltage working ranges by selecting the analog devices with different voltage thresholds, so that the analog voltage processing circuit meeting the digital voltage domain can meet the requirements of wide power supply voltage working range and low required voltage of the digital voltage domain. For example, in a 12 nm fet compact implementation, the digital domain voltage may range from 500mV to 1050mV, and by choosing analog devices with different voltage thresholds, the output voltage Vout of the voltage processing circuit 10 may be adjusted to meet the wide range of digital domain voltage requirements.

In addition, the requirement of Low Voltage in the digital domain can be met by selecting an analog device with an Ultra Low Voltage Threshold (ulvt). The ulvt device can be an MOS tube, so that the supply voltage output by the voltage processing circuit can be as low as 450mV, the circuit can work in a digital voltage domain, and the requirement of low supply voltage of the digital voltage domain is met. As in a 12 nm field effect transistor compact scheme, the supply voltage can be as low as 500mV. The circuit can not be realized by PNP, NPN and other devices in the traditional analog voltage conversion circuit. On one hand, the triode is in a driving mode of driving large current by small current, the triode is conducted, and the generated current is large, so that the load voltage is large, and the requirement of low voltage of a digital domain cannot be met; on the other hand, the voltage regulating range of the voltage conversion circuit formed by the triodes is small, and the requirement of wide range of digital domain voltage cannot be met.

The following describes an implementation structure and an operation principle of the voltage processing circuit provided in the embodiment of the present application. Fig. 1c is a schematic structural diagram of a voltage processing circuit according to an embodiment of the present disclosure. As shown in fig. 1c, the voltage processing circuit 10 includes: a current generation circuit 101, a current comparator 102, a current sampling circuit 103, and a voltage output circuit 104. The current generation circuit 101, the current comparator 102, the current sampling circuit 103, and the voltage output circuit 104 may be composed of voltage-driven analog devices.

In the present embodiment, the current generating circuit 101, the current comparator 102, and the voltage output circuit 104 are electrically connected to a power source terminal Vin for supplying power to the power receiving device. Specifically, analog devices in the current generation circuit 101, the current comparator 102, and the voltage output circuit 104 are electrically connected to a power supply terminal Vin that supplies power to the power-receiving device. The analog devices in the current comparator 102 may be electrically connected to the analog devices in the current generation circuit 101 to form a mirror circuit, and the analog devices in the current comparator 102 may also be electrically connected to the analog devices in the current sampling circuit 103 to form a mirror circuit.

In the present embodiment, the reference current I1 can be generated in the case where the analog device in the current generation circuit 101 is driven. Since the analog device in the current comparator 102 forms a mirror circuit with the current generation circuit 101, a mirror current I2 of the reference current I1 can be generated. The mirror current of the reference current is equal to the reference current in magnitude and same in direction.

The analog devices in the current comparator 102 are also electrically connected to the analog devices in the voltage output circuit 104. The current comparator 102 generates a mirror current I2 of the reference current, which triggers the analog device in the voltage output circuit 104 to output the supply voltage Vout, i.e. the voltage output circuit 104 generates the supply voltage Vout. The analog device in the current sampling circuit 103 is electrically connected to the voltage output circuit 104, and can sample the output voltage of the analog device in the voltage output circuit 104 to obtain the sampling current I3. Accordingly, the supply voltage Vout output by the voltage output circuit 104 is sampled by the current sampling circuit 103 to obtain a sampling current I3. Since the analog device in the current comparator 102 is also electrically connected to the current sampling circuit 103 to form a mirror circuit, the analog device in the current comparator 102 can also generate a mirror current I4 of the sampling current I3.

In the present embodiment, the current comparator 102 may adjust the supply voltage Vout output by the analog device of the voltage output circuit 104 according to the magnitude relationship between the mirror current I3 of the reference current and the mirror current I4 of the sampling current. Specifically, the current comparator 102 may adjust the magnitude of the turn-on signal of the analog device of the voltage output circuit 104 according to the magnitude relationship between the mirror current I3 of the reference current and the mirror current I4 of the sampling current, so as to adjust the turn-on capability of the voltage output circuit 104, and adjust the supply voltage Vout output by the voltage output circuit 104 by adjusting the turn-on capability of the voltage output circuit 104.

The supply voltage Vout output by the voltage output circuit 104 changes, which causes the sampling current I3 collected by the current sampling circuit 103 to change, and thus causes the mirror current I4 of the sampling current I3 to change, and this is repeated until the mirror current I4 of the sampling current is equal to the mirror current I3 of the reference current. The mirror current I4 of the sampling current is equal to the mirror current I3 of the reference current, the conduction capability of the analog device in the voltage output circuit 104 is balanced, and the stable power supply voltage Vout is output, that is, the volt-ampere (IV) characteristic of the analog device in the voltage output circuit 104 is utilized to realize the voltage stabilization of the power supply terminal, which is helpful for improving the stability of the power supply voltage.

The voltage output circuit 104 may be electrically connected to the current-receiving device, and may output the power supply voltage Vout to the current-receiving device, so as to provide the voltage-stabilized power supply voltage Vout to the current-receiving device, thereby reducing the influence of the power supply voltage fluctuation on the current-receiving device.

In the embodiment of the present application, the current generation circuit 101, the current comparator 102, the current sampling circuit 103, and the voltage output circuit 104 may be composed of voltage-driven analog devices, but are not limited to the specific implementation form thereof. In some embodiments, the current generation circuit 101, the current comparator 102, the current sampling circuit 103, and the voltage output circuit 104 may be implemented by voltage-driven analog devices, and by using analog devices with different threshold voltages, the requirements of a digital voltage domain on a wide operating range of a power supply voltage and a low power supply voltage are met, so as to implement an analog voltage processing circuit meeting the digital voltage domain.

The following describes an exemplary implementation of the current generation circuit 101, the current comparator 102, the current sampling circuit 103, and the voltage output circuit 104 provided in this embodiment.

In some embodiments, as shown in fig. 2, the current generation circuit includes: a voltage difference circuit 1011 and a first mirror circuit 1012 connected in series. The differential voltage circuit 1011 and the first mirror circuit 1012 include: analog devices driven by voltage. The analog devices in the differential voltage circuit 1011 are electrically connected to the power source terminal Vin. The analog devices in the current comparator 102 are electrically connected to the serial connection path between the differential voltage circuit 1011 and the first mirror circuit 1012, and form a mirror circuit with the first mirror circuit 1012.

The voltage difference circuit 1011 may generate a voltage difference in a case where the analog device thereof is driven, and may generate the reference current I0 based on the generated voltage difference. The voltage difference circuit 1011 can output the reference current I0 to the first mirror circuit 1012. Accordingly, the analog devices in the first mirror circuit 1012 may mirror the reference current I0, and generate a mirror current of the reference current I0 as the reference current I1.

In the embodiment of the present application, the specific implementation form of the differential voltage circuit 1011 is not limited. In some embodiments, as may be obtained in conjunction with the circuit diagrams shown in fig. 3-8, the analog components of the differential pressure circuit 1011 may include: a first PMOS circuit 1011a and a second PMOS circuit 1011b having different threshold voltages. The threshold voltage of the first PMOS circuit is larger than or smaller than that of the second PMOS circuit. The differential voltage circuit 1011 may further include: and a resistor R1.

Considering that the threshold voltages of the MOS transistors with the same specification are the same or similar, and the threshold voltages of the MOS transistors with different specifications are different, in this embodiment, in order to achieve the difference between the threshold voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b, the first PMOS circuit 1011a and the second PMOS circuit 1011b may adopt PMOS transistors with different specifications. Alternatively, the first PMOS circuit 1011a and the second PMOS circuit 1011b may be implemented by PMOS transistors with the same specification and different numbers. The specification of the PMOS tube refers to the type and the size of the PMOS tube. The PMOS tubes have the same specification, which means that the types and the sizes of the PMOS tubes are the same. The specification of the PMOS tubes can be different, and the PMOS tubes can be different in type and/or size.

For the embodiment that uses the same number of PMOS transistors to make the first PMOS circuit 1011a and the second PMOS circuit 1011b, the number of PMOS transistors in the first PMOS circuit 1011a is greater than or less than the number of PMOS transistors in the second PMOS circuit 1011b. For a circuit comprising a plurality of PMOS tubes, the PMOS tubes are connected in parallel. Plural means 2 or more. The more the number of the PMOS tubes connected in parallel is, the larger the threshold voltage of the PMOS circuit is. For the case that the threshold voltage of the first PMOS circuit is larger than that of the second PMOS circuit, the first PMOS circuit comprises a larger number of PMOS tubes than the second PMOS circuit comprises.

For example, the first PMOS circuit 1011a includes: a plurality of PMOS tubes MP1 connected in parallel; the second PMOS circuit 1011b includes: at least one PMOS tube MP2 with the same specification as the PMOS tube MP1; wherein, the number of the PMOS tubes MP1 is larger than that of the PMOS tubes MP 2. The second PMOS circuit 1011b includes a plurality of PMOS transistors MP2, and the plurality of PMOS transistors MP2 are connected in parallel.

In the embodiment of the application, for a PMOS circuit comprising a plurality of PMOS tubes connected in parallel, a plurality of PMOS tubes share a common source and a drain; the gates of the PMOS transistors are electrically connected to a driving circuit (not shown). Correspondingly, the PMOS circuit comprises a plurality of PMOS tubes connected in parallel, wherein the grid electrode of the PMOS tube refers to the grid electrode of each PMOS tube, and the source electrode and the drain electrode are respectively the source electrode and the drain electrode which are common to the PMOS tubes.

Referring to fig. 3 to 8, the sources of the first PMOS circuit 1011a and the second PMOS circuit 1011b are electrically connected to the power source terminal Vin. Gates of the first PMOS circuit 1011a and the second PMOS circuit 1011b are electrically connected to both ends of the resistor R1. The first PMOS circuit 1011a and the second PMOS circuit 1011b may be activated by a driving circuit (not shown in fig. 3-8). Because the threshold voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b are different, the first PMOS circuit 1011a and the second PMOS circuit are activated, the voltages at the two ends of the resistor R1 are the gate voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b, respectively, the voltages at the two ends of the resistor R1 are different, and a voltage difference is generated at the two ends of the resistor R1. Further, the resistor R1 generates a reference current I0 due to the voltage difference; and outputs I0 to the first branch 1012a of the first mirror circuit 1012.

The second branch 1012b of the first mirror circuit 1012 is electrically connected to the first PMOS circuit 1011 a. The first PMOS circuit 1011a is enabled to trigger the second branch 1012b of the first mirror circuit to generate a mirror current of the reference current I0, i.e. the reference current I1. Specifically, the first PMOS circuit 1011a is turned on to trigger the second branch 1012b of the first mirror circuit to be turned on, the second branch 1012b generates a current, and since the second branch 1012b of the first mirror circuit and the first branch 1012a form a mirror circuit, the current generated by the second branch 1012b is equal to the reference current I0 flowing through the first branch 1012a, and the second branch 1012b generates a mirror current of the reference current I0, i.e., the reference current I1.

Alternatively, as shown in fig. 3-8, for the first mirror circuit 1012, the analog devices of the first branch 1012a may include: an NMOS transistor MN2; the analog devices of the second branch 1012b of the first mirror circuit include: and the NMOS transistor MN1 has the same specification as the NMOS transistor MN2. The drain electrode of the NMOS tube MN2 is electrically connected with the resistor R1; the grid electrode of the NMOS tube MN2 is electrically connected with the grid electrode of the NMOS tube MN 1; the drain electrode of the NMOS transistor MN1 is electrically connected with the drain electrode of the first PMOS circuit 1011a, and the drain electrode of the NMOS transistor MN1 is in short circuit with the grid electrode; the source electrodes of the NMOS transistor MN1 and the NMOS transistor MN2 are grounded.

Based on the connection relationship, the first PMOS circuit 1011a and the second PMOS circuit 1011b are started, the PMOS transistor MP1 in the first PMOS circuit 1011a and the PMOS transistor MP2 in the second PMOS circuit 1011b are turned on, the gate voltages of the NMOS transistors MN1 and MN2 are pulled up to be greater than the threshold voltages of the NMOS transistors MN1 and MN2, and the NMOS transistors MN1 and MN2 are triggered to be turned on. The NMOS transistor MN2 is turned on to form a path 1 from the power source terminal Vin to ground through the second PMOS circuit 1011b, the resistor R1 and the NMOS transistor MN2, as shown by the dotted line in fig. 5, with the second PMOS circuit 1011b and the resistor R1. For the resistor R1 in the path 1, the voltage at two ends of the resistor R1 is respectively equal to the gate voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b, and the gate voltages of the first PMOS circuit 1011a and the second PMOS circuit 1011b are different, so that a voltage difference is generated at two ends of the resistor R1, and then the resistor R1 generates a reference current I0, which is output to the NMOS transistor MN2. Accordingly, the drain current of the NMOS transistor MN2 is I0.

As shown by the dotted line in fig. 5, the NMOS transistor MN1 is turned on, and forms a path 2 from the power source terminal Vin to the ground through the first PMOS circuit 1011a and the NMOS transistor MN1 with the first PMOS circuit 1011a, and since the NMOS transistor MN1 and the NMOS transistor MN2 form a mirror circuit, the drain current I1 of the NMOS transistor MN1 is equal to the drain current I0 of the NMOS transistor MN2, and the drain current of the NMOS transistor MN2 can be understood as a mirror image of the drain current of the NMOS transistor MN1, that is, the NMOS transistor MN1 generates the reference current I1 which is a mirror image of the reference current I0.

Referring to fig. 3-8, the current comparator 102 is electrically connected to a serial connection path between the drain of the first PMOS circuit 1011a and the drain of the NMOS transistor MN1, and forms a mirror circuit with the NMOS transistor MN1. Therefore, the current comparator 102 generates a mirror current I2 of the reference current I1 during the start-up of the first PMOS circuit 1011 a. Specifically, the first PMOS circuit 1011a is activated, triggering the current comparator 102 to conduct, forming a path, and the current comparator 102 generates a current. Since the current comparator 102 and the NMOS transistor MN1 form a mirror circuit, the current in the current comparator 102 is equal to the reference current I1, i.e. the current comparator 102 generates a mirror current I2 of the reference current I1.

For the current comparator 102, as shown in fig. 2, the current comparator 102 may include: a first circuit unit 1021 and a second circuit unit 1022 connected in series with each other. The first circuit unit 1021 and the second circuit unit 1022 include voltage-driven analog devices. The voltage output circuit 104 is electrically connected to the serial path a of the first circuit unit 1021 and the second circuit unit 1022. The analog devices in the first circuit unit 1021 are electrically connected to the serial connection path between the voltage difference circuit 1011 and the first mirror image circuit 1012, and form a mirror image circuit with the first mirror image circuit 1012. When a voltage difference exists, the voltage difference circuit 1011 triggers the analog device in the first circuit unit 1021 to turn on, and a current is generated on the serial connection path a between the first circuit unit 1021 and the second circuit unit 1022, and since the first circuit unit 1021 and the first mirror circuit 1012 form a mirror circuit, the first circuit unit 1021 turns on, and the current generated on the serial connection path a is equal to the reference current I1 generated by the current generating circuit, that is, the mirror current I2 of the reference current I1 is generated on the serial connection path a.

With reference to the specific circuit structure of the differential voltage circuit 1011 and the first mirror image circuit 1012 shown in fig. 3-8, the first circuit unit 1021 is electrically connected to the serial connection path between the drain of the first PMOS circuit 1011a and the drain of the NMOS transistor MN1, so that when the first PMOS circuit 1011a is activated, the voltage at the connection end of the serial connection path between the drains of the first PMOS circuit 1021 and the first PMOS circuit 1011a and the drain of the NMOS transistor MN1 can be pulled up, thereby triggering the first circuit unit 1021 to be turned on, and generating the mirror image current I2 of the reference current I1 on the serial connection path a between the first circuit unit 1021 and the second circuit unit 1022.

Referring next to fig. 2, the second circuit unit 1022 is electrically connected to an analog device in the current sampling circuit 103, and forms a mirror circuit with the current sampling circuit 103. The current sampling circuit 103 may sample a supply voltage Vout output by an analog device in the voltage output circuit 104 to obtain a sampling current I3. The analog devices in the second circuit unit 1022 and the circuit sampling circuit 103 form a mirror circuit, so that a mirror current I4 of the sampling current I3 can be generated on the serial path a between the second circuit unit 1022 and the first circuit unit 1021.

Accordingly, the current comparator 102 adjusts the magnitude of the turn-on signal of the analog device in the voltage output circuit 104 according to the magnitude relationship between the mirror current I2 of the reference current and the mirror current I4 of the sampling current on the serial path a of the first circuit unit 1021 and the second circuit unit 1022, so as to adjust the output voltage of the voltage output circuit 104. Specifically, since the voltage output circuit 104 is electrically connected to the serial connection path a of the first circuit unit 1021 and the second circuit unit 1022, a mirror current I2 of the reference current and a mirror current I4 of the sampling current exist on the serial connection path a, and when the mirror current I2 of the reference current is not equal to the mirror current I4 of the sampling current, the turn-on signal of the analog device in the voltage output circuit 104 is pulled up or down to adjust the turn-on capability of the voltage output circuit 104 according to the magnitude relationship between the mirror current I2 of the reference current and the mirror current I4 of the sampling current on the serial connection path a, so as to adjust the supply voltage Vout output by the voltage output circuit 104. The magnitude relationship between the mirror current I2 of the reference current and the mirror current I4 of the sampling current on the series path a, and whether to pull up or pull down the conducting signal of the voltage output circuit 104, is specifically determined by the specific implementation structures of the voltage output circuit 104 and the current comparator 102.

The operation principle of the current comparator 102 and the voltage output circuit 104 will be described below with reference to specific circuit structures. In the embodiment of the present application, as shown in fig. 3 to 8, the analog devices of the voltage output circuit 104 may include: and a MOS tube. The MOS transistor has a gate electrically connected to the serial connection path a between the first circuit unit 1021 and the second circuit unit 1022, a source electrically connected to the power source terminal Vin, and a drain serving as a voltage output terminal and electrically connected to the current sampling circuit 103. The current difference between the mirror current I2 of the reference current and the mirror current I4 of the sampling current can adjust the magnitude of the turn-on signal of the trigger voltage output circuit 104, so as to adjust the output voltage of the voltage output circuit 104.

The MOS transistor in the voltage output circuit 104 may be a PMOS transistor or an NMOS transistor. The implementation form of the MOS transistor in the voltage output circuit 104 may affect the circuit structure of the current comparator. The following description will exemplarily take the MOS transistor in the voltage output circuit 104 as a PMOS transistor or an NMOS transistor, respectively.

As shown in fig. 3-5, the analog devices for the voltage output circuit 104 include: for the embodiment of the PMOS transistor MP5, the first circuit unit 1021 includes: and an NMOS transistor MN3. The source electrode of the NMOS transistor MN3 is grounded. The drain of the NMOS transistor MN3 is electrically connected to the second circuit unit 1022, forming the series path a. The gate of the NMOS transistor MN3 is electrically connected to the series path of the voltage difference circuit 1011 and the first mirror circuit 1012. The voltage difference circuit 1011 can trigger the NMOS transistor MN3 to turn on when a voltage difference exists, and generate a mirror current I2 of the reference current I1 on the series connection path a.

With reference to the specific circuit structure of the voltage difference circuit 1011 and the first mirror circuit 1012 shown in fig. 3-5, the NMOS transistor MN3 is electrically connected to the serial connection path between the drain of the first PMOS circuit 1011a and the drain of the NMOS transistor MN1, so as to receive the analysis that the current in the path 1 is equal to the reference current I0, i.e. the current in the path 1 is the mirror current of the reference current I0, as the reference current I1. Therefore, when the first PMOS circuit 1011a is activated, the first PMOS circuit 1011a is turned on, the gate voltage of the NMOS transistor MN3 is pulled high, and the NMOS transistor MN3 is turned on, thereby generating a drain current. Since the NMOS transistor MN3 and the NMOS transistor MN1 form a mirror circuit, the drain current of the NMOS transistor MN3 is equal to the reference current I1, which is equivalent to the mirror current I2 of the reference current I1 generated by the drain of the NMOS transistor MN3. Since the NMOS transistor MN3 is connected in series with the second circuit unit 1022 to form the series path a, a mirror current I2 of the reference current I1 is generated on the drain of the NMOS transistor MN3 and the series path a of the second circuit unit 1022.

Accordingly, as shown in fig. 3 to 5, the analog device of the second circuit unit 1022 includes: an NMOS transistor MN4 and a second mirror circuit 1022a including a voltage-driven analog device. The analog device of the second mirror circuit 1032a is connected in series with the drain of the NMOS transistor MN3 to form a series path a. The drain of the NMOS transistor MN4 is also connected in series with the second mirror 1022a, forming a series path B.

The gate of the NMOS transistor MN4 is electrically connected to the analog device in the current sampling circuit 103, and forms a mirror circuit with the analog device in the current sampling circuit 103. Under the condition that the sampling current I3 exists, the current sampling circuit 103 triggers the NMOS tube MN4 to be conducted, and generates a mirror current I4 of the sampling current I3 on the serial connection path B.

The analog device in the second mirror circuit 1022a may mirror the mirror current I4 of the sampling current I3 on the serial path B, and generate a current equal to the mirror current I4 on the serial path a of the NMOS transistor MN3, which may also be referred to as the mirror current I4 of the sampling current.

Alternatively, as shown in fig. 3-5, the analog device of the second mirror circuit 1022a may include: PMOS pipe MP3 and PMOS pipe MP4. The source electrodes of the PMOS tubes MP3 and MP4 are electrically connected with the power supply end Vin; the grid electrode of the PMOS pipe MP3 is electrically connected with the grid electrode of the PMOS pipe MP4. The drain electrode of the PMOS tube MP3 is electrically connected with the drain electrode of the NMOS tube MN3 to form a serial connection path A. The grid electrode and the drain electrode of the PMOS tube MP4 are in short circuit; the drain electrode of the PMOS pipe MP4 is electrically connected with the drain electrode of the NMOS pipe MN 4.

With the circuit structures shown in fig. 3 to fig. 5, when the sampling current I3 exists in the current sampling circuit 103, the current sampling circuit 103 is turned on, so that the gate voltage of the NMOS transistor MN4 is pulled high, and the NMOS transistor MN4 is turned on, thereby generating a drain current. Since the NMOS transistor MN4 and the current sampling circuit 103 form a mirror circuit, the drain current of the NMOS transistor MN4 is equal to the sampling current I3, that is, the NMOS transistor MN4 generates a mirror current I4 of the sampling current I3.

The NMOS transistor MN4 is turned on, the drain voltage of the PMOS transistor MP4 is pulled low, and since the drain of the PMOS transistor MP4 is shorted to the gate and the gates of the PMOS transistors MP3 and MP4 are shorted, the gate voltages of the PMOS transistors MP3 and MP4 are also pulled low, the PMOS transistors MP3 and MP4 are turned on, forming a path 3 from the power supply terminal Vin to the ground through the PMOS transistor MP3 and the NMOS transistor MN3, and a path 4 from the power supply terminal Vin to the ground through the PMOS transistor MP4 and the NMOS transistor MN4, as shown by the dotted line in fig. 5. For the path 4, since the drain of the PMOS transistor MP4 is connected in series with the drain of the NMOS transistor MN4 to form the series path B, the drain current of the PMOS transistor MP4 is equal to the mirror current I4 of the sampling current I3, and the PMOS transistor MP3 and the PMOS transistor MP4 form the second mirror circuit 1012a, so the drain current of the PMOS transistor MP3 is equal to the mirror current I4 of the sampling current I3, that is, the PMOS transistor MP3 generates the mirror current I4 of the sampling current I3 on the series path a with the NMOS transistor MN3.

For the series path a of the PMOS transistor MP3 and the NMOS transistor MN3, there are a mirror current I2 of the reference current and a mirror current I4 of the sampling current I3, and in the starting stage of the voltage processing circuit, the mirror current I2 of the reference current and the mirror current I4 of the sampling current I3 are not equal, which results in the mirror current I2 of the reference current and the mirror current I4 of the sampling current in the current comparator 102, and adjusts the gate voltage of the PMOS transistor MP5 in the voltage output circuit 104 to adjust the conduction capability of the PMOS transistor MP5, so as to adjust the supply voltage output by the drain of the PMOS transistor MP 5. The supply voltage output by the drain of the PMOS transistor MP5 changes, which causes the sampling current I3 collected by the current sampling circuit 103 to change, and further causes the mirror current I4 of the sampling current I3 in the current comparator 102 to change, and sequentially reciprocates until the mirror current I4 of the sampling current in the current comparator 102 is equal to the mirror current I2 of the reference current, the gate voltage of the PMOS transistor MP5 does not change any more, and a stable supply voltage is output.

Specifically, it is assumed that, in the starting stage of the voltage processing circuit, the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current, and since the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current, the gate voltage of the PMOS transistor MP5 connected on the series connection path a can be pulled up, the conduction capability of the PMOS transistor MP5 is reduced, and the supply voltage Vout output by the drain of the PMOS transistor MP5 is reduced. Further, as the supply voltage Vout output by the drain of the PMOS transistor MP5 decreases, the sampling current I3 collected by the current sampling circuit 103 decreases, which further causes the mirror current I4 of the sampling current I3 in the current comparator 102 to decrease, and repeats in sequence until the mirror current I4 of the sampling current I3 in the current comparator 102 is equal to the mirror current I2 of the reference current. When the mirror current I4 of the sampling current I3 is equal to the mirror current I2 of the reference current, the gate voltage of the PMOS transistor MP5 is not changed any more, the conduction capability thereof is stabilized, and the supply voltage Vout output by the drain of the PMOS transistor MP5 is stabilized, that is, the voltage stabilization is realized by using the IV characteristic of the PMOS transistor MP 5.

In other embodiments, as shown in fig. 6-8, the MOS transistor included in the voltage output circuit 104 is an NMOS transistor MN7. The source electrode of the MOS transistor MN7 is electrically connected with a power end Vin; the gate of the NMOS transistor MN7 is electrically connected to the serial connection path a of the first circuit unit 1021 and the second circuit unit 1022. The current comparator 102 adjusts the magnitude of the on-signal triggering the gate of the NMOS transistor MN7 according to the magnitude relationship between the mirror current of the reference current in the serial path a and the output current, so as to adjust the supply voltage Vout output by the drain of the NMOS transistor MN7.

Accordingly, for the embodiment in which the MOS transistor included in the voltage output circuit 104 is the NMOS transistor MN7, in conjunction with fig. 6 to 8, the analog device of the first circuit unit 1021 includes: an NMOS transistor MN3 and a third mirror circuit 1021a including a voltage-driven analog device. The source electrode of the NMOS tube MN3 is grounded; the drain of the NMOS transistor MN3 is electrically connected to the third mirror circuit 1021a, forming a serial path B. The analog devices of the third mirror circuit 1021a are electrically connected to the second circuit unit 1022, forming a serial path a.

As shown in fig. 6-8, the gate of the NMOS transistor MN3 is electrically connected to the serial connection path of the voltage difference circuit 1011 and the first mirror image circuit 1012 to form a mirror image circuit with the first mirror image circuit 1012; under the condition that the voltage difference exists, the voltage difference circuit triggers the NMOS tube MN3 to be conducted, and the mirror current I2 of the reference current I1 is generated on the serial connection path B. In the description of the NMOS transistor MN3 generating the mirror current I2 of the reference current I1 on the serial path B, reference is made to the related embodiments of fig. 3-5, where the NMOS transistor MN3 generates the mirror current I2 of the reference current I1 on the serial path a.

Accordingly, the analog device of the third mirror circuit 1021a mirrors the current on the serial path B, and generates a mirror current I2 on the serial path a, which is the same current as the current on the serial path B, i.e. the reference current I1.

Alternatively, as shown in fig. 6 to 8 in combination, the analog device of the third mirror circuit 1021a includes: PMOS pipe MP3 and PMOS pipe MP4. The source electrodes of the PMOS tubes MP3 and MP4 are electrically connected with a power supply end; the grid electrode of the PMOS tube MP3 is electrically connected with the grid electrode of the PMOS tube MP4; the drain electrode of the PMOS tube MP3 is electrically connected with the drain electrode of the NMOS tube MN3 to form a serial connection path B. The gate and the drain of the PMOS transistor MP4 are shorted, and the drain of the PMOS transistor MP4 is connected in series with the second circuit unit 1022 to form a series connection path a.

In this embodiment, the NMOS transistor MN3 is turned on to trigger the PMOS transistor MP3 and the PMOS transistor MP4 to be turned on, and a mirror current I2 of the reference current I1 is generated on the serial connection path B between the PMOS transistor MP3 and the NMOS transistor MN3; the PMOS transistor MP4 is turned on, and generates a current on the series path a equal to the current on the series path B, i.e. a mirror current I2 of the reference current.

Specifically, in connection with the above analysis of the conduction of the NMOS transistor MN3 in fig. 3-5, in conjunction with the specific circuit structure shown in fig. 6-8, the NMOS transistor MN3 is turned on, the drain voltage of the PMOS transistor MP3 connected in series with the NMOS transistor is pulled low, and the drain of the PMOS transistor MP3 is shorted to the gate, and the gates of the PMOS transistors MP3 and MP4 are shorted, so the gate voltages of the PMOS transistors MP3 and MP4 are pulled low, and the PMOS transistors MP3 and MP4 are turned on, thereby forming a path 5 from the power source terminal Vin to the ground through the PMOS transistor MP3 and the NMOS transistor MN3, and a path 6 from the power source terminal Vin to the ground through the PMOS transistor MP4 and the second circuit unit 1022, as shown by the dotted line in fig. 8. Wherein, the series path B is located on the path 5, and the series path A is located on the path 6. Since the NMOS transistor MN3 and the NMOS transistor MN1 form a mirror circuit, the drain current of the NMOS transistor MN3 is equal to the reference current, i.e., the drain current of the NMOS transistor MN3 is equal to the mirror current I2 of the reference current I1. Accordingly, the current on the series path B is equal to the mirror current I2 of the reference current I1.

Further, since the drain of the PMOS transistor MP3 is connected in series with the drain of the NMOS transistor MN3, the drain current of the PMOS transistor MP3 is also equal to the mirror current I2 of the reference current I1. On the other hand, since the PMOS transistor MP4 and the PMOS transistor MP3 form a mirror circuit, the drain current of the PMOS transistor MP4 is equal to the drain current of the MOS transistor MP3, i.e. equal to the mirror current I2 of the reference current I1. Accordingly, the current in the series path a is equal to the mirror current I2 of the reference current I1, i.e. the mirror current I2 of the reference current I1 is generated in the series path a of the PMOS transistor MP4 and the second circuit unit 1022.

Accordingly, the analog device of the second circuit unit includes: an NMOS tube MN4; the drain of the NMOS transistor MN4 is connected in series with the drain of the PMOS transistor MP4 to form a series connection path A.

The grid electrode of the NMOS tube MN4 is electrically connected with the analog device of the current sampling circuit 103 and forms a mirror image circuit with the analog device of the current sampling circuit 103; under the condition that the sampling current exists, the current sampling circuit 103 can trigger the conduction of the NMOS transistor MN4, and the mirror current of the sampling current is generated on the serial connection path A. Specifically, the current sampling circuit 103 may trigger the NMOS transistor MN4 to turn on when the sampling current exists, and the NMOS transistor MN4 generates a drain current. Since the NMOS transistor MN4 forms a mirror circuit with the current sampling circuit 103, the drain current of the NMOS transistor MN4 is equal to the mirror current I4 of the sampling current I3. Since the drain of the NMOS transistor MN4 is connected in series with the PMOS transistor MP4 of the first circuit unit 1021 to form the series path a, the current on the series path a is equal to the drain current of the NMOS transistor MN4, i.e. a mirror current I4 of the sampling current I3 is generated on the series path a.

For the series path a of the PMOS transistor MP4 and the NMOS transistor MN4, there are a mirror current I2 of the reference current and a mirror current I4 of the sampling current I3, and at the start stage of the voltage processing circuit, the mirror current I2 of the reference current and the mirror current I4 of the sampling current I3 are not equal, which results in the mirror current I2 of the reference current and the mirror current I4 of the sampling current in the current comparator 102, and adjusts the gate voltage of the NMOS transistor MN7 in the voltage output circuit 104 to adjust the conduction capability of the NMOS transistor MN7, thereby adjusting the supply voltage output by the drain of the NMOS transistor MN7. The supply voltage output by the drain of the NMOS transistor MN7 changes, which causes the magnitude of the sampling current I3 collected by the current sampling circuit 103 to change, and further causes the mirror current I4 of the sampling current I3 in the current comparator 102 to change, and the steps are repeated in sequence until the mirror current I4 of the sampling current in the current comparator 102 is equal to the mirror current I2 of the reference current, and the gate voltage of the NMOS transistor MN7 no longer changes, and stable supply voltage is output.

Specifically, assuming that the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current at the start-up stage of the voltage processing circuit, since the mirror current I4 of the sampling current I3 is greater than the mirror current I2 of the reference current, the gate voltage of the NMOS transistor MN7 connected to the series connection path a may be pulled down, the conduction capability of the PMOS transistor MP5 is reduced, and the supply voltage Vout output by the drain of the NMOS transistor MN7 is reduced. Further, as the supply voltage Vout output by the drain of the NMOS transistor MN7 is reduced, the sampling current I3 collected by the current sampling circuit 103 is reduced, which further causes the mirror current I4 of the sampling current I3 in the current comparator 102 to be reduced, and the steps are repeated until the mirror current I4 of the sampling current I3 in the current comparator 102 is equal to the mirror current I2 of the reference current. When the mirror current I4 of the sampling current I3 is equal to the mirror current I2 of the reference current, the gate voltage of the NMOS transistor MN7 is not changed any more, the conduction capability thereof is stabilized, and further the supply voltage Vout output by the drain of the NMOS transistor MN7 is stabilized.

In the embodiment of the present application, regardless of which MOS transistor is used as the voltage output circuit 104, as shown in fig. 3 to 8, the current sampling circuit 103 may include: a switching circuit 1031 including voltage-driven analog devices and an NMOS transistor MN5.

The analog device of the switch circuit 1031 is electrically connected between the voltage output circuit 104 and the drain of the NMOS transistor MN5. The voltage output circuit 104 includes: in the case of a MOS transistor, the analog device of the switch circuit 1031 is electrically connected between the drain of the voltage output circuit 104 and the drain of the NMOS transistor MN5.

The grid electrode of the NMOS tube MN5 is electrically connected with the grid electrode of the NMOS tube MN4; the grid electrode of the NMOS tube MN5 is in short circuit with the drain electrode; the source of the NMOS transistor MN5 is grounded. In this way, the NMOS transistor MN5 forms a mirror circuit with the NMOS transistor MN 4.

The analog device of the switch circuit 1031 may be turned on when the voltage output circuit 104 outputs the supply voltage, and trigger the NMOS transistor MN5 to be turned on, so as to form a path from the supply voltage Vout output from the voltage output circuit 104 to the ground through the switch circuit 1031 and the NMOS transistor MN5, where the path generates a current, i.e., a sampling current I3, thereby implementing current sampling of the supply voltage Vout by the current sampling circuit 103.

Alternatively, as shown in fig. 3-5, the analog devices of the switching circuit 1031 may include: and an NMOS transistor MN6. The drain electrode of the NMOS transistor MN6 is electrically connected with the voltage output circuit 104; the grid electrode and the drain electrode of the NMOS tube MN6 are in short circuit; the source electrode of the NMOS pipe MN6 is electrically connected with the drain electrode of the NMOS pipe MN5. For the current sampling circuits shown in fig. 3-5, the drain of the NMOS transistor MN6 is electrically connected to the voltage output terminal of the voltage output circuit 104, and the drain of the NMOS transistor MN6 is shorted with the gate, so that the voltage output circuit 104 outputs the supply voltage to pull up the gate voltage of the NMOS transistor MN6, and the NMOS transistor MN6 is turned on.

The NMOS tube MN6 is connected to pull up the drain voltage of the NMOS tube MN5, and the drain of the NMOS tube MN5 is in short circuit with the gate, so that the NMOS tube MN6 is connected to pull up the gate voltage of the NMOS tube MN5 to trigger the connection of the NMOS tube MN5, a path of the power supply voltage Vout output from the voltage output circuit 104 to the ground through the NMOS tube MN6 and the NMOS tube MN5 is formed, the path can generate current, namely sampling current I3, and the current sampling of the power supply voltage Vout by the current sampling circuit 103 is realized.

In other embodiments, as shown in fig. 6-8, the analog devices of the switching circuit 1031 may also include: PMOS pipe MP6. The source electrode of the PMOS pipe MP6 is electrically connected with the voltage output circuit; the grid electrode of the PMOS pipe MP6 is in short circuit with the drain electrode; the drain electrode of the PMOS pipe MP6 is electrically connected with the drain electrode of the NMOS pipe MN5.

For the current sampling circuit shown in fig. 4, the source of the PMOS transistor MP6 is electrically connected to the voltage output terminal of the voltage output circuit 104, so that the voltage output circuit 104 outputs a supply voltage to pull up the source voltage of the PMOS transistor MP6, so that the voltage difference between the source voltage and the gate voltage of the PMOS transistor MP6 is greater than the threshold voltage of the PMOS transistor MP6, and the PMOS transistor MP6 is turned on.

The PMOS tube MP6 is connected to pull up the drain voltage of the NMOS tube MN5, and the drain of the NMOS tube MN5 is in short circuit with the gate, so that the PMOS tube MP6 is connected to pull up the gate voltage of the NMOS tube MN5 to trigger the connection of the NMOS tube MN5, a path of the power supply voltage Vout output from the voltage output circuit 104 to the ground through the PMOS tube MP6 and the NMOS tube MN5 is formed, the path can generate current, namely sampling current I3, and the current sampling of the power supply voltage Vout by the current sampling circuit 103 is realized.

The current sampling circuit in the voltage processing circuit provided in fig. 3-8 described above uses MOS transistors as sampling devices, and using the I-V characteristics of the MOS transistors can reduce the influence of the change of the reference voltage I1 on the supply voltage output by the voltage sampling circuit, and reduce the change of the supply voltage Vout caused by the change of the reference current I1.

It should be noted that the circuit structures shown in fig. 3 to 8 are merely exemplary. In some embodiments, the current sampling circuit 103 shown in fig. 3-5 may be combined with the current generating circuit 101, the current comparator 102, and the voltage output circuit 104 shown in fig. 6-8 to form another voltage processing circuit. In other embodiments, the current sampling circuit 103 shown in fig. 6-8 may be combined with the current generating circuit 101, the current comparator 102, and the voltage output circuit 104 shown in fig. 3-5 to form a further voltage processing circuit; and so on.

It should be further noted that, in the voltage processing circuit provided in the embodiment of the present application, in addition to improving the stability of the output voltage, the voltage processing circuit provided in fig. 3 to 8 may be configured to stabilize the voltage of the power source terminal Vin for supplying power to the power receiving device by using MOS transistors with different voltage thresholds, so as to obtain different power supply voltages and meet different voltage requirements of the power receiving device, thereby meeting the requirements of a digital voltage domain on a wide range of power supply voltages. On the other hand, the MOS transistor may be an Ultra Low Voltage Threshold (ulvt) MOS transistor, and the supply Voltage output by the Voltage processing circuit may be as Low as 450mV, which may meet the requirement that the supply Voltage of the digital Voltage domain is very Low, for example, the Voltage of the digital Voltage domain may be as Low as 500mV. The circuit can not be realized by PNP, NPN and other devices in the traditional analog voltage conversion circuit.

The current comparator in the voltage processing circuit provided by fig. 3-8 adopts a loop structure formed by MOS transistors, and the MOS transistors have high cut-off frequency, so that the current comparator has high response speed and is applicable to high-frequency digital circuits.

The voltage processing circuit provided by the embodiment of the application can be applied to any power receiving device and is used for providing stable power supply voltage for the power receiving device. For example, the voltage processing circuit provided by the embodiment of the application can be used as a power supply module of the digital temperature sensor to provide stable voltage for the digital temperature sensor, so that the influence of power supply voltage fluctuation on the temperature measurement accuracy of the digital temperature sensor can be reduced, and the improvement of the temperature measurement accuracy of the digital temperature sensor is facilitated.

The following is an exemplary description of the digital temperature sensor provided in the embodiments of the present application.

Fig. 9 is a schematic structural diagram of a digital temperature sensor according to an embodiment of the present application. As shown in fig. 9, the digital Temperature Sensor (TS) includes: a voltage processing circuit 10 composed of voltage-driven analog devices and a temperature sensing module S2. Wherein, the temperature sensing module S2 includes: a temperature sensing circuit 20 and a temperature determining circuit 30. Wherein, the voltage processing circuit 10 is electrically connected with the temperature sensing circuit 20.

In the present embodiment, the input terminal of the voltage processing circuit 10 is electrically connected to the power supply terminal Vin powered by the digital temperature sensor TS; the output of which is electrically connected to the temperature sensing circuit 20 and the temperature determining circuit 30. The voltage processing circuit 10 may stabilize the power supply voltage using the IV characteristics of its analog devices and provide the stabilized supply voltage Vout to the temperature sensing circuit 20 and the temperature determination circuit 30. For a specific implementation form and an operation principle of the voltage processing circuit 10, reference may be made to the related contents described in fig. 1b and fig. 1c and the foregoing fig. 2 to fig. 8, which are not repeated herein.

The temperature sensing circuit 20 is electrically connected to the temperature determining circuit 30. As shown in fig. 1a, the temperature sensing circuit 20 can generate a signal to be measured corresponding to the temperature of the device under test. The signal to be measured can reflect the temperature information of the device to be measured to a certain extent. The temperature sensing circuit 20 outputs the generated signal to be measured to the temperature determining circuit 30.

Accordingly, the temperature determination circuit 30 can determine the temperature of the device under test according to the signal to be measured, thereby realizing the temperature measurement of the device under test.

Alternatively, the temperature determination circuit 30 may determine the temperature of the device under test according to the signal under test and the corresponding relationship between the pre-calibrated detection signal and the temperature.

Wherein, the detection signal in the corresponding relation between the detection signal and the temperature refers to: the temperature sensing circuit 20 generates a signal carrying temperature information. In this embodiment, a specific implementation form of the correspondence relationship between the detection signal and the temperature is not limited. In some embodiments, the correspondence between the detection signal and the temperature may be implemented as a mathematical model with the detection signal as an independent variable and the temperature as a dependent variable. Accordingly, the temperature determination circuit 30 may send the signal to be measured to the mathematical model as an independent variable of the mathematical model to solve, and obtain a dependent variable value of the mathematical model, where the dependent variable value is the temperature corresponding to the signal to be measured.

The corresponding relationship between the detection signal and the temperature can be obtained by calibrating the temperature sensor before each measurement, or by calibrating the temperature sensor before delivery. Accordingly, as shown in fig. 10, the digital temperature sensor TS may further include: a temperature calibration circuit 40. The temperature calibration circuit 40 is electrically connected between the temperature sensing circuit 20 and the temperature determination circuit 30, and is used for calibrating the corresponding relationship between the detection signal and the temperature; and supplies the correspondence relationship between the detection signal and the temperature to the temperature determination circuit 30.

In some embodiments, when the digital temperature sensor is subjected to temperature calibration, the digital temperature sensor can be placed in a thermostat, and the temperature control precision of the thermostat is higher than the temperature measurement precision requirement of the temperature sensor. For example, the temperature measurement precision of the temperature sensor is required to be less than or equal to +/-0.05 ℃; the temperature control precision of the constant temperature device is higher than +/-0.05 ℃, for example, the constant temperature device can be +/-0.01 ℃, +/-0.001 ℃ and the like.

Accordingly, when the digital temperature sensor TS is temperature-calibrated, the set temperature of the thermostat may be defined as a calibration temperature. In this embodiment, when the temperature calibration is performed on the digital temperature sensor TS, the digital temperature sensor TS may be tested multiple times at different calibration temperatures. The temperature of the thermostat can be set to a calibration temperature for each test, so that the temperature sensing circuit 20 can sense the calibration temperature and generate a test signal corresponding to the calibration temperature to be output to the temperature correction circuit 40. In this embodiment, in order to improve the temperature calibration accuracy, the temperature sensor TS may be tested multiple times at the same calibration temperature, the temperature sensing circuit 20 may sense the calibration temperature, and the generated multiple test signals are output to the temperature correction circuit 40, so that the temperature correction circuit 40 may obtain multiple sets of test signals corresponding to the multiple calibration temperatures sensed by the temperature sensing circuit 20. Wherein each calibration temperature corresponds to a set of test signals, which may include a plurality of test signals generated by the temperature sensing circuit 20 from a plurality of tests at the corresponding calibration temperature. Multiple times means 2 times or more than 2 times. Plural means 2 or more.

Further, the temperature calibration circuit 40 may calibrate a corresponding relationship between the detection signal output by the temperature sensing circuit and the temperature according to the plurality of sets of test signals and the calibration temperature during the process of obtaining the plurality of sets of test signals.

In some embodiments, the temperature correction circuit 40 may calculate an average value of the test signal at each calibration temperature to obtain a test average signal corresponding to each of the plurality of calibration temperatures; calculating coefficients of a mathematical model reflecting the corresponding relation between the detection signals and the temperatures by using the plurality of calibration temperatures and the test mean value signals corresponding to the plurality of calibration temperatures; then, the coefficients of the mathematical model are introduced into the mathematical model to obtain the mathematical model with the detection signal as independent variable and the temperature as dependent variable.

The above description is only made with reference to the calibration logic of the temperature correction circuit 40, and the specific configuration for realizing the temperature correction circuit 40 is not limited. In some embodiments, as shown in fig. 11, the temperature correction circuit 40 may include: a cumulative average module 401 and a parameter calculation module 402. The cumulative average module 401 may perform cumulative average on the test signal at each calibration temperature to obtain a test average signal at the calibration temperature. The parameter calculation module 402 calculates coefficients of a mathematical model reflecting the correspondence between the detection signals and the temperatures using the plurality of calibration temperatures and the test mean signals corresponding to the plurality of calibration temperatures.

In the embodiment of the present application, the specific implementation forms of the cumulative averaging module 401 and the parameter calculating module 402 are not limited. In some embodiments, as shown in fig. 11, the cumulative averaging module 401 may include: an accumulator and a divider. Alternatively, the accumulator may be comprised of a cascade of a plurality of adders. The number of adders equals (n-1). Where n represents the number of test signals at each calibration temperature. n is not less than 2 and is an integer.

The accumulator can perform summation calculation on the test signal at each calibration temperature, and input the summed signal into the divider for average calculation to obtain a test average value signal at the calibration temperature. As shown in fig. 11, the accumulator performs summation calculation on the test signals x11, x12,. And x1n at the calibration temperature y1, and inputs the summed signal into the divider for average calculation to obtain a test mean signal x1 at the calibration temperature y 1; similarly, a test mean signal x2 at a standard temperature y2 can be obtained.

The specific circuit structure of the parameter calculating module 402 can be determined by the implementation form of the mathematical model, and the implementation form of the temperature sensing circuit 20 determines the relationship between the temperature and the detection signal carrying the temperature information output by the temperature sensing circuit 20. The following provides an exemplary description of a specific implementation circuit of the temperature sensing circuit provided in the embodiments of the present application.

As shown in fig. 12, the temperature sensing circuit 20 includes: a plurality of Ring Oscillators (ROSCs) 201 having different temperature sensing coefficients, and a calculation circuit 202 electrically connected to the plurality of Ring oscillators 201. Plural means 2 or more. Fig. 12 illustrates only 2 ring oscillators 201, but the number is not limited thereto.

The plurality of ring oscillators 201 are electrically connected to the voltage processing circuit 10. The voltage processing circuit 10 outputs a supply voltage Vout for supplying the plurality of ring oscillators 201. For the ring oscillator 201, the property of the temperature sensing material in the ring oscillator 201 changes with the change of the temperature, which causes the oscillation period of the ring oscillator 201 to change with the change of the temperature, for example, the oscillation period of the ring oscillator 201 can increase with the rise of the temperature. Based on this, in the present embodiment, the ring oscillator 201 may be employed to sense the temperature. The ring oscillator 201 senses the temperature of the device under test and generates a clock signal corresponding to the temperature of the device under test; further, the ring oscillator 201 may also output a clock signal to the connected computing circuitry 202.

Although the oscillation period of a single ring oscillator changes with the change of temperature, the variation relationship between the oscillation period and the temperature has certain uncertainty. Considering that the oscillation periods of different ring oscillators 201 have the same variation trend influenced by temperature, the ratio of the oscillation periods of the ring oscillators 201 has a certain linear relationship with the temperature variation. In this way, the temperature sensing circuit 20 provided in the present embodiment is provided with a plurality of ring oscillators 201 having different temperature sensing coefficients. Since the ring oscillators 201 have different temperature sensing coefficients, different ring oscillators 201 can output clock signals with different oscillation periods at the same temperature.

In the present embodiment, the number and specific implementation form of the ring oscillators 201 are not limited. Alternatively, the ring oscillator 201 may include: m cascaded inverters. Wherein M is an odd number greater than 1. For two adjacent connected inverters, the output end of the previous inverter is electrically connected with the input end of the next inverter. The temperature sensing coefficients of the inverters in different ring oscillators 201 are different. The number of inverters in different ring oscillators 201 may be the same or different.

Alternatively, as shown in fig. 13, the inverters in the ring oscillator 201 may be CMOS inverters. The specifications of MOS transistors included in the CMOS inverters in the different ring oscillators 201 are different. This is mainly because: the gate oxide thickness and the doping concentration of the MOS tube can cause the drift of the process parameters of the MOS tube. The change of the process parameters of the MOS tube can directly cause the change of the threshold voltage and the carrier mobility of the MOS tube. And the carrier mobility and the threshold voltage of the MOS transistor can change along with the change of temperature. Therefore, the different temperature sensing coefficients of the MOS transistors of different specifications lead to different temperature sensing coefficients of the ring oscillators formed by the MOS transistors of different specifications, and further lead to different frequencies of the clock signals output by the ring oscillators formed by the MOS transistors of different specifications at the same temperature.

For a CMOS inverter, as shown in fig. 13, for a CMOS inverter, it may include: PMOS pipe and NMOS pipe. Specifications of PMOS tubes and NMOS tubes in different ring oscillators are different. The source of the PMOS transistor is electrically connected to the voltage processing circuit 10 for receiving the supply voltage Vout. The grid electrode of the PMOS tube is electrically connected with the grid electrode of the NMOS tube; the drain electrode of the PMOS tube is electrically connected with the drain electrode of the NMOS tube; the source electrode of the NMOS tube is grounded. For the CMOS phase inverter, the input end of the CMOS phase inverter can be led out from the connecting path of the grid electrode of the PMOS tube and the grid electrode of the NMOS tube, and the output end of the CMOS phase inverter can be led out from the connecting path of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. The input end of the CMOS inverter is electrically connected with the output end of the last CMOS inverter in cascade connection; the output end of the CMOS phase inverter is electrically connected with the input end of the next CMOS phase inverter in cascade connection. The dotted line connecting the CMOS inverter numbered 2 and the CMOS inverter numbered M (M is an odd number larger than 1) in fig. 13 means: the two inverters are indirectly connected through the other CMOS inverter. In the embodiment of the present application, the number of CMOS inverters included in the ring oscillator is an odd number greater than 1, but the number of CMOS inverters included in the ring oscillator 201 is not limited.

The operation of the ring oscillator formed by the CMOS inverter shown in fig. 13 will be described as an example. As shown in fig. 13, the CMOS inverter numbered k in fig. 13 is simply referred to as a CMOS inverter k for convenience of description. Where k =1,2. M is the total number of CMOS inverters included in the ring oscillator and is an odd number greater than 1.

As shown in fig. 13, the voltage processing circuit 10 is electrically connected to the source of the PMOS transistor in the CMOS inverter, and when the voltage processing circuit 10 supplies power to the CMOS inverter, the supply voltage Vout output by the voltage processing circuit 10 can pull up the source voltage of the PMOS transistor, so that the PMOS transistor is turned on. The PMOS tube in the CMOS phase inverter 1 is conducted to output a high level signal, and the grid voltage of the PMOS tube and the grid voltage of the NMOS tube in the CMOS phase inverter 2 can be pulled up, so that the PMOS tube in the CMOS phase inverter 2 is cut off, the NMOS tube is conducted, and a low level signal is output. NMOS tube in CMOS phase inverter 2 is conducted, and CMOS phase inverter 2 is pulled downAnd the grid voltage of the PMOS tube and the NMOS tube in the next CMOS phase inverter is connected, the PMOS tube in the next CMOS phase inverter connected with the CMOS phase inverter 2 is conducted, and by analogy, the PMOS tube in the CMOS phase inverter M is conducted to output high level. The conduction of the PMOS tube in the CMOS phase inverter M can pull up the gate voltage of the PMOS tube and the NMOS tube in the CMOS phase inverter 1, the conduction of the NMOS tube in the CMOS phase inverter 1 can pull down the gate voltage of the PMOS tube and the NMOS tube in the CMOS phase inverter 2, and the PMOS tube in the CMOS phase inverter M is cut off, the NMOS tube in the CMOS phase inverter M is conducted and outputs a low-level signal. FIG. 14 is a waveform diagram illustrating operation of the ring oscillator of FIG. 13. Wherein the oscillation period of the clock signal is T =2Mt ₀ ，t ₀ The delay time of one CMOS inverter is indicated, and M indicates the number of CMOS inverters included in the ring oscillator.

Because the temperature sensing coefficients of different ring oscillators 201 are different, different ring oscillators 201 can output clock signals with different oscillation periods at the same temperature. Based on this, in the present embodiment, the calculating circuit 202 may calculate the ratio of the frequencies of the clock signals output by the plurality of ring oscillators as the signal to be measured carrying the temperature information generated by the temperature sensing circuit 20.

In the embodiment of the present application, a specific implementation form of the calculation circuit 202 is not limited. In some embodiments, optionally, as shown in fig. 12, the computing circuitry 202 may include: a plurality of counters 202a connected to the plurality of ring oscillators 201, respectively, and a division unit 202b connected to the plurality of counters 202a. Wherein one counter 202a is connected to each ring oscillator 201. A counter 202a that counts pulses of the clock signal output from the ring oscillator 201 connected thereto; and supplies the counted number of pulses to the dividing unit 202b.

The dividing unit 202b may calculate a ratio of the number of pulses included in the clock signals output from the plurality of ring oscillators 201 as a ratio of the frequencies of the clock signals output from the plurality of ring oscillators 201.

In the embodiment of the application, a counter is connected to each ring oscillator. The operation principle and the implementation structure of the computing circuit 202 are exemplarily described below by taking the number of ring oscillators as 2 as an example. In the embodiment of the present application, for convenience of description and distinction, two ring oscillators 201 are respectively defined as: the first ring oscillator 201a and the second ring oscillator 201b define the counter 202a connected to the first ring oscillator 201a as: a first counter Acc1 and a second counter Acc2. Accordingly, the division unit 202b includes: a flip-flop 202a electrically connected to the first counter Acc1 and the second counter Acc2, and a divider 202b electrically connected to the flip-flop 202a. The first counter Acc1 may be electrically connected to the signal input terminal of the flip-flop 202a, and the second counter Acc2 is electrically connected to the enable terminal of the flip-flop 202a.

The first counter Acc1 may perform pulse counting on the clock signal output from the first ring oscillator 201a, and supply the number of pulses of the clock signal output from the connected ring oscillator to the flip-flop 202a. When the enable terminal of the flip-flop 202a is in an inactive state, the flip-flop 202a may register the number of pulses output by the first counter Acc 1; when the enable terminal of the flip-flop 202a is activated, the flip-flop 202a may output the number of pulses output by the first counter Acc 1. For example, with the D flip-flop shown in fig. 12, the signal input terminal D of the D flip-flop is electrically connected to the first counter 201a, and the enable terminal (CLK port) is electrically connected to the second counter 201 b. When the enable end of the D flip-flop is in an inactive state, the D flip-flop can register the number of pulses output by the first counter ACC 1; when the enable terminal of the D flip-flop is activated, the D flip-flop may output the number of pulses output by the first counter Acc 1.

The second counter Acc2 may count pulses of the clock signal output by the second ring oscillator 201b, and the flip-flop 202a may be triggered to output the number of pulses counted by the first counter Acc1 to the divider 202b when the second counter Acc2 is full of pulse counts. Specifically, the second counter 201b may pulse count the clock pulses output by the connected second ring oscillator and, when the pulse count expires, output an activation signal to the enable port (CLK port) of the flip-flop 202a, which may trigger the flip-flop 202a to output the number of pulses counted by the registered first counter 201 a. For example, with the D flip-flop shown in fig. 12, the signal input terminal D of the D flip-flop is electrically connected to the first counter Acc1, and the enable terminal (CLK port) is electrically connected to the second counter Acc2. The second counter Acc2 outputs a high level signal to the enable port (CLK port) of the D flip-flop when the pulse count is full, so that the D flip-flop can output the number of pulses output by the first counter Acc1 registered by the signal input terminal D when the enable terminal of the D flip-flop is activated.

In the embodiment of the present application, for convenience of calculation, the number of pulses when the second counter 201b is full may be stored at the divisor end of the divider 202b in advance, and when the dividend end of the divider 202b receives the number of pulses counted by the first counter ACC1 output by the flip-flop 202a, the ratio between the number of pulses counted by the first counter ACC1 and the number of pulses when the second counter ACC2 is full may be calculated as the ratio between the frequencies of the clock signals output by the first ring oscillator 201a connected to the first counter ACC1 and the second ring oscillator 201b connected to the second counter ACC2, and the ratio may be used as the detection signal (or the signal to be detected) output by the temperature sensing circuit 20.

Compared with the uncertainty between the variation relationship between the oscillation period and the temperature of a single ring oscillator, the temperature sensing circuit provided by the embodiment adopts the ratio of the frequencies of the clock information generated by the plurality of ring oscillators as the signal to be measured, and can obtain the certain linear relationship between the ratio of the frequencies of the clock information generated by the plurality of ring oscillators and the temperature, so that the digital temperature sensor provided by the embodiment performs temperature calculation by utilizing the certain linear relationship between the ratio of the frequencies of the clock information generated by the plurality of ring oscillators and the temperature, and the temperature measurement accuracy of the digital temperature sensor can be further improved.

Since the ratio of the frequencies of the clock signals output from the plurality of clock oscillators 201 has a certain linear relationship with the temperature, a mathematical model reflecting the correspondence relationship between the detection signal and the temperature can be implemented as a polynomial function. The independent variable of the polynomial function is the detection signal, the dependent variable is the temperature, and the coefficient of the polynomial function is calibrated by the temperature correction circuit 40.

For mathematical models of polynomial function classes, the parameter calculation module 402 may include: adder, divider and multiplier. The adder, the divider and the multiplier are matched with each other, and the coefficient of the mathematical model reflecting the corresponding relation between the detection signal and the temperature can be calculated by utilizing a plurality of calibration temperatures and test mean value signals corresponding to the calibration temperatures. The connection structure of the adder, divider, and multiplier in the temperature correction circuit 40 may be implemented as a circuit structure that solves the coefficients of the polynomial function.

For example, assume that a polynomial function reflecting the correspondence between the detection signal and the temperature is a univariate linear function y = ax + b; wherein, x represents the detection signal, y represents the temperature corresponding to the detection signal, and a and b are coefficients to be calibrated. Accordingly, as shown in fig. 11, the temperature correction circuit 40 may include: multipliers, adders and dividers. The adder, multiplier, and divider constitute the connection configuration shown in fig. 11, can calculate the coefficient a = (y 1-y 2)/(x 1-x 2) of y = ax + b, and output the calculated coefficient a to the temperature determination circuit 30; in fig. 11, a coefficient b = y1-a × x1 of y = ax + b may be calculated, and the calculated coefficient b may be output to the temperature determination circuit 30.

Further, the temperature correction circuit 40 may output the calculated coefficients of the mathematical model to the temperature determination circuit 30. The temperature determining circuit 30 can store the coefficient of the mathematical model, and when the actual temperature is tested, the temperature sensing circuit 20 senses the temperature, and the generated signal to be tested corresponding to the temperature of the device to be tested is input into the mathematical model for calculation, so as to determine the temperature of the device to be tested.

The circuit configuration of the temperature determination circuit 30 is determined by the implementation form of a mathematical model reflecting the correspondence relationship between the detection signal and the temperature. Namely, the input terminal of the temperature determination circuit 30 is electrically connected to the temperature sensing circuit 20, and is configured to receive the signal to be measured corresponding to the temperature generated by the temperature sensing circuit 20. The output end of the temperature determination circuit 30 outputs the temperature corresponding to the signal to be measured. The circuit structure of the temperature determination circuit 30 is constructed as the above mathematical model.

In some embodiments, the mathematical model reflecting the correspondence between the detection signal and the temperature may be implemented as a polynomial function, in which the independent variable of the polynomial function is the detection signal, and the coefficients of the polynomial function are calibrated by the temperature correction circuit 40. Accordingly, the circuit structure of the temperature determination circuit 30 is constructed as a polynomial function. For example, assume that the polynomial function is a univariate linear function y = ax + b; wherein x represents the detection signal, y represents the temperature corresponding to the detection signal, and a and b are the coefficients calibrated by the temperature calibration circuit 40. Accordingly, as shown in fig. 11, the temperature determination circuit 30 may include: multipliers and adders. The input end A of the multiplier is electrically connected with the temperature sensing circuit 20 and is used for receiving the signal to be detected output by the temperature sensing circuit 20; the other input end B of the multiplier is electrically connected with the temperature calibration circuit 40 and is used for receiving the coefficient a calibrated by the temperature calibration circuit 40; the input end of the adder is electrically connected to the output end of the multiplier and the temperature calibration circuit 40, respectively, and is used for receiving the (a × x) output by the multiplier and the coefficient b output by the temperature calibration circuit 40, where the output of the adder is the y value, that is, the temperature corresponding to the signal x to be measured.

It should be noted that the temperature determination circuit 30 and the temperature correction circuit 40 shown in fig. 11 are only exemplary and are not limited.

The digital temperature sensor provided by the embodiment adopts an analog circuit to design a voltage processing circuit suitable for a digital voltage domain, can stabilize the power supply voltage, can reduce the power supply voltage fluctuation of the digital temperature sensor, is favorable for reducing the influence of the voltage fluctuation on the temperature measurement precision of the temperature sensor, and is further favorable for improving the temperature measurement precision of the digital temperature sensor.

On the other hand, the analog devices with different voltage thresholds are selected, so that the analog voltage processing circuit can adapt to different digital domain voltage working ranges, meet the requirements of wide power supply voltage working range and low required voltage of the digital voltage domain, and can meet the requirements of analog voltage processing circuits of the digital voltage domain.

It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A digital temperature sensor, comprising: the temperature sensing circuit, the temperature determining circuit and the voltage processing circuit are composed of voltage-driven analog devices;

the input end of the voltage processing circuit is electrically connected with a power supply end for supplying power to the digital temperature sensor, and the output end of the voltage processing circuit is electrically connected with the temperature sensing circuit and the temperature determining circuit, and is used for stabilizing the power supply voltage by using the volt-ampere characteristic of the analog device and providing the stabilized power supply voltage for the temperature sensing circuit and the temperature determining circuit;

the temperature sensing circuit is electrically connected with the temperature determining circuit and used for generating a to-be-detected signal corresponding to the temperature of the to-be-detected device and outputting the to-be-detected signal to the temperature determining circuit;

and the temperature determining circuit is used for determining the temperature of the tested device according to the signal to be tested.

2. The sensor of claim 1, wherein the voltage processing circuit comprises: the current generation circuit, the current comparator, the current sampling circuit and the voltage output circuit are composed of voltage-driven analog devices; the current generating circuit, the current comparator and the voltage output circuit are electrically connected with the power supply end;

the current generation circuit is used for generating a reference current under the condition that an analog device of the current generation circuit is driven; the analog device of the current comparator is electrically connected with the analog device of the current generating circuit to form a mirror image circuit, and the mirror image circuit is used for generating a mirror image current of the reference current;

the analog device of the voltage output circuit is electrically connected with the current comparator and the current sampling circuit and is used for generating power supply voltage, and the power supply voltage is sampled by the analog device of the current sampling circuit to obtain sampling current;

the analog device of the current comparator is also electrically connected with the analog device of the current sampling circuit to form a mirror image circuit, and the mirror image circuit is used for generating a mirror image current of the sampling current;

the current comparator is further used for adjusting the power supply voltage output by the analog device of the voltage output circuit according to the magnitude relation of the mirror image current of the reference current and the mirror image current of the sampling current.

3. The sensor of claim 2, wherein the current generating circuit comprises: the voltage difference circuit and the first mirror image circuit are connected in series; the analog device of the differential pressure circuit is electrically connected with the power supply end; the analog device of the current comparator is electrically connected to the serial connection path of the voltage difference circuit and the first mirror image circuit and forms a mirror image circuit with the analog device of the first mirror image circuit;

the voltage difference circuit generates a voltage difference in a case where the analog device thereof is driven, generates a reference current based on the generated voltage difference, and outputs the reference current to the first mirror circuit;

the first mirror image circuit is used for generating a mirror image current of the reference current by using an analog device of the first mirror image circuit as the reference current.

4. The sensor of claim 3, wherein the analog components of the differential pressure circuit comprise: a first PMOS circuit and a second PMOS circuit; the differential pressure circuit further comprises a resistor (R1); the source electrodes of the first PMOS circuit and the second PMOS circuit are electrically connected with the power supply end;

the threshold voltage of the first PMOS circuit is larger than that of the second PMOS circuit; the grids of the first PMOS circuit and the second PMOS circuit are electrically connected to two ends of the resistor (R1);

in the starting process of the first PMOS circuit and the second PMOS circuit, voltage difference is generated at two ends of a resistor (R1), and the reference current is generated due to the voltage difference and is output to a first branch of the first mirror circuit;

the second branch of the first mirror image circuit is electrically connected with the drain electrode of the first PMOS circuit; and the first PMOS circuit is started to trigger the second branch circuit of the first mirror image circuit to generate the reference current.

5. The sensor of claim 3, wherein the current comparator comprises: the first circuit unit and the second circuit unit are connected in series; the first and second circuit units include: a voltage driven analog device;

the analog device of the first circuit unit is connected to a serial connection path of the differential pressure circuit and the first mirror image circuit and forms a mirror image circuit with the first mirror image circuit; the voltage difference circuit triggers an analog device of the first circuit unit to be conducted under the condition that voltage difference exists, and mirror current of the reference current is generated on a serial connection path A of the first circuit unit and the second circuit unit;

the analog device of the second circuit unit is electrically connected with the current sampling circuit to form a mirror image circuit, and the mirror image circuit is used for generating a mirror image current of the sampling current on the serial connection path A;

the analog device of the voltage output circuit is electrically connected to the serial connection path A; and the current comparator is used for adjusting the size of a conducting signal triggering an analog device of the voltage output circuit according to the size relation between the mirror image current of the reference current on the serial connection path A and the mirror image current of the sampling current so as to adjust the output voltage of the voltage output circuit.

6. The sensor of claim 5, wherein the analog device of the first circuit unit comprises: an NMOS transistor MN3; the source electrode of the NMOS tube MN3 is grounded;

the drain electrode of the NMOS tube MN3 is electrically connected with the second circuit unit to form the serial connection path A;

the grid electrode of the NMOS tube MN3 is electrically connected to a serial connection path of the voltage difference circuit and the first mirror image circuit, and the voltage difference circuit triggers the NMOS tube MN3 to be conducted under the condition that voltage difference exists, so that the mirror image current of the reference current is generated on the serial connection path A.

7. The sensor of claim 6, wherein the analog device of the second circuit unit comprises: the NMOS transistor MN4 and a second mirror image circuit comprising a voltage-driven analog device; the analog device of the second mirror image circuit is connected with the drain electrode of the NMOS tube MN3 in series to form a series connection path A; the NMOS tube MN4 is connected with the analog device of the second mirror image circuit in series to form a series connection path B;

the grid electrode of the NMOS tube MN4 is electrically connected with the analog device of the current sampling circuit and forms a mirror image circuit with the analog device of the current sampling circuit; the current sampling circuit triggers the NMOS tube MN4 to be conducted under the condition that the sampling current exists, and the mirror current of the sampling current is generated on the serial connection path B;

and the analog device of the second mirror image circuit generates a mirror image current of the sampling current on the serial connection path A.

8. The sensor of claim 7, wherein the analog components of the second mirror circuit comprise: PMOS pipe MP3 and PMOS pipe MP4;

the source electrodes of the PMOS tubes MP3 and MP4 are electrically connected with a power supply end; the grid electrode of the PMOS tube MP3 is electrically connected with the grid electrode of the PMOS tube MP4;

the drain electrode of the PMOS pipe MP3 is electrically connected with the drain electrode of the NMOS pipe MN3 to form the serial connection path A;

the grid electrode and the drain electrode of the PMOS tube MP4 are in short circuit; the drain electrode of the PMOS tube MP4 is electrically connected with the drain electrode of the NMOS tube MN4;

the NMOS tube MN4 is conducted to trigger the PMOS tubes MP4 and MP3 to be conducted, and the sampling is generated on the serial connection path B; and the PMOS pipe MP3 is conducted, and the mirror current of the sampling current is generated on the serial connection path A.

9. The sensor of claim 8, wherein the analog components of the voltage output circuit comprise: PMOS pipe MP5; the source electrode of the PMOS pipe MP5 is electrically connected with a power supply end;

the grid electrode of the PMOS tube MP5 is electrically connected to the serial connection path A;

the current comparator can adjust the gate voltage of the PMOS transistor MP5 according to the magnitude relation between the mirror current of the reference current on the serial connection path a and the mirror current of the output current, so as to adjust the supply voltage output by the drain of the PMOS transistor MP 5.

10. The sensor of claim 7, wherein the analog devices in the current sampling circuit comprise: the NMOS transistor MN5 and a switch circuit comprising a voltage-driven analog device;

the analog device in the switch circuit is electrically connected between the voltage output circuit and the drain electrode of the NMOS transistor MN 5;

the grid electrode of the NMOS tube MN5 is electrically connected with the grid electrode of the NMOS tube MN4; the grid electrode and the drain electrode of the NMOS tube MN5 are in short circuit; the source electrode of the NMOS tube MN5 is grounded; the NMOS tube MN5 and the NMOS tube MN4 form a mirror image circuit;

and an analog device in the switch circuit is switched on when the voltage output circuit outputs the power supply voltage, and triggers the NMOS tube MN5 to be switched on to generate the sampling current.

11. The sensor of claim 1, wherein the temperature sensing circuit comprises: a plurality of ring oscillators with different temperature sensing coefficients and a calculation circuit connected with the plurality of ring oscillators; the plurality of ring oscillators are electrically connected with the output end of the voltage processing circuit and are used for generating clock signals corresponding to the temperature of the device under test; and outputting the clock signal to a connected computing circuit;

and the calculation circuit is used for calculating the ratio of the frequencies of the clock signals output by the plurality of ring oscillators to be used as the signal to be measured.

12. The sensor of claim 11, further comprising:

the temperature correction circuit is electrically connected between the temperature sensing circuit and the temperature determining circuit and is used for calibrating the corresponding relation between the detection signal output by the temperature sensing circuit and the temperature; and providing the correspondence to the temperature determination circuit;

and the temperature determining circuit is used for determining the temperature of the device to be tested according to the signal to be tested and the corresponding relation.