US20080277767A1 - Semiconductor device including a planarized surface and method thereof - Google Patents
Semiconductor device including a planarized surface and method thereof Download PDFInfo
- Publication number
- US20080277767A1 US20080277767A1 US12/219,201 US21920108A US2008277767A1 US 20080277767 A1 US20080277767 A1 US 20080277767A1 US 21920108 A US21920108 A US 21920108A US 2008277767 A1 US2008277767 A1 US 2008277767A1
- Authority
- US
- United States
- Prior art keywords
- material layer
- layer
- buried
- removal rate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.
Description
- This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2002-46575, filed Aug. 7, 2002 in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in its entirety.
- 1. Field of the Invention
- The present invention relates generally to the field of semiconductor devices, and more particularly, to a method of planarizing the surface of a semiconductor device and reduce the occurrence of the dishing phenomenon and a semiconductor device manufactured according to the method. The present invention also relates to a method of increasing the removal rate ratio of a medium material layer to an oxide layer during chemical mechanical polishing (CMP).
- 2. Description of the Related Art
- As the density and size of semiconductor devices decrease and the interconnection structure of semiconductor devices are multiplied, the height of the steps on the surfaces of the semiconductor devices have increased. In order to planarize the surface steps, a spin-on glass (SOG) process, an etch back process, or a chemical mechanical polishing (CMP) process is typically used.
- When CMP is used as a wide area planarizing technique, a wafer surface is pressed against a polishing pad while an abrasive slurry flows to a contact area of the wafer and the polishing pad. The wafer surface chemically reacts with the slurry, while the polishing pad and the wafer, which rotate relative to each other, physically planarize irregularities on the wafer surface.
-
FIGS. 1 and 2 are cross-sectional views illustrating a conventional method of separating an active region, where operations of a semiconductor device occur, from a field region, which is an inactive region, by filling a trench with an oxide layer in a shallow trench isolation (STI) process and planarizing the surface of the oxide layer using CMP. - Referring to
FIG. 1 , anetch stop layer 12 for CMP (e.g., a silicon nitride layer) is formed on asilicon substrate 10. A photolithography process using a photoresist layer (not shown) is then performed so that an etch stop layer pattern is formed which defines a region where trenches will be located. Next, thesilicon substrate 10 is etched using the etch stop layer pattern as an etch mask so that atrench region 14 having a desired depth is formed. Asilicon oxide layer 16 is blanket-deposited on thesilicon substrate 10 and thetrench region 14. As a result, thetrench region 14 is filled with an oxide layer having an excellent gap-fill characteristic. - Optionally, a pad oxide layer (not shown) may be formed on the
substrate 10 before the etch stop layer 12 (e.g., silicon nitride layer) is formed. In another example, a thermal oxide layer (not shown) or a liner layer (not shown) may be formed on the bottom and the sidewalls of thetrench region 14 before thesilicon oxide layer 16 is deposited in thetrench region 14. - Referring to
FIG. 2 , CMP is performed on thesilicon oxide layer 16 to expose theetch stop layer 12. Thereafter, theetch stop layer 12 is removed so that a field region for isolating devices is formed. In the field region, thetrench region 14 in thesilicon substrate 10 is filled with a silicon oxide layer 16 a. - A plurality of
trench regions 14 having various widths can be formed in thesilicon substrate 10 depending upon the circuit design. When the width of thetrench region 14 is large, a large amount of thesilicon oxide layer 16 remains after CMP. As a result, CMP is excessively performed to remove the remainingsilicon oxide layer 16. Thus, a large amount of thesilicon oxide layer 16 in the trench region 14 (which has a relatively small width) is removed, which results in a dishing phenomenon (e.g., thesilicon oxide layer 16 has a concave shape), as is shown inFIG. 2 . Because the dishing phenomenon deteriorates the surface planarity of the silicon substrate and causes defects in the semiconductor device, it is desirable to reduce the occurrence of the dishing phenomenon. - At least one exemplary embodiment of the present invention provides a method of planarizing the surface of a semiconductor device to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer, such as a patterned silicon nitride layer, which defines a trench region, is formed on a base material layer (e.g., a substrate). The substrate is etched to form a trench region, and a medium material layer and a buried material layer (e.g., an oxide layer) are subsequently formed on the substrate to fill the trench region. The medium material layer can be formed over the entire surface of the substrate, e.g., on the patterned etch stop layer and in the trench region, or it can be formed on the patterned etch stop layer and not in the trench region. Alternatively, the medium material layer can be selectively removed from the trench layer. Any material that has a higher removal rate during chemical mechanical polishing (CMP) is suitable for use as the medium material layer. A boron phosphorous silicate glass (BPSG) may be used as the medium material layer and a PE-TEOS oxide layer, a USG oxide layer, or an HDP oxide layer may be used as the oxide layer.
- Once the medium material layer and the oxide layer are formed on the substrate and the trench region is filled, a first CMP process is performed on the oxide layer until the medium material layer is exposed. A second CMP process is then performed until the patterned etch stop layer is exposed and a highly planarized oxide layer is formed. Because the medium material layer has a higher removal rate in the CMP processes than the oxide layer, occurrences of the dishing phenomenon can be reduced.
- In addition, a slurry that includes an anionic surfactant can be used to increase the CMP removal ratio of the medium material layer to the oxide layer. Exemplary embodiments use a ceria-based abrasive that includes ammonium polycarboxylate (APC) as an additive. The APC can be added to the slurry in an amount of approximately 2.0 to 4.5 parts by weight. The adsorption of APC onto the oxide layer decreases the removal rate of the oxide layer. Further, the polishing rate ratio of the medium material layer (e.g., BPSG layer) to the oxide layer may be at least 10:1 during CMP.
- Additionally, at least one exemplary embodiment of the present invention provides a semiconductor device that includes a base material layer, such as a silicon substrate, that includes a depression region (e.g., a trench region), a medium material layer formed on the bottom of the depression region, and a buried material layer positioned on the medium material layer. The medium material layer and the buried material layer fill the depression region. In addition, the buried material layer has a planarized surface.
- The base material layer may be an insulating material layer or a conductive material layer formed on a silicon substrate. Any material that has a higher polishing removal rate than the buried oxide layer can be used. In at least one exemplary embodiment, the etch stop layer is a silicon nitride layer, and the buried material layer is an oxide layer, such as, for example, a PE-TEOS layer, an HDP oxide layer, or a USG layer. The medium material layer may be a BPSG layer.
- Exemplary embodiments of the present invention will be readily understood with reference to the following detailed description thereof provided in conjunction with the attached drawings in which:
-
FIGS. 1 and 2 are cross-sectional views illustrating a conventional method for planarizing the surface of a semiconductor device; -
FIGS. 3 through 6 are cross-sectional views illustrating a method for planarizing the surface of a semiconductor according to an exemplary embodiment of the present invention; and -
FIG. 7 is a graph illustrating the removal rate and the removal rate ratio of a medium material layer and a buried material layer according to the density of an additive added to a slurry when performing a method for planarizing the surface of a semiconductor according to at least one exemplary embodiment of the present invention. - Exemplary embodiments of the present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure can be thorough and complete and will fully convey the concept of the present invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals in different drawings represent the same elements. Similarly, throughout the specification, like numbers refer to like elements.
-
FIGS. 3 through 6 are cross-sectional views illustrating a method according to at least one exemplary embodiment of the present invention for separating a semiconductor device into an active region, where operations of the semiconductor device occur, and a field region, which is an inactive region, by filling trenches with an oxide layer in a shallow trench isolation (STI) process and planarizing the surface of the semiconductor device using a planarizing process (e.g., a chemical mechanical polishing (CMP) process). - Referring to
FIG. 3 , an etch stop layer (not shown), for example, a silicon nitride layer, for CMP is formed on a base material layer (e.g., a silicon substrate 20) as a target layer for a surface planarizing process. Thereafter, a photolithography process using a photoresist layer (not shown) is performed so that a siliconnitride layer pattern 22 defining atrench region 24 is formed. Optionally, a pad oxide layer (not shown) may be deposited on thesilicon substrate 20 before the etch stop layer (e.g., silicon nitride layer) is deposited in order to form a dual-layered etch stop layer that includes the silicon nitride layer and the pad oxide layer. - The
silicon substrate 20 is etched using the siliconnitride layer pattern 22 as an etch mask to form atrench region 24 having a desired depth. A medium material layer (e.g., a boron phosphorus silicate glass (BPSG) layer 27), is then blanket-deposited over thesilicon substrate 20 and thetrench region 24. Alternatively, theBPSG layer 27 can be formed on the silicon nitride layer and not in thetrench region 24 or theBPSG layer 27 can be selectively removed from thetrench region 24 so that the BPSG layer is formed on the silicon nitride layer and not in thetrench region 24. - The
BPSG layer 27 may be used as the medium material layer because theBPSG layer 27 is weak due to the presence of boron and phosphorus. As a result, theBPSG layer 27 has a higher removal rate during CMP than a buried material layer (e.g., an oxide layer) which, as described below, fills thetrench region 24 in a subsequent process. Although BPSG is specifically disclosed herein as an example of the medium material, any material having a higher removal rate during CMP than the buried material layer can be used as the medium material layer. When a difference between the polishing removal rate of the buried material layer and the polishing removal rate of the medium material layer exists, occurrences of the dishing phenomenon can be reduced. - Referring to
FIG. 4 , a buriedoxide layer 28 is blanket-deposited on theBPSG layer 27 to fill thetrench region 24. As a result, thetrench region 24 is filled with an oxide layer having excellent gap-fill characteristics. Suitable examples of the oxide layer include, but are not limited to, a PE-TEOS oxide layer, a USG oxide layer, and an HDP oxide layer. Optionally, a thermal oxide layer (not shown) or a silicon liner layer (not shown) can be formed on the bottom and the sidewalls of thetrench region 24 before the buriedoxide layer 28 is deposited in thetrench region 24. - Referring to
FIG. 5 , a first CMP is performed on the buriedoxide layer 28 on the surface of thesilicon substrate 20 until the surface of theBPSG layer 27 is exposed. A concave buriedoxide layer 28 a may be formed in thetrench region 24 depending upon the width of thetrench region 24. - Referring to
FIG. 6 , a second CMP is performed until the surface of thesilicon nitride layer 22 is exposed. This second CMP forms a highly planarizedburied oxide layer 28 b, which reduces the occurrence of the dishing phenomenon. Optionally, thesilicon nitride layer 22 can be removed to form a trench device isolation region. - As discussed above, during CMP, a wafer surface is pressed against a polishing pad while an abrasive slurry flows to a contact area of the wafer and the polishing pad. In exemplary embodiments of the present invention, a slurry is used to increase the difference between the polishing removal rate of the buried
oxide layer 28 and the polishing removal rate of theBPSG layer 27. In general, the CMP removal rate of the BPSG layer is higher than that of the oxide layer, which, as described above, may be a PE-TEOS oxide layer, a USG oxide layer, or an HDP oxide layer. The CMP removal rates of the layers change depending on the reflow condition of theBPSG layer 27, the densities of boron and phosphorous in theBPSG layer 27, and the type of slurry used. - An experiment was performed to determine how the CMP removal rate and the removal rate ratio, e.g., selectivity, of a PE-TEOS oxide layer and a BPSG layer change according to the type of slurry used. In the experiment conducted, an AMAT Mirra polisher was used, and IC1000 and Suba4 were used as a top pad and a sub pad of a platen pad, respectively. Slurry-A is a silica-based slurry and slurry-B1 and slurry-B2 are ceria-based slurries. The results of the experiment are shown in Table 1.
-
TABLE 1 PE-TEOS Removal rate Slurry removal rate BPSG removal rate ratio slurry-A 2,226 Å/min 6,122 Å/min 2.7 slurry-B1 2,260 Å/min 5,200 Å/min 2.3 slurry-B2 4,985 Å/min 8,346 Å/min 1.7 - Referring to Table 1, although the molecular structure of the BPSG layer and the molecular structure of the oxide layer are similar, the molecular structure of the BPSG layer is weak due to the inclusion of boron and phosphorus. As a result, the CMP removal rate of the BPSG layer is typically higher than the CMP removal rate of the oxide layer. For example, the removal rate ratio of the BPSG layer to the oxide layer can be one to three.
- A second experiment was performed to determine if the CMP removal rate ratio of the BPSG layer to the oxide layer could be increased. In the second experiment, an AMAT Mirra polisher was used, and IC1000 and Suba4 were used as the top pad and the sub pad of the platen pad, respectively. The slurry was a silica-based slurry that included an abrasive in an amount of 1 part by weight. The amount of additive added to the slurry was varied and the removal rate was measured. The additive added to the slurry was an anionic surfactant, such as ammonium polycarboxylate (APC)
- It was determined that the difference between the polishing removal rate of the BPSG layer and the polishing removal rate of the PE-TEOS layer increases depending on the amount of APC added to the slurry. The results of the experiment are illustrated in Table 2 and in
FIG. 7 . -
TABLE 2 PE-TEOS BPSG removal Removal rate APC density removal rate rate ratio (selectivity) 0 wt % 5,552 Å/min 7,596 Å/min 1.4 0.8 wt % 4,985 Å/min 8,346 Å/min 1.7 2.0 wt % 949 Å/min 8,304 Å/min 8.8 2.8 wt % 168 Å/min 7,241 Å/min 43.2 4.0 wt % 135 Å/min 2,633 Å/min 19.5 - As shown in Table 2 and
FIG. 7 , the density of APC adsorbed onto the surface of the oxide layer increases with an increase in the density of APC in the slurry. Thus, adsorbed APC represses the removal of the oxide layer during CMP and decreases the removal rate. PE-TEOS and BPSG layers perform similar to that of APC; however, the adsorbed amount of APC and the removal rate of the PE-TEOS layer are different from the adsorbed amount of APC and the removal rate of the BPSG layer at a given density of APC. In particular, since the BPSG layer is weaker than the oxide layer due to the inclusion of boron and phosphorus in the BPSG layer and since the adsorbed amount of APC in the BPSG layer is less than the adsorbed amount of APC in the oxide layer, the BPSG layer may have a higher density of APC than the oxide layer. As a result, the removal rate ratio, e.g., the selectivity of the BPSG layer to the PE-TEOS layer can exceed 40:1 at a specific APC density. - In exemplary embodiments of the present invention, the removal rate ratio of the medium material layer to the buried material layer may be over 5:1 and may be over 10:1 to reduce the occurrence of the dishing phenomenon in trench regions that have a wide width. The density of APC in the slurry may be in the range of about 2.0 to 4.5 parts by weight.
- Although at least one exemplary embodiment of the present invention describes the
trench region 24 formed in thesilicon substrate 20 as being filled and the surface of thetrench region 24 as being planarized, exemplary embodiments of the present invention can be applied to the surface planarizing process for removing steps on various other materials, such as, for example, an insulating layer and/or a conductive layer, deposited on thesilicon substrate 20. - In addition, although specific material layers such as the buried
oxide layer 28 and themedium material layer 27 have been described above, various materials which have a difference in their removal rates during CMP can be used, and would be easily identified by one of ordinary skill in the art. Further, various types of slurries for CMP can be used to increase the difference between the removal rates, e.g., the removal rates of the oxide layer and the BPSG layer. - According to exemplary embodiments of the present invention, a medium material layer that has a higher removal rate during CMP than the removal rate of the buried oxide layer and a CMP slurry which increases the removal rate ratio between the BPSG layer and the oxide layer are used. As a result, occurrences of the dishing phenomenon in the depression region is reduced in the surface planarizing process, (e.g., CMP, etch back, or spin-on glass), even when the width of the depression region (e.g., trench region) is large.
- Although exemplary embodiments of this invention have been described in detail hereinabove, it should be understood by those of ordinary skill in the art that various changes in form and details may be made therein and will still fall within the spirit and scope of the present invention as defined in the appended claims.
Claims (27)
1-13. (canceled)
14. A semiconductor device comprising:
a base material layer having a depression region;
a medium material layer formed on the bottom of the depression region; and
a buried material layer formed on the medium material layer in the depression region, the buried material layer forming a surface co-planar with the surface of the base material layer.
15. The semiconductor device of claim 14 , wherein the buried material layer has a lower removal rate during chemical mechanical polishing than a removal rate of the medium material layer during chemical mechanical polishing.
16. The semiconductor device of claim 15 , further comprising an etch stop layer formed on the base material layer at an outer side of the depression region.
17. The semiconductor device of claim 16 , wherein the buried material layer forms a surface co-planar with the surface of the etch stop layer.
18. The semiconductor device of claim 16 , wherein the base material layer is a silicon substrate and the depression region is a trench region penetrating the base material layer.
19. The semiconductor device of claim 16 , wherein the base material layer is selected from the group consisting of an insulating material layer and a conductive material layer formed on a silicon substrate, and the depression region is a trench region penetrating the base material layer.
20. The semiconductor device of claim 18 , wherein the etch stop layer is a silicon nitride layer, and the buried material layer is an oxide layer.
21. The semiconductor device of claim 20 , wherein the oxide layer is selected from the group consisting of a PE-TEOS layer, an HDP oxide layer and a USG layer, and the medium material layer is a BPSG layer.
22. A method for reducing the occurrence of a dishing phenomenon in a semiconductor device comprising:
forming a depression region in a base material layer;
depositing a medium material layer on the base material layer;
depositing a buried material layer; and
planarizing until the medium material layer is removed and a planarized buried material layer is formed;
wherein the buried material layer has a lower removal rate during planarizing than a removal rate of the medium material layer during the planarizing.
23. The method of claim 22 , wherein said forming step comprises:
forming an etch stop layer pattern on the base material layer; and
etching the base material layer using the etch stop layer pattern as an etch mask to form the depression region.
24. The method of claim 22 , wherein said performing step is performed until the etch stop layer pattern is exposed.
25. The method of claim 22 , further comprising selectively removing the medium material layer from the depression region before depositing the buried material layer.
26. The method of claim 22 , wherein the planarizing step includes chemical mechanical polishing.
27. The method of claim 26 , wherein the base material layer is a silicon substrate, the depression region is a trench region penetrating the base material layer, the etch stop layer pattern is a silicon nitride layer, and the buried material layer is an oxide layer.
28. The method of claim 27 , wherein the oxide layer is selected from the group consisting of a PE-TEOS layer, a USG layer and an HDP layer.
29. The method of claim 27 , further comprising flowing a slurry over the medium material layer and the buried material layer during the chemical mechanical polishing.
30. The method of claim 29 , wherein the slurry contains ammonium polycarboxylate (APC) as an additive.
31. The method of claim 30 , wherein the APC is added to the slurry in an amount of from approximately 2.0 to 4.5 parts by weight.
32. The method of claim 22 , further comprising forming at least one of a thermal oxide layer and a silicon liner layer in the depression region before depositing the buried material layer.
33. A method of increasing a removal rate ratio of a medium material layer to a buried material layer comprising:
adding a slurry including an anionic surfactant to a contact area on a semiconductor device;
adsorbing the anionic surfactant onto the surface of at least the buried material layer;
wherein the adsorbed anionic surfactant represses the removal rate of the buried material layer and increases the removal rate ratio of the medium material layer to the buried material layer.
34. The method of claim 33 , wherein the buried material layer is an oxide layer selected from the group consisting of a PE-TEOS layer, a USG layer and an HDP layer.
35. The method of claim 34 , wherein the medium material layer is a boron phosphorous silicate glass layer.
36. The method of claim 35 , wherein the removal rate ratio is a ratio of the removal rate of the medium material layer in a chemical mechanical polishing process to the removal rate of the buried material layer in a chemical mechanical polishing process.
37. The method of claim 33 , wherein the anionic surfactant is ammonium polycarboxylate.
38. A method of planarizing the surface of a semiconductor device, the method comprising:
etching a base material layer having an etch stop layer pattern to form a depression region on the base material layer;
forming a medium material layer on at least the etch stop layer pattern;
depositing a buried material layer on the medium material layer to fill the depression region;
removing the buried material layer until the surface of the medium material layer is exposed; and
planarizing the medium material layer and the buried material layer until the surface of the etch stop layer pattern is exposed to form a semiconductor device according to claim 14 .
39. A method for reducing the occurrence of a dishing phenomenon in a semiconductor device comprising:
forming a depression region in a base material layer;
depositing a medium material layer on the base material layer;
depositing a buried material layer having a lower removal rate during planarizing than a removal rate of the medium material during the planarizing; and
planarizing until the medium layer is removed and a planarized buried material layer is formed to create a semiconductor device according to claim 14 .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/219,201 US20080277767A1 (en) | 2002-08-07 | 2008-07-17 | Semiconductor device including a planarized surface and method thereof |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0046575A KR100518536B1 (en) | 2002-08-07 | 2002-08-07 | Method of planarizing the surface of semiconductor device and semiconductor device manufactured by the same |
KR2002-46575 | 2002-08-07 | ||
US10/419,076 US7413959B2 (en) | 2002-08-07 | 2003-04-21 | Semiconductor device including a planarized surface and method thereof |
US12/219,201 US20080277767A1 (en) | 2002-08-07 | 2008-07-17 | Semiconductor device including a planarized surface and method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/419,076 Division US7413959B2 (en) | 2002-08-07 | 2003-04-21 | Semiconductor device including a planarized surface and method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080277767A1 true US20080277767A1 (en) | 2008-11-13 |
Family
ID=31492817
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/419,076 Expired - Fee Related US7413959B2 (en) | 2002-08-07 | 2003-04-21 | Semiconductor device including a planarized surface and method thereof |
US12/219,201 Abandoned US20080277767A1 (en) | 2002-08-07 | 2008-07-17 | Semiconductor device including a planarized surface and method thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/419,076 Expired - Fee Related US7413959B2 (en) | 2002-08-07 | 2003-04-21 | Semiconductor device including a planarized surface and method thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US7413959B2 (en) |
KR (1) | KR100518536B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080204580A1 (en) * | 2007-02-28 | 2008-08-28 | Micron Technology, Inc. | Method, apparatus and system providing imaging device with color filter array |
US20140213034A1 (en) * | 2013-01-29 | 2014-07-31 | United Microelectronics Corp. | Method for forming isolation structure |
US9157012B2 (en) * | 2011-12-21 | 2015-10-13 | Basf Se | Process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of borophosphosilicate glass (BPSG) material in the presence of a CMP composition comprising anionic phosphate or phosphonate |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100518536B1 (en) * | 2002-08-07 | 2005-10-04 | 삼성전자주식회사 | Method of planarizing the surface of semiconductor device and semiconductor device manufactured by the same |
US7442621B2 (en) * | 2004-11-22 | 2008-10-28 | Freescale Semiconductor, Inc. | Semiconductor process for forming stress absorbent shallow trench isolation structures |
KR101138113B1 (en) * | 2004-12-28 | 2012-04-24 | 매그나칩 반도체 유한회사 | Method for Forming Metal-Line of Semiconductor Device |
KR100654000B1 (en) * | 2005-10-31 | 2006-12-06 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device having metal silicide layer |
JP2007329342A (en) * | 2006-06-08 | 2007-12-20 | Toshiba Corp | Chemical mechanical polishing method |
KR101987367B1 (en) * | 2011-12-15 | 2019-06-11 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069057A (en) * | 1998-05-18 | 2000-05-30 | Powerchip Semiconductor Corp. | Method for fabricating trench-isolation structure |
US6245635B1 (en) * | 1998-11-30 | 2001-06-12 | United Microelectronics Corp. | Method of fabricating shallow trench isolation |
US6268265B1 (en) * | 1998-07-07 | 2001-07-31 | Samsung Electronics Co., Ltd. | Trench isolation method for semiconductor integrated circuit |
US20020087537A1 (en) * | 2000-12-29 | 2002-07-04 | Evans David J. | Method and apparatus for searching a data stream for character patterns |
US6461225B1 (en) * | 2000-04-11 | 2002-10-08 | Agere Systems Guardian Corp. | Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP) |
US20020151177A1 (en) * | 2001-04-12 | 2002-10-17 | Cabot Microelectrics Corporation | Method of reducing in-trench smearing during polishing |
US20030166381A1 (en) * | 2002-02-28 | 2003-09-04 | Samsung Electronics Co., Ltd. | Chemical mechanical polishing slurry and chemical mechanical polishing method using the same |
US20040029375A1 (en) * | 2002-08-07 | 2004-02-12 | Lee Jae-Dong | Method of planarizing a surface of a semiconductor device and a semiconductor device manufactured according to the same |
US20050106872A1 (en) * | 2003-11-17 | 2005-05-19 | Taiwan Semiconductor Manufacturing Co. | Copper CMP defect reduction by extra slurry polish |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63228732A (en) * | 1987-03-18 | 1988-09-22 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPH01134947A (en) * | 1987-11-20 | 1989-05-26 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH0834242B2 (en) * | 1988-12-08 | 1996-03-29 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
KR0183738B1 (en) * | 1995-09-14 | 1999-04-15 | 김광호 | Element isolation method of semiconductor device |
JPH11134947A (en) | 1997-10-30 | 1999-05-21 | Sony Corp | Digital interface cable |
JP2953447B2 (en) * | 1997-11-14 | 1999-09-27 | 日本電気株式会社 | Manufacturing method of groove-separated semiconductor device |
JP2000332099A (en) * | 1999-05-21 | 2000-11-30 | Matsushita Electronics Industry Corp | Semiconductor device and manufacture thereof |
KR100781870B1 (en) * | 2001-05-14 | 2007-12-05 | 주식회사 하이닉스반도체 | Forming Method for Field Oxide of Semiconductor Device |
-
2002
- 2002-08-07 KR KR10-2002-0046575A patent/KR100518536B1/en not_active IP Right Cessation
-
2003
- 2003-04-21 US US10/419,076 patent/US7413959B2/en not_active Expired - Fee Related
-
2008
- 2008-07-17 US US12/219,201 patent/US20080277767A1/en not_active Abandoned
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069057A (en) * | 1998-05-18 | 2000-05-30 | Powerchip Semiconductor Corp. | Method for fabricating trench-isolation structure |
US6268265B1 (en) * | 1998-07-07 | 2001-07-31 | Samsung Electronics Co., Ltd. | Trench isolation method for semiconductor integrated circuit |
US6245635B1 (en) * | 1998-11-30 | 2001-06-12 | United Microelectronics Corp. | Method of fabricating shallow trench isolation |
US6461225B1 (en) * | 2000-04-11 | 2002-10-08 | Agere Systems Guardian Corp. | Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP) |
US20020087537A1 (en) * | 2000-12-29 | 2002-07-04 | Evans David J. | Method and apparatus for searching a data stream for character patterns |
US20020151177A1 (en) * | 2001-04-12 | 2002-10-17 | Cabot Microelectrics Corporation | Method of reducing in-trench smearing during polishing |
US20030166381A1 (en) * | 2002-02-28 | 2003-09-04 | Samsung Electronics Co., Ltd. | Chemical mechanical polishing slurry and chemical mechanical polishing method using the same |
US6887137B2 (en) * | 2002-02-28 | 2005-05-03 | Samsung Electronics Co., Ltd. | Chemical mechanical polishing slurry and chemical mechanical polishing method using the same |
US20040029375A1 (en) * | 2002-08-07 | 2004-02-12 | Lee Jae-Dong | Method of planarizing a surface of a semiconductor device and a semiconductor device manufactured according to the same |
US20050106872A1 (en) * | 2003-11-17 | 2005-05-19 | Taiwan Semiconductor Manufacturing Co. | Copper CMP defect reduction by extra slurry polish |
US6946397B2 (en) * | 2003-11-17 | 2005-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chemical mechanical polishing process with reduced defects in a copper process |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080204580A1 (en) * | 2007-02-28 | 2008-08-28 | Micron Technology, Inc. | Method, apparatus and system providing imaging device with color filter array |
US9157012B2 (en) * | 2011-12-21 | 2015-10-13 | Basf Se | Process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of borophosphosilicate glass (BPSG) material in the presence of a CMP composition comprising anionic phosphate or phosphonate |
US20140213034A1 (en) * | 2013-01-29 | 2014-07-31 | United Microelectronics Corp. | Method for forming isolation structure |
Also Published As
Publication number | Publication date |
---|---|
US20040029375A1 (en) | 2004-02-12 |
US7413959B2 (en) | 2008-08-19 |
KR100518536B1 (en) | 2005-10-04 |
KR20040013580A (en) | 2004-02-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20080277767A1 (en) | Semiconductor device including a planarized surface and method thereof | |
US6540935B2 (en) | Chemical/mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same | |
US6248667B1 (en) | Chemical mechanical polishing method using double polishing stop layer | |
US5494857A (en) | Chemical mechanical planarization of shallow trenches in semiconductor substrates | |
US6626968B2 (en) | Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same | |
JP2001015460A (en) | Fabrication of semiconductor device | |
US7087528B2 (en) | Chemical-mechanical polishing (CMP) process for shallow trench isolation | |
KR100843140B1 (en) | Method of forming isolation regions structures thereof | |
US6136713A (en) | Method for forming a shallow trench isolation structure | |
US6541349B2 (en) | Shallow trench isolation using non-conformal dielectric and planarizatrion | |
WO1999046081A1 (en) | Multi-step chemical mechanical polishing process and device | |
WO2000002235A1 (en) | Method of planarizing integrated circuits | |
KR100726746B1 (en) | Semiconductor device fabrication method | |
US7094653B2 (en) | Method for forming STI structures with controlled step height | |
US6190999B1 (en) | Method for fabricating a shallow trench isolation structure | |
CN108520863B (en) | Method for manufacturing shallow trench insulation structure | |
US6498102B2 (en) | Method for planarizing a semiconductor device using ceria-based slurry | |
US6133114A (en) | Method for fabricating a shallow trench isolation | |
KR100731090B1 (en) | Method of forming isolation layer of semiconductor device | |
KR100835406B1 (en) | Method for manufacturing iso layer of semiconductor device | |
KR20070109483A (en) | Method for fabricating isolation layer in flash memory device | |
JP2001210710A (en) | Forming process of shallow trench isolation utilizing sacrificial layer | |
US7091103B2 (en) | TEOS assisted oxide CMP process | |
KR20090038141A (en) | Method of fabricating trench isolation in semicondtor device | |
US20110159692A1 (en) | Method for fabricating semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, JAE-DONG;HAN. YONG-PIL;HONG, CHANG-KI;REEL/FRAME:021293/0632;SIGNING DATES FROM 20030227 TO 20030411 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |