US20080162977A1 - Modular memory controller clocking architecture - Google Patents
Modular memory controller clocking architecture Download PDFInfo
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- US20080162977A1 US20080162977A1 US11/647,656 US64765606A US2008162977A1 US 20080162977 A1 US20080162977 A1 US 20080162977A1 US 64765606 A US64765606 A US 64765606A US 2008162977 A1 US2008162977 A1 US 2008162977A1
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- delay
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- reference clock
- memory controller
- dll
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Definitions
- the present invention relates to computer systems; more particularly, the present invention relates to interfacing with memory devices.
- a memory controller is an integrated circuit located on the motherboard, or processor die, within a computer system that manages the flow of data to and from a main memory device. Particularly, memory controllers include logic necessary to read and write data to dynamic RAM (DRAM). A component of the logic includes a clocking architecture to carry out transactions with the DRAM.
- DRAM dynamic RAM
- the clocking architecture typically includes special delay locked loops (DLL) that are used to transmit de-skew and receive de-skew.
- DLL delay locked loops
- the conventional clocking architecture implements a relatively large number of logic components to control all de-skewing for a single memory controller channel.
- FIG. 1 is a block diagram of one embodiment of a computer system
- FIGS. 2A and 2B illustrate a conventional transmit delay locked loop architecture
- FIG. 3 illustrates a conventional receive delay locked loop architecture
- FIGS. 4A and 4B illustrate one embodiment of a global clocking architecture
- FIG. 5 illustrates one embodiment of a modular clocking architecture
- FIG. 6 illustrates another embodiment of a modular clocking architecture
- FIG. 7 is a block diagram of another embodiment of a computer system.
- FIG. 1 is a block diagram of one embodiment of a computer system 100 .
- Computer system 100 includes a central processing unit (CPU) 102 coupled to interconnect 105 .
- CPU 102 is a processor in the Pentium® family of processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used. For instance, CPU 102 may be implemented as multiple processors, or multiple processor cores.
- a chipset 107 is also coupled to interconnect 105 .
- Chipset 107 may include a memory control hub (MCH) 110 .
- MCH 110 may include a memory controller 112 that is coupled to a main system memory 115 .
- Main system memory 115 stores data and sequences of instructions that are executed by CPU 102 or any other device included in system 100 .
- main system memory 115 includes one or more DIMMs incorporating dynamic random access memory (DRAM) devices; however, main system memory 115 may be implemented using other memory types. Additional devices may also be coupled to interconnect 105 , such as multiple CPUs and/or multiple system memories.
- DIMMs dynamic random access memory
- main system memory 115 may be implemented using other memory types. Additional devices may also be coupled to interconnect 105 , such as multiple CPUs and/or multiple system memories.
- MCH 110 may be coupled to an input/output control hub (ICH) 140 via a hub interface.
- ICH 140 provides an interface to input/output (I/O) devices within computer system 100 .
- ICH 140 may support standard I/O operations on I/O interconnects such as peripheral component interconnect (PCI), accelerated graphics port (AGP), universal serial interconnect (USB), low pin count (LPC) interconnect, or any other kind of I/O interconnect (not shown).
- PCI peripheral component interconnect
- AGP accelerated graphics port
- USB universal serial interconnect
- LPC low pin count
- ICH 140 is coupled to a wireless transceiver 160 .
- FIG. 7 illustrates another embodiment of computer system 100 .
- memory controller 112 is included within CPU 102 .
- memory 115 is coupled to CPU 102 .
- Further chipset 107 includes a control hub 740 .
- memory controller performs memory transactions with main memory 115 by transferring data between computer system 100 and memory 115 .
- memory controller 112 includes a clocking mechanism having delay locked loops (DLL) that are used to transmit de-skew and receive de-skew.
- DLL delay locked loops
- FIG. 2A illustrates a conventional transmit delay locked loop architecture.
- the mechanism includes a DLL coupled to a phase locked loop (PLL) and several slave delay lines.
- a delay locked loop serves as a component to maintain delay tracking over PVT.
- Each slave delay line is coupled to a phase interpolator (PI) and a CMOS converter, which is further coupled to a transmitter.
- PI phase interpolator
- CMOS converter complementary metal-oxide-semiconductor
- the DLL sets the requisite delay in each of a number of delay elements within the DLL. This delay tracks Process, Voltage & Temperature (PVT) variations, is converted to an analog voltage (bias) and coupled to the slave delay lines.
- PVT Process, Voltage & Temperature
- the PI coupled to each slave delay line creates a finer step of the delay and distributes the resultant clocks to each of the high speed 10 transmitters, such as the Stub Series Termination Logic (SSTL) driver.
- SSTL Stub Series Termination Logic
- the conventional clocking mechanism features the physical locations of the High Speed Drivers being far away from the clocking circuitry (e.g. ⁇ 3000 um away) in the original design
- FIG. 3 illustrates a conventional receive delay locked loop architecture.
- the slave delay lines receive a channel strobe or clock from the DRAMs.
- the slave delay lines are pre-programmed to a specific delay such that the internal strobe or clock would be center strobe with respect to the receive data.
- Another DLL and slave delay lines are used to create the requisite delay for every 8 bits (or byte) of receiving data.
- the problem with the conventional memory controller clocking mechanism is that the memory controller uses a total of nine DLLs & nineteen slave delay lines to control all of the de-skewing in a one channel memory controller. Further, the transmit deskew delays are generated at one location and then transmitted to the individual I/O transmitters, which are far away from the generation location. This results in area and power inefficiencies, as well as lost deskew setting accuracy when the data rate is scaled up.
- memory controller 112 includes a clocking architecture for both transmit and receive clock circuitries that reduces the number of delay locked loops and the number of slave delay lines, resulting in a reduction in silicon area and power, while providing comparable to better resolution to the conventional mechanism.
- FIG. 4A illustrates one embodiment of a global clocking mechanism 400 .
- Clocking mechanism 400 includes a PLL 410 and data/command modules 420 .
- Each module 420 includes a Master DLL (MDLL).
- MDLL Master DLL
- a PLL 410 supplies a true differential reference clock to the MDLLs that provides a low jitter reference clock.
- Clocking mechanism 400 also includes high speed input/output (HSIO) interfaces that facilitate data transfers with memory 112 .
- HSIO high speed input/output
- FIG. 4B illustrates another embodiment of global clocking mechanism 400 , where the location of the MDLL in each module 420 has a location to enable share between the transmit and receive circuitry. This feature improves accuracy, the number of clock components and power.
- FIG. 5 illustrates one embodiment of a module 420 coupled to PLL 410 .
- module 420 includes both transmit and receive clocking circuitry. The transmit side is shown on the top half component of FIG. 5 , while the receive side is shown as the bottom half component.
- Module 420 includes MDLL 510 , slave delay lines 520 , as well as additional components (e.g., PIs, converters, etc.).
- MDLL 510 On the transmit side of module 420 , MDLL 510 generates de-skew clocks together with a set of PIs as well as maintaining the required delay.
- the PIs are now used for transmit bit de-skew. Therefore in one embodiment, eleven PIs are implemented, as opposed to the eleven slave delay lines employed in conventional transmit clocking components. Because the size of each PI is smaller than each slave delay line, there is a reduction in the silicon area needed to fabricate module 420 .
- the delay generated by MDLL 510 is converted to an analog bias voltage, as shown in FIG. 5 .
- the bias voltage is connected to slave delay lines 520 for data receiving de-skewing.
- no additional DLL is required for the receive directions, which further reduces the needed silicon area.
- FIG. 6 illustrates one embodiment of a detailed view of module 420 .
- the transmit component at the bottom of FIG. 6 shows a phase deductor (PD) 600 and delay elements of MDLL 510 .
- PD phase deductor
- Each of delay elements, other than the last, has its output coupled to the next delay element and a multiplexer.
- the last delay element has an output coupled to the multiplexer and PD 600 .
- the PI is capable of receiving, via the multiplexer, the full delay setting of all of the delay elements, or finer delay settings.
- the bias voltage is then transmitted from the transmit component to the slave delay line 520 of the receive component.
- the slave delay lines also include delay elements coupled to a PI via a multiplexer.
- the slave delay lines receive a channel receive/clock strobe.
- the modular clocking mechanism enables a reduction of the number DLLs from nine to four, and the number of slave delay lines from nineteen to eight.
- the de-skew resolution is provided back by the additional PIs. Therefore, the modular clocking mechanism has a superior power to data rate scaling than conventional architectures due to the optimal and efficient use of circuit components.
Abstract
Description
- The present invention relates to computer systems; more particularly, the present invention relates to interfacing with memory devices.
- A memory controller is an integrated circuit located on the motherboard, or processor die, within a computer system that manages the flow of data to and from a main memory device. Particularly, memory controllers include logic necessary to read and write data to dynamic RAM (DRAM). A component of the logic includes a clocking architecture to carry out transactions with the DRAM.
- The clocking architecture typically includes special delay locked loops (DLL) that are used to transmit de-skew and receive de-skew. However, the conventional clocking architecture implements a relatively large number of logic components to control all de-skewing for a single memory controller channel.
- The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
-
FIG. 1 is a block diagram of one embodiment of a computer system; -
FIGS. 2A and 2B illustrate a conventional transmit delay locked loop architecture; -
FIG. 3 illustrates a conventional receive delay locked loop architecture; -
FIGS. 4A and 4B illustrate one embodiment of a global clocking architecture; -
FIG. 5 illustrates one embodiment of a modular clocking architecture; -
FIG. 6 illustrates another embodiment of a modular clocking architecture; and -
FIG. 7 is a block diagram of another embodiment of a computer system. - A modular memory controller clocking architecture is described. In the following detailed description of the present invention numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
- Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
-
FIG. 1 is a block diagram of one embodiment of acomputer system 100.Computer system 100 includes a central processing unit (CPU) 102 coupled to interconnect 105. In one embodiment,CPU 102 is a processor in the Pentium® family of processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used. For instance,CPU 102 may be implemented as multiple processors, or multiple processor cores. - In a further embodiment, a
chipset 107 is also coupled to interconnect 105.Chipset 107 may include a memory control hub (MCH) 110. MCH 110 may include amemory controller 112 that is coupled to amain system memory 115.Main system memory 115 stores data and sequences of instructions that are executed byCPU 102 or any other device included insystem 100. - In one embodiment,
main system memory 115 includes one or more DIMMs incorporating dynamic random access memory (DRAM) devices; however,main system memory 115 may be implemented using other memory types. Additional devices may also be coupled to interconnect 105, such as multiple CPUs and/or multiple system memories. - MCH 110 may be coupled to an input/output control hub (ICH) 140 via a hub interface. ICH 140 provides an interface to input/output (I/O) devices within
computer system 100. ICH 140 may support standard I/O operations on I/O interconnects such as peripheral component interconnect (PCI), accelerated graphics port (AGP), universal serial interconnect (USB), low pin count (LPC) interconnect, or any other kind of I/O interconnect (not shown). In one embodiment, ICH 140 is coupled to awireless transceiver 160. -
FIG. 7 illustrates another embodiment ofcomputer system 100. In this embodiment,memory controller 112 is included withinCPU 102. As a result,memory 115 is coupled toCPU 102.Further chipset 107 includes a control hub 740. - Notwithstanding the embodiment, memory controller performs memory transactions with
main memory 115 by transferring data betweencomputer system 100 andmemory 115. To perform the memory transactions,memory controller 112 includes a clocking mechanism having delay locked loops (DLL) that are used to transmit de-skew and receive de-skew.FIG. 2A illustrates a conventional transmit delay locked loop architecture. - On the transmit side shown in
FIG. 2A , the mechanism includes a DLL coupled to a phase locked loop (PLL) and several slave delay lines. A delay locked loop serves as a component to maintain delay tracking over PVT. Each slave delay line is coupled to a phase interpolator (PI) and a CMOS converter, which is further coupled to a transmitter. - The DLL sets the requisite delay in each of a number of delay elements within the DLL. This delay tracks Process, Voltage & Temperature (PVT) variations, is converted to an analog voltage (bias) and coupled to the slave delay lines. The PI coupled to each slave delay line creates a finer step of the delay and distributes the resultant clocks to each of the high speed 10 transmitters, such as the Stub Series Termination Logic (SSTL) driver.
- In a memory controller implementing a conventional clocking mechanism, there are typically eleven groups of transmitters that are skewed independently. Hence, there are eleven slave delay lines and corresponding clock buffers in the transmit direction. These clocking circuitries are located at a centralized location, as shown in
FIG. 2B . Thus, the conventional clocking mechanism features the physical locations of the High Speed Drivers being far away from the clocking circuitry (e.g. ˜3000 um away) in the original design -
FIG. 3 illustrates a conventional receive delay locked loop architecture. On the receive side, there are slave delay lines receiving a channel strobe or clock from the DRAMs. The slave delay lines are pre-programmed to a specific delay such that the internal strobe or clock would be center strobe with respect to the receive data. Another DLL and slave delay lines are used to create the requisite delay for every 8 bits (or byte) of receiving data. In a typical one channel memory controller, there are 8 bytes of receiving data. As a result, there will be eight sets of slave delay lines. - The problem with the conventional memory controller clocking mechanism is that the memory controller uses a total of nine DLLs & nineteen slave delay lines to control all of the de-skewing in a one channel memory controller. Further, the transmit deskew delays are generated at one location and then transmitted to the individual I/O transmitters, which are far away from the generation location. This results in area and power inefficiencies, as well as lost deskew setting accuracy when the data rate is scaled up.
- According to one embodiment,
memory controller 112 includes a clocking architecture for both transmit and receive clock circuitries that reduces the number of delay locked loops and the number of slave delay lines, resulting in a reduction in silicon area and power, while providing comparable to better resolution to the conventional mechanism. -
FIG. 4A illustrates one embodiment of aglobal clocking mechanism 400.Clocking mechanism 400 includes aPLL 410 and data/command modules 420. Eachmodule 420 includes a Master DLL (MDLL). According to one embodiment, aPLL 410 supplies a true differential reference clock to the MDLLs that provides a low jitter reference clock.Clocking mechanism 400 also includes high speed input/output (HSIO) interfaces that facilitate data transfers withmemory 112. -
FIG. 4B illustrates another embodiment ofglobal clocking mechanism 400, where the location of the MDLL in eachmodule 420 has a location to enable share between the transmit and receive circuitry. This feature improves accuracy, the number of clock components and power. -
FIG. 5 illustrates one embodiment of amodule 420 coupled toPLL 410. As shown inFIG. 5 ,module 420 includes both transmit and receive clocking circuitry. The transmit side is shown on the top half component ofFIG. 5 , while the receive side is shown as the bottom half component.Module 420 includesMDLL 510,slave delay lines 520, as well as additional components (e.g., PIs, converters, etc.). - On the transmit side of
module 420,MDLL 510 generates de-skew clocks together with a set of PIs as well as maintaining the required delay. The PIs are now used for transmit bit de-skew. Therefore in one embodiment, eleven PIs are implemented, as opposed to the eleven slave delay lines employed in conventional transmit clocking components. Because the size of each PI is smaller than each slave delay line, there is a reduction in the silicon area needed to fabricatemodule 420. - In one embodiment, the delay generated by
MDLL 510 is converted to an analog bias voltage, as shown inFIG. 5 . The bias voltage is connected toslave delay lines 520 for data receiving de-skewing. In such an embodiment, no additional DLL is required for the receive directions, which further reduces the needed silicon area. -
FIG. 6 illustrates one embodiment of a detailed view ofmodule 420. The transmit component at the bottom ofFIG. 6 shows a phase deductor (PD) 600 and delay elements ofMDLL 510. Each of delay elements, other than the last, has its output coupled to the next delay element and a multiplexer. The last delay element has an output coupled to the multiplexer andPD 600. Thus, the PI is capable of receiving, via the multiplexer, the full delay setting of all of the delay elements, or finer delay settings. - The bias voltage is then transmitted from the transmit component to the
slave delay line 520 of the receive component. The slave delay lines also include delay elements coupled to a PI via a multiplexer. The slave delay lines receive a channel receive/clock strobe. - As shown above, the modular clocking mechanism enables a reduction of the number DLLs from nine to four, and the number of slave delay lines from nineteen to eight. The de-skew resolution is provided back by the additional PIs. Therefore, the modular clocking mechanism has a superior power to data rate scaling than conventional architectures due to the optimal and efficient use of circuit components.
- Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.
Claims (20)
Priority Applications (7)
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US11/647,656 US7388795B1 (en) | 2006-12-28 | 2006-12-28 | Modular memory controller clocking architecture |
DE102007060805A DE102007060805B4 (en) | 2006-12-28 | 2007-12-18 | Memory controller and computer system with the same and method for controlling a memory |
GB0724806A GB2445260B (en) | 2006-12-28 | 2007-12-19 | Modular memory controller clocking architecture |
TW096148620A TWI364761B (en) | 2006-12-28 | 2007-12-19 | Modular memory controller clocking architecture |
JP2007332041A JP2008165790A (en) | 2006-12-28 | 2007-12-25 | Modular memory controller clocking architecture |
KR1020070138902A KR101077685B1 (en) | 2006-12-28 | 2007-12-27 | Modular memory controller clocking architecture |
CN2007101997737A CN101236775B (en) | 2006-12-28 | 2007-12-28 | Memory controller, method for controlling clock and computer system |
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US11/647,656 US7388795B1 (en) | 2006-12-28 | 2006-12-28 | Modular memory controller clocking architecture |
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US7388795B1 US7388795B1 (en) | 2008-06-17 |
US20080162977A1 true US20080162977A1 (en) | 2008-07-03 |
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JP (1) | JP2008165790A (en) |
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DE (1) | DE102007060805B4 (en) |
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2006
- 2006-12-28 US US11/647,656 patent/US7388795B1/en not_active Expired - Fee Related
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2007
- 2007-12-18 DE DE102007060805A patent/DE102007060805B4/en not_active Expired - Fee Related
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CN107769923A (en) * | 2016-08-23 | 2018-03-06 | 中国科学院声学研究所 | A kind of true random-number generating method based on cpu clock and USB independent clocks |
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DE102007060805B4 (en) | 2010-06-17 |
TWI364761B (en) | 2012-05-21 |
KR101077685B1 (en) | 2011-10-27 |
DE102007060805A1 (en) | 2008-08-07 |
TW200836196A (en) | 2008-09-01 |
KR20080063157A (en) | 2008-07-03 |
CN101236775A (en) | 2008-08-06 |
US7388795B1 (en) | 2008-06-17 |
GB2445260A (en) | 2008-07-02 |
GB0724806D0 (en) | 2008-01-30 |
JP2008165790A (en) | 2008-07-17 |
CN101236775B (en) | 2012-06-06 |
GB2445260B (en) | 2008-12-10 |
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