JP2005234646A - Clock signal adjusting circuit, integrated circuit, method for controlling clock signal adjusting circuit, channel adapter device, disk adapter device, and storage device controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively reduce clock skew. <P>SOLUTION: This clock signal adjusting circuit is provided with: a plurality of phase adjusting circuits which accept the input of first and second clock signals and output third clock signals to control the phase of the first clock signal to be matched with the phase of the second clock signal; and a signal selecting circuit which selects one of the third clock signals to be outputted by those respective phase adjusting circuits and outputs the selected third clock output signal as the second clock signal to each of the phase adjusting circuits. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock signal adjustment circuit, an integrated circuit, a control method of a clock signal adjustment circuit, a channel adapter device, a disk adapter device, and a storage device control device.

In recent years, the amount of data handled in an information processing system is increasing, and a storage device such as a disk array device is required to have a large amount and a high-speed data transfer capability.
Japanese Patent Laid-Open No. 11-65699

  Under such circumstances, even higher speed and larger scale are required for integrated circuits (ICs) constituting the CPU, memory, data transfer device, and the like inside the storage apparatus. On the other hand, with the miniaturization of the manufacturing process of integrated circuits, the influence of fluctuations in manufacturing conditions on circuit performance is increasing. In order to suppress these effects as much as possible, circuit design is made with consideration to reduce clock skew, but there is still manufacturing variation in the actually manufactured circuit, which is caused by manufacturing variation. It is difficult to effectively suppress clock skew.

  The present invention has been made in view of such a background, and can effectively reduce clock skew, a clock signal adjustment circuit, an integrated circuit, a clock signal adjustment circuit control method, a channel adapter device, and a disk. An object is to provide an adapter device and a storage device control device.

  In order to achieve the above object, a main invention of the present invention is such that the input of the first and second clock signals is received, and the phase of the first clock signal is controlled to match the phase of the second clock signal. A plurality of phase adjustment circuits that output the third clock signal and one of the third clock signals output from each of the phase adjustment circuits, and select the selected third clock signal as the phase And a signal selection circuit for outputting each of the adjustment circuits as the second clock signal.

  According to the present invention, clock skew can be effectively reduced.

=== Clock Signal Adjustment Circuit ===
FIG. 1 shows a configuration of a clock signal adjustment circuit 1 described as an embodiment of the present invention. The clock signal adjustment circuit 1 is inputted with four circuit blocks 20 each formed in a region partitioned on a predetermined circuit board or LSI circuit pattern, and clock signals extracted from the circuit blocks 20. And a signal selection circuit 40. The same clock signal (external clock signal) supplied from the clock input terminal 11 is input to each circuit block 20.

  Each circuit block 20 includes a DLL (Delay Locked Loop) circuit 23 (phase adjustment circuit), a clock tree 30 connected to the subsequent stage of the DLL circuit 23, and a load circuit 22 connected to the subsequent stage of the clock tree 30 (in this embodiment, a flip-flop). Circuit). The DLL circuit 23 reduces a clock skew between the external clock signal and the clock signal input to the load circuit 22 (a timing shift that occurs between clock signals at different locations). The DLL circuit 23 includes a first input terminal 231 to which an external clock signal is input, a second input terminal 232, and an output terminal 233. The DLL circuit 23 uses an external clock signal (first clock signal) input to the first input terminal 231 as a clock signal (second clock signal) whose phase is input to the second input terminal 232. Control is performed so as to match the phase, and the external clock signal after control is output from the output terminal 233.

  The clock signal output from the output terminal 233 of the DLL circuit 23 is supplied to the apex (root) of the clock tree 30 connected to the subsequent stage of the DLL circuit 23. The clock tree 30 is configured by connecting buffer circuits, clock gate circuits, logic gate circuits, and the like in multiple stages according to CTS (Clock Tree Synthesis). It should be noted that the total number of stages of the clock tree 30 in each circuit block 20 is the same in order to align the delay of the clock signal supplied to the load circuit 22 of each circuit block 20 between the circuit blocks 20.

  The clock signal output from the buffer circuit at the final stage of the clock tree 30 is supplied to the load circuit 22 and also to the signal selection circuit 40. The signal selection circuit 40 selects and outputs one of the clock signals (third clock signal) output from each circuit block 20. The clock signal output from the signal selection circuit 40 is input to the second input terminal 232 of the DLL circuit 23 of each circuit block 20. In this way, the DLL circuit 23 of each circuit block 20 constituting the clock signal adjustment circuit 1 controls the phase of the external clock signal based on the common clock signal fed back from the signal selection circuit 40. Therefore, according to the clock signal adjusting circuit 1, not only the clock skew in each circuit block 20 is reduced, but also the clock skew between the circuit blocks 20 is effectively reduced. That is, even if the clock skew value generated by the performance variation (manufacturing variation) of the DLL circuit 23, the clock tree 30 and the like due to the variation of the manufacturing condition differs for each circuit block 20, the clock skew between the circuit blocks 20 is different. The queue can be reduced. Therefore, the yield of circuit manufacturing can be increased and the reliability of the circuit can be improved. In addition, this makes it possible to reduce a design margin required when designing a circuit, and further increase the number of logic gates, so that more complex logic can be handled. The speed of the circuit can be increased by increasing the frequency of the clock signal for operating the circuit.

  It should be noted that the wiring distance from the branch point 12 where the external clock signal is branched to the DLL circuit 23 of each circuit block 20 is made equal, and the wiring from the signal selection circuit 40 to the DLL circuit 23 of each circuit block 20 is made equal. As a result, the clock skew between the circuit blocks 20 can be more effectively reduced.

=== Signal Selection Circuit 40 ===
Next, a specific configuration of the signal selection circuit 40 described above will be described. FIG. 2 shows an example of the signal selection circuit 40. In FIG. 2, clock signals C <b> 1 to C <b> 4 are clock signals output from each circuit block 20 and input to the signal selection circuit 40. REQ is a signal for performing on / off control of the operation of the signal selection circuit 40 (hereinafter referred to as a timing instruction signal). In the signal selection circuit 40, the clock signals C 1 to C 4 are input to the multiplexer 41 and the selection signal determination circuit 42. The selection signal determination circuit 42 controls the multiplexer 41 so that the latest clock signal among the clock signals C1 to C4 input to the multiplexer 41 is output.

  FIG. 3 shows an example of the selection signal determination circuit 42. The selection signal determination circuit 42 is connected to four flip-flop circuits 43, a buffer circuit 45 connected to the subsequent stage of each flip-flop circuit 43, a latch circuit 44 connected to the subsequent stage of each buffer circuit 45, and a subsequent stage of each latch circuit 44. Encoder circuit 46 and EOR (Exclusive OR: exclusive OR) circuit 47.

  The clock signals C1 to C4 are input to the clock terminal 431 of each flip-flop circuit 43. “1” is input to the data input terminal 432 of each flip-flop circuit 43. A signal output from the output terminal 433 of each flip-flop circuit 43 passes through the buffer circuit 45 and is input to the data input terminal 442 of each corresponding latch circuit 44. An output signal from the output terminal 443 of each latch circuit 44 is input to the encoder circuit 46. The timing instruction signal REQ is input to the reset terminal 434 of the flip-flop circuit 43 and the reset terminal 444 of the latch circuit 44. An output signal output from the output terminal 434 of each flip-flop circuit 43 is input to the EOR circuit 47. The output signal of the EOR circuit 47 is input to the clock terminal 441 of the latch circuit 44.

  FIG. 4 is a timing chart for explaining the operation of the selection signal determination circuit 42 shown in FIG. First, when the timing instruction signal REQ is input to the reset terminal 434 of the flip-flop circuit 43 and the reset terminal 444 of the latch circuit 44 at time T0, the flip-flop circuit 43 and the latch circuit 44 are reset, and the flip-flop circuit The output of 43 is all “0”. At this time, the output (NE) from the EOR circuit 47 is “0”, and all the outputs from the latch circuit 44 are also “0”.

  Next, when the clock signal C1 is input to the selection signal determination circuit 42 at time T1, the output of the EOR circuit 47 becomes “1”, and the latch circuit 44 outputs the input signal from the flip-flop circuit 43 as it is. The clock signal C2 is input at time T2 and the clock signal C3 is input at time T3. However, the EOR circuit 47 is kept outputting “1”, and the latch circuit 44 outputs the input signal from the flip-flop circuit 43. to continue.

  Next, when the clock signal C4 is input to the selection signal determination circuit 42 at time T4, the outputs of all the flip-flop circuits 43 are “1” and the outputs of the EOR circuits 47 are “0”. Here, each latch circuit 44 is in a state of latching “1”, “1”, “1”, “0”, respectively. In this case, the encoder circuit 46 outputs a control signal for outputting the clock signal C4 to the multiplexer 41.

=== Synchronization with external clock ===
In the clock signal adjustment circuit 1 described above, it is necessary to synchronize an externally input clock signal (external clock signal) and a clock signal (internal clock signal) for operating the clock signal adjustment circuit 1. There is. In this case, it is necessary to reduce the clock skew between the external clock signal and the internal clock signal.

  In addition to the configuration of the clock signal adjustment circuit 1 shown in FIG. 1, the clock signal adjustment circuit 1 shown in FIG. 5 includes a PLL (Phase Locked Loop) circuit 21 and a frequency divider circuit between the clock input terminal 11 and the circuit block 20. 24. In this circuit, the PLL circuit 21 multiplies the frequency of the external clock signal, and the frequency dividing circuit 24 divides the frequency to match the frequency of the external clock signal and the frequency of the internal clock signal (external). Clock frequency adjustment circuit).

  The PLL circuit 21 serves to adjust the phase of the input clock signal (external clock phase adjustment circuit), similarly to the DLL circuit 23 arranged in the circuit block 20. The clock signal output from the PLL circuit 21 is input to the frequency dividing circuit 24. The clock signal output from the frequency dividing circuit 24 is input to the first input terminal 231 of the DLL circuit 23 of the circuit block 20 and is fed back to the PLL circuit 21. The PLL circuit 21 controls the phase of the external clock signal so as to match the phase of the fed back clock signal. As a result, the phases of the external clock signal input to the PLL circuit 21 and the clock signal input to each circuit block 20 are adjusted, and the external clock signal is input to the PLL circuit 21 and then input to the circuit block 20. The clock skew in the route up to this time is reduced.

=== Layout of Circuit Board ===
FIG. 6 is an example of a layout of a circuit board on which the clock signal adjustment circuit 1 including the PLL circuit 21 and the frequency dividing circuit 24 described above is formed. In this layout, four DLL circuits 23 are arranged at the center of the circuit board of the clock signal adjustment circuit 1. The wiring distance between the frequency divider 24 and the DLL circuit 23 is equal. In the circuit block 20, the clock tree 30 is wired by a so-called H-tree wiring system.
In this layout, the wiring distances between the frequency dividing circuit 24 and the DLL circuit 23, between the DLL circuits 23, and between the signal selection circuit 40 and the DLL circuit 23 are equal. Thereby, the clock skew can be reduced more effectively.
Note that the signal line on the circuit board is provided with a variable wiring width or shield wiring in consideration of the influence of voltage, temperature, crosstalk noise, and the like. In this circuit board, this also reduces the clock skew.

=== Multi-stage configuration of circuit blocks ===
In larger-scale circuits, the clock skew generated before the external clock signal is supplied from the PLL circuit 21 to each circuit block 20 is reduced, thereby reducing the clock skew of the entire circuit more effectively. Can be made.
The clock signal adjustment circuit 1 shown in FIG. 7 includes four circuit blocks 60, and each circuit block 60 includes four circuit blocks 20. That is, the clock signal adjustment circuit 1 includes a total of 16 circuit blocks.

  A DLL circuit 51 (second phase adjustment circuit) is provided between the frequency divider 24 and each DLL circuit 23 (first phase adjustment circuit). Further, a signal selection circuit 52 (second signal selection circuit) that operates in the same manner as the signal selection circuit 40 (first signal selection circuit) described above is provided. A clock signal output from each of the DLL circuits 51 is input to the signal selection circuit 52.

  The external clock signal (fourth clock signal) phase-adjusted by the PLL circuit 21 is input to the first input terminal 511 of the DLL circuit 51 (second phase adjustment circuit). The clock signal (first clock signal) output from the output terminal 513 of the DLL circuit 51 is supplied to the first input terminal 231 of the DLL circuit 23 of the circuit block 20 and also to the signal selection circuit 52. The Similarly to the signal selection circuit 40 described above, the signal selection circuit 52 selects and outputs the input clock signal having the largest delay. The clock signal (fifth clock signal) output from the signal selection circuit 52 is input to the second input terminal 512 of the DLL circuit 51. That is, the DLL circuit 51 corresponding to each circuit block 60 controls the phase of the external clock signal based on the common clock signal fed back from the signal selection circuit 52.

  According to the clock signal adjustment circuit 1, not only the clock skew between the output side of the PLL circuit 21 and the input side of each circuit block 60 is reduced, but also the clock skew between the circuit blocks 60 is reduced. . Also in the circuit block 60, the clock skew inside each circuit block 20 and between the circuit blocks 20 is reduced by the above-described configuration. As a result, the clock skew of the entire clock signal adjustment circuit 1 is reduced, and the clock skew can be effectively reduced even in a larger scale circuit.

  FIG. 8 is an example of mounting the clock signal adjustment circuit 1 having the configuration shown in FIG. 7 on a circuit board. In this layout, four DLL circuits 51 are arranged in the center of the circuit board of the clock signal adjustment circuit 1. Four DLL circuits 23 are arranged in the center of each circuit block 60. The wiring distance from the frequency dividing circuit 24 to the DLL 51 is equal. The wiring distance from the DLL circuit 51 to the circuit block 60 is also equal. Further, the wiring distance from the DLL circuit 51 to the next-stage DLL circuit 23 is also equal. In this layout, the clock tree 30 is configured in each of a plurality of circuit blocks (16 in the present embodiment) to reduce the scale of the clock tree 30. With the above layout, the clock skew can be effectively reduced in this circuit board.

=== Application to Storage Device Controller ===
Next, an example in which the above-described clock signal adjustment circuit 1 is applied to a storage device control apparatus such as a disk array apparatus will be described.

  FIG. 9 is a diagram showing an overall configuration of the information processing system 2 including the storage device control apparatus 200 to which the present invention is applied. The information processing system 2 according to the present embodiment includes an information processing apparatus 100 that provides various information processing services, and a storage device control apparatus 200 that provides a storage area of a storage device 300 such as a disk drive to the information processing apparatus 100. Consists of including.

  The information processing apparatus 100 is a computer having a CPU (Central Processing Unit) and a memory. Various functions provided by the information processing apparatus are realized by executing various programs by the CPU of the information processing apparatus 100. The information processing apparatus 100 is, for example, a personal computer, a workstation, a mainframe computer, or the like. The information processing apparatus 100 may be a single computer or a plurality of computers. The information processing apparatus 100 executes an operating system, and various application programs are executed on the operating system.

  The information processing apparatus 100 is connected to the storage device control apparatus 200 via a SAN (Storage Area Network) 400. Communication between the information processing apparatus 100 and the storage device control apparatus 200 performed via the SAN 400 is performed according to the fiber channel protocol. As a communication protocol performed between the information processing apparatus 100 and the storage device control apparatus, for example, LAN (Local Area Network), SCSI (Small Computer System Interface), iSCSI (Internet Small Computer System Interface), ESCON ( Enterprise System Connection (registered trademark), FICON (Fibre Connection) (registered trademark), ACONARC (Advanced Connection Architecture) (registered trademark), and FIBARC (Fibre connection Architecture) (registered trademark) can be used. Further, the information processing apparatus 100 and the storage device control apparatus 200 may be directly connected by a SCSI cable or the like.

  The information processing apparatus 100 transmits a data input / output request to the storage device control apparatus 200 according to the fiber channel protocol. When the storage device control apparatus 200 receives a data input / output request from the information processing apparatus 100, the storage device control apparatus 200 performs processing related to data input / output with respect to the storage device 300 in response to the received data input / output request.

  The storage device control apparatus 200 is a storage apparatus that provides storage resources to the information processing apparatus 100. The storage device control apparatus 200 includes a plurality of storage devices 300 and manages storage areas provided by the storage device 300. The storage device 300 may be configured integrally with the storage device control apparatus 200, or as an apparatus independent of the storage device control apparatus 200, for example, the storage device control apparatus 200 via a communication path such as SCSI, LAN, or SAN. It is good also as a form connected with.

  As shown in FIG. 9, the storage device control device 200 includes a channel adapter device 210, a shared memory 220, a cache memory 230, a disk adapter device 240, and a crossbar switch 250.

  The channel adapter device 210 communicates with the information processing device 100. The disk adapter device 240 performs control related to data input / output with respect to the storage device 300. The shared memory 220 and the cache memory 230 are shared by the channel adapter device 210 and the disk adapter device 240. The shared memory 220 is mainly used for storing control information and commands, while the cache memory 230 is mainly used for storing data. The crossbar switch 250 (switch device) connects the channel adapter device 210, the shared memory 220, the cache memory 230, and the disk adapter device 240 so that they can communicate with each other. Data and commands are exchanged among the channel adapter device 210, the shared memory 220, the cache memory 230, and the disk adapter device 240 via the crossbar switch 250.

  FIG. 10 is a block diagram showing the configuration of the channel adapter device 210. In the channel adapter device 210, a CPU 211, a memory 212, an NVRAM 213, a communication interface 214, a data transfer processor 215, and a connector 217 are mounted on the same substrate. By fitting the connector 217 with the connector on the storage device control apparatus 200 side, the channel adapter apparatus 210 is electrically connected to the storage device control apparatus 200. As a result, the channel adapter device 210 can communicate with the shared memory 220, the cache memory 230, the disk adapter device 240, the crossbar switch 250, and the like.

  The CPU 211 is responsible for overall control of the channel adapter device 210. The memory 212 is a storage device that is read and written by the CPU 211. The NVRAM 213 is a non-volatile storage device for storing application programs executed by the CPU 211 and data necessary for the processing. The CPU 211 implements various functions by reading the application program stored in the NVRAM 213 into the memory 212 and executing the application program read into the memory 212. Note that a read-only storage device such as a ROM may be used instead of the NVRAM 213. Further, application programs and data stored in the NVRAM 213 may be stored in the storage device 300.

  The communication interface 214 is an interface for connecting to the SAN 400 and performing communication with the information processing apparatus 100. The communication interface 214 has a function of performing communication according to, for example, a fiber channel protocol. The communication interface 214 includes a plurality of communication ports 216 and is connected to the SAN 400 via the communication port 216.

  The data transfer processor 215 is a device that controls data transfer. For example, the data transfer processor 215 transfers data received by the communication interface 214 to the memory 212, and transfers data stored in the memory 212 to the cache memory 230.

  When the channel adapter apparatus 210 receives a data input / output request from the information processing apparatus 100, the channel adapter apparatus 210 creates an I / O command instructing data input / output to the storage device 300 in response to the received data input / output request. Creation of the I / O command is performed by the CPU 211 provided in the channel adapter device 210. The channel adapter device 210 instructs the disk adapter device 240 to control data input / output with respect to the storage device 300 by writing the generated I / O command to the shared memory 220.

  The clock signal adjusting circuit 1 described above can be applied to such a channel adapter device 210. For example, the CPU 211 receives the third clock signal that is received by the channel adapter device 210 and receives the input of the first and second clock signals and controls the phase of the first clock signal to match the phase of the second clock signal. A plurality of phase adjustment circuits to be supplied to the memory 212, the communication interface 214, and the data transfer processor 215, and one of the third clock signals output from each of the phase adjustment circuits. And a signal selection circuit that outputs the clock signal as a second clock signal to each of the phase adjustment circuits. Note that a phase adjustment circuit may be provided so as to supply the third clock signal to the NVRAM 213, the connector 217, or the like.

  In this way, the clock skew among the CPU 211, the memory 212, the communication interface 214, and the data transfer processor 215 in the channel adapter device 210 is reduced. Therefore, it is possible to suppress the design margin related to the clock skew of the channel adapter device 210, increase the number of logic stages, and cope with more complicated logic. Further, the frequency of the clock signal for operating the channel adapter device 210 can be increased to further increase the speed of the channel adapter device 210.

  FIG. 11 is a block diagram showing a configuration of the disk adapter device 240. In the disk adapter device 240, a CPU 241, a memory 242, a disk interface 244, a data transfer processor 245, and a connector 247 are mounted on the same substrate.

  The configuration of the disk adapter device 240 is substantially the same as that of the channel adapter device 210 described above. The disk adapter device 240 includes a disk interface 244 for accessing the storage device 300 in place of the communication interface 214 of the channel adapter device 210.

  The disk adapter device 240 monitors the shared memory 220 and reads the written I / O command to the memory 242. In response to the read I / O command, the disk adapter device 240 performs control related to data input / output with respect to the storage device 300, such as transmitting a SCSI command to the storage device 300, for example. The disk adapter device 240 can also access data according to a RAID configuration (for example, RAID 0, 1, 5) when the storage device 300 is managed by RAID.

  The above-described clock signal adjustment circuit 1 can be applied to such a disk adapter device 240. For example, the CPU 241 receives the third clock signal that is received by the disk adapter device 240 and receives the first and second clock signals and controls the phase of the first clock signal to match the phase of the second clock signal. A plurality of phase adjustment circuits to be supplied to each of the memory 242, the disk interface 244, and the data transfer processor 245, and one of the third clock signals output from each of the phase adjustment circuits. And a signal selection circuit that outputs the clock signal as a second clock signal to each of the phase adjustment circuits. Note that a phase adjustment circuit may be provided so as to supply the third clock signal to the NVRAM 243, the connector 247, or the like.

  By doing so, clock skew among the CPU 241, memory 242, disk interface 244, and data transfer processor 245 in the disk adapter device 240 is reduced. Therefore, it is possible to suppress a design margin related to the clock skew of the disk adapter device 240, increase the number of logic stages, and cope with more complicated logic. Further, the frequency of the clock signal for operating the disk adapter device 240 can be increased to further increase the speed of the disk adapter device 240.

  The clock signal adjustment circuit 1 can also be applied to the main body of the storage device control apparatus 200. In this case, the storage device control apparatus 200 includes a channel adapter apparatus 210 that receives a data input / output request to the storage device 300 from the information processing apparatus 100, a disk adapter apparatus 240 that performs control related to data input / output to the storage device 300, and a channel. A crossbar switch 250 that connects the cache memory 230 that stores data exchanged between the adapter device 210 and the disk adapter device 240, the channel adapter device 210, the disk adapter device 240, and the cache memory 230 so that they can communicate with each other. A third clock signal that receives input of the first and second clock signals and controls the phase of the first clock signal to match the phase of the second clock signal, the channel adapter device 210, the disk adapter apparatus 40, the cache memory 230, and the crossbar switch 250, a plurality of phase adjustment circuits, and one of the third clock signals output from each of the phase adjustment circuits are selected, and the selected third clock signal is selected. And a signal selection circuit for outputting each of the phase adjustment circuits as a second clock signal. Note that a phase adjustment circuit may be provided so as to supply the third clock signal to the shared memory 220 or the storage device 300.

  In the storage device control device 200, a common clock signal is supplied to the channel adapter device 210, the shared memory 220, the cache memory 230, the disk adapter device 240, and the crossbar switch. According to the storage device control apparatus 200 configured as described above, the phase of the clock signal supplied to each apparatus is adjusted based on the common clock signal, and therefore the value of the clock skew generated in each apparatus differs due to manufacturing variations. Even in such a case, the clock skew between the devices can be reduced. Therefore, the reliability of the storage device control apparatus 200 can be improved. In addition, since the design margin required when designing the circuit of the storage device control apparatus 200 can be reduced and the number of logic gates can be increased, the storage device control apparatus 200 can be adapted to more complex logic. . The speed of the storage device control apparatus 200 can be increased by increasing the frequency of the clock signal for operating the storage device control apparatus 200.

  Further, when the clock signal adjustment circuit 1 is applied to the channel adapter device 210 or the disk adapter device 240 included in the storage device control apparatus 200 as described above, the storage device control apparatus 200 is further increased in speed and improved in reliability. Can be achieved.

  Although the present embodiment has been described above, the above examples are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, the clock signal adjustment circuit 1 can be applied to the shared memory 220, the cache memory 230, the crossbar switch 250, the storage device 300, the information processing apparatus 100, and the like.

  Further, the DLL circuits 23 and 51 of the clock signal adjustment circuit 1 can be replaced with a circuit capable of matching the phases of the two clock signals. For example, a PLL circuit or SMD (Synchronous Mirror Delay) circuit may be used instead of the DLL circuit 23 or 51 described above.

  Further, when the external clock signal and the internal clock signal have the same frequency, the frequency dividing circuit 24 can be omitted. When frequency multiplication is not performed as described above, a DLL circuit or an SMD circuit can be employed instead of the PLL circuit 21. In this case, since the clock skew due to the jitter of the PLL circuit 21 can also be reduced, the clock skew of the entire circuit can be more effectively reduced.

  In addition, a DLL circuit may be used instead of the PLL circuit 21 and a means for multiplying the frequency may be provided separately.

  Further, the wiring system in each circuit block 20 may be a clock mesh system or a fishbone system in addition to the clock tree system.

  Further, the clock signal adjustment circuit 1 can be integrated to be an integrated circuit of one chip or a plurality of chips.

It is a figure which shows the structure of the clock signal adjustment circuit 1 by one Embodiment of this invention. 3 is a block diagram illustrating an example of a signal selection circuit 40 according to one embodiment of the invention. FIG. FIG. 4 is a circuit diagram illustrating an example of a selection signal determination circuit according to an embodiment of the present invention. 6 is a timing chart for explaining the operation of a selection signal determination circuit according to an embodiment of the present invention. 1 is a block diagram of a clock signal adjustment circuit 1 that adjusts the phase of an external clock signal and an internal clock signal according to an embodiment of the present invention. FIG. 6 is a diagram for explaining a layout of a clock signal adjustment circuit 1 including a PLL circuit 21 and a frequency divider circuit 24 according to an embodiment of the present invention. 1 is a block diagram of a clock signal adjustment circuit 1 configured to reduce clock skew until an external clock signal reaches a circuit block 20 according to an embodiment of the present invention. It is a figure which shows an example of the layout of the circuit board 500 of the clock signal adjustment circuit 1 of the structure shown in FIG. 8 by one Embodiment of this invention. It is a figure showing the whole information processing system 2 composition by one embodiment of the present invention. It is a block diagram which shows the structure of the channel adapter apparatus 210 by one Embodiment of this invention. It is a block diagram which shows the structure of the disk adapter apparatus 240 by one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock signal adjustment circuit 10 Signal line 11 Clock input terminal 20 Circuit block 21 PLL circuit 22 Flip-flop circuit 23 DLL circuit 231 1st input terminal 232 2nd input terminal 233 Output terminal 24 Dividing circuit 30 Clock tree 40 Signal selection Circuit 41 multiplexer 42 selection signal determination circuit 43 flip-flop circuit 431 clock terminal 432 data input terminal 433 output terminal 434 reset terminal 44 latch circuit 441 clock terminal 442 data input terminal 443 output terminal 444 reset terminal 45 buffer circuit 46 encoder circuit 47 EOR circuit 51 DLL circuit 52 signal selection circuit 60 circuit block 2 information processing system 100 information processing apparatus 200 storage device control apparatus 300 storage device 400 S N
210 Channel adapter device 211 CPU
212 memory 213 NVRAM
214 Communication Interface 215 Data Transfer Processor 220 Shared Memory 230 Cache Memory 240 Disk Adapter Device 241 CPU
242 Memory 243 NVRAM
244 Disk interface 245 Data transfer processor 250 Crossbar switch

Claims (16)

A plurality of phase adjustment circuits for receiving a first clock signal and a second clock signal, and outputting a third clock signal controlled to match the phase of the first clock signal with the phase of the second clock signal; ,
Selecting one of the third clock signals output from each of the phase adjustment circuits, and outputting the selected third clock signal as the second clock signal to each of the phase adjustment circuits Circuit,
A clock signal adjustment circuit comprising:   2. The clock signal adjustment circuit according to claim 1, wherein the phase adjustment circuit is a DLL circuit. The clock signal adjustment circuit according to claim 1,
The signal selection circuit selects the one having the largest delay among the third clock signals in the selection;
A clock signal adjustment circuit characterized by the above. The clock signal adjustment circuit according to claim 1,
The signal selection circuit receives an external timing instruction signal and selects one of the third clock signals at a timing according to the received timing instruction signal;
A clock signal adjustment circuit characterized by the above. The clock signal adjustment circuit according to claim 1,
The third clock signal output from the phase adjustment circuit is distributed and supplied to each of the buffer circuits connected in a tree shape at the subsequent stage of the phase adjustment circuit,
The signal selection circuit selects one of the third clock signals output from the buffer circuit connected to the same level in each of the phase adjustment circuits;
A clock signal adjustment circuit characterized by the above. The clock signal adjustment circuit according to claim 1,
A signal line for distributing the third clock signal is wired by an H-tree wiring method;
A clock signal adjustment circuit characterized by the above. The clock signal adjustment circuit according to claim 1,
An external clock signal input from the outside and the first clock signal are input, and the phase of the external clock signal is controlled to match the phase of the first clock signal, and each of the phase adjustment circuits is controlled. An external clock phase adjustment circuit that outputs the first clock signal;
A clock signal adjustment circuit characterized by the above.   8. The clock signal adjustment circuit according to claim 7, wherein the external clock phase adjustment circuit is a PLL circuit. The clock signal adjustment circuit according to claim 7,
An external clock frequency adjusting circuit that controls the frequency of the clock signal output from the external clock phase adjusting circuit and outputs the clock signal as the first clock signal to each of the phase adjusting circuits;
A clock signal adjustment circuit characterized by the above. The clock signal adjustment circuit according to claim 1,
A plurality of circuit blocks including a plurality of first phase adjustment circuits and a first signal selection circuit;
Accepting inputs of the fourth and fifth clock signals, controlling the phase of the fourth clock signal to match the phase of the fifth clock signal, and controlling each of the first phase adjustment circuits to the first phase adjustment circuit. A plurality of second phase adjustment circuits that output as clock signals of
The second signal that selects one of the first clock signals output from each of the second phase adjustment circuits and outputs the first clock signal as the fifth clock signal to each of the second phase adjustment circuits. A selection circuit;
A clock signal adjustment circuit characterized by the above. The clock signal adjustment circuit according to claim 1,
The signal selection circuit includes:
A plurality of flip-flop circuits for receiving the input of the third clock signal output from each of the phase adjustment circuits;
An EOR circuit that receives input of a signal output from each of the flip-flop circuits;
A plurality of latch circuits for receiving signals output from the flip-flop circuits as data inputs and receiving signals output from the EOR circuits as clock inputs;
An encoder circuit that receives data output from each of the latch circuits and outputs a signal indicating any of the third clock signals;
A multiplexer that selects any one of the third clock signals in accordance with an output from the encoder circuit;
A clock signal adjustment circuit comprising:   12. An integrated circuit obtained by integrating the clock signal adjusting circuit according to claim 1. A plurality of phase adjustment circuits for receiving a first clock signal and a second clock signal, and outputting a third clock signal controlled to match the phase of the first clock signal with the phase of the second clock signal; A signal selection circuit that receives input of a plurality of clock signals, and selects and outputs one of the inputted clock signals, and a control method of a clock signal adjustment circuit comprising:
As the first clock signal to be input to the phase adjustment circuit, a common clock signal is input,
The signal selection circuit selects one of the third clock signals output from each of the phase adjustment circuits, and sends the selected third clock signal to each of the phase adjustment circuits. Output as a signal,
A control method of a clock signal adjustment circuit characterized by the above. A channel adapter device that receives a data input / output request for a storage device from an information processing device, a disk adapter device that performs control related to data input / output to the storage device, and the channel adapter device and the disk adapter device. A channel adapter device used in a storage device control device comprising a cache memory for storing data, the channel adapter device, the disk adapter device, and a switch device that connects the cache memory so that they can communicate with each other. ,
A CPU, a memory, a communication interface for receiving the data input / output request, a data transfer processor for transferring data,
A third clock signal that receives input of the first and second clock signals and controls the phase of the first clock signal to match the phase of the second clock signal, the CPU, the memory, A plurality of phase adjustment circuits for supplying each of the communication interface and the data transfer processor;
Selecting one of the third clock signals output from each of the phase adjustment circuits, and outputting the selected third clock signal as the second clock signal to each of the phase adjustment circuits Circuit,
A channel adapter device comprising: A channel adapter device that receives a data input / output request for a storage device from an information processing device, a disk adapter device that performs control related to data input / output to the storage device, and the channel adapter device and the disk adapter device. A disk adapter device used in a storage device control device comprising a cache memory for storing data, the channel adapter device, the disk adapter device, and a switch device that connects the cache memory so that they can communicate with each other. ,
A CPU, a memory, a data transfer processor for transferring the data input / output request, a disk interface for transmitting a command for instructing data input / output to the storage device,
A third clock signal that receives input of the first and second clock signals and controls the phase of the first clock signal to match the phase of the second clock signal, the CPU, the memory, and A plurality of phase adjustment circuits for supplying to each of the disk interfaces;
Selecting one of the third clock signals output from each of the phase adjustment circuits, and outputting the selected third clock signal as the second clock signal to each of the phase adjustment circuits Circuit,
A disk adapter device comprising: A channel adapter device for receiving a data input / output request to the storage device from the information processing device;
A disk adapter device for controlling data input / output with respect to the storage device;
A cache memory for storing data exchanged between the channel adapter device and the disk adapter device;
A switch device that connects the channel adapter device, the disk adapter device, and the cache memory so that they can communicate with each other;
A third clock signal that receives input of the first and second clock signals and controls the phase of the first clock signal to match the phase of the second clock signal is transmitted to the channel adapter device and the disk. A plurality of phase adjustment circuits for supplying to each of the adapter device, the cache memory, and the switch device;
Selecting one of the third clock signals output from each of the phase adjustment circuits, and outputting the selected third clock signal as the second clock signal to each of the phase adjustment circuits Circuit,
A storage device control apparatus comprising:

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