US20080094776A1 - Cylindrical capacitor - Google Patents
Cylindrical capacitor Download PDFInfo
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- US20080094776A1 US20080094776A1 US11/960,726 US96072607A US2008094776A1 US 20080094776 A1 US20080094776 A1 US 20080094776A1 US 96072607 A US96072607 A US 96072607A US 2008094776 A1 US2008094776 A1 US 2008094776A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
Definitions
- the present invention relates to a cylindrical capacitor and a method of fabricating the same. More particularly, the present invention relates to a high mechanical strength cylindrical capacitor and a method of fabricating the same.
- a semiconductor memory mainly comprises a transistor and a capacitor.
- the process of fabricating the semiconductor memory needs to fabricate patterns with a high aspect ratio, the area available for accommodating the capacitor of each device is substantially reduced.
- the number of required capacitors also correspondingly increases. To satisfy this growing demand for capacitors, some basic modification is required to made to the existing techniques of manufacturing semiconductor device.
- the minimum capacitance of each capacitor unit in a dynamic random access memory (DRAM) is greater than 25 fF.
- DRAM dynamic random access memory
- the two major methods include: 1) using high dielectric constant (high k) material to produce the capacitor dielectric layer; and, 2) increasing the surface area of the capacitor by forming a cylindrical structure, forming a rod structure, forming a wing structure or forming a complicated structure by performing multiple processes.
- the most common means of increasing the surface area of a capacitor unit is still the cylindrical structure.
- the height of the capacitor cylinder has to be increased as the allowed dimension is reduced. Yet, raising the height of the capacitor cylinder will destabilize the entire capacitor cylinder so that the capacitor cylinder is easily toppled. As a result, there will be a substantial drop in the production yield of the capacitor.
- At least one objective of the present invention is to provide a method of fabricating a cylindrical capacitor with a higher mechanical strength so that the fabrication yield of the cylindrical capacitor is increased.
- At least another objective of the present invention is to provide a cylindrical capacitor that can improve the mechanical strength of the cylindrical capacitor and increase the density of the capacitor.
- the present invention provides a method of fabricating a cylindrical capacitor.
- the method includes providing a substrate with a plug formed therein.
- a first dielectric layer, a structure layer, a second dielectric layer and an etching stop layer are sequentially formed over the substrate.
- a hole that exposes the plug is formed in the first dielectric layer, the structure layer, the second dielectric layer and the etching stop layer.
- a conductive layer is formed over the substrate to cover the etching stop layer and the interior surface of the hole.
- the conductive layer disposed on the top of the hole is removed to expose a portion of the second dielectric layer.
- the remaining conductive layer serves as a bottom electrode.
- An isotropic etching of a portion of the exposed second dielectric layer is performed to form an opening at the top of the hole.
- the etching stop layer is removed and a material layer is filled inside the opening and the hole.
- the second dielectric layer is removed.
- an anisotropic etching of the structure layer is performed to expose a portion of the first dielectric layer.
- the first dielectric layer is removed to expose the entire bottom electrode.
- a capacitor dielectric layer is formed over the surface of the bottom electrode.
- a top electrode is formed over the surface of the capacitor dielectric layer.
- the steps for forming the hole include forming a first photoresist layer over the etching stop layer so that the area for forming the hole in the etching stop layer is exposed.
- the first photoresist layer as a etching mask, the etching stop layer, the second dielectric layer, the structure layer and the first dielectric layer are etched.
- the first photoresist layer is removed.
- the steps for removing the conductive layer at the top of the hole include filling the hole with a second photoresist layer.
- the second photoresist layer is etched back to expose the conductive layer at the top of the hole.
- the exposed conductive layer is exposed.
- the second photoresist layer is also removed.
- the structure layer can be a silicon nitride layer and the etching stop layer can also be a silicon nitride layer.
- the material layer comprises photoresist or polysilicon.
- the step for removing the second dielectric layer includes performing a wet etching process.
- the step for forming the capacitor dielectric layer on the surface of the bottom electrode includes performing an atomic layer deposition process.
- the present invention also provides a cylindrical capacitor having at least a substrate, a plurality of cylindrical bottom electrodes, a plurality of structure layers, a plurality of top electrodes and a capacitor dielectric layer.
- the substrate has a plurality of plugs formed therein.
- the cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs.
- the structure layers surround the periphery of the cylindrical bottom electrodes.
- the structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other.
- the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode.
- the width of each structure layer is smaller than half the distance between two opposing cylindrical bottom electrodes.
- the width of each structure layer is greater than half the distance between two neighboring cylindrical bottom electrodes.
- the structure layer includes a silicon nitride layer.
- a semiconductor process is used to form a structure layers that strengthens the cylindrical capacitor.
- the mechanical strength of the cylindrical capacitor is increased and the fabrication yield is improved.
- the location of the structure layer inside the cylindrical capacitor structure of the present invention can be changed and the distance between capacitors can be reduced without making mutual contact. Therefore, density of the capacitor can be increased.
- FIG. 1 is a top view showing a part of the structure of a cylindrical capacitor according to one embodiment of the present invention.
- FIGS. 2 A, 2 B-I, 2 B-II, 2 C-I, 2 C-II, 2 D-I, 2 D-II, 2 E-I, 2 E-II, 2 F-I, 2 F-II, 2 G-I, 2 G-II, 2 H-I and 2 H-II are schematic cross-sectional views showing the steps for forming the cylindrical bottom electrode and the structure layer shown in FIG. 1 .
- FIGS. 3 -I and 3 -II are the schematic cross-sectional views showing the cylindrical capacitors formed after carrying out the steps in FIGS. 2 A through 2 H-II according to one embodiment of the present invention.
- FIG. 1 is a top view showing part of the structure of a cylindrical capacitor according to one embodiment of the present invention. To illustrate the characteristic of the present invention more clearly, the top electrode and the capacitor dielectric layer of the capacitor are not shown.
- the cylindrical capacitor 100 in the present invention includes at least a substrate (not shown), a plurality of cylindrical bottom electrodes 102 , a plurality of structure layers 104 , a plurality of top electrodes (not shown) and a plurality of capacitor dielectric layers (not shown).
- the cylindrical bottom electrodes 102 are disposed on the substrate.
- the structure layers 104 surround the periphery of the cylindrical bottom electrodes 102 .
- the structure layers 104 that surround the two opposing cylindrical bottom electrodes 102 has no mutual contact as shown by the line segment II-II that passes through two opposing cylindrical bottom electrodes 102 .
- the structure layers 104 that surround the two neighboring cylindrical bottom electrodes 102 are in contact with each other as shown by the line segment I-I that passes through two neighboring cylindrical bottom electrodes 102 .
- the width W 1 of the structure layer 104 is smaller than half the distance D 1 between two opposing cylindrical bottom electrodes 102 .
- the width W 1 of the structure layer 104 is greater than half the distance D 2 between two neighboring cylindrical bottom electrodes 102 .
- FIGS. 2A through 2F and FIG. 3 are schematic cross-sectional views showing the steps for fabricating a cylindrical capacitor according to one embodiment of the present invention.
- FIGS. 2A through 2F are schematic cross-sectional views showing the steps for forming the cylindrical bottom electrodes 102 and the structure layers 104 shown in FIG. 1 .
- FIGS. 2B to 2 H also show two schematic cross-sectional views along the line segment I-I and line II-II of FIG. 1 as 2 B-I, 2 B-II, . . . , 2 H-I, 2 H-II.
- FIGS. 3 -I and 3 -II are the schematic cross-sectional views showing the cylindrical capacitors formed after carrying out the steps in FIGS. 2 A through 2 H-II according to one embodiment of the present invention.
- FIGS. 3 -I and 3 -II are schematic cross-sectional views along the line segment I-I and the line segment II-II of FIG. 1 .
- a substrate having plugs 206 formed therein is provided.
- the substrate may be a silicon chip 200 comprising an inter-layer dielectric layer 204 formed thereon such that the plugs 206 are formed in the dielectric layer 204 , for example.
- the silicon chip 200 also has doped regions 202 in contact with the respective plugs 206 .
- a first dielectric layer 208 , a structure layer 210 , a second dielectric layer 212 and an etching stop layer 214 are sequentially formed over the substrate.
- the position of the structure layer 210 can be adjusted according to the actual demand instead of constrained by the location as shown in the present embodiment.
- the aforementioned structure layer 210 comprises a silicon nitride layer, for example.
- the etching stop layer 214 may also comprise a silicon nitride layer.
- a first photoresist layer 216 is formed over the etching stop layer 214 .
- the first photoresist layer 216 is patterned to expose the area in the etching stop layer 214 for forming a hole 218 .
- the etching stop layer 214 , the second dielectric layer 212 , the structure layer 210 and the first dielectric layer 208 are etched to form the hole 218 that exposes the plug 206 where the bottom electrode ( 102 as shown in 1 ) is subsequently formed.
- the first photoresist layer ( 216 as shown in FIG. 2B ) and a conductive layer 220 are formed over the substrate to cover the etching stop layer 214 and the inner surface of the hole 218 .
- a portion of the conductive layer ( 220 as shown in FIG. 2C ) at the top of the hole 218 is removed to expose a portion of the second dielectric layer 212 .
- the remaining portion of the conductive layer serves as a bottom electrode 220 a.
- the method of removing the portion of the conductive layer at the top of the hole 218 includes filling the hole 218 with a second photoresist layer 222 and then etching back the second photoresist layer 222 to expose the portion of the conductive layer at the top of the hole 218 . Finally, the exposed portion of the conductive layer is etched using the second photoresist layer 222 as an etching mask.
- the second photoresist layer ( 222 as shown in FIG. 2D ) is removed. Thereafter, an isotropic etching process is performed for removing a portion of the exposed second dielectric layer 212 to form an opening 224 at the top of the hole 218 .
- the etching stop layer ( 214 as shown in FIG. 2E ) is removed.
- a material is formed over the substrate and fill the opening 224 and the hole 218 to form a material layer 226 .
- the material layer 226 includes photoresist, polysilicon or any other material having a high etching selectivity with respect to the second dielectric layer 212 and the etching stop layer 214 , for example.
- the second dielectric layer ( 212 as shown in FIG. 2F ) is removed by performing a wet etching process, for example.
- a wet etching process for example.
- an anisotropic etching of the structure layer ( 210 as shown in FIG. 2F ) is performed to expose a portion of the first dielectric layer 208 .
- the structure layer 210 a so obtained is the structure layer 104 in FIG. 1 .
- the first dielectric layer ( 208 as shown in FIG. 2G ) is removed to expose the bottom electrode 220 a completely.
- the bottom electrode 220 a is a cylindrical bottom electrode with a substantially increased mechanical strength due to the support provided by the structure layer 210 a.
- a capacitor dielectric layer 304 is formed on the surface of the bottom electrode 220 a.
- the capacitor dielectric layer 304 is formed, for example, by performing an atomic layer deposition (ALD) process.
- ALD atomic layer deposition
- a top electrode 302 is formed on the capacitor dielectric layer 304 .
- the cylindrical capacitor 100 of the present invention not only has mechanical support but also has a higher density of the capacitor.
- the major advantages of the present invention includes providing an improved semiconductor process for forming the cylindrical capacitor and a structure layer for supporting the capacitor so that the mechanical strength of the cylindrical capacitor is increased and the product yield is improved. Furthermore, the location of the structure layer included in the cylindrical capacitor structure of the present invention can be changed and the distance between neighboring capacitors can be reduced without contacting each other so that the density of the capacitor is increased.
Abstract
A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.
Description
- This application is a divisional of an application Ser. No. 11/308,680, filed on Apr. 21, 2006, now allowed, which claims the priority benefit of Taiwan application serial no. 95101042, filed on Jan. 11, 2006. The entirety of each of the above-mentioned patent applications is incorporated herein by reference and made a part of this specification.
- 1. Field of the Invention
- The present invention relates to a cylindrical capacitor and a method of fabricating the same. More particularly, the present invention relates to a high mechanical strength cylindrical capacitor and a method of fabricating the same.
- 2. Description of the Related Art
- A semiconductor memory mainly comprises a transistor and a capacitor. As the process of fabricating the semiconductor memory needs to fabricate patterns with a high aspect ratio, the area available for accommodating the capacitor of each device is substantially reduced. However, as the memory space needed to operate a computer software program grows rapidly, the number of required capacitors also correspondingly increases. To satisfy this growing demand for capacitors, some basic modification is required to made to the existing techniques of manufacturing semiconductor device.
- At present, the minimum capacitance of each capacitor unit in a dynamic random access memory (DRAM) is greater than 25 fF. With the reduction in design dimension, a number of methods for increasing the capacitance of each capacitor unit have been suggested. The two major methods include: 1) using high dielectric constant (high k) material to produce the capacitor dielectric layer; and, 2) increasing the surface area of the capacitor by forming a cylindrical structure, forming a rod structure, forming a wing structure or forming a complicated structure by performing multiple processes. The most common means of increasing the surface area of a capacitor unit is still the cylindrical structure. However, even for the cylindrical capacitor, the height of the capacitor cylinder has to be increased as the allowed dimension is reduced. Yet, raising the height of the capacitor cylinder will destabilize the entire capacitor cylinder so that the capacitor cylinder is easily toppled. As a result, there will be a substantial drop in the production yield of the capacitor.
- Accordingly, at least one objective of the present invention is to provide a method of fabricating a cylindrical capacitor with a higher mechanical strength so that the fabrication yield of the cylindrical capacitor is increased.
- At least another objective of the present invention is to provide a cylindrical capacitor that can improve the mechanical strength of the cylindrical capacitor and increase the density of the capacitor.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the present invention provides a method of fabricating a cylindrical capacitor. The method includes providing a substrate with a plug formed therein. Next, a first dielectric layer, a structure layer, a second dielectric layer and an etching stop layer are sequentially formed over the substrate. Thereafter, a hole that exposes the plug is formed in the first dielectric layer, the structure layer, the second dielectric layer and the etching stop layer. Next, a conductive layer is formed over the substrate to cover the etching stop layer and the interior surface of the hole. Next, the conductive layer disposed on the top of the hole is removed to expose a portion of the second dielectric layer. The remaining conductive layer serves as a bottom electrode. An isotropic etching of a portion of the exposed second dielectric layer is performed to form an opening at the top of the hole. Next, the etching stop layer is removed and a material layer is filled inside the opening and the hole. Next, the second dielectric layer is removed. Using the material layer as a etching mask, an anisotropic etching of the structure layer is performed to expose a portion of the first dielectric layer. The first dielectric layer is removed to expose the entire bottom electrode. Next, a capacitor dielectric layer is formed over the surface of the bottom electrode. Finally, a top electrode is formed over the surface of the capacitor dielectric layer.
- According to an embodiment of the present invention, the steps for forming the hole include forming a first photoresist layer over the etching stop layer so that the area for forming the hole in the etching stop layer is exposed. Next, using the first photoresist layer as a etching mask, the etching stop layer, the second dielectric layer, the structure layer and the first dielectric layer are etched. Furthermore, after forming the hole, the first photoresist layer is removed.
- According to one embodiment of the present invention, the steps for removing the conductive layer at the top of the hole include filling the hole with a second photoresist layer. Next, the second photoresist layer is etched back to expose the conductive layer at the top of the hole. Thereafter, using the second photoresist layer as a etching mask, the exposed conductive layer is exposed. Furthermore, after removing the conductive layer at the top of the hole, the second photoresist layer is also removed.
- According to one embodiment of the present invention, the structure layer can be a silicon nitride layer and the etching stop layer can also be a silicon nitride layer. In addition, the material layer comprises photoresist or polysilicon.
- According to one embodiment of the present invention, the step for removing the second dielectric layer includes performing a wet etching process.
- According to one embodiment of the present invention, the step for forming the capacitor dielectric layer on the surface of the bottom electrode includes performing an atomic layer deposition process.
- The present invention also provides a cylindrical capacitor having at least a substrate, a plurality of cylindrical bottom electrodes, a plurality of structure layers, a plurality of top electrodes and a capacitor dielectric layer. The substrate has a plurality of plugs formed therein. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layers surround the periphery of the cylindrical bottom electrodes. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode.
- According to one embodiment of the present invention, the width of each structure layer is smaller than half the distance between two opposing cylindrical bottom electrodes.
- According to one embodiment of the present invention, the width of each structure layer is greater than half the distance between two neighboring cylindrical bottom electrodes.
- According to one embodiment of the present invention, the structure layer includes a silicon nitride layer.
- In the present invention, a semiconductor process is used to form a structure layers that strengthens the cylindrical capacitor. Hence, the mechanical strength of the cylindrical capacitor is increased and the fabrication yield is improved. Moreover, the location of the structure layer inside the cylindrical capacitor structure of the present invention can be changed and the distance between capacitors can be reduced without making mutual contact. Therefore, density of the capacitor can be increased.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a top view showing a part of the structure of a cylindrical capacitor according to one embodiment of the present invention. - FIGS. 2A, 2B-I, 2B-II, 2C-I, 2C-II, 2D-I, 2D-II, 2E-I, 2E-II, 2F-I, 2F-II, 2G-I, 2G-II, 2H-I and 2H-II are schematic cross-sectional views showing the steps for forming the cylindrical bottom electrode and the structure layer shown in
FIG. 1 . - FIGS. 3-I and 3-II are the schematic cross-sectional views showing the cylindrical capacitors formed after carrying out the steps in FIGS. 2A through 2H-II according to one embodiment of the present invention.
- Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIG. 1 is a top view showing part of the structure of a cylindrical capacitor according to one embodiment of the present invention. To illustrate the characteristic of the present invention more clearly, the top electrode and the capacitor dielectric layer of the capacitor are not shown. - As shown in
FIG. 1 , the cylindrical capacitor 100 in the present invention includes at least a substrate (not shown), a plurality of cylindricalbottom electrodes 102, a plurality of structure layers 104, a plurality of top electrodes (not shown) and a plurality of capacitor dielectric layers (not shown). The cylindricalbottom electrodes 102 are disposed on the substrate. The structure layers 104 surround the periphery of the cylindricalbottom electrodes 102. The structure layers 104 that surround the two opposing cylindricalbottom electrodes 102 has no mutual contact as shown by the line segment II-II that passes through two opposing cylindricalbottom electrodes 102. On the contrary, the structure layers 104 that surround the two neighboring cylindricalbottom electrodes 102 are in contact with each other as shown by the line segment I-I that passes through two neighboring cylindricalbottom electrodes 102. For example, the width W1 of thestructure layer 104 is smaller than half the distance D1 between two opposing cylindricalbottom electrodes 102. In addition, the width W1 of thestructure layer 104 is greater than half the distance D2 between two neighboring cylindricalbottom electrodes 102. -
FIGS. 2A through 2F andFIG. 3 are schematic cross-sectional views showing the steps for fabricating a cylindrical capacitor according to one embodiment of the present invention.FIGS. 2A through 2F are schematic cross-sectional views showing the steps for forming the cylindricalbottom electrodes 102 and the structure layers 104 shown inFIG. 1 . Furthermore,FIGS. 2B to 2H also show two schematic cross-sectional views along the line segment I-I and line II-II ofFIG. 1 as 2B-I, 2B-II, . . . , 2H-I, 2H-II. FIGS. 3-I and 3-II are the schematic cross-sectional views showing the cylindrical capacitors formed after carrying out the steps in FIGS. 2A through 2H-II according to one embodiment of the present invention. FIGS. 3-I and 3-II are schematic cross-sectional views along the line segment I-I and the line segment II-II ofFIG. 1 . - As shown in
FIG. 2A , asubstrate having plugs 206 formed therein is provided. The substrate may be asilicon chip 200 comprising aninter-layer dielectric layer 204 formed thereon such that theplugs 206 are formed in thedielectric layer 204, for example. In general, thesilicon chip 200 also has dopedregions 202 in contact with the respective plugs 206. Next, a firstdielectric layer 208, astructure layer 210, asecond dielectric layer 212 and anetching stop layer 214 are sequentially formed over the substrate. The position of thestructure layer 210 can be adjusted according to the actual demand instead of constrained by the location as shown in the present embodiment. Furthermore, theaforementioned structure layer 210 comprises a silicon nitride layer, for example. Theetching stop layer 214 may also comprise a silicon nitride layer. Thereafter, in preparation for the subsequent fabrication of the hole for forming the bottom electrode, afirst photoresist layer 216 is formed over theetching stop layer 214. - As shown in FIGS. 2B-I and 2B-II, the
first photoresist layer 216 is patterned to expose the area in theetching stop layer 214 for forming ahole 218. Next, using thefirst photoresist layer 216 as an etching mask, theetching stop layer 214, thesecond dielectric layer 212, thestructure layer 210 and thefirst dielectric layer 208 are etched to form thehole 218 that exposes theplug 206 where the bottom electrode (102 as shown in 1) is subsequently formed. - As shown in FIGS. 2C-I and 2C-II, the first photoresist layer (216 as shown in
FIG. 2B ) and aconductive layer 220 are formed over the substrate to cover theetching stop layer 214 and the inner surface of thehole 218. - As shown in FIGS. 2D-I and 2D-II, a portion of the conductive layer (220 as shown in
FIG. 2C ) at the top of thehole 218 is removed to expose a portion of thesecond dielectric layer 212. The remaining portion of the conductive layer serves as abottom electrode 220 a. The method of removing the portion of the conductive layer at the top of thehole 218 includes filling thehole 218 with asecond photoresist layer 222 and then etching back thesecond photoresist layer 222 to expose the portion of the conductive layer at the top of thehole 218. Finally, the exposed portion of the conductive layer is etched using thesecond photoresist layer 222 as an etching mask. - As shown in FIGS. 2E-I and 2E-II, the second photoresist layer (222 as shown in
FIG. 2D ) is removed. Thereafter, an isotropic etching process is performed for removing a portion of the exposedsecond dielectric layer 212 to form anopening 224 at the top of thehole 218. - As shown in FIGS. 2F-I and 2F-II, the etching stop layer (214 as shown in
FIG. 2E ) is removed. Next, a material is formed over the substrate and fill theopening 224 and thehole 218 to form amaterial layer 226. Thematerial layer 226 includes photoresist, polysilicon or any other material having a high etching selectivity with respect to thesecond dielectric layer 212 and theetching stop layer 214, for example. - As shown in FIGS. 2G-I and 2G-II, the second dielectric layer (212 as shown in
FIG. 2F ) is removed by performing a wet etching process, for example. Next, using thematerial layer 226 as a mask, an anisotropic etching of the structure layer (210 as shown inFIG. 2F ) is performed to expose a portion of thefirst dielectric layer 208. Thestructure layer 210 a so obtained is thestructure layer 104 inFIG. 1 . - As shown in FIGS. 2H-I and 2H-II, the first dielectric layer (208 as shown in
FIG. 2G ) is removed to expose thebottom electrode 220 a completely. Thebottom electrode 220 a is a cylindrical bottom electrode with a substantially increased mechanical strength due to the support provided by thestructure layer 210 a. - Thereafter, as shown in FIGS. 3-I and 3-II, a
capacitor dielectric layer 304 is formed on the surface of thebottom electrode 220 a. Thecapacitor dielectric layer 304 is formed, for example, by performing an atomic layer deposition (ALD) process. Then, atop electrode 302 is formed on thecapacitor dielectric layer 304. - As shown in FIGS. 1, 3-I and 3-II, due to the location of the
structure layer 104 and width, the cylindrical capacitor 100 of the present invention not only has mechanical support but also has a higher density of the capacitor. - In summary, the major advantages of the present invention includes providing an improved semiconductor process for forming the cylindrical capacitor and a structure layer for supporting the capacitor so that the mechanical strength of the cylindrical capacitor is increased and the product yield is improved. Furthermore, the location of the structure layer included in the cylindrical capacitor structure of the present invention can be changed and the distance between neighboring capacitors can be reduced without contacting each other so that the density of the capacitor is increased.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (4)
1. A cylindrical capacitor, comprising:
a substrate having a plurality of plugs formed therein;
a plurality of cylindrical bottom electrodes disposed on the substrate and electrically connected to the respective plugs;
a plurality of structure layers surrounding a periphery of the respective cylindrical bottom electrodes, wherein
the structure layers that surround two opposing cylindrical bottom electrodes have no mutual contact; and
the structure layers that surround two neighboring cylindrical bottom electrodes contact each other;
a plurality of top electrodes covering the respective cylindrical bottom electrodes; and
a capacitor dielectric layer disposed between each top electrode and corresponding cylindrical bottom electrode.
2. The cylindrical capacitor of claim 1 , wherein the width of the structure layer is smaller than half the distance between two opposing cylindrical bottom electrodes.
3. The cylindrical capacitor of claim 1 , wherein the width of the structure layer is greater than half the distance between two neighboring cylindrical bottom electrodes.
4. The cylindrical capacitor of claim 1 , wherein the structure layer includes a silicon nitride layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/960,726 US20080094776A1 (en) | 2006-01-11 | 2007-12-20 | Cylindrical capacitor |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095101042A TWI297931B (en) | 2006-01-11 | 2006-01-11 | Cylindrical capacitor and method of manufacturing the same |
TW95101042 | 2006-01-11 | ||
US11/308,680 US7332393B2 (en) | 2006-01-11 | 2006-04-21 | Method of fabricating a cylindrical capacitor |
US11/960,726 US20080094776A1 (en) | 2006-01-11 | 2007-12-20 | Cylindrical capacitor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/308,680 Division US7332393B2 (en) | 2006-01-11 | 2006-04-21 | Method of fabricating a cylindrical capacitor |
Publications (1)
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US20080094776A1 true US20080094776A1 (en) | 2008-04-24 |
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US11/308,680 Expired - Fee Related US7332393B2 (en) | 2006-01-11 | 2006-04-21 | Method of fabricating a cylindrical capacitor |
US11/960,726 Abandoned US20080094776A1 (en) | 2006-01-11 | 2007-12-20 | Cylindrical capacitor |
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US11/308,680 Expired - Fee Related US7332393B2 (en) | 2006-01-11 | 2006-04-21 | Method of fabricating a cylindrical capacitor |
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KR100979243B1 (en) * | 2008-04-29 | 2010-08-31 | 주식회사 하이닉스반도체 | Semiconductor device and method of manufacturing the same |
CN113764579B (en) * | 2020-06-04 | 2023-06-30 | 长鑫存储技术有限公司 | Capacitor structure, manufacturing method thereof and memory |
CN112928069B (en) * | 2021-02-05 | 2023-02-28 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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US6031262A (en) * | 1996-11-14 | 2000-02-29 | Nec Corporation | Semiconductor memory device having capacitor-over-bitline cell with multiple cylindrical storage electrode offset from node contact and process of fabrication thereof |
US7425740B2 (en) * | 2005-10-07 | 2008-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
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US5807782A (en) * | 1995-09-25 | 1998-09-15 | Vanguard International Semiconductor Corporation | Method of manufacturing a stacked capacitor having a fin-shaped storage electrode on a dynamic random access memory cell |
JP3941133B2 (en) * | 1996-07-18 | 2007-07-04 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
JP4199338B2 (en) * | 1998-10-02 | 2008-12-17 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
TW434886B (en) * | 1999-11-04 | 2001-05-16 | Taiwan Semiconductor Mfg | Manufacturing method of stacked capacitor |
KR100449030B1 (en) | 2002-01-24 | 2004-09-16 | 삼성전자주식회사 | Stack Capacitor and Method of Fabricating the Same |
KR100538098B1 (en) | 2003-08-18 | 2005-12-21 | 삼성전자주식회사 | Semiconductor device including a capacitor having improved structural stability and enhanced capacitance, and Method for manufacturing the same |
-
2006
- 2006-01-11 TW TW095101042A patent/TWI297931B/en not_active IP Right Cessation
- 2006-04-21 US US11/308,680 patent/US7332393B2/en not_active Expired - Fee Related
-
2007
- 2007-12-20 US US11/960,726 patent/US20080094776A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031262A (en) * | 1996-11-14 | 2000-02-29 | Nec Corporation | Semiconductor memory device having capacitor-over-bitline cell with multiple cylindrical storage electrode offset from node contact and process of fabrication thereof |
US7425740B2 (en) * | 2005-10-07 | 2008-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for a 1T-RAM bit cell and macro |
Also Published As
Publication number | Publication date |
---|---|
TW200727407A (en) | 2007-07-16 |
US20070161178A1 (en) | 2007-07-12 |
TWI297931B (en) | 2008-06-11 |
US7332393B2 (en) | 2008-02-19 |
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