US20080048333A1 - Semiconductor Device Having Buried Word Line Interconnects and Method of Fabricating the Same - Google Patents
Semiconductor Device Having Buried Word Line Interconnects and Method of Fabricating the Same Download PDFInfo
- Publication number
- US20080048333A1 US20080048333A1 US11/842,416 US84241607A US2008048333A1 US 20080048333 A1 US20080048333 A1 US 20080048333A1 US 84241607 A US84241607 A US 84241607A US 2008048333 A1 US2008048333 A1 US 2008048333A1
- Authority
- US
- United States
- Prior art keywords
- word line
- peripheral circuit
- interconnect
- buried
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Definitions
- the present invention relates to semiconductor devices, and more particularly, to semiconductor devices having buried word lines and methods of fabricating the same.
- Integrated circuits include discrete devices, such as transistors, and interconnects for electrically connecting the discrete devices to each other.
- a typical transistor has a source region, a drain region and a gate electrode, which are disposed on a semiconductor substrate. The source and drain regions are spaced apart from each other in an active region of the semiconductor substrate. The gate electrode is disposed between the source region and the drain region and insulated from the active region.
- a memory device such as a dynamic random access memory (DRAM) typically has a plurality of cell transistors disposed in a cell array region and p-channel metal oxide semiconductor (pMOS) transistors and n-channel metal oxide semiconductor (nMOS) transistors disposed in a peripheral circuit region.
- the cell transistors are disposed at predetermined intervals in the cell array region.
- Gate electrodes of the cell transistors are connected to a word line.
- a conventional technique for forming a buried word line involves burying the word line at a lower level than a top surface of the active region.
- a semiconductor device having a buried word line is disclosed in U.S. Pat. No. 6,770,535 B2 entitled to “Semiconductor Integrated Circuit Device and Process for Manufacturing the Same” by Yamada et al.
- Planar transistors such as high-voltage transistors may be disposed in the peripheral circuit region. Gate electrodes of the planar transistors may be disposed at a higher level than the active region. In addition, a plurality of gate lines may be formed at the same level as the gate electrodes.
- the buried word line typically must be electrically connected to a gate line of the peripheral circuit region corresponding thereto.
- a technique for electrically connecting the buried word line with the gate line using a bypass interconnect and a contact plug has been developed. According to the technique using a bypass interconnect and a contact plug, a first interlayer insulating layer covering the buried word line and the gate line is formed, the bypass interconnect is disposed on the first interlayer insulating layer, and the contact plug penetrating the first interlayer insulating layer is used.
- interconnects crossing between the buried word line and the gate line may be disposed on the first interlayer insulating layer.
- a second interlayer insulating layer is formed on the first interlayer insulating layer
- the bypass interconnect is disposed on the second interlayer insulating layer
- a contact plug penetrating the first and second interlayer insulating layers is used.
- the contact plug may difficult to form, and a signal transmission path may be lengthened. Consequently, a technique using a bypass interconnect and a contact plug may not provide an advantageous structure for high integration, and may degrade electrical characteristics and reliability.
- a semiconductor device in some embodiments of the present invention, includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein.
- a buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region.
- a gate line is disposed on the substrate in the peripheral circuit region.
- a unitary word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
- the second portion of the word line interconnect may extend vertically from the first portion of the word line interconnect to contact a bottom surface of the gate line.
- the first portion of the word line interconnect may be laterally offset with respect to the buried word line.
- the top surface of the first portion of the word line interconnect may be at substantially the same level at the top surface of the buried word line and the first portion of the word line interconnect may have substantially the same cross-sectional area as the buried word line.
- An insulating pattern may be disposed on the first portion of the word line interconnect and the buried word line. A bottom surface of the insulating pattern may be lower than the top surfaces of the cell active regions.
- a bit line may be disposed on the insulating pattern and may cross the buried word line.
- the semiconductor device may further include second and third spaced-apart gate lines on the substrate in the peripheral circuit region on respective sides of the bit line.
- a buried peripheral circuit interconnect may be disposed in the substrate in the peripheral circuit region beneath the bit line, and may connect the first and second gate lines and have a portion beneath the bit line that has a top surface at substantially the same level as the top surface of the buried word line.
- FIG. 1 An isolation region is formed in a semiconductor substrate, defining cell active regions in a cell region and peripheral circuit active regions in a peripheral circuit region.
- a word line trench is formed in the substrate in the cell region and an adjoining word line interconnect trench is formed in the peripheral circuit region.
- a word line pattern is formed in the word line trench and a word line interconnect pattern is formed in the word line interconnect trench.
- a gate line is formed on the substrate in the peripheral circuit region, the gate line having an end portion that overlaps the word line interconnect pattern.
- the word line pattern and the word line interconnect pattern are etched back to form a word line in the word line trench having a top surface lower than a top surface of the cell active regions and a word line interconnect in the word line interconnect trench having a first portion connected to the word line and a top surface lower than the top surfaces of the cell active regions and a second portion extending vertically from the first portion to contact a bottom surface of the gate line.
- An insulating pattern is formed on the buried word line and the first portion of the word line interconnect.
- forming a word line trench includes forming a first sacrificial mask pattern on the substrate having the isolation layer, forming sacrificial spacers on sidewalls of the first sacrificial mask pattern, forming a second sacrificial mask pattern filling a gap between the sacrificial spacers, removing the sacrificial spacers and etching the isolation layer and the semiconductor substrate using the first and second sacrificial mask patterns as etching masks to form the word line trench and the word line interconnect trench.
- Forming a first sacrificial mask pattern on the substrate may be preceded by forming a peripheral circuit gate dielectric layer on the peripheral circuit active regions, forming a peripheral circuit gate conductive layer on the peripheral circuit gate dielectric layer and forming a sacrificial oxide layer on the peripheral circuit gate conductive layer.
- forming a gate line includes etching the first and second sacrificial mask patterns and the sacrificial oxide layer to expose the peripheral circuit gate conductive layer, forming a metal layer covering the peripheral circuit gate conductive layer, the word line pattern, and the word line interconnect pattern and patterning the metal layer and the peripheral circuit gate conductive layer to form the gate line.
- the word line pattern and the word line interconnect pattern may be formed from a common metal layer.
- a bit line is formed on the insulating pattern and crossing the buried word line.
- a peripheral circuit interconnect trench may be formed in the substrate in the peripheral circuit region concurrent with forming the word line trench in the substrate in the cell region and the adjoining word line interconnect trench in the peripheral circuit region.
- a peripheral circuit interconnect pattern may be formed in the peripheral circuit interconnect trench concurrent with forming the word line pattern in the word line trench and the word line interconnect pattern in the word line interconnect trench.
- Second and third spaced apart gate lines may be formed in the peripheral circuit region on respective sides of the bit line concurrent with forming the first gate line on the substrate in the peripheral circuit region, the first and second gate lines overlapping and contacting the peripheral circuit interconnect pattern.
- the peripheral circuit interconnect pattern may be etched back concurrent with etching back the word line pattern and the word line interconnect pattern to form a peripheral circuit interconnect having a first portion with a top surface that is lower than a top surface of the peripheral circuit active regions and second portions that extend vertically from the first portion to contact bottom surfaces of respective ones of the second and third gate lines.
- An insulating pattern may be formed on the first portion of the peripheral circuit interconnect concurrent with forming the insulating pattern on the buried word line and the first portion of the word line interconnect.
- Some embodiments of the invention provides semiconductor devices including interconnects that may be advantageous to high integration and may have excellent electrical characteristics.
- inventions provide methods of fabricating a semiconductor device including interconnects that may be advantageous to high integration and may have excellent electrical characteristics.
- the present invention provides semiconductor devices having buried interconnects.
- a device has an isolation layer disposed on a semiconductor substrate. By the isolation layer, cell active regions are defined in a cell region, and peripheral circuit active regions are defined in a peripheral circuit region.
- a buried word line is disposed in the cell region. The buried word line is disposed at a lower level than the top surface of the cell active region.
- a buried interconnect is disposed in the peripheral circuit region. The buried interconnect is disposed at a lower level than the top surface of the peripheral circuit active regions.
- Gate lines are disposed at a higher level than the buried interconnect. The gate lines have regions overlapping the buried interconnect. In the overlapping regions, the buried interconnect contacts the gate lines.
- the buried interconnect may project toward the gate lines in the overlapping region.
- the gate line may project toward the buried interconnect in the overlapping region.
- the buried interconnect may be disposed at the same level as the buried word line.
- the buried interconnect may have the same cross-sectional area as the buried word line.
- the buried interconnect may be the same material layer as the buried word line.
- the buried interconnect and the buried word line may have a metal layer.
- the metal layer may be a titanium nitride (TiN) layer.
- the buried interconnect and the buried word line may be in contact with each other.
- the buried interconnect may have two overlapping regions spaced apart from each other.
- One of the gate lines passing through an n-channel metal oxide semiconductor (nMOS) region may contact one part of the buried interconnect in one of the overlapping regions.
- the other one of the gate lines passing through a p-channel metal oxide semiconductor (pMOS) region may contact the other part of the buried interconnect in the other of the overlapping regions.
- the gate lines may be disposed at a higher level than the peripheral circuit active regions.
- an insulating pattern may be disposed on the buried interconnect and buried word line.
- the bottom surface of the insulating pattern may be disposed at a lower level than the top surfaces of the adjacent active regions.
- a bit line crossing the buried interconnect may be disposed on the insulating pattern.
- the present invention provides methods of fabricating semiconductor devices.
- a method may include: providing a semiconductor substrate having a cell region and a peripheral circuit region; forming an isolation layer defining cell active regions in the cell region and peripheral circuit active regions in the peripheral circuit region; etching the cell active regions and the isolation layer, and simultaneously forming word line trenches in the cell region and interconnect trenches in the peripheral circuit region; simultaneously forming word lines in the word line trenches and interconnect patterns in the interconnect trenches; forming gate lines on the semiconductor substrate having the interconnect patterns, the gate lines having regions overlapping the interconnect patterns; etching-back the word lines and the interconnect patterns and forming buried word lines and buried interconnects, the buried interconnects contacting the gate lines in the overlapping regions; and forming an insulating pattern on the buried word lines and the buried interconnects.
- forming the word line trenches and the interconnect trenches may include: forming a first sacrificial mask pattern on the substrate having the isolation layer; forming sacrificial spacers on sidewalls of the first sacrificial mask pattern; forming a second sacrificial mask pattern filling a gap between the sacrificial spacers; removing the sacrificial spacers; and etching the isolation layer and the cell active layers using the first and second sacrificial mask patterns as etching masks.
- the first and second mask patterns may be formed of a material layer having an etch selectivity with respect to the active regions and the isolation layer.
- the sacrificial spacers may be formed of a polysilicon layer.
- the word line trenches and the interconnect trenches may be formed to have a smaller width than the resolution limit of a photolithography process.
- a peripheral circuit gate dielectric layer may be formed on the peripheral circuit active regions.
- a peripheral circuit gate conductive layer may be formed on the semiconductor substrate having the peripheral circuit gate dielectric layer.
- a sacrificial oxide layer may be formed on the peripheral circuit gate conductive layer.
- forming the gate lines may include: while the word lines and the interconnect patterns are formed, etching the sacrificial mask patterns and the sacrificial oxide layer and exposing the peripheral circuit gate conductive layer; forming a metal layer covering the peripheral circuit gate conductive layer, the word lines, and the interconnect patterns; and continuously patterning the metal layer and the peripheral circuit gate conductive layer.
- the word lines and the interconnect patterns may be formed of a metal layer.
- the word line trenches may be formed to be connected to the interconnect trenches corresponding thereto, respectively.
- the bottom surface of the insulating pattern may be formed at a lower level than the top surfaces of the adjacent active regions.
- a bit line disposed on the insulating pattern and crossing the buried interconnects may be formed.
- a method may include: providing a semiconductor substrate having a cell region and a peripheral circuit region; forming an isolation layer defining cell active regions in the cell region and peripheral circuit active regions in the peripheral circuit region; etching the cell active regions and the isolation layer, and simultaneously forming word line trenches in the cell region and interconnect trenches in the peripheral circuit region; simultaneously forming buried word lines in the word line trenches and buried interconnects in the interconnect trenches; forming gate lines on the semiconductor substrate having the buried interconnects, the gate lines having regions overlapping the buried interconnects, the buried interconnects contacting the gate lines in the overlapping regions; and forming an insulating pattern on the buried word lines and the buried interconnects disposed at a lower level than top surfaces of the adjacent active regions.
- FIG. 1 is a plan view of a semiconductor device having buried interconnects according to first exemplary embodiments of the present invention.
- FIGS. 2 through 14 are composites of cross-sectional views illustrating operations for forming the semiconductor device of FIG. 1 .
- FIG. 15 is a plan view of a semiconductor device having buried interconnects according to second exemplary embodiments of the present invention.
- FIGS. 16 to 21 are composites of cross-sectional views illustrating operations for forming the semiconductor device of FIG. 15 .
- FIG. 22 is a plan view of a semiconductor device having buried interconnects according to third exemplary embodiments of the present invention.
- FIG. 23 is a composite of cross-sectional views illustrating operations for forming the semiconductor device of FIG. 23 .
- FIG. 24 is a plan view of a semiconductor device having buried interconnects according to fourth exemplary embodiments of the present invention.
- first,” “second,” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used merely as a convenience to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. For example, a first element, component, region, layer and/or section could be termed a second element, component, region, layer and/or section without departing from the teachings of the present invention.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, may be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, “height” refers to a direction that is generally orthogonal to the faces of a substrate.
- Embodiments of the present invention may be described with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations, as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result from, e.g., manufacturing. For example, a region illustrated as a rectangle may have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and are not intended to limit the scope of the present invention. Like reference numerals refer to like elements throughout.
- FIG. 1 is a plan view of a semiconductor device.
- FIGS. 2 to 14 are composites of cross-sectional views illustrating methods of fabricating the semiconductor device of FIG. 1 , in which a cross-section 1 is taken along line I-I′ of FIG. 1 , a cross-section 2 is taken along line II-II′ of FIG. 1 , a cross-section 3 is taken along line III-III′ of FIG. 1 , and a cross-section 4 is taken along line IV-IV′ of FIG. 1 .
- an isolation layer 55 defining active regions 53 , 54 and 54 P may be formed on a semiconductor substrate 51 .
- the isolation layer 55 may be formed by a trench isolation technique.
- the isolation layer 55 may be formed of an insulating layer, such as a silicon oxide layer.
- the semiconductor substrate 51 may be a silicon wafer having a peripheral circuit region 10 and a cell region 20 .
- the active regions 53 , 54 and 54 P may include cell active regions 53 , n-channel metal oxide semiconductor (nMOS) peripheral circuit active regions 54 , and a p-channel metal oxide semiconductor (pMOS) peripheral circuit active regions 54 P.
- the cell active regions 53 may be arranged at predetermined intervals in row and column directions.
- the nMOS peripheral circuit active regions 54 and the pMOS peripheral circuit active regions 54 P may be disposed in the peripheral circuit region 10 .
- the well-ion implantation process may include a process of implanting p-type impurity ions and a process of implanting n-type impurity ions.
- the process of implanting p-type impurity ions into the cell active regions 53 and the nMOS peripheral circuit active regions 54 may be performed, and also, the process of implanting n-type impurity ions into the pMOS peripheral circuit active regions 54 P may be performed.
- nMOS transistors may be formed in the cell active regions 53 and the nMOS peripheral circuit active regions 54
- pMOS transistors may be formed in the pMOS peripheral circuit active regions 54 P.
- a peripheral circuit gate dielectric layer 57 may be formed on the active regions 53 , 54 and 54 P.
- a peripheral circuit gate conductive layer 58 , a sacrificial oxide layer 59 , and a first sacrificial mask layer 61 may be sequentially stacked on the semiconductor substrate 51 having the peripheral circuit gate dielectric layer 57 .
- the peripheral circuit gate dielectric layer 57 may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof.
- the peripheral circuit gate dielectric layer 57 may be formed to cover the surfaces of the active regions 53 , 54 and 54 P.
- the peripheral circuit gate conductive layer 58 may be a conductive layer, such as an undoped polysilicon layer.
- the peripheral circuit gate conductive layer 58 may cover the top surface of the semiconductor substrate 51 having the peripheral circuit gate dielectric layer 57 .
- the sacrificial oxide layer 59 may be a silicon oxide layer, such as a thermal oxide layer.
- the sacrificial oxide layer 59 may cover the top surface of the peripheral circuit gate conductive layer 58 .
- the first sacrificial mask layer 61 may be a material layer having an etch selectivity with respect to the peripheral circuit gate conductive layer 58 , the active regions 53 , 54 and 54 P, and the isolation layer 55 .
- the first sacrificial mask layer 61 may be a nitride layer such as a silicon nitride layer.
- the first sacrificial mask layer 61 is patterned to form a first sacrificial mask pattern 61 ′ having first openings 61 P.
- the sacrificial oxide layer 59 may be exposed at the bottom of the first openings 61 P.
- the first openings 61 P may be formed in a groove shape in a column direction in the cell region 20 . Also, the first openings 61 P may be formed parallel to each other. In addition, the first openings 61 P may be formed to cross over the cell active regions 53 . Furthermore, the first openings 61 P may extend from the cell region 20 to the peripheral circuit region 10 .
- the first openings 61 P may be formed in the peripheral circuit region 10 as well. In this case, the first openings 61 P may be formed on the isolation layer 55 .
- sacrificial spacers 65 may be formed on sidewalls of the first sacrificial mask pattern 61 ′.
- the sacrificial spacers 65 may be formed from a material layer having an etch selectivity with respect to the first sacrificial mask pattern 61 ′.
- the sacrificial spacers 65 may be polysilicon.
- a polysilicon layer covering inner walls of the first openings 61 P and the top surface of the first sacrificial mask pattern 61 ′ may be formed.
- the polysilicon layer may be anisotropically etched, so that the sacrificial oxide layer 59 may be exposed. In this case, the polysilicon layer may remain on the sidewalls of the first openings 61 P.
- the thickness of the sacrificial spacers 65 can be adjusted by controlling deposition conditions of the polysilicon layer.
- the sacrificial spacers 65 may have a smaller thickness than the resolution limit of a photolithography process.
- the anisotropic etching process may be omitted.
- a patterning process for separating a sacrificial spacer 65 may be performed. Specifically, a photoresist pattern 67 may be formed on the semiconductor substrate 51 having the sacrificial spacers 65 . One of the sacrificial spacers 65 is partially etched using the photoresist pattern 67 as an etching mask, so that a second opening 67 P exposing the sacrificial oxide layer 59 may be formed. The second opening 67 P may be selectively formed at both ends of a first one of the openings 61 P. For example, the second opening 67 P may be formed to overlap both ends of the first openings 61 P extending from the cell region 20 to the peripheral circuit region 10 . Subsequently, the photoresist pattern 67 may be removed.
- a second sacrificial mask pattern 69 filling a gap between the sacrificial spacers 65 and the first and second openings 61 P and 67 P may be formed.
- a second sacrificial mask layer filling the first openings 61 P and the second openings 67 P and covering the semiconductor substrate 51 may be formed.
- the second sacrificial mask layer is planarized until the sacrificial spacer 65 is exposed, so that the second sacrificial mask pattern 69 may be formed.
- a chemical-mechanical polishing (CMP) process or etch back process may be used for planarization of the second sacrificial mask layer.
- the sacrificial spacers 65 may be removed.
- An isotropic etching having an etch selectivity between the sacrificial mask patterns 61 ′ and 69 and the sacrificial spacers 65 may be used to remove the sacrificial spacers 65 .
- the isotropic etching may have a high etch rate with respect to the sacrificial spacers 65 . Consequently, the sacrificial mask patterns 61 ′ and 69 may remain on the semiconductor substrate 51 .
- the sacrificial oxide layer 59 , the peripheral circuit gate conductive layer 58 , the peripheral circuit gate dielectric layer 57 , the isolation layer 55 , and the cell active regions 53 are anisotropically etched, so that word line trenches 71 and interconnect trenches 72 may be formed.
- the word line trenches 71 may be formed in the cell region 20
- the interconnect trenches 72 may be formed in the peripheral circuit region 10 .
- the word line trenches 71 may be connected to the interconnect trenches 72 corresponding thereto, respectively. In other words, the word line trenches 71 may extend to be connected to the interconnect trenches 72 .
- Sizes of the word line trenches 71 and the interconnect trenches 72 may be determined by the sacrificial spacer 65 .
- the word line trenches 71 and the interconnect trenches 72 may also be formed to have a width smaller than the resolution limit of a photolithography process.
- the sacrificial mask patterns 61 ′ and 69 may be removed.
- An isotropic etching process may be used to remove the sacrificial mask patterns 61 ′ and 69 .
- a cell gate dielectric layer 77 may be formed on inner walls of the word line trenches 71 .
- the cell gate dielectric layer 77 may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof.
- the cell gate dielectric layer 77 may be formed to uniformly cover surfaces of the cell active regions 53 exposed to the word line trenches 71 .
- a word conductive layer may be formed on the semiconductor substrate 51 having the cell gate dielectric layer 77 .
- the word conductive layer is planarized, so that word lines 78 may be formed in the word line trenches 71 , and simultaneously, interconnect patterns 79 may be formed in the interconnect trenches 72 .
- a CMP process or etch back process may be used for planarization of the word conductive layer.
- the sacrificial oxide layer 59 is removed, so that the peripheral circuit gate conductive layer 58 may be exposed.
- the word lines 78 and the interconnect patterns 79 may be formed of a metal layer, such as a titanium nitride (TiN) layer.
- the peripheral circuit gate conductive layer 58 , the word lines 78 , and the interconnect patterns 79 may be exposed on substantially the same plane.
- the word lines 78 and the interconnect patterns 79 may be formed at a lower level than the top surface of the peripheral circuit gate conductive layer 58 .
- the word lines 78 may contact the interconnect patterns 79 corresponding thereto, respectively.
- the sacrificial mask patterns 61 ′ and 69 may be removed after the word lines 78 and the interconnect patterns 79 are formed.
- Impurity ions may be implanted into the peripheral circuit gate conductive layer 58 .
- n-type impurity ions may be implanted into the peripheral circuit gate conductive layer 58 in an nMOS region
- p-type impurity ions may be implanted into a peripheral circuit gate conductive layer 58 P in a pMOS region.
- an upper conductive layer 81 covering the peripheral circuit gate conductive layers 58 and 58 P, the word lines 78 , and the interconnect patterns 79 may be formed.
- the upper conductive layer 81 may be formed of a metal layer such as tungsten (W) or tungsten silicide (WSi).
- the upper conductive layer 81 may contact the peripheral circuit gate conductive layers 58 and 58 P, the word lines 78 , and the interconnect patterns 79 .
- a hard mask pattern 83 may be formed on the upper conductive layer 81 .
- the hard mask pattern 83 may be formed of a nitride layer, such as a silicon nitride layer.
- the upper conductive layer 81 and the peripheral circuit gate conductive layers 58 and 58 P are etched back using the hard mask pattern 83 as an etching mask, so that gate lines 85 , 87 and 88 may be formed.
- the gate lines 85 , 87 and 88 may include first gate lines 85 , second gate lines 87 , and third gate lines 88 .
- patterned peripheral circuit gate conductive layers 58 ′ and 58 P′ may remain.
- the gate lines 85 , 87 and 88 may have regions CA overlapping the interconnect patterns 79 .
- interconnect patterns 79 parts of the interconnect patterns 79 , except for the overlapped regions CA, and the word lines 78 may be exposed.
- the exposed interconnect patterns 79 and the word lines 78 are etched back, so that buried word line interconnects 79 ′ and buried word lines 78 ′ may be formed.
- the word line interconnects 79 ′ have a unitary structure including a first portion at the same level as the buried word lines 78 ′ and a second portion 79 E that extends vertically from the first portion to contact the gate lines 85 , 87 and 88 in the overlapping regions CA.
- the buried word lines 78 ′ and first portions of the buried interconnects 79 ′ have top surfaces lower than the top surfaces of the adjacent active regions 53 , 54 and 54 P.
- the word line interconnect may be formed from a common conductive layer with the buried word line, such that some embodiments may be viewed as providing a direct or plugless connection of a buried word line to a gate line.
- Upper word line trenches 71 ′ may be formed on the buried word lines 78 ′, and upper interconnect trenches 72 ′ may be formed on the buried interconnects 79 ′.
- the buried word lines 78 ′ may contact respective ones of the buried interconnects 79 ′. In this case, the buried interconnects 79 ′ may be in contact with one of the first gate lines 85 . The buried word lines 78 ′ may be electrically connected with the first gate lines 85 .
- the second gate lines 87 may be formed to cross over the nMOS peripheral circuit active regions 54 .
- the peripheral circuit gate dielectric layer 57 and the patterned peripheral circuit gate conductive layers 58 ′ sequentially stacked between the nMOS peripheral circuit active regions 54 and the second gate lines 87 may be conserved.
- the third gate lines 88 may be formed to cross over the pMOS peripheral circuit active regions 54 P.
- the peripheral circuit gate dielectric layer 57 and the patterned peripheral circuit gate conductive layers 58 P′ sequentially stacked between the pMOS peripheral circuit active regions 54 P and the third gate lines 88 may be conserved.
- the buried interconnects 79 ′ may be formed between the second gate lines 87 and the third gate lines 88 . In this case, one end of the buried interconnects 79 ′ may overlap the second gate lines 87 , and the other end thereof may overlap the third gate lines 88 . Respective ends of the buried interconnects 79 ′ may project toward the second and third gate lines 87 and 88 , respectively.
- low-concentration impurity regions 92 may be formed in the nMOS peripheral circuit active regions 54 on respective sides of the second gate lines 87 .
- Spacers 91 may be formed on sidewalls of the patterned peripheral circuit gate conductive layers 58 ′ and the gate lines 85 , 87 and 88 .
- the spacers 91 may be formed of a silicon oxide layer, a silicon nitride layer, or a combination thereof.
- Source and drain regions 93 , 94 and 95 may be formed in the active regions 53 , 54 and 54 P.
- a first interlayer insulating layer 97 may be formed on the semiconductor substrate 51 .
- the first interlayer insulating layer 97 may be formed of a silicon oxide layer.
- the first interlayer insulating layer 97 is planarized, so that the hard mask pattern 83 may be exposed.
- a CMP process or etch back process may be used for planarization of the first interlayer insulating layer 97 .
- an insulating pattern 91 ′ may be formed on the buried word lines 78 ′ and the buried interconnects 79 ′. More specifically, while the spacers 91 are formed, the insulating pattern 91 ′ may be formed in the upper word line trenches 71 ′ and the upper interconnect trenches 72 ′. Alternatively, the upper word line trenches 71 ′ and the upper interconnect trenches 72 ′ may be filled by the first interlayer insulating layer 97 . Referring to FIGS.
- the first interlayer insulating layer 97 is patterned, so that bit contact holes 101 and 102 exposing the source and drain regions 93 and 94 may be formed.
- Bit plugs 103 and 104 filling the bit contact holes 101 and 102 may be formed.
- Bit lines 105 and 106 contacting the bit plugs 103 and 104 may be formed on the first interlayer insulating layer 97 .
- the bit lines 105 and 106 and the bit plugs 103 and 104 may be formed of a metal layer, a polysilicon layer, or a combination thereof.
- the bit lines 105 and 106 may include first bit lines 105 formed in the cell region 20 and second bit lines 106 formed in the peripheral circuit region 10 .
- a second interlayer insulating layer 110 may be formed on the semiconductor substrate 51 having the bit lines 105 and 106 .
- the second interlayer insulating layer 110 may be a silicon oxide layer.
- Node contact holes 111 penetrating the second interlayer insulating layer 110 and the first interlayer insulating layer 97 and exposing the source and drain regions 95 may be formed.
- Node plugs 113 filling the node contact holes 111 may be formed.
- Storage nodes 115 contacting the node plugs 113 may be formed on the second interlayer insulating layer 110 .
- the storage nodes 115 and the node plugs 113 may be a metal layer, a polysilicon layer, or a combination thereof.
- the device may have an isolation layer 55 disposed on a semiconductor substrate 51 .
- the semiconductor substrate 51 may be a silicon wafer having a peripheral circuit region 10 and a cell region 20 .
- cell active regions 53 may be defined in the cell region 20
- peripheral circuit active regions 54 and 54 P may be defined in the peripheral circuit region 10 .
- the cell active regions 53 may be arranged at predetermined intervals in row and column directions in the cell region 20 .
- the peripheral circuit active regions 54 and 54 P may include nMOS peripheral circuit active regions 54 and pMOS peripheral circuit active regions 54 P.
- the isolation layer 55 may be an insulating layer such as a silicon oxide layer.
- Buried word lines 78 ′ may be disposed in the cell region 20 .
- the buried word lines 78 ′ may be disposed at a lower level than the top surface of the cell active regions 53 .
- Buried interconnects 79 ′ may be disposed in the peripheral circuit region 10 .
- the buried interconnects 79 ′ may be disposed at a lower level than the top surface of the peripheral circuit active regions 54 and 54 p.
- Bottoms and sidewalls of the buried interconnects 79 ′ and the buried word lines 78 ′ may be surrounded by a cell gate dielectric layer 77 .
- the cell gate dielectric layer 77 may be interposed between the buried word lines 78 ′ and the cell active regions 53 .
- the cell gate dielectric layer 77 may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof.
- the buried interconnects 79 ′ may be disposed at the same level as the buried word lines 78 ′. In other words, bottom surfaces of the buried interconnects 79 ′ and the buried word lines 78 ′ may be disposed on the same plane. In addition, the buried interconnects 79 ′ may have the same cross-sectional area as the buried word lines 78 ′. The buried interconnects 79 ′ and the buried word lines 78 ′ may have a smaller width than the resolution limit of a photolithography process. Furthermore, the buried interconnects 79 ′ may be the same material layer as the buried word lines 78 ′. In this case, the buried interconnects 79 ′ and the buried word lines 78 ′ may have a metal layer. The metal layer may be a titanium nitride (TiN) layer.
- TiN titanium nitride
- the gate lines 85 , 87 and 88 may be disposed at a higher level than the buried interconnects 79 ′.
- a hard mask pattern 83 may be provided on the gate lines 85 , 87 and 88 .
- the hard mask pattern 83 may be a nitride layer such as a silicon nitride layer.
- the gate lines 85 , 87 and 88 may include first gate lines 85 , second gate lines 87 , and third gate lines 88 .
- the gate lines 85 , 87 and 88 may be a metal layer such as a tungsten (W) layer or a tungsten silicide (WSi) layer.
- the gate lines 85 , 87 and 88 may be disposed at a higher level than the peripheral circuit active regions 54 and 54 P.
- the gate lines 85 , 87 and 88 may have overlapping regions CA overlapping the buried interconnects 79 ′. In the overlapping regions CA, the buried interconnects 79 ′ may contact the gate lines 85 , 87 and 88 . The buried interconnects 79 ′ may project toward the gate lines 85 , 87 and 88 in the overlapping regions CA. In other words, the buried interconnects 79 ′ may have projections 79 E projecting upward.
- the buried word lines 78 ′ may contact the buried interconnects 79 ′ corresponding thereto, respectively.
- the buried interconnects 79 ′ may be in contact with one of the first gate lines 85 .
- the overlapping regions CA may be provided between the buried interconnects 79 ′ and the first gate lines 85 .
- the buried interconnects 79 ′ may have the projections 79 E projecting toward the first gate lines 85 . Consequently, the buried word lines 78 ′ may be electrically connected with the first gate lines 85 .
- the second gate lines 87 may be disposed to cross over the nMOS peripheral circuit active regions 54 .
- the third gate lines 88 may be disposed to cross over the pMOS peripheral circuit active regions 54 P.
- the buried interconnects 79 ′ may be disposed between the second gate lines 87 and the third gate lines 88 . In this case, one end of the buried interconnects 79 ′ may overlap the second gate lines 87 , and the other end thereof may overlap the third gate lines 88 . In other words, the projections 79 E projecting toward the second and third gate lines 87 and 88 may be provided at the both ends of the buried interconnects 79 ′.
- a peripheral circuit gate dielectric layer 57 and patterned peripheral circuit gate conductive layers 58 ′ may be sequentially stacked between the nMOS peripheral circuit active regions 54 and the second gate lines 87 .
- the peripheral circuit gate dielectric layer 57 may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof.
- the patterned peripheral circuit gate conductive layers 58 ′ may be a polysilicon layer.
- peripheral circuit gate dielectric layer 57 and the patterned peripheral circuit gate conductive layers 58 P′ may be sequentially stacked. Also, between the isolation layer 55 and the gate lines 85 , 87 and 88 , the peripheral circuit gate dielectric layer 57 and the patterned peripheral circuit gate conductive layers 58 ′ and 58 P′ may be sequentially stacked.
- Spacers 91 may be disposed on sidewalls of the patterned peripheral circuit gate conductive layers 58 ′ and the second gate lines 87 .
- the spacers 91 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
- Low-concentration impurity regions 92 may be disposed in the nMOS peripheral circuit active regions 54 under the spacers 91 .
- Source and drain regions 93 , 94 and 95 may be disposed in the active regions 53 , 54 and 54 P adjacent to both sides of the buried word lines 78 ′ and the gate lines 87 and 88 .
- An insulating pattern 91 ′ may be disposed on the buried interconnects 79 ′ and the buried word lines 78 ′.
- the bottom surface of the insulating pattern 91 ′ may be disposed at a lower level than the top surfaces of the adjacent active regions 53 , 54 and 54 P.
- the insulating pattern 91 ′ may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
- a first interlayer insulating layer 97 may be provided on the semiconductor substrate 51 having the insulating pattern 91 ′.
- the first interlayer insulating layer 97 may be an insulating layer such as a silicon oxide layer.
- Bit lines 105 and 106 may be disposed on the first interlayer insulating layer 97 .
- the bit lines 105 and 106 may cross over the buried interconnects 79 ′ and the buried word lines 78 ′.
- the bit lines 105 and 106 may include first bit lines 105 disposed in the cell region 20 and second bit lines 106 disposed in the peripheral circuit region 10 .
- the bit lines 105 and 106 may be connected to the source and drain regions 93 and 94 through bit plugs 103 and 104 penetrating the first interlayer insulating layer 97 .
- the bit lines 105 and 106 and the bit plugs 103 and 104 may be a metal layer, a polysilicon layer, or a combination thereof.
- the semiconductor substrate 51 having the bit lines 105 and 106 may be covered by a second interlayer insulating layer 110 .
- the second interlayer insulating layer 110 may be an insulating layer, such as a silicon oxide layer.
- Storage nodes 115 may be disposed on the second interlayer insulating layer 110 .
- the storage nodes 115 may be connected to the source and drain regions 95 through node plugs 113 sequentially penetrating the second interlayer insulating layer 110 and the first interlayer insulating layer 97 .
- the storage nodes 115 and the node plugs 113 may be a metal layer, a polysilicon layer, or a combination thereof.
- the buried interconnects 79 ′ may be disposed at a lower level than the top surfaces of the active regions 53 , 54 and 54 P.
- arrangement of the bit lines 105 and 106 disposed on the insulating pattern 91 ′ is not disturbed.
- a signal transmission path can be shortened in comparison with a conventional bypass interconnect method using a bit line layer or a metal interconnect layer. Consequently, a semiconductor device having excellent electrical characteristics and advantageous to high integration can be embodied.
- FIG. 15 is a plan view of a semiconductor device having buried interconnects according to the second exemplary embodiments of the present invention.
- FIGS. 16 to 21 are composites of cross-sectional views illustrating operations for fabricating the semiconductor device of FIG. 15 , in which a cross-section 5 is taken along line V-V′ of FIG. 15 , a cross-section 6 is taken along line VI-VI′ of FIG. 15 , and a cross-section 7 is taken along line VII-VII′ of FIG. 15 .
- an isolation layer 155 defining active regions 153 and 153 P in a peripheral circuit region may be formed in a semiconductor substrate 151 .
- the semiconductor substrate 151 may be a silicon wafer having an nMOS region 10 N and a pMOS region 10 P.
- the active regions 153 and 153 P may include nMOS peripheral circuit active regions 153 and pMOS peripheral circuit active regions 153 P.
- the nMOS peripheral circuit active regions 153 may be arranged in the nMOS region 10 N, and the pMOS peripheral circuit active regions 153 P may be arranged in the pMOS region 10 P.
- a peripheral circuit gate dielectric layer 157 may be formed on the active regions 153 and 153 P.
- a peripheral circuit gate conductive layer 158 and a sacrificial oxide layer 159 may be sequentially stacked on the semiconductor substrate 151 having the peripheral circuit gate dielectric layer 157 .
- a first sacrificial mask pattern 161 may be formed on the peripheral circuit gate conductive layer 158 .
- the first sacrificial mask pattern 161 may be formed of a material layer having an etch selectivity with respect to the peripheral circuit gate conductive layer 158 , the active regions 153 and 153 P, and the isolation layer 155 .
- a sacrificial spacer 165 may be formed on sidewalls of the first sacrificial mask pattern 161 .
- the sacrificial spacer 165 may be formed of a material layer having an etch selectivity with respect to the first sacrificial mask pattern 161 .
- the sacrificial spacer 165 may be formed of a polysilicon layer.
- the sacrificial spacer 165 may be formed to have a smaller thickness than the resolution limit of a photolithography process. Subsequently, a patterning process for separating the sacrificial spacer 165 may be performed. Specifically, a photoresist pattern 167 may be formed on the semiconductor substrate 151 having the sacrificial spacer 165 . The photoresist pattern 167 may have a first opening 167 P partially exposing the sacrificial spacer 165 .
- the sacrificial spacer 165 is etched using the photoresist pattern 167 as an etching mask, so that a second opening 165 P exposing the sacrificial oxide layer 159 may be formed.
- the second opening 165 P may be selectively formed at both ends of the sacrificial spacer 165 .
- the photoresist pattern 167 may be removed.
- a second sacrificial mask pattern 169 filling a gap between the sacrificial spacers 165 and the second opening 165 P may be formed.
- the sacrificial spacer 165 may be removed.
- An isotropic etching having an etch selectivity between the sacrificial mask patterns 161 and 169 and the sacrificial spacer 165 may be used for removal of the sacrificial spacer 165 . Consequently, the sacrificial mask patterns 161 and 169 may remain on the semiconductor substrate 151 .
- the sacrificial oxide layer 159 , the peripheral circuit gate conductive layer 158 , the peripheral circuit gate dielectric layer 157 , and the isolation layer 155 are anisotropically etched using the sacrificial mask patterns 161 and 169 as etching masks, so that interconnect trenches 172 may be formed.
- the size of the interconnect trenches 172 may be determined by the sacrificial spacer 165 .
- the interconnect trenches 172 may also be formed to have a smaller width than the resolution limit of a photolithography process.
- the sacrificial mask patterns 161 and 169 may be removed.
- a cell gate dielectric layer 177 may be formed on an inner wall of the interconnect trenches 172 .
- interconnect patterns 179 are formed in the interconnect trenches 172 .
- the sacrificial oxide layer 159 is removed, so that the peripheral circuit gate conductive layer 158 may be exposed.
- the peripheral circuit gate conductive layer 158 and the interconnect patterns 179 may be exposed on substantially the same plane.
- the interconnect patterns 179 may be formed at a lower level than the top surface of the peripheral circuit gate conductive layer 158 .
- the sacrificial mask patterns 161 and 169 may be removed after the cell gate dielectric layer 177 and the interconnect patterns 179 are formed. Subsequently, impurity ions may be implanted into the peripheral circuit gate conductive layer 158 .
- impurity ions may be implanted into the peripheral circuit gate conductive layer 158 in the nMOS region, and p-type impurity ions may be implanted into a peripheral circuit gate conductive layer 158 P in the pMOS region.
- An upper conductive layer 181 covering the peripheral circuit gate conductive layers 158 and 158 P and the interconnect patterns 179 may be formed.
- a hard mask pattern 183 may be formed on the upper conductive layer 181 .
- the upper conductive layer 181 and the peripheral circuit gate conductive layers 158 and 158 P are etched using the hard mask pattern 183 as an etching mask, so that gate lines 187 and 188 may be formed.
- the gate lines 187 and 188 may include first gate lines 187 and second gate lines 188 .
- the first gate lines 187 may be arranged in the nMOS region 10 N, and the second gate lines 188 may be arranged in the pMOS region 10 P.
- Patterned peripheral circuit gate conductive layers 158 ′ and 158 P′ may remain under the gate lines 187 and 188 .
- the gate lines 187 and 188 may have regions CA overlapping the interconnect patterns 179 .
- interconnect patterns 179 may be exposed.
- the exposed interconnect patterns 179 are etched back, so that buried interconnects 179 ′ may be formed.
- the buried interconnects 179 ′ may be formed at a lower level than the top surfaces of the adjacent active regions 153 and 153 P.
- the interconnect patterns 179 may be conserved under the gate lines 187 and 188 .
- the buried interconnects 179 ′ may have projections 179 E projecting upward.
- the buried interconnects 179 ′ may project toward the gate lines 187 and 188 in the overlapping regions CA.
- the buried interconnects 179 ′ may contact the gate lines 187 and 188 .
- the first gate lines 187 may be formed to cross over the nMOS peripheral circuit active regions 153 .
- the peripheral circuit gate dielectric layer 157 and the patterned peripheral circuit gate conductive layers 158 ′ sequentially stacked between the nMOS peripheral circuit active regions 153 and the first gate lines 187 may be conserved.
- the second gate lines 188 may be formed to cross over the pMOS peripheral circuit active regions 153 P.
- the peripheral circuit gate dielectric layer 157 and the patterned peripheral circuit gate conductive layers 158 P′ sequentially stacked between the pMOS peripheral circuit active regions 153 P and the second gate lines 188 may be conserved.
- the buried interconnects 179 ′ may be formed between the first gate lines 187 and the second gate lines 188 .
- one end of the buried interconnects 179 ′ may overlap the first gate lines 187
- the other end thereof may overlap the second gate lines 188 .
- the ends of the buried interconnects 179 ′ may project toward the first and second gate lines 187 and 188 , respectively.
- An insulating pattern 197 may be formed on the buried interconnects 179 ′.
- the insulating pattern 197 may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. Consequently, the semiconductor substrate 151 may be covered by the hard mask pattern 183 and the insulating pattern 197 .
- the first gate lines 187 may be disposed in the nMOS region 10 N, and the second gate lines 188 may be disposed in the pMOS region 10 P.
- the first gate lines 187 may be electrically connected with the second gate lines 188 by the buried interconnects 179 ′.
- FIG. 22 is a plan view of a semiconductor device having buried interconnects according to the third exemplary embodiments of the present invention.
- FIG. 23 is a composite of cross-sectional views illustrating operations for fabricating the semiconductor device of FIG. 22 , in which a cross-section 8 is taken along line VIII-VIII′ of FIG. 22 , and a cross-section 9 is taken along line IX-IX′ of FIG. 22 .
- the patterning process for separating the sacrificial spacer ( 165 of FIG. 17 ) as described with reference to FIGS. 16 and 17 is omitted in the method of fabricating a semiconductor device according to the third exemplary embodiments of the present invention. More specifically, the second opening ( 165 P of FIG. 17 ) formed at both ends of the sacrificial spacer ( 165 of FIG. 17 ) is not formed.
- a semiconductor substrate according to the third exemplary embodiments of the present invention may have an isolation layer 255 disposed on a semiconductor substrate 251 .
- the semiconductor substrate 251 may be a silicon wafer having an nMOS region 10 N and a pMOS region 10 P.
- nMOS peripheral circuit active regions 253 may be defined in the nMOS region 10 N
- pMOS peripheral circuit active regions 253 P may be defined in the pMOS region 10 P.
- Buried interconnects 279 may be disposed in interconnect trenches formed in the isolation layer 255 .
- the buried interconnects 279 may be disposed at a lower level than the top surface of the peripheral circuit active regions 253 and 253 P.
- the bottom and sidewalls of the buried interconnects 279 may be surrounded by a cell gate dielectric layer 277 .
- Gate lines 287 and 288 may be disposed at a higher level than the buried interconnects 279 .
- a hard mask pattern 283 may be provided on the gate lines 287 and 288 .
- the gate lines 287 and 288 may include first gate lines 287 and second gate lines 288 .
- the gate lines 287 and 288 may be disposed at a higher level than the peripheral circuit active regions 253 and 253 P.
- the gate lines 287 and 288 may have regions CA overlapping the buried interconnects 279 .
- the buried interconnects 279 may contact the gate lines 287 and 288 .
- the buried interconnects 279 may project toward the gate lines 287 and 288 in the overlapping regions CA. In other words, the buried interconnects 279 may have projections 279 E projecting upward.
- the first gate lines 287 may be disposed to cross over the nMOS peripheral circuit active regions 253 .
- the second gate lines 288 may be disposed to cross over the pMOS peripheral circuit active regions 253 P.
- a pair of the buried interconnects 279 may be disposed between the first gate lines 287 and the second gate lines 288 . In this case, one end of the buried interconnects 279 may overlap the first gate lines 287 , and the other end thereof may overlap the second gate lines 288 . In addition, one pair of the buried interconnects 279 parallel to each other may be in contact with each other in the overlapping regions CA.
- a peripheral circuit gate dielectric layer 257 and patterned peripheral circuit gate conductive layers 258 may be sequentially stacked between the nMOS peripheral circuit active regions 253 and the first gate lines 287 .
- the peripheral circuit gate dielectric layer 257 and patterned peripheral circuit gate conductive layers 258 P may be sequentially stacked between the pMOS peripheral circuit active regions 253 P and the second gate lines 288 . Also, the peripheral circuit gate dielectric layer 257 and the patterned peripheral circuit gate conductive layers 258 and 258 P may be sequentially stacked between the isolation layer 255 and the gate lines 287 and 288 .
- An insulating pattern 297 may be disposed on the buried interconnects 279 .
- the bottom surface of the insulating pattern 297 may be disposed at a lower level than the top surfaces of the adjacent active regions 253 and 253 P. Consequently, the semiconductor substrate 251 may be covered by the hard mask pattern 283 and the insulating pattern 297 .
- the first gate lines 287 may be disposed in the nMOS region 10 N, and the second gate lines 288 may be disposed in the pMOS region 10 P.
- the first gate lines 287 may be electrically connected with the second gate lines 288 by one pair of the buried interconnects 279 .
- a semiconductor device having buried interconnects and methods of fabricating the same according to fourth exemplary embodiments of the present invention will be described with reference to FIG. 24 .
- a buried interconnect 379 is formed, and then gate lines 387 and 388 are formed.
- the semiconductor device may have an isolation layer 355 disposed on a semiconductor substrate 351 .
- the semiconductor substrate 351 may be a silicon wafer having an nMOS region and a pMOS region.
- an nMOS peripheral circuit active region 353 may be defined in the nMOS region
- a pMOS peripheral circuit active regions 353 P may be defined in the pMOS region.
- the buried interconnect 379 may be disposed in an interconnect trench formed in the isolation layer 355 .
- the buried interconnect 379 may be disposed at a lower level than the top surfaces of the peripheral circuit active regions 353 and 353 P.
- the bottom and sidewalls of the buried interconnect 379 may be surrounded by a cell gate dielectric layer 377 .
- the gate lines 387 and 388 may be disposed at a higher level than the buried interconnect 379 .
- a hard mask pattern 383 may be provided on the gate lines 387 and 388 .
- the gate lines 387 and 388 may include a first gate line 387 and a second gate line 388 .
- the gate lines 387 and 388 may be disposed at a higher level than the peripheral circuit active regions 353 and 353 P.
- the gate lines 387 and 388 may have regions CA overlapping the buried interconnect 379 . In the overlapping regions CA, the buried interconnect 379 may contact the gate lines 387 and 388 . The gate lines 387 and 388 may project toward the buried interconnect 379 in the overlapping regions CA. In other words, projections 387 E and 388 E projecting downward may be provided to the gate lines 387 and 388 .
- the first gate line 387 may be disposed cross over the nMOS peripheral circuit active regions 353
- the second gate line 388 may be disposed cross over the pMOS peripheral circuit active regions 353 P.
- the buried interconnect 379 may be disposed between the first gate line 387 and the second gate line 388 . In this case, one end of the buried interconnect 379 may overlap the first gate line 387 , and the other end thereof may overlap the second gate line 388 .
- a peripheral circuit gate dielectric layer 357 and patterned peripheral circuit gate conductive layers 358 may be sequentially stacked between the nMOS peripheral circuit active regions 353 and the first gate line 387 .
- the peripheral circuit gate dielectric layer 357 and a patterned peripheral circuit gate conductive layer 358 P may be sequentially stacked between the pMOS peripheral circuit active regions 353 P and the second gate line 388 .
- the peripheral circuit gate dielectric layer 357 and the patterned peripheral circuit gate conductive layers 358 and 358 P may be sequentially stacked between the isolation layer 355 and the gate lines 387 and 388 .
- An insulating pattern 397 may be disposed on the buried interconnect 379 .
- the bottom surface of the insulating pattern 397 may be disposed at a lower level than the top surfaces of the adjacent active regions 353 and 353 P. Consequently, the semiconductor substrate 351 may be covered by the hard mask pattern 383 and the insulating pattern 397 .
- a buried word line is formed in a cell region while a buried interconnect is formed in a peripheral circuit region.
- the buried interconnect and the buried word line may be formed at a lower level than the top surface of an adjacent active region.
- Gate lines are disposed at a higher level than the buried interconnect.
- the gate lines have regions overlapping the buried interconnect. In the overlapping regions, the buried interconnect contacts the gate lines.
- An insulating pattern is provided on the buried interconnect and the buried word line.
- One of the gate lines may be electrically connected to the other gate line or the buried word line through the buried interconnect. Therefore, a signal transmission path can be shortened in comparison with a conventional interconnect method.
- bit lines may be disposed on the insulating pattern.
- the buried interconnect is provided under the insulating pattern and thus does not disturb arrangement of the bit lines.
Abstract
A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
Description
- This application claims priority to Korean Patent Application No. 2006-0080700, filed Aug. 24, 2006, the contents of which are hereby incorporated herein by reference in their entirety.
- The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having buried word lines and methods of fabricating the same.
- Integrated circuits include discrete devices, such as transistors, and interconnects for electrically connecting the discrete devices to each other. A typical transistor has a source region, a drain region and a gate electrode, which are disposed on a semiconductor substrate. The source and drain regions are spaced apart from each other in an active region of the semiconductor substrate. The gate electrode is disposed between the source region and the drain region and insulated from the active region.
- Recently, as semiconductor devices have become more highly integrated, techniques have been developed that involve burying a gate electrode in a gate trench crossing the active region. A memory device, such as a dynamic random access memory (DRAM), typically has a plurality of cell transistors disposed in a cell array region and p-channel metal oxide semiconductor (pMOS) transistors and n-channel metal oxide semiconductor (nMOS) transistors disposed in a peripheral circuit region. The cell transistors are disposed at predetermined intervals in the cell array region. Gate electrodes of the cell transistors are connected to a word line.
- A conventional technique for forming a buried word line involves burying the word line at a lower level than a top surface of the active region. For example, a semiconductor device having a buried word line is disclosed in U.S. Pat. No. 6,770,535 B2 entitled to “Semiconductor Integrated Circuit Device and Process for Manufacturing the Same” by Yamada et al.
- Planar transistors such as high-voltage transistors may be disposed in the peripheral circuit region. Gate electrodes of the planar transistors may be disposed at a higher level than the active region. In addition, a plurality of gate lines may be formed at the same level as the gate electrodes.
- However, the buried word line typically must be electrically connected to a gate line of the peripheral circuit region corresponding thereto. A technique for electrically connecting the buried word line with the gate line using a bypass interconnect and a contact plug has been developed. According to the technique using a bypass interconnect and a contact plug, a first interlayer insulating layer covering the buried word line and the gate line is formed, the bypass interconnect is disposed on the first interlayer insulating layer, and the contact plug penetrating the first interlayer insulating layer is used.
- Other interconnects crossing between the buried word line and the gate line may be disposed on the first interlayer insulating layer. In order to electrically connect the buried word line with the gate line, a second interlayer insulating layer is formed on the first interlayer insulating layer, the bypass interconnect is disposed on the second interlayer insulating layer, and a contact plug penetrating the first and second interlayer insulating layers is used. The contact plug may difficult to form, and a signal transmission path may be lengthened. Consequently, a technique using a bypass interconnect and a contact plug may not provide an advantageous structure for high integration, and may degrade electrical characteristics and reliability.
- In some embodiments of the present invention, a semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A unitary word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
- The second portion of the word line interconnect may extend vertically from the first portion of the word line interconnect to contact a bottom surface of the gate line. The first portion of the word line interconnect may be laterally offset with respect to the buried word line. The top surface of the first portion of the word line interconnect may be at substantially the same level at the top surface of the buried word line and the first portion of the word line interconnect may have substantially the same cross-sectional area as the buried word line. An insulating pattern may be disposed on the first portion of the word line interconnect and the buried word line. A bottom surface of the insulating pattern may be lower than the top surfaces of the cell active regions. A bit line may be disposed on the insulating pattern and may cross the buried word line.
- In further embodiments, the semiconductor device may further include second and third spaced-apart gate lines on the substrate in the peripheral circuit region on respective sides of the bit line. A buried peripheral circuit interconnect may be disposed in the substrate in the peripheral circuit region beneath the bit line, and may connect the first and second gate lines and have a portion beneath the bit line that has a top surface at substantially the same level as the top surface of the buried word line.
- Further embodiments of the present invention provide methods of fabricating a semiconductor device. An isolation region is formed in a semiconductor substrate, defining cell active regions in a cell region and peripheral circuit active regions in a peripheral circuit region. A word line trench is formed in the substrate in the cell region and an adjoining word line interconnect trench is formed in the peripheral circuit region. A word line pattern is formed in the word line trench and a word line interconnect pattern is formed in the word line interconnect trench. A gate line is formed on the substrate in the peripheral circuit region, the gate line having an end portion that overlaps the word line interconnect pattern. The word line pattern and the word line interconnect pattern are etched back to form a word line in the word line trench having a top surface lower than a top surface of the cell active regions and a word line interconnect in the word line interconnect trench having a first portion connected to the word line and a top surface lower than the top surfaces of the cell active regions and a second portion extending vertically from the first portion to contact a bottom surface of the gate line. An insulating pattern is formed on the buried word line and the first portion of the word line interconnect.
- In some embodiments, forming a word line trench includes forming a first sacrificial mask pattern on the substrate having the isolation layer, forming sacrificial spacers on sidewalls of the first sacrificial mask pattern, forming a second sacrificial mask pattern filling a gap between the sacrificial spacers, removing the sacrificial spacers and etching the isolation layer and the semiconductor substrate using the first and second sacrificial mask patterns as etching masks to form the word line trench and the word line interconnect trench. Forming a first sacrificial mask pattern on the substrate may be preceded by forming a peripheral circuit gate dielectric layer on the peripheral circuit active regions, forming a peripheral circuit gate conductive layer on the peripheral circuit gate dielectric layer and forming a sacrificial oxide layer on the peripheral circuit gate conductive layer. In some embodiments, forming a gate line includes etching the first and second sacrificial mask patterns and the sacrificial oxide layer to expose the peripheral circuit gate conductive layer, forming a metal layer covering the peripheral circuit gate conductive layer, the word line pattern, and the word line interconnect pattern and patterning the metal layer and the peripheral circuit gate conductive layer to form the gate line. The word line pattern and the word line interconnect pattern may be formed from a common metal layer.
- In further embodiments, a bit line is formed on the insulating pattern and crossing the buried word line. A peripheral circuit interconnect trench may be formed in the substrate in the peripheral circuit region concurrent with forming the word line trench in the substrate in the cell region and the adjoining word line interconnect trench in the peripheral circuit region. A peripheral circuit interconnect pattern may be formed in the peripheral circuit interconnect trench concurrent with forming the word line pattern in the word line trench and the word line interconnect pattern in the word line interconnect trench. Second and third spaced apart gate lines may be formed in the peripheral circuit region on respective sides of the bit line concurrent with forming the first gate line on the substrate in the peripheral circuit region, the first and second gate lines overlapping and contacting the peripheral circuit interconnect pattern. The peripheral circuit interconnect pattern may be etched back concurrent with etching back the word line pattern and the word line interconnect pattern to form a peripheral circuit interconnect having a first portion with a top surface that is lower than a top surface of the peripheral circuit active regions and second portions that extend vertically from the first portion to contact bottom surfaces of respective ones of the second and third gate lines. An insulating pattern may be formed on the first portion of the peripheral circuit interconnect concurrent with forming the insulating pattern on the buried word line and the first portion of the word line interconnect.
- Some embodiments of the invention provides semiconductor devices including interconnects that may be advantageous to high integration and may have excellent electrical characteristics.
- Other embodiments of the invention provide methods of fabricating a semiconductor device including interconnects that may be advantageous to high integration and may have excellent electrical characteristics.
- In some embodiments, the present invention provides semiconductor devices having buried interconnects. A device has an isolation layer disposed on a semiconductor substrate. By the isolation layer, cell active regions are defined in a cell region, and peripheral circuit active regions are defined in a peripheral circuit region. A buried word line is disposed in the cell region. The buried word line is disposed at a lower level than the top surface of the cell active region. A buried interconnect is disposed in the peripheral circuit region. The buried interconnect is disposed at a lower level than the top surface of the peripheral circuit active regions. Gate lines are disposed at a higher level than the buried interconnect. The gate lines have regions overlapping the buried interconnect. In the overlapping regions, the buried interconnect contacts the gate lines.
- In some embodiments of the present invention, the buried interconnect may project toward the gate lines in the overlapping region.
- In other embodiments, the gate line may project toward the buried interconnect in the overlapping region.
- In still other embodiments, the buried interconnect may be disposed at the same level as the buried word line. In addition, the buried interconnect may have the same cross-sectional area as the buried word line. Furthermore, the buried interconnect may be the same material layer as the buried word line. In this case, the buried interconnect and the buried word line may have a metal layer. The metal layer may be a titanium nitride (TiN) layer.
- In yet other embodiments, the buried interconnect and the buried word line may be in contact with each other.
- In yet other embodiments, the buried interconnect may have two overlapping regions spaced apart from each other. One of the gate lines passing through an n-channel metal oxide semiconductor (nMOS) region may contact one part of the buried interconnect in one of the overlapping regions. The other one of the gate lines passing through a p-channel metal oxide semiconductor (pMOS) region may contact the other part of the buried interconnect in the other of the overlapping regions.
- In yet other embodiments, the gate lines may be disposed at a higher level than the peripheral circuit active regions.
- In yet other embodiments, an insulating pattern may be disposed on the buried interconnect and buried word line. The bottom surface of the insulating pattern may be disposed at a lower level than the top surfaces of the adjacent active regions.
- In yet other embodiments, a bit line crossing the buried interconnect may be disposed on the insulating pattern.
- In other embodiments, the present invention provides methods of fabricating semiconductor devices. A method may include: providing a semiconductor substrate having a cell region and a peripheral circuit region; forming an isolation layer defining cell active regions in the cell region and peripheral circuit active regions in the peripheral circuit region; etching the cell active regions and the isolation layer, and simultaneously forming word line trenches in the cell region and interconnect trenches in the peripheral circuit region; simultaneously forming word lines in the word line trenches and interconnect patterns in the interconnect trenches; forming gate lines on the semiconductor substrate having the interconnect patterns, the gate lines having regions overlapping the interconnect patterns; etching-back the word lines and the interconnect patterns and forming buried word lines and buried interconnects, the buried interconnects contacting the gate lines in the overlapping regions; and forming an insulating pattern on the buried word lines and the buried interconnects.
- In some embodiments of the present invention, forming the word line trenches and the interconnect trenches may include: forming a first sacrificial mask pattern on the substrate having the isolation layer; forming sacrificial spacers on sidewalls of the first sacrificial mask pattern; forming a second sacrificial mask pattern filling a gap between the sacrificial spacers; removing the sacrificial spacers; and etching the isolation layer and the cell active layers using the first and second sacrificial mask patterns as etching masks. The first and second mask patterns may be formed of a material layer having an etch selectivity with respect to the active regions and the isolation layer. The sacrificial spacers may be formed of a polysilicon layer. The word line trenches and the interconnect trenches may be formed to have a smaller width than the resolution limit of a photolithography process.
- In other embodiments, before the first sacrificial mask pattern is formed, a peripheral circuit gate dielectric layer may be formed on the peripheral circuit active regions. A peripheral circuit gate conductive layer may be formed on the semiconductor substrate having the peripheral circuit gate dielectric layer. A sacrificial oxide layer may be formed on the peripheral circuit gate conductive layer.
- In still other embodiments, forming the gate lines may include: while the word lines and the interconnect patterns are formed, etching the sacrificial mask patterns and the sacrificial oxide layer and exposing the peripheral circuit gate conductive layer; forming a metal layer covering the peripheral circuit gate conductive layer, the word lines, and the interconnect patterns; and continuously patterning the metal layer and the peripheral circuit gate conductive layer.
- In yet other embodiments, the word lines and the interconnect patterns may be formed of a metal layer.
- In yet other embodiments, the word line trenches may be formed to be connected to the interconnect trenches corresponding thereto, respectively.
- In yet other embodiments, the bottom surface of the insulating pattern may be formed at a lower level than the top surfaces of the adjacent active regions.
- In yet other embodiments, a bit line disposed on the insulating pattern and crossing the buried interconnects may be formed.
- In additional embodiments, the present invention provides additional methods of fabricating a semiconductor device. A method may include: providing a semiconductor substrate having a cell region and a peripheral circuit region; forming an isolation layer defining cell active regions in the cell region and peripheral circuit active regions in the peripheral circuit region; etching the cell active regions and the isolation layer, and simultaneously forming word line trenches in the cell region and interconnect trenches in the peripheral circuit region; simultaneously forming buried word lines in the word line trenches and buried interconnects in the interconnect trenches; forming gate lines on the semiconductor substrate having the buried interconnects, the gate lines having regions overlapping the buried interconnects, the buried interconnects contacting the gate lines in the overlapping regions; and forming an insulating pattern on the buried word lines and the buried interconnects disposed at a lower level than top surfaces of the adjacent active regions.
- The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of exemplary embodiments of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
-
FIG. 1 is a plan view of a semiconductor device having buried interconnects according to first exemplary embodiments of the present invention. -
FIGS. 2 through 14 are composites of cross-sectional views illustrating operations for forming the semiconductor device ofFIG. 1 . -
FIG. 15 is a plan view of a semiconductor device having buried interconnects according to second exemplary embodiments of the present invention. -
FIGS. 16 to 21 are composites of cross-sectional views illustrating operations for forming the semiconductor device ofFIG. 15 . -
FIG. 22 is a plan view of a semiconductor device having buried interconnects according to third exemplary embodiments of the present invention. -
FIG. 23 is a composite of cross-sectional views illustrating operations for forming the semiconductor device ofFIG. 23 . -
FIG. 24 is a plan view of a semiconductor device having buried interconnects according to fourth exemplary embodiments of the present invention. - The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set fourth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
- It will be understood that when an element or layer is referred to as being “on,” “connected to” and/or “coupled to” another element or layer, the element or layer may be directly on, connected and/or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” and/or “directly coupled to” another element or layer, no intervening elements or layers are present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will also be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used merely as a convenience to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. For example, a first element, component, region, layer and/or section could be termed a second element, component, region, layer and/or section without departing from the teachings of the present invention.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, may be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, “height” refers to a direction that is generally orthogonal to the faces of a substrate.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit of the invention. As used herein, the singular terms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprising,” “includes,” “including,” “have”, “having” and variants thereof specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence and/or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Embodiments of the present invention may be described with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations, as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result from, e.g., manufacturing. For example, a region illustrated as a rectangle may have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and are not intended to limit the scope of the present invention. Like reference numerals refer to like elements throughout.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- Semiconductor devices and methods of fabricating the same according to first exemplary embodiments of the present invention will now be described with reference to
FIGS. 1 to 14 .FIG. 1 is a plan view of a semiconductor device.FIGS. 2 to 14 are composites of cross-sectional views illustrating methods of fabricating the semiconductor device ofFIG. 1 , in which across-section 1 is taken along line I-I′ ofFIG. 1 , across-section 2 is taken along line II-II′ ofFIG. 1 , across-section 3 is taken along line III-III′ ofFIG. 1 , and across-section 4 is taken along line IV-IV′ ofFIG. 1 . - Referring to
FIGS. 1 and 2 , anisolation layer 55 definingactive regions semiconductor substrate 51. Theisolation layer 55 may be formed by a trench isolation technique. Theisolation layer 55 may be formed of an insulating layer, such as a silicon oxide layer. - The
semiconductor substrate 51 may be a silicon wafer having aperipheral circuit region 10 and acell region 20. Theactive regions active regions 53, n-channel metal oxide semiconductor (nMOS) peripheral circuitactive regions 54, and a p-channel metal oxide semiconductor (pMOS) peripheral circuitactive regions 54P. In thecell region 20, the cellactive regions 53 may be arranged at predetermined intervals in row and column directions. The nMOS peripheral circuitactive regions 54 and the pMOS peripheral circuitactive regions 54P may be disposed in theperipheral circuit region 10. - Subsequently, a process of implanting well ions into the
active regions active regions 53 and the nMOS peripheral circuitactive regions 54 may be performed, and also, the process of implanting n-type impurity ions into the pMOS peripheral circuitactive regions 54P may be performed. In this case, nMOS transistors may be formed in the cellactive regions 53 and the nMOS peripheral circuitactive regions 54, and pMOS transistors may be formed in the pMOS peripheral circuitactive regions 54P. Referring toFIGS. 1 and 3 , a peripheral circuitgate dielectric layer 57 may be formed on theactive regions conductive layer 58, asacrificial oxide layer 59, and a firstsacrificial mask layer 61 may be sequentially stacked on thesemiconductor substrate 51 having the peripheral circuitgate dielectric layer 57. - The peripheral circuit
gate dielectric layer 57 may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The peripheral circuitgate dielectric layer 57 may be formed to cover the surfaces of theactive regions conductive layer 58 may be a conductive layer, such as an undoped polysilicon layer. The peripheral circuit gateconductive layer 58 may cover the top surface of thesemiconductor substrate 51 having the peripheral circuitgate dielectric layer 57. - The
sacrificial oxide layer 59 may be a silicon oxide layer, such as a thermal oxide layer. Thesacrificial oxide layer 59 may cover the top surface of the peripheral circuit gateconductive layer 58. - The first
sacrificial mask layer 61 may be a material layer having an etch selectivity with respect to the peripheral circuit gateconductive layer 58, theactive regions isolation layer 55. The firstsacrificial mask layer 61 may be a nitride layer such as a silicon nitride layer. - Referring to
FIGS. 1 and 4 , the firstsacrificial mask layer 61 is patterned to form a firstsacrificial mask pattern 61′ havingfirst openings 61P. Thesacrificial oxide layer 59 may be exposed at the bottom of thefirst openings 61P. - The
first openings 61P may be formed in a groove shape in a column direction in thecell region 20. Also, thefirst openings 61P may be formed parallel to each other. In addition, thefirst openings 61P may be formed to cross over the cellactive regions 53. Furthermore, thefirst openings 61P may extend from thecell region 20 to theperipheral circuit region 10. - The
first openings 61P may be formed in theperipheral circuit region 10 as well. In this case, thefirst openings 61P may be formed on theisolation layer 55. Referring toFIGS. 1 and 5 ,sacrificial spacers 65 may be formed on sidewalls of the firstsacrificial mask pattern 61′. Thesacrificial spacers 65 may be formed from a material layer having an etch selectivity with respect to the firstsacrificial mask pattern 61′. Thesacrificial spacers 65 may be polysilicon. - For example, a polysilicon layer covering inner walls of the
first openings 61P and the top surface of the firstsacrificial mask pattern 61′ may be formed. The polysilicon layer may be anisotropically etched, so that thesacrificial oxide layer 59 may be exposed. In this case, the polysilicon layer may remain on the sidewalls of thefirst openings 61P. Here, the thickness of thesacrificial spacers 65 can be adjusted by controlling deposition conditions of the polysilicon layer. Thesacrificial spacers 65 may have a smaller thickness than the resolution limit of a photolithography process. Alternatively, the anisotropic etching process may be omitted. - Referring to
FIGS. 1 and 6 , a patterning process for separating asacrificial spacer 65 may be performed. Specifically, aphotoresist pattern 67 may be formed on thesemiconductor substrate 51 having thesacrificial spacers 65. One of thesacrificial spacers 65 is partially etched using thephotoresist pattern 67 as an etching mask, so that asecond opening 67P exposing thesacrificial oxide layer 59 may be formed. Thesecond opening 67P may be selectively formed at both ends of a first one of theopenings 61P. For example, thesecond opening 67P may be formed to overlap both ends of thefirst openings 61P extending from thecell region 20 to theperipheral circuit region 10. Subsequently, thephotoresist pattern 67 may be removed. - Referring to
FIGS. 1 and 7 , a secondsacrificial mask pattern 69 filling a gap between thesacrificial spacers 65 and the first andsecond openings - Specifically, a second sacrificial mask layer filling the
first openings 61P and thesecond openings 67P and covering thesemiconductor substrate 51 may be formed. The second sacrificial mask layer is planarized until thesacrificial spacer 65 is exposed, so that the secondsacrificial mask pattern 69 may be formed. A chemical-mechanical polishing (CMP) process or etch back process may be used for planarization of the second sacrificial mask layer. - Referring to
FIGS. 1 and 8 , thesacrificial spacers 65 may be removed. An isotropic etching having an etch selectivity between thesacrificial mask patterns 61′ and 69 and thesacrificial spacers 65 may be used to remove thesacrificial spacers 65. In other words, the isotropic etching may have a high etch rate with respect to thesacrificial spacers 65. Consequently, thesacrificial mask patterns 61′ and 69 may remain on thesemiconductor substrate 51. - Using the
sacrificial mask patterns 61′ and 69 as etching masks, thesacrificial oxide layer 59, the peripheral circuit gateconductive layer 58, the peripheral circuitgate dielectric layer 57, theisolation layer 55, and the cellactive regions 53 are anisotropically etched, so thatword line trenches 71 andinterconnect trenches 72 may be formed. Theword line trenches 71 may be formed in thecell region 20, and theinterconnect trenches 72 may be formed in theperipheral circuit region 10. Theword line trenches 71 may be connected to theinterconnect trenches 72 corresponding thereto, respectively. In other words, theword line trenches 71 may extend to be connected to theinterconnect trenches 72. - Sizes of the
word line trenches 71 and theinterconnect trenches 72 may be determined by thesacrificial spacer 65. When thesacrificial spacer 65 has a smaller width than the resolution limit of a photolithography process, theword line trenches 71 and theinterconnect trenches 72 may also be formed to have a width smaller than the resolution limit of a photolithography process. - Referring to
FIGS. 1 and 9 , thesacrificial mask patterns 61′ and 69 may be removed. An isotropic etching process may be used to remove thesacrificial mask patterns 61′ and 69. A cellgate dielectric layer 77 may be formed on inner walls of theword line trenches 71. The cellgate dielectric layer 77 may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The cellgate dielectric layer 77 may be formed to uniformly cover surfaces of the cellactive regions 53 exposed to theword line trenches 71. - On the
semiconductor substrate 51 having the cellgate dielectric layer 77, a word conductive layer may be formed. The word conductive layer is planarized, so that word lines 78 may be formed in theword line trenches 71, and simultaneously,interconnect patterns 79 may be formed in theinterconnect trenches 72. A CMP process or etch back process may be used for planarization of the word conductive layer. Subsequently, thesacrificial oxide layer 59 is removed, so that the peripheral circuit gateconductive layer 58 may be exposed. - The word lines 78 and the
interconnect patterns 79 may be formed of a metal layer, such as a titanium nitride (TiN) layer. The peripheral circuit gateconductive layer 58, the word lines 78, and theinterconnect patterns 79 may be exposed on substantially the same plane. In addition, the word lines 78 and theinterconnect patterns 79 may be formed at a lower level than the top surface of the peripheral circuit gateconductive layer 58. Furthermore, the word lines 78 may contact theinterconnect patterns 79 corresponding thereto, respectively. - The
sacrificial mask patterns 61′ and 69 may be removed after the word lines 78 and theinterconnect patterns 79 are formed. - Impurity ions may be implanted into the peripheral circuit gate
conductive layer 58. For example, n-type impurity ions may be implanted into the peripheral circuit gateconductive layer 58 in an nMOS region, and p-type impurity ions may be implanted into a peripheral circuit gateconductive layer 58P in a pMOS region. Referring toFIGS. 1 and 10 , an upperconductive layer 81 covering the peripheral circuit gateconductive layers interconnect patterns 79 may be formed. The upperconductive layer 81 may be formed of a metal layer such as tungsten (W) or tungsten silicide (WSi). The upperconductive layer 81 may contact the peripheral circuit gateconductive layers interconnect patterns 79. - Referring to
FIGS. 1 and 11 , ahard mask pattern 83 may be formed on the upperconductive layer 81. Thehard mask pattern 83 may be formed of a nitride layer, such as a silicon nitride layer. - The upper
conductive layer 81 and the peripheral circuit gateconductive layers hard mask pattern 83 as an etching mask, so that gate lines 85, 87 and 88 may be formed. The gate lines 85, 87 and 88 may includefirst gate lines 85, second gate lines 87, and third gate lines 88. Under the gate lines 85, 87 and 88, patterned peripheral circuit gateconductive layers 58′ and 58P′ may remain. In addition, the gate lines 85, 87 and 88 may have regions CA overlapping theinterconnect patterns 79. - As the result, parts of the
interconnect patterns 79, except for the overlapped regions CA, and the word lines 78 may be exposed. The exposedinterconnect patterns 79 and the word lines 78 are etched back, so that buried word line interconnects 79′ and buriedword lines 78′ may be formed. - In contrast with conventional contacts using contact plugs to contact buried word lines, the word line interconnects 79′ have a unitary structure including a first portion at the same level as the buried
word lines 78′ and asecond portion 79E that extends vertically from the first portion to contact the gate lines 85, 87 and 88 in the overlapping regions CA. The buriedword lines 78′ and first portions of the buried interconnects 79′ have top surfaces lower than the top surfaces of the adjacentactive regions - Upper
word line trenches 71′ may be formed on the buriedword lines 78′, andupper interconnect trenches 72′ may be formed on the buried interconnects 79′. - The buried
word lines 78′ may contact respective ones of the buried interconnects 79′. In this case, the buried interconnects 79′ may be in contact with one of the first gate lines 85. The buriedword lines 78′ may be electrically connected with the first gate lines 85. - The
second gate lines 87 may be formed to cross over the nMOS peripheral circuitactive regions 54. The peripheral circuitgate dielectric layer 57 and the patterned peripheral circuit gateconductive layers 58′ sequentially stacked between the nMOS peripheral circuitactive regions 54 and thesecond gate lines 87 may be conserved. - The
third gate lines 88 may be formed to cross over the pMOS peripheral circuitactive regions 54P. The peripheral circuitgate dielectric layer 57 and the patterned peripheral circuit gateconductive layers 58P′ sequentially stacked between the pMOS peripheral circuitactive regions 54P and thethird gate lines 88 may be conserved. - The buried interconnects 79′ may be formed between the
second gate lines 87 and the third gate lines 88. In this case, one end of the buried interconnects 79′ may overlap the second gate lines 87, and the other end thereof may overlap the third gate lines 88. Respective ends of the buried interconnects 79′ may project toward the second andthird gate lines - Referring to
FIGS. 1 and 12 , low-concentration impurity regions 92 may be formed in the nMOS peripheral circuitactive regions 54 on respective sides of the second gate lines 87.Spacers 91 may be formed on sidewalls of the patterned peripheral circuit gateconductive layers 58′ and the gate lines 85, 87 and 88. Thespacers 91 may be formed of a silicon oxide layer, a silicon nitride layer, or a combination thereof. Source anddrain regions active regions - Subsequently, a first
interlayer insulating layer 97 may be formed on thesemiconductor substrate 51. The firstinterlayer insulating layer 97 may be formed of a silicon oxide layer. The firstinterlayer insulating layer 97 is planarized, so that thehard mask pattern 83 may be exposed. A CMP process or etch back process may be used for planarization of the firstinterlayer insulating layer 97. - While the
spacers 91 and the firstinterlayer insulating layer 97 are formed, an insulatingpattern 91′ may be formed on the buriedword lines 78′ and the buried interconnects 79′. More specifically, while thespacers 91 are formed, the insulatingpattern 91′ may be formed in the upperword line trenches 71′ and theupper interconnect trenches 72′. Alternatively, the upperword line trenches 71′ and theupper interconnect trenches 72′ may be filled by the firstinterlayer insulating layer 97. Referring toFIGS. 1 and 13 , the firstinterlayer insulating layer 97 is patterned, so that bit contact holes 101 and 102 exposing the source and drainregions Bit lines interlayer insulating layer 97. The bit lines 105 and 106 and the bit plugs 103 and 104 may be formed of a metal layer, a polysilicon layer, or a combination thereof. The bit lines 105 and 106 may includefirst bit lines 105 formed in thecell region 20 andsecond bit lines 106 formed in theperipheral circuit region 10. - Referring to
FIGS. 1 and 14 , a secondinterlayer insulating layer 110 may be formed on thesemiconductor substrate 51 having thebit lines interlayer insulating layer 110 may be a silicon oxide layer. Node contact holes 111 penetrating the secondinterlayer insulating layer 110 and the firstinterlayer insulating layer 97 and exposing the source and drainregions 95 may be formed. Node plugs 113 filling the node contact holes 111 may be formed.Storage nodes 115 contacting the node plugs 113 may be formed on the secondinterlayer insulating layer 110. Thestorage nodes 115 and the node plugs 113 may be a metal layer, a polysilicon layer, or a combination thereof. - Now, referring to
FIGS. 1 and 14 , a semiconductor device according to first exemplary embodiments of the present invention will be described. The device may have anisolation layer 55 disposed on asemiconductor substrate 51. Thesemiconductor substrate 51 may be a silicon wafer having aperipheral circuit region 10 and acell region 20. - By the
isolation layer 55, cellactive regions 53 may be defined in thecell region 20, and peripheral circuitactive regions peripheral circuit region 10. The cellactive regions 53 may be arranged at predetermined intervals in row and column directions in thecell region 20. The peripheral circuitactive regions active regions 54 and pMOS peripheral circuitactive regions 54P. Theisolation layer 55 may be an insulating layer such as a silicon oxide layer. - Buried word lines 78′ may be disposed in the
cell region 20. The buriedword lines 78′ may be disposed at a lower level than the top surface of the cellactive regions 53. Buried interconnects 79′ may be disposed in theperipheral circuit region 10. The buried interconnects 79′ may be disposed at a lower level than the top surface of the peripheral circuitactive regions 54 and 54 p. - Bottoms and sidewalls of the buried interconnects 79′ and the buried
word lines 78′ may be surrounded by a cellgate dielectric layer 77. Thus, the cellgate dielectric layer 77 may be interposed between the buriedword lines 78′ and the cellactive regions 53. The cellgate dielectric layer 77 may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof. - The buried interconnects 79′ may be disposed at the same level as the buried
word lines 78′. In other words, bottom surfaces of the buried interconnects 79′ and the buriedword lines 78′ may be disposed on the same plane. In addition, the buried interconnects 79′ may have the same cross-sectional area as the buriedword lines 78′. The buried interconnects 79′ and the buriedword lines 78′ may have a smaller width than the resolution limit of a photolithography process. Furthermore, the buried interconnects 79′ may be the same material layer as the buriedword lines 78′. In this case, the buried interconnects 79′ and the buriedword lines 78′ may have a metal layer. The metal layer may be a titanium nitride (TiN) layer. - The gate lines 85, 87 and 88 may be disposed at a higher level than the buried interconnects 79′. A
hard mask pattern 83 may be provided on the gate lines 85, 87 and 88. Thehard mask pattern 83 may be a nitride layer such as a silicon nitride layer. - The gate lines 85, 87 and 88 may include
first gate lines 85, second gate lines 87, and third gate lines 88. The gate lines 85, 87 and 88 may be a metal layer such as a tungsten (W) layer or a tungsten silicide (WSi) layer. The gate lines 85, 87 and 88 may be disposed at a higher level than the peripheral circuitactive regions - The gate lines 85, 87 and 88 may have overlapping regions CA overlapping the buried interconnects 79′. In the overlapping regions CA, the buried interconnects 79′ may contact the gate lines 85, 87 and 88. The buried interconnects 79′ may project toward the gate lines 85, 87 and 88 in the overlapping regions CA. In other words, the buried interconnects 79′ may have
projections 79E projecting upward. - The buried
word lines 78′ may contact the buried interconnects 79′ corresponding thereto, respectively. In this case, the buried interconnects 79′ may be in contact with one of the first gate lines 85. In other words, the overlapping regions CA may be provided between the buried interconnects 79′ and the first gate lines 85. In the overlapping regions CA, the buried interconnects 79′ may have theprojections 79E projecting toward the first gate lines 85. Consequently, the buriedword lines 78′ may be electrically connected with the first gate lines 85. - The
second gate lines 87 may be disposed to cross over the nMOS peripheral circuitactive regions 54. Thethird gate lines 88 may be disposed to cross over the pMOS peripheral circuitactive regions 54P. The buried interconnects 79′ may be disposed between thesecond gate lines 87 and the third gate lines 88. In this case, one end of the buried interconnects 79′ may overlap the second gate lines 87, and the other end thereof may overlap the third gate lines 88. In other words, theprojections 79E projecting toward the second andthird gate lines - A peripheral circuit
gate dielectric layer 57 and patterned peripheral circuit gateconductive layers 58′ may be sequentially stacked between the nMOS peripheral circuitactive regions 54 and the second gate lines 87. The peripheral circuitgate dielectric layer 57 may be a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The patterned peripheral circuit gateconductive layers 58′ may be a polysilicon layer. - Between the pMOS peripheral circuit
active regions 54P and thethird gate line 88, the peripheral circuitgate dielectric layer 57 and the patterned peripheral circuit gateconductive layers 58P′ may be sequentially stacked. Also, between theisolation layer 55 and the gate lines 85, 87 and 88, the peripheral circuitgate dielectric layer 57 and the patterned peripheral circuit gateconductive layers 58′ and 58P′ may be sequentially stacked. -
Spacers 91 may be disposed on sidewalls of the patterned peripheral circuit gateconductive layers 58′ and the second gate lines 87. Thespacers 91 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. - Low-
concentration impurity regions 92 may be disposed in the nMOS peripheral circuitactive regions 54 under thespacers 91. Source anddrain regions active regions word lines 78′ and the gate lines 87 and 88. - An insulating
pattern 91′ may be disposed on the buried interconnects 79′ and the buriedword lines 78′. The bottom surface of the insulatingpattern 91′ may be disposed at a lower level than the top surfaces of the adjacentactive regions pattern 91′ may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. - A first
interlayer insulating layer 97 may be provided on thesemiconductor substrate 51 having the insulatingpattern 91′. The firstinterlayer insulating layer 97 may be an insulating layer such as a silicon oxide layer. -
Bit lines interlayer insulating layer 97. The bit lines 105 and 106 may cross over the buried interconnects 79′ and the buriedword lines 78′. The bit lines 105 and 106 may includefirst bit lines 105 disposed in thecell region 20 andsecond bit lines 106 disposed in theperipheral circuit region 10. The bit lines 105 and 106 may be connected to the source and drainregions interlayer insulating layer 97. The bit lines 105 and 106 and the bit plugs 103 and 104 may be a metal layer, a polysilicon layer, or a combination thereof. - The
semiconductor substrate 51 having thebit lines interlayer insulating layer 110. The secondinterlayer insulating layer 110 may be an insulating layer, such as a silicon oxide layer.Storage nodes 115 may be disposed on the secondinterlayer insulating layer 110. Thestorage nodes 115 may be connected to the source and drainregions 95 through node plugs 113 sequentially penetrating the secondinterlayer insulating layer 110 and the firstinterlayer insulating layer 97. Thestorage nodes 115 and the node plugs 113 may be a metal layer, a polysilicon layer, or a combination thereof. - As described above, according to the first embodiments of the present invention, the buried interconnects 79′ may be disposed at a lower level than the top surfaces of the
active regions bit lines pattern 91′ is not disturbed. In addition, a signal transmission path can be shortened in comparison with a conventional bypass interconnect method using a bit line layer or a metal interconnect layer. Consequently, a semiconductor device having excellent electrical characteristics and advantageous to high integration can be embodied. - A semiconductor device having buried interconnects and methods of fabrication therefor according to second exemplary embodiments of the present invention will now be described with reference to
FIGS. 15 to 21 .FIG. 15 is a plan view of a semiconductor device having buried interconnects according to the second exemplary embodiments of the present invention.FIGS. 16 to 21 are composites of cross-sectional views illustrating operations for fabricating the semiconductor device ofFIG. 15 , in which across-section 5 is taken along line V-V′ ofFIG. 15 , across-section 6 is taken along line VI-VI′ ofFIG. 15 , and across-section 7 is taken along line VII-VII′ ofFIG. 15 . - Referring to
FIGS. 15 and 16 , anisolation layer 155 definingactive regions semiconductor substrate 151. Thesemiconductor substrate 151 may be a silicon wafer having annMOS region 10N and apMOS region 10P. Theactive regions active regions 153 and pMOS peripheral circuitactive regions 153P. The nMOS peripheral circuitactive regions 153 may be arranged in thenMOS region 10N, and the pMOS peripheral circuitactive regions 153P may be arranged in thepMOS region 10P. - A peripheral circuit
gate dielectric layer 157 may be formed on theactive regions conductive layer 158 and asacrificial oxide layer 159 may be sequentially stacked on thesemiconductor substrate 151 having the peripheral circuitgate dielectric layer 157. - A first
sacrificial mask pattern 161 may be formed on the peripheral circuit gateconductive layer 158. The firstsacrificial mask pattern 161 may be formed of a material layer having an etch selectivity with respect to the peripheral circuit gateconductive layer 158, theactive regions isolation layer 155. Asacrificial spacer 165 may be formed on sidewalls of the firstsacrificial mask pattern 161. Thesacrificial spacer 165 may be formed of a material layer having an etch selectivity with respect to the firstsacrificial mask pattern 161. Thesacrificial spacer 165 may be formed of a polysilicon layer. Thesacrificial spacer 165 may be formed to have a smaller thickness than the resolution limit of a photolithography process. Subsequently, a patterning process for separating thesacrificial spacer 165 may be performed. Specifically, aphotoresist pattern 167 may be formed on thesemiconductor substrate 151 having thesacrificial spacer 165. Thephotoresist pattern 167 may have afirst opening 167P partially exposing thesacrificial spacer 165. - Referring to
FIGS. 15 and 17 , thesacrificial spacer 165 is etched using thephotoresist pattern 167 as an etching mask, so that asecond opening 165P exposing thesacrificial oxide layer 159 may be formed. Thesecond opening 165P may be selectively formed at both ends of thesacrificial spacer 165. Subsequently, thephotoresist pattern 167 may be removed. - Referring to
FIGS. 15 and 18 , a secondsacrificial mask pattern 169 filling a gap between thesacrificial spacers 165 and thesecond opening 165P may be formed. Referring toFIGS. 15 and 19 , thesacrificial spacer 165 may be removed. An isotropic etching having an etch selectivity between thesacrificial mask patterns sacrificial spacer 165 may be used for removal of thesacrificial spacer 165. Consequently, thesacrificial mask patterns semiconductor substrate 151. - The
sacrificial oxide layer 159, the peripheral circuit gateconductive layer 158, the peripheral circuitgate dielectric layer 157, and theisolation layer 155 are anisotropically etched using thesacrificial mask patterns interconnect trenches 172 may be formed. - The size of the
interconnect trenches 172 may be determined by thesacrificial spacer 165. When thesacrificial spacer 165 has a smaller width than the resolution limit of a photolithography process, theinterconnect trenches 172 may also be formed to have a smaller width than the resolution limit of a photolithography process. - Referring to
FIGS. 15 and 20 , thesacrificial mask patterns gate dielectric layer 177 may be formed on an inner wall of theinterconnect trenches 172. Subsequently,interconnect patterns 179 are formed in theinterconnect trenches 172. Thesacrificial oxide layer 159 is removed, so that the peripheral circuit gateconductive layer 158 may be exposed. - The peripheral circuit gate
conductive layer 158 and theinterconnect patterns 179 may be exposed on substantially the same plane. In addition, theinterconnect patterns 179 may be formed at a lower level than the top surface of the peripheral circuit gateconductive layer 158. - Alternatively, the
sacrificial mask patterns gate dielectric layer 177 and theinterconnect patterns 179 are formed. Subsequently, impurity ions may be implanted into the peripheral circuit gateconductive layer 158. For example, n-type impurity ions may be implanted into the peripheral circuit gateconductive layer 158 in the nMOS region, and p-type impurity ions may be implanted into a peripheral circuit gateconductive layer 158P in the pMOS region. - An upper
conductive layer 181 covering the peripheral circuit gateconductive layers interconnect patterns 179 may be formed. Ahard mask pattern 183 may be formed on the upperconductive layer 181. - Referring to
FIGS. 15 and 21 , the upperconductive layer 181 and the peripheral circuit gateconductive layers hard mask pattern 183 as an etching mask, so thatgate lines first gate lines 187 and second gate lines 188. Thefirst gate lines 187 may be arranged in thenMOS region 10N, and thesecond gate lines 188 may be arranged in thepMOS region 10P. - Patterned peripheral circuit gate
conductive layers 158′ and 158P′ may remain under thegate lines gate lines interconnect patterns 179. - As a result, parts of the
interconnect patterns 179 except for the overlapping regions CA may be exposed. The exposedinterconnect patterns 179 are etched back, so that buried interconnects 179′ may be formed. The buried interconnects 179′ may be formed at a lower level than the top surfaces of the adjacentactive regions - In the overlapping regions CA, the
interconnect patterns 179 may be conserved under thegate lines interconnects 179′ may haveprojections 179E projecting upward. In other words, the buriedinterconnects 179′ may project toward thegate lines interconnects 179′ may contact thegate lines - The
first gate lines 187 may be formed to cross over the nMOS peripheral circuitactive regions 153. The peripheral circuitgate dielectric layer 157 and the patterned peripheral circuit gateconductive layers 158′ sequentially stacked between the nMOS peripheral circuitactive regions 153 and thefirst gate lines 187 may be conserved. - The
second gate lines 188 may be formed to cross over the pMOS peripheral circuitactive regions 153P. The peripheral circuitgate dielectric layer 157 and the patterned peripheral circuit gateconductive layers 158P′ sequentially stacked between the pMOS peripheral circuitactive regions 153P and thesecond gate lines 188 may be conserved. - The buried interconnects 179′ may be formed between the
first gate lines 187 and the second gate lines 188. In this case, one end of the buriedinterconnects 179′ may overlap thefirst gate lines 187, and the other end thereof may overlap the second gate lines 188. The ends of the buriedinterconnects 179′ may project toward the first andsecond gate lines - An
insulating pattern 197 may be formed on the buriedinterconnects 179′. The insulatingpattern 197 may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. Consequently, thesemiconductor substrate 151 may be covered by thehard mask pattern 183 and the insulatingpattern 197. - As described above, the
first gate lines 187 may be disposed in thenMOS region 10N, and thesecond gate lines 188 may be disposed in thepMOS region 10P. Thefirst gate lines 187 may be electrically connected with thesecond gate lines 188 by the buriedinterconnects 179′. - Now, a semiconductor device having buried interconnects and method of fabricating the same according to third exemplary embodiments of the present invention will be described with reference to
FIGS. 22 and 23 .FIG. 22 is a plan view of a semiconductor device having buried interconnects according to the third exemplary embodiments of the present invention.FIG. 23 is a composite of cross-sectional views illustrating operations for fabricating the semiconductor device ofFIG. 22 , in which across-section 8 is taken along line VIII-VIII′ ofFIG. 22 , and across-section 9 is taken along line IX-IX′ ofFIG. 22 . - Referring to
FIGS. 22 and 23 , the patterning process for separating the sacrificial spacer (165 ofFIG. 17 ) as described with reference toFIGS. 16 and 17 is omitted in the method of fabricating a semiconductor device according to the third exemplary embodiments of the present invention. More specifically, the second opening (165P ofFIG. 17 ) formed at both ends of the sacrificial spacer (165 ofFIG. 17 ) is not formed. - Consequently, a semiconductor substrate according to the third exemplary embodiments of the present invention may have an
isolation layer 255 disposed on asemiconductor substrate 251. Thesemiconductor substrate 251 may be a silicon wafer having annMOS region 10N and apMOS region 10P. By theisolation layer 255, nMOS peripheral circuitactive regions 253 may be defined in thenMOS region 10N, and pMOS peripheral circuitactive regions 253P may be defined in thepMOS region 10P. -
Buried interconnects 279 may be disposed in interconnect trenches formed in theisolation layer 255. The buried interconnects 279 may be disposed at a lower level than the top surface of the peripheral circuitactive regions interconnects 279 may be surrounded by a cellgate dielectric layer 277.Gate lines hard mask pattern 283 may be provided on thegate lines first gate lines 287 and second gate lines 288. The gate lines 287 and 288 may be disposed at a higher level than the peripheral circuitactive regions - The gate lines 287 and 288 may have regions CA overlapping the buried interconnects 279. In the overlapping regions CA, the buried
interconnects 279 may contact thegate lines gate lines interconnects 279 may haveprojections 279E projecting upward. - The
first gate lines 287 may be disposed to cross over the nMOS peripheral circuitactive regions 253. Thesecond gate lines 288 may be disposed to cross over the pMOS peripheral circuitactive regions 253P. A pair of the buriedinterconnects 279 may be disposed between thefirst gate lines 287 and the second gate lines 288. In this case, one end of the buriedinterconnects 279 may overlap thefirst gate lines 287, and the other end thereof may overlap the second gate lines 288. In addition, one pair of the buriedinterconnects 279 parallel to each other may be in contact with each other in the overlapping regions CA. - A peripheral circuit
gate dielectric layer 257 and patterned peripheral circuit gateconductive layers 258 may be sequentially stacked between the nMOS peripheral circuitactive regions 253 and the first gate lines 287. - The peripheral circuit
gate dielectric layer 257 and patterned peripheral circuit gateconductive layers 258P may be sequentially stacked between the pMOS peripheral circuitactive regions 253P and the second gate lines 288. Also, the peripheral circuitgate dielectric layer 257 and the patterned peripheral circuit gateconductive layers isolation layer 255 and thegate lines - An
insulating pattern 297 may be disposed on the buried interconnects 279. The bottom surface of the insulatingpattern 297 may be disposed at a lower level than the top surfaces of the adjacentactive regions semiconductor substrate 251 may be covered by thehard mask pattern 283 and the insulatingpattern 297. - As described above, the
first gate lines 287 may be disposed in thenMOS region 10N, and thesecond gate lines 288 may be disposed in thepMOS region 10P. Thefirst gate lines 287 may be electrically connected with thesecond gate lines 288 by one pair of the buried interconnects 279. - Now, a semiconductor device having buried interconnects and methods of fabricating the same according to fourth exemplary embodiments of the present invention will be described with reference to
FIG. 24 . In the methods of fabricating a semiconductor device according to the fourth exemplary embodiments of the present invention, a buriedinterconnect 379 is formed, and thengate lines - The semiconductor device according to the fourth exemplary embodiments of the present invention may have an
isolation layer 355 disposed on asemiconductor substrate 351. Thesemiconductor substrate 351 may be a silicon wafer having an nMOS region and a pMOS region. By theisolation layer 355, an nMOS peripheral circuitactive region 353 may be defined in the nMOS region, and a pMOS peripheral circuitactive regions 353P may be defined in the pMOS region. The buriedinterconnect 379 may be disposed in an interconnect trench formed in theisolation layer 355. The buriedinterconnect 379 may be disposed at a lower level than the top surfaces of the peripheral circuitactive regions interconnect 379 may be surrounded by a cellgate dielectric layer 377. The gate lines 387 and 388 may be disposed at a higher level than the buriedinterconnect 379. Ahard mask pattern 383 may be provided on thegate lines first gate line 387 and asecond gate line 388. The gate lines 387 and 388 may be disposed at a higher level than the peripheral circuitactive regions - The gate lines 387 and 388 may have regions CA overlapping the buried
interconnect 379. In the overlapping regions CA, the buriedinterconnect 379 may contact thegate lines interconnect 379 in the overlapping regions CA. In other words,projections gate lines - The
first gate line 387 may be disposed cross over the nMOS peripheral circuitactive regions 353, and thesecond gate line 388 may be disposed cross over the pMOS peripheral circuitactive regions 353P. The buriedinterconnect 379 may be disposed between thefirst gate line 387 and thesecond gate line 388. In this case, one end of the buriedinterconnect 379 may overlap thefirst gate line 387, and the other end thereof may overlap thesecond gate line 388. - A peripheral circuit
gate dielectric layer 357 and patterned peripheral circuit gateconductive layers 358 may be sequentially stacked between the nMOS peripheral circuitactive regions 353 and thefirst gate line 387. The peripheral circuitgate dielectric layer 357 and a patterned peripheral circuit gateconductive layer 358P may be sequentially stacked between the pMOS peripheral circuitactive regions 353P and thesecond gate line 388. Also, the peripheral circuitgate dielectric layer 357 and the patterned peripheral circuit gateconductive layers isolation layer 355 and thegate lines - An
insulating pattern 397 may be disposed on the buriedinterconnect 379. The bottom surface of the insulatingpattern 397 may be disposed at a lower level than the top surfaces of the adjacentactive regions semiconductor substrate 351 may be covered by thehard mask pattern 383 and the insulatingpattern 397. - As described above, according to some embodiments of the present invention, a buried word line is formed in a cell region while a buried interconnect is formed in a peripheral circuit region. The buried interconnect and the buried word line may be formed at a lower level than the top surface of an adjacent active region. Gate lines are disposed at a higher level than the buried interconnect. The gate lines have regions overlapping the buried interconnect. In the overlapping regions, the buried interconnect contacts the gate lines. An insulating pattern is provided on the buried interconnect and the buried word line. One of the gate lines may be electrically connected to the other gate line or the buried word line through the buried interconnect. Therefore, a signal transmission path can be shortened in comparison with a conventional interconnect method.
- In addition, bit lines may be disposed on the insulating pattern. In this case, the buried interconnect is provided under the insulating pattern and thus does not disturb arrangement of the bit lines.
- Consequently, it is possible to provide a semiconductor device having excellent electrical characteristics and advantageous to high integration.
- The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. The invention is defined by the following claims.
Claims (21)
1. A semiconductor device comprising:
a semiconductor substrate having a cell region and a peripheral circuit region defined therein;
a buried word line in the substrate in the cell region and having a top surface lower than top surfaces of cell active regions in the cell region;
a gate line on the substrate in the peripheral circuit region; and
a unitary word line interconnect in the substrate in the peripheral circuit region, the word line interconnect comprising a first portion contacting the buried word line and having a top surface lower than top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
2. The semiconductor device of claim 1 , wherein the second portion of the word line interconnect extends vertically from the first portion of the word line interconnect to contact a bottom surface of the gate line.
3. The semiconductor device of claim 1 , wherein the top surface of the first portion of the word line interconnect is at substantially the same level as the top surface of the buried word line.
4. The semiconductor device of claim 1 , wherein the first portion of the word line interconnect has substantially the same cross-sectional area as the buried word line.
5. The semiconductor device of claim 1 , wherein the word line interconnect and the buried word line comprise a common metal layer.
6. The semiconductor device of claim 1 , wherein the gate line has a top surface that is higher than top surfaces of peripheral circuit active regions in the peripheral circuit region.
7. The semiconductor device of claim 1 , further comprising an insulating pattern disposed on the first portion of the word line interconnect and the buried word line.
8. The semiconductor device of claim 7 , wherein a bottom surface of the insulating pattern is lower than the top surfaces of the cell active regions.
9. The semiconductor device of claim 7 , further comprising a bit line disposed on the insulating pattern and crossing the buried word line.
10. The semiconductor device of claim 9 , further comprising:
first and second spaced-apart gate lines on the substrate in the peripheral circuit region on respective sides of the bit line;
a buried peripheral circuit interconnect in the substrate in the peripheral circuit region beneath the bit line, the buried peripheral circuit interconnect connecting the first and second gate lines and having a portion beneath the bit line that has a top surface at substantially the same level as the top surface of the buried word line.
11. The semiconductor device of claim 1 , wherein the first portion of the word line interconnect is laterally offset with respect to the buried word line.
12. A method of fabricating a semiconductor device, comprising:
forming an isolation region in a semiconductor substrate, the isolation region defining cell active regions in a cell region and peripheral circuit active regions in a peripheral circuit region;
forming a word line trench in the substrate in the cell region and an adjoining word line interconnect trench in the peripheral circuit region;
forming a word line pattern in the word line trench and a word line interconnect pattern in the word line interconnect trench;
forming a gate line on the substrate in the peripheral circuit region, the gate line having an end portion that overlaps the word line interconnect pattern;
etching back the word line pattern and the word line interconnect pattern to form word line in the word line trench having a top surface lower than top surfaces of the cell active regions and a word line interconnect in the word line interconnecting trench having a first portion connected to the word line and a top surface lower than the top surfaces of the cell active regions and a second portion extending vertically from the first portion to contact a bottom surface of the gate line; and
forming an insulating pattern on the buried word line and the first portion of the word line interconnect.
13. The method of claim 12 , wherein forming a word line trench in the cell region and an adjoining word line interconnect trench in the peripheral circuit region comprises:
forming a first sacrificial mask pattern on the substrate having the isolation layer;
forming sacrificial spacers on sidewalls of the first sacrificial mask pattern;
forming a second sacrificial mask pattern filling a gap between the sacrificial spacers;
removing the sacrificial spacers; and
etching the isolation layer and the semiconductor substrate using the first and second sacrificial mask patterns as etching masks to form the word line trench and the word line interconnect trench.
14. The method of claim 13 , wherein forming a first sacrificial mask pattern on the substrate having the isolation layer is preceded by:
forming a peripheral circuit gate dielectric layer on the peripheral circuit active regions;
forming a peripheral circuit gate conductive layer on the peripheral circuit gate dielectric layer; and
forming a sacrificial oxide layer on the peripheral circuit gate conductive layer.
15. The method of claim 14 , wherein forming a gate line comprises:
etching the first and second sacrificial mask patterns and the sacrificial oxide layer to expose the peripheral circuit gate conductive layer;
forming a metal layer covering the peripheral circuit gate conductive layer, the word line pattern, and the word line interconnect pattern; and
patterning the metal layer and the peripheral circuit gate conductive layer to form the gate line.
16. The method of claim 12 , wherein the word line pattern and the word line interconnect pattern are formed from a common metal layer.
17. The method of claim 12 , wherein a bottom surface of the insulating pattern is lower than top surfaces of the cell active regions.
18. The method of claim 12 , further comprising forming a bit line on the insulating pattern and crossing the buried word line.
19. The method of claim 18 , further comprising:
forming a peripheral circuit interconnect trench in the substrate in the peripheral circuit region concurrent with forming the word line trench in the substrate in the cell region and the adjoining word line interconnect trench in the peripheral circuit region;
forming a peripheral circuit interconnect pattern in the peripheral circuit interconnect trench concurrent with forming the word line pattern in the word line trench and the word line interconnect pattern in the word line interconnect trench;
forming second and third spaced apart gate lines in the peripheral circuit region on respective sides of the bit line concurrent with forming the first gate line on the substrate in the peripheral circuit region, the first and second gate lines overlapping and contacting the peripheral circuit interconnect pattern;
etching back the peripheral circuit interconnect pattern concurrent with etching back the word line pattern and the word line interconnect pattern to form a peripheral circuit interconnect having a first portion with a top surface that is lower than a top surface of the peripheral circuit active regions and second portions that extend vertically from the first portion to contact bottom surfaces of respective ones of the second and third gate lines; and
forming an insulating pattern on the first portion of the peripheral circuit interconnect concurrent with forming the insulating pattern on the buried word line and the first portion of the word line interconnect.
20. The method of claim 12 , wherein the buried word line extends along a line across the cell region, and wherein the first portion of the word line interconnect is laterally offset with respect to the line.
21.-44. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/473,751 US8895400B2 (en) | 2006-08-24 | 2012-05-17 | Methods of fabricating semiconductor devices having buried word line interconnects |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2006-80700 | 2006-08-24 | ||
KR1020060080700A KR100782488B1 (en) | 2006-08-24 | 2006-08-24 | Semiconductor device having buried interconnections and method of fabricating the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/473,751 Division US8895400B2 (en) | 2006-08-24 | 2012-05-17 | Methods of fabricating semiconductor devices having buried word line interconnects |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080048333A1 true US20080048333A1 (en) | 2008-02-28 |
Family
ID=39112606
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/842,416 Abandoned US20080048333A1 (en) | 2006-08-24 | 2007-08-21 | Semiconductor Device Having Buried Word Line Interconnects and Method of Fabricating the Same |
US13/473,751 Active 2027-10-21 US8895400B2 (en) | 2006-08-24 | 2012-05-17 | Methods of fabricating semiconductor devices having buried word line interconnects |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/473,751 Active 2027-10-21 US8895400B2 (en) | 2006-08-24 | 2012-05-17 | Methods of fabricating semiconductor devices having buried word line interconnects |
Country Status (2)
Country | Link |
---|---|
US (2) | US20080048333A1 (en) |
KR (1) | KR100782488B1 (en) |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7462903B1 (en) * | 2005-09-14 | 2008-12-09 | Spansion Llc | Methods for fabricating semiconductor devices and contacts to semiconductor devices |
US20090072289A1 (en) * | 2007-09-18 | 2009-03-19 | Dae-Ik Kim | Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same |
US20100102371A1 (en) * | 2008-10-27 | 2010-04-29 | Yeom Kye-Hee | Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning |
US20100193880A1 (en) * | 2007-09-18 | 2010-08-05 | Makoto Yoshida | Semiconductor device and method of forming the same |
US20100193901A1 (en) * | 2009-01-30 | 2010-08-05 | Se-Aug Jang | Semiconductor device and method for fabricating the same |
US20100221875A1 (en) * | 2007-02-21 | 2010-09-02 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same |
US20110020993A1 (en) * | 2009-07-23 | 2011-01-27 | Jong-Man Park | Semiconductor Device and Method of Fabricating the Same |
US20110210421A1 (en) * | 2010-02-26 | 2011-09-01 | Chul Lee | Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device |
US20110241102A1 (en) * | 2010-04-06 | 2011-10-06 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and buried channel array transistor, methods of fabricating the same, and semiconductor modules, electronic circuit boards and electronic systems including the same |
US20120007186A1 (en) * | 2010-07-06 | 2012-01-12 | Hynix Semiconductor Inc. | Semiconductor device and method of manufacturing the same |
US20120286354A1 (en) * | 2011-05-11 | 2012-11-15 | Hynix Semiconductor Inc. | Semiconductor device and method of manufacturing the same |
US20130040408A1 (en) * | 2011-08-11 | 2013-02-14 | KyungTae Nam | Method of fabricating resistance variable memory device and devices and systems formed thereby |
US20130137270A1 (en) * | 2011-11-24 | 2013-05-30 | Powerchip Technology Corporation | Method for forming contact hole |
US8823149B2 (en) * | 2012-12-11 | 2014-09-02 | Globalfoundries Inc. | Contact landing pads for a semiconductor device and methods of making same |
US8956928B2 (en) | 2012-11-30 | 2015-02-17 | Globalfoundries Inc | Contact structure for a semiconductor device and methods of making same |
US20150187899A1 (en) * | 2014-01-02 | 2015-07-02 | SK Hynix Inc. | Semiconductor device and method for forming the same |
US9240415B2 (en) | 2013-07-05 | 2016-01-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
EP3139405A1 (en) * | 2015-09-01 | 2017-03-08 | IMEC vzw | Buried interconnect for semicondutor circuits |
US20170110507A1 (en) * | 2015-10-20 | 2017-04-20 | Kiseok Suh | Semiconductor device and method of forming the same |
US9929013B2 (en) * | 2016-01-11 | 2018-03-27 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device |
US10043812B1 (en) * | 2017-09-14 | 2018-08-07 | United Microelectronics Corp. | Semiconductive structure with word line and method of fabricating the same |
US20180260510A1 (en) * | 2017-03-09 | 2018-09-13 | United Microelectronics Corp. | Method for forming contact plug layout |
US10388654B2 (en) | 2018-01-11 | 2019-08-20 | Globalfoundries Inc. | Methods of forming a gate-to-source/drain contact structure |
CN111490048A (en) * | 2019-01-25 | 2020-08-04 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
DE102015122667B4 (en) * | 2014-12-26 | 2020-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | CONNECTING STRUCTURE WITH NON-ALIGNMENT METAL LINES CONNECTED BY ANOTHER CONNECTING LAYER |
CN113113303A (en) * | 2021-04-02 | 2021-07-13 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
US11195753B2 (en) * | 2018-09-18 | 2021-12-07 | International Business Machines Corporation | Tiered-profile contact for semiconductor |
DE102010016274B4 (en) | 2009-04-03 | 2022-05-05 | Samsung Electronics Co., Ltd. | semiconductor device |
EP3971975A4 (en) * | 2019-12-10 | 2023-01-11 | Changxin Memory Technologies, Inc. | Semiconductor device and manufacturing method therefor |
WO2024051689A1 (en) * | 2022-09-06 | 2024-03-14 | International Business Machines Corporation | Buried metal signal rail for memory arrays |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101024771B1 (en) | 2008-12-24 | 2011-03-24 | 주식회사 하이닉스반도체 | Semiconductor having buried wordline and method for manufacturing the same |
US20130310517A1 (en) | 2012-05-17 | 2013-11-21 | Xerox Corporation | Methods for manufacturing curable inks for digital offset printing applications and the inks made therefrom |
US9868873B2 (en) | 2012-05-17 | 2018-01-16 | Xerox Corporation | Photochromic security enabled ink for digital offset printing applications |
US9611403B2 (en) | 2012-05-17 | 2017-04-04 | Xerox Corporation | Fluorescent security enabled ink for digital offset printing applications |
US9499701B2 (en) | 2013-05-17 | 2016-11-22 | Xerox Corporation | Water-dilutable inks and water-diluted radiation curable inks useful for ink-based digital printing |
US9745484B2 (en) | 2013-09-16 | 2017-08-29 | Xerox Corporation | White ink composition for ink-based digital printing |
US9724909B2 (en) | 2013-12-23 | 2017-08-08 | Xerox Corporation | Methods for ink-based digital printing with high ink transfer efficiency |
US10113076B2 (en) | 2014-09-30 | 2018-10-30 | Xerox Corporation | Inverse emulsion acrylate ink compositions for ink-based digital lithographic printing |
US9956760B2 (en) | 2014-12-19 | 2018-05-01 | Xerox Corporation | Multilayer imaging blanket coating |
US9815992B2 (en) | 2015-01-30 | 2017-11-14 | Xerox Corporation | Acrylate ink compositions for ink-based digital lithographic printing |
US9890291B2 (en) | 2015-01-30 | 2018-02-13 | Xerox Corporation | Acrylate ink compositions for ink-based digital lithographic printing |
US10323154B2 (en) | 2015-02-11 | 2019-06-18 | Xerox Corporation | White ink composition for ink-based digital printing |
US9751326B2 (en) | 2015-02-12 | 2017-09-05 | Xerox Corporation | Hyperbranched ink compositions for controlled dimensional change and low energy curing |
US9956757B2 (en) | 2015-03-11 | 2018-05-01 | Xerox Corporation | Acrylate ink compositions for ink-based digital lithographic printing |
US9744757B1 (en) | 2016-08-18 | 2017-08-29 | Xerox Corporation | Methods for rejuvenating an imaging member of an ink-based digital printing system |
KR102459430B1 (en) * | 2018-01-08 | 2022-10-27 | 삼성전자주식회사 | Semiconductor devices and method for fabricating the same |
US10535378B1 (en) | 2018-07-19 | 2020-01-14 | Micron Technology, Inc. | Integrated assemblies which include non-conductive-semiconductor-material and conductive-semiconductor-material, and methods of forming integrated assemblies |
US10438953B1 (en) * | 2018-07-24 | 2019-10-08 | Micron Technology, Inc. | Integrated circuitry construction, a DRAM construction, and a method used in forming an integrated circuitry construction |
US11939478B2 (en) | 2020-03-10 | 2024-03-26 | Xerox Corporation | Metallic inks composition for digital offset lithographic printing |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4443868A (en) * | 1980-11-04 | 1984-04-17 | Fujitsu Limited | Semiconductor memory device |
US5736761A (en) * | 1995-05-24 | 1998-04-07 | Siemens Aktiengesellschaft | DRAM cell arrangement and method for its manufacture |
US20010025973A1 (en) * | 2000-01-25 | 2001-10-04 | Satoru Yamada | Semiconductor integrated circuit device and process for manufacturing the same |
US20010053577A1 (en) * | 1997-07-08 | 2001-12-20 | Leonard Forbes | Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines |
US20030011032A1 (en) * | 2000-12-14 | 2003-01-16 | Taku Umebayashi | Semiconductor device and it's manufacturing method |
US6657255B2 (en) * | 2001-10-30 | 2003-12-02 | General Semiconductor, Inc. | Trench DMOS device with improved drain contact |
US6689660B1 (en) * | 1997-07-08 | 2004-02-10 | Micron Technology, Inc. | 4 F2 folded bit line DRAM cell structure having buried bit and word lines |
US20050048714A1 (en) * | 1998-12-03 | 2005-03-03 | Noble Wendell P. | Trench DRAM cell with vertical device and buried word lines |
US20050255661A1 (en) * | 2004-05-13 | 2005-11-17 | Ryota Katsumata | Semiconductor device and manufacturing method therefor |
US20060046398A1 (en) * | 2004-09-01 | 2006-03-02 | Micron Technology, Inc. | Low resistance peripheral local interconnect contacts with selective wet strip of titanium |
US7034408B1 (en) * | 2004-12-07 | 2006-04-25 | Infineon Technologies, Ag | Memory device and method of manufacturing a memory device |
US20060128070A1 (en) * | 2003-03-10 | 2006-06-15 | Samsung Electronics Co., Ltd. | Non-volatile memory device and fabricating method thereof |
US20060214209A1 (en) * | 2005-03-25 | 2006-09-28 | Doyle Daniel H | High density semiconductor memory and method of making |
US20060244024A1 (en) * | 2005-05-02 | 2006-11-02 | Dirk Manger | Memory cell array and method of manufacturing the same |
US20060270159A1 (en) * | 2005-05-27 | 2006-11-30 | Rolf Weis | Method of forming a memory cell array and a memory cell array |
US20060291321A1 (en) * | 2005-06-24 | 2006-12-28 | Monolithic System Technology, Inc. | Word line driver for DRAM embedded in a logic process |
US20070215920A1 (en) * | 2006-03-07 | 2007-09-20 | Infineon Technologies Ag | Semiconductor component arrangement comprising a trench transistor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100273678B1 (en) * | 1997-06-30 | 2000-12-15 | 김영환 | Memory device and method for fabricating the same |
JP3413569B2 (en) * | 1998-09-16 | 2003-06-03 | 株式会社日立製作所 | Insulated gate semiconductor device and method of manufacturing the same |
JP4854868B2 (en) | 2001-06-14 | 2012-01-18 | ローム株式会社 | Semiconductor device |
KR100390915B1 (en) * | 2001-06-29 | 2003-07-12 | 주식회사 하이닉스반도체 | Method for forming metal line in semiconductor device |
US6754131B2 (en) * | 2002-08-29 | 2004-06-22 | Micron Technology, Inc. | Word line driver for negative voltage |
KR101051158B1 (en) | 2004-03-04 | 2011-07-21 | 주식회사 하이닉스반도체 | Method of manufacturing MOSPF |
KR100675288B1 (en) * | 2005-11-04 | 2007-01-29 | 삼성전자주식회사 | Fabrication methods of semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby |
-
2006
- 2006-08-24 KR KR1020060080700A patent/KR100782488B1/en active IP Right Grant
-
2007
- 2007-08-21 US US11/842,416 patent/US20080048333A1/en not_active Abandoned
-
2012
- 2012-05-17 US US13/473,751 patent/US8895400B2/en active Active
Patent Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4443868A (en) * | 1980-11-04 | 1984-04-17 | Fujitsu Limited | Semiconductor memory device |
US5736761A (en) * | 1995-05-24 | 1998-04-07 | Siemens Aktiengesellschaft | DRAM cell arrangement and method for its manufacture |
US6689660B1 (en) * | 1997-07-08 | 2004-02-10 | Micron Technology, Inc. | 4 F2 folded bit line DRAM cell structure having buried bit and word lines |
US20010053577A1 (en) * | 1997-07-08 | 2001-12-20 | Leonard Forbes | Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines |
US6465298B2 (en) * | 1997-07-08 | 2002-10-15 | Micron Technology, Inc. | Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines |
US20050048714A1 (en) * | 1998-12-03 | 2005-03-03 | Noble Wendell P. | Trench DRAM cell with vertical device and buried word lines |
US6770535B2 (en) * | 2000-01-25 | 2004-08-03 | Hitachi, Ltd. | Semiconductor integrated circuit device and process for manufacturing the same |
US20010025973A1 (en) * | 2000-01-25 | 2001-10-04 | Satoru Yamada | Semiconductor integrated circuit device and process for manufacturing the same |
US20030011032A1 (en) * | 2000-12-14 | 2003-01-16 | Taku Umebayashi | Semiconductor device and it's manufacturing method |
US6657255B2 (en) * | 2001-10-30 | 2003-12-02 | General Semiconductor, Inc. | Trench DMOS device with improved drain contact |
US20060128070A1 (en) * | 2003-03-10 | 2006-06-15 | Samsung Electronics Co., Ltd. | Non-volatile memory device and fabricating method thereof |
US20050255661A1 (en) * | 2004-05-13 | 2005-11-17 | Ryota Katsumata | Semiconductor device and manufacturing method therefor |
US20060046398A1 (en) * | 2004-09-01 | 2006-03-02 | Micron Technology, Inc. | Low resistance peripheral local interconnect contacts with selective wet strip of titanium |
US7034408B1 (en) * | 2004-12-07 | 2006-04-25 | Infineon Technologies, Ag | Memory device and method of manufacturing a memory device |
US20060214209A1 (en) * | 2005-03-25 | 2006-09-28 | Doyle Daniel H | High density semiconductor memory and method of making |
US20060244024A1 (en) * | 2005-05-02 | 2006-11-02 | Dirk Manger | Memory cell array and method of manufacturing the same |
US20060270159A1 (en) * | 2005-05-27 | 2006-11-30 | Rolf Weis | Method of forming a memory cell array and a memory cell array |
US20060291321A1 (en) * | 2005-06-24 | 2006-12-28 | Monolithic System Technology, Inc. | Word line driver for DRAM embedded in a logic process |
US20070215920A1 (en) * | 2006-03-07 | 2007-09-20 | Infineon Technologies Ag | Semiconductor component arrangement comprising a trench transistor |
Cited By (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7462903B1 (en) * | 2005-09-14 | 2008-12-09 | Spansion Llc | Methods for fabricating semiconductor devices and contacts to semiconductor devices |
US20100221875A1 (en) * | 2007-02-21 | 2010-09-02 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same |
US9299827B2 (en) | 2007-02-21 | 2016-03-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gates having connection lines thereon |
US8872262B2 (en) * | 2007-02-21 | 2014-10-28 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gates having connection lines thereon |
US20100193880A1 (en) * | 2007-09-18 | 2010-08-05 | Makoto Yoshida | Semiconductor device and method of forming the same |
US8450786B2 (en) | 2007-09-18 | 2013-05-28 | Samsung Electronics Co., Ltd. | Semiconductor devices including buried gate electrodes |
US8766356B2 (en) | 2007-09-18 | 2014-07-01 | Samsung Electronics Co., Ltd. | Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon |
US8063425B2 (en) | 2007-09-18 | 2011-11-22 | Samsung Electronics Co., Ltd. | Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same |
US8120123B2 (en) * | 2007-09-18 | 2012-02-21 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
US20090072289A1 (en) * | 2007-09-18 | 2009-03-19 | Dae-Ik Kim | Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same |
US20100102371A1 (en) * | 2008-10-27 | 2010-04-29 | Yeom Kye-Hee | Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning |
US8486818B2 (en) * | 2008-10-27 | 2013-07-16 | Samsung Electronics Co., Ltd. | Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning |
US20100193901A1 (en) * | 2009-01-30 | 2010-08-05 | Se-Aug Jang | Semiconductor device and method for fabricating the same |
US8736017B2 (en) * | 2009-01-30 | 2014-05-27 | SK Hynix Inc. | Semiconductor device and method for fabricating the same |
DE102010016274B4 (en) | 2009-04-03 | 2022-05-05 | Samsung Electronics Co., Ltd. | semiconductor device |
US20110020993A1 (en) * | 2009-07-23 | 2011-01-27 | Jong-Man Park | Semiconductor Device and Method of Fabricating the Same |
US8169074B2 (en) | 2009-07-23 | 2012-05-01 | Samsung Electronics Co., Ltd. | Semiconductor devices including first and second silicon interconnection regions |
US8502341B2 (en) * | 2010-02-26 | 2013-08-06 | Samsung Electronics Co., Ltd. | Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device |
US20110210421A1 (en) * | 2010-02-26 | 2011-09-01 | Chul Lee | Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device |
US9786600B2 (en) | 2010-04-06 | 2017-10-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and peripheral transistor |
US8461687B2 (en) * | 2010-04-06 | 2013-06-11 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same |
US20110241102A1 (en) * | 2010-04-06 | 2011-10-06 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and buried channel array transistor, methods of fabricating the same, and semiconductor modules, electronic circuit boards and electronic systems including the same |
US9231104B2 (en) | 2010-04-06 | 2016-01-05 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and peripheral transistor |
US8901645B2 (en) | 2010-04-06 | 2014-12-02 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and peripheral transitor |
US8618605B2 (en) * | 2010-07-06 | 2013-12-31 | Hynix Semiconductor Inc. | Semiconductor device and method of manufacturing the same |
US20120007186A1 (en) * | 2010-07-06 | 2012-01-12 | Hynix Semiconductor Inc. | Semiconductor device and method of manufacturing the same |
US20120286354A1 (en) * | 2011-05-11 | 2012-11-15 | Hynix Semiconductor Inc. | Semiconductor device and method of manufacturing the same |
US8823086B2 (en) * | 2011-05-11 | 2014-09-02 | Hynix Semiconductor Inc. | Semiconductor device and method of manufacturing the same |
US20130040408A1 (en) * | 2011-08-11 | 2013-02-14 | KyungTae Nam | Method of fabricating resistance variable memory device and devices and systems formed thereby |
US20130137270A1 (en) * | 2011-11-24 | 2013-05-30 | Powerchip Technology Corporation | Method for forming contact hole |
US8709946B2 (en) * | 2011-11-24 | 2014-04-29 | Powerchip Technology Corporation | Method for forming contact hole |
US8951920B2 (en) | 2011-12-11 | 2015-02-10 | Globalfoundries Inc. | Contact landing pads for a semiconductor device and methods of making same |
US9064733B2 (en) | 2012-11-30 | 2015-06-23 | Globalfoundries Inc. | Contact structure for a semiconductor device and methods of making same |
US8956928B2 (en) | 2012-11-30 | 2015-02-17 | Globalfoundries Inc | Contact structure for a semiconductor device and methods of making same |
US8823149B2 (en) * | 2012-12-11 | 2014-09-02 | Globalfoundries Inc. | Contact landing pads for a semiconductor device and methods of making same |
US9240415B2 (en) | 2013-07-05 | 2016-01-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of forming the same |
US20160093710A1 (en) * | 2014-01-02 | 2016-03-31 | SK Hynix Inc. | Semiconductor device and method for forming the same |
US9236439B2 (en) * | 2014-01-02 | 2016-01-12 | SK Hynix Inc. | Semiconductor device and method for forming the same |
US20150187899A1 (en) * | 2014-01-02 | 2015-07-02 | SK Hynix Inc. | Semiconductor device and method for forming the same |
DE102015122667B4 (en) * | 2014-12-26 | 2020-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | CONNECTING STRUCTURE WITH NON-ALIGNMENT METAL LINES CONNECTED BY ANOTHER CONNECTING LAYER |
EP3139405A1 (en) * | 2015-09-01 | 2017-03-08 | IMEC vzw | Buried interconnect for semicondutor circuits |
US20170110507A1 (en) * | 2015-10-20 | 2017-04-20 | Kiseok Suh | Semiconductor device and method of forming the same |
US9911787B2 (en) * | 2015-10-20 | 2018-03-06 | Samsung Electronics Co, Ltd. | Semiconductor device and method of forming the same |
US9929013B2 (en) * | 2016-01-11 | 2018-03-27 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device |
US10169521B2 (en) * | 2017-03-09 | 2019-01-01 | United Microelectronics Corp. | Method for forming contact plug layout |
US20180260510A1 (en) * | 2017-03-09 | 2018-09-13 | United Microelectronics Corp. | Method for forming contact plug layout |
US10043812B1 (en) * | 2017-09-14 | 2018-08-07 | United Microelectronics Corp. | Semiconductive structure with word line and method of fabricating the same |
US10388654B2 (en) | 2018-01-11 | 2019-08-20 | Globalfoundries Inc. | Methods of forming a gate-to-source/drain contact structure |
US11195753B2 (en) * | 2018-09-18 | 2021-12-07 | International Business Machines Corporation | Tiered-profile contact for semiconductor |
US20220068713A1 (en) * | 2018-09-18 | 2022-03-03 | International Business Machines Corporation | Tiered-Profile Contact for Semiconductor |
CN111490048A (en) * | 2019-01-25 | 2020-08-04 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
US11094586B2 (en) * | 2019-01-25 | 2021-08-17 | Samsung Electronics Co., Ltd. | Semiconductor device including interconnections having different structures and method of fabricating the same |
EP3971975A4 (en) * | 2019-12-10 | 2023-01-11 | Changxin Memory Technologies, Inc. | Semiconductor device and manufacturing method therefor |
CN113113303A (en) * | 2021-04-02 | 2021-07-13 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
WO2024051689A1 (en) * | 2022-09-06 | 2024-03-14 | International Business Machines Corporation | Buried metal signal rail for memory arrays |
Also Published As
Publication number | Publication date |
---|---|
US8895400B2 (en) | 2014-11-25 |
KR100782488B1 (en) | 2007-12-05 |
US20120264280A1 (en) | 2012-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8895400B2 (en) | Methods of fabricating semiconductor devices having buried word line interconnects | |
KR100650468B1 (en) | A semiconductor integrated circuit device and a method of manufacture thereof | |
US7713873B2 (en) | Methods of forming contact structures semiconductor devices | |
US7799643B2 (en) | Method of fabricating semiconductor device having self-aligned contact plug | |
US8344517B2 (en) | Integrated circuit devices including air spacers separating conductive structures and contact plugs and methods of fabricating the same | |
US6413821B1 (en) | Method of fabricating semiconductor device including nonvolatile memory and peripheral circuit | |
US6891271B2 (en) | Non-volatile memory device | |
US7435634B2 (en) | Methods of forming semiconductor devices having stacked transistors | |
US6518124B1 (en) | Method of fabricating semiconductor device | |
US9299827B2 (en) | Semiconductor integrated circuit devices including gates having connection lines thereon | |
US9209192B2 (en) | Semiconductor device and method of fabricating the same | |
US20050029664A1 (en) | Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof | |
US8610189B2 (en) | Semiconductor device enabling further microfabrication | |
US20050095794A1 (en) | Method of fabricating recess channel array transistor | |
US20070138599A1 (en) | Semiconductor device having a single sidewall fin field effect transistor and method for fabricating the same | |
US8592978B2 (en) | Method of fabricating semiconductor device and the semiconductor device | |
US11251188B2 (en) | Semiconductor memory device and a method of fabricating the same | |
KR100335121B1 (en) | Semiconductor memory device and method for fabricating the same | |
US10147728B1 (en) | Semiconductor device and method for fabricating the same | |
JP2008205379A (en) | Nonvolatile semiconductor memory and its production process | |
US7956440B2 (en) | Capacitor and semiconductor device including the same | |
US7846825B2 (en) | Method of forming a contact hole and method of manufacturing a semiconductor device having the same | |
JP2008166330A (en) | Semiconductor device | |
JP4439429B2 (en) | Manufacturing method of semiconductor device | |
KR19990071432A (en) | Dynamic semiconductor memory device and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SEO, HYEOUNG WON;KIM, YUN GI;SON, YOUNG WOONG;AND OTHERS;REEL/FRAME:019723/0774 Effective date: 20070608 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |