US20070157146A1 - Method of packing-based macro placement and semiconductor chip using the same - Google Patents

Method of packing-based macro placement and semiconductor chip using the same Download PDF

Info

Publication number
US20070157146A1
US20070157146A1 US11/608,417 US60841706A US2007157146A1 US 20070157146 A1 US20070157146 A1 US 20070157146A1 US 60841706 A US60841706 A US 60841706A US 2007157146 A1 US2007157146 A1 US 2007157146A1
Authority
US
United States
Prior art keywords
packing
macro
macros
placement
tree
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/608,417
Other languages
English (en)
Inventor
Tung-Chieh Chen
Ping-Hung Yu
Yao-Wen Chang
Fwu-Juh Huang
Tien-Yueh Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US11/608,417 priority Critical patent/US20070157146A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, FWU-JUH, LIU, TIEN-YUEH, YU, PING-HUNG, CHANG, YAO-WEN, CHEN, TUNG-CHIEH
Publication of US20070157146A1 publication Critical patent/US20070157146A1/en
Priority to US12/571,576 priority patent/US8661388B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/392Floor-planning or layout, e.g. partitioning or placement

Definitions

  • the invention relates to mixed-size design of integrated circuits and, in particular, to packing-based macro placement.
  • a first type of mixed-size placement algorithm places macros and standard cells simultaneously, which typically does not consider macro orientations and requires a robust macro legalizer to remove overlaps if macros/cells are not distributed evenly.
  • a simulated annealing based multilevel placer mPG-MS disclosed in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference by C.-C. Chang et. al in 2003, fixes macros level by level from large macros to small macros.
  • a min-cut based pacer Feng Shui disclosed in Proceedings of ACM International Symposium on Physical Design by A. Khatkhate et. al in 2004, considers standard cells and macros simultaneously using a fractional cut technique, which allows horizontal cut lines to not align with row boundaries.
  • APlace disclosed in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design by A. B. Kagng et. al in 2004, uses a bell-shaped potential function considering macro heights/widths based on non-linear programming to determine a global placement which evenly distributes macros/cells.
  • mPL disclosed in Proceedings of ACM International Symposium on Physical Design by T. Chan et. al in 2005, uses a generalized force-directed method for placement.
  • UPlace disclosed in Proceedings of ACM International Symposium on Physical Design by B. Yao et. al in 2005, uses quadratic programming and a discrete cosine transformation method to distribute macro/cells evenly, and a zone refinement technique for legalization is then applied.
  • a second type combines floorplanning and placement techniques.
  • a min-cut floorplacer Capo disclosed in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design in 2004, is an example.
  • the fixed-outline floorplanning is applied when necessary during min-cut placement to find allowable positions for macros. Embedded into a placement flow, floorplacement can consider macro orientations and find legal solutions more easily.
  • a third type separates the mixed-size placement into two stages, macro placement and standard-cell placement. Macro positions are determined before standard cells are placed into the rest area.
  • a combinational technique is disclosed in ACM Transactions on Design Automation of Electronic Systems by S. N. Adya in 2005. A standard cell placer is used to obtain an initial placement. Standard cells are clustered as several soft macros based on the initial placement, and fixed-outline floorplanning is applied to find an overlap-free macro placement. Then, macros are fixed and standard cells replaced using a standard cell placer in the remaining space.
  • the two-stage mixed-size placement is more robust since it guarantees a feasible solution as long as an overlap-free macro placement is obtained.
  • macro orientations and placement constraints such as pre-placed macros and placement blockages, can be easily handled.
  • An embodiment of a semiconductor chip comprises first and second groups of macros.
  • the first and second groups of macros are respectively close packed toward first and second directions of the semiconductor chip.
  • Another embodiment of a semiconductor chip comprises first and second groups of macros.
  • the first and second groups of macros are respectively close packed toward first and second edges of the semiconductor chip.
  • Another embodiment of a semiconductor chip comprises first and second groups of macros.
  • the first and second groups of macros are respectively close packed toward first and second corners of the semiconductor chip.
  • An embodiment of a k-level binary multi-packing tree comprises k branch nodes and k+1 packing sub-trees.
  • Each of the k branch nodes corresponds to one level.
  • Each of the k+1 packing sub-trees comprises a group of macros and corresponds to one of the nodes.
  • An embodiment of a method of macro placement comprises creating a k-level binary multi-packing tree as disclosed and packing the macros of each packing sub-tree in a placement region.
  • An embodiment of a multi-packing tree (MPT) macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.
  • the k-level binary multi-packing tree comprises k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros.
  • An embodiment of a mixed-size placement design flow comprises reading initial input files in a LEF/DEF format, performing preliminary macro placement with a conventional macro placer, performing detailed macro placement with the disclosed MPT macro placer, and generating final output files in a DEF format.
  • An embodiment of a cost function for evaluating a macro placement comprises at least one parameter of area of the macro placement, total wirelength of real nets and pseudo nets in the macro placement, total macro displacement from a preliminary macro placement, overlap length of the macro placement, and thickness of the macro placement.
  • the invention provides a multi-packing tree (MPT)-based macro placer which places macros around a boundary of a placement region and reserves a center thereof for standard cells.
  • the MPT macro placer is very fast for operations and packing of binary trees, with only amortized linear time needed to transform an MPT to its corresponding macro placement. As a result, a solution of macro placement is efficiently searched by simulated annealing.
  • the packing techniques are, further, efficient and effective for area minimization, such that the MPT-base macro placer can solve mixed-size placement problems with very large macros and a large number of macros. Since macro orientations and spacing between macros are considered, the MPT-base macro placer leads to significantly shorter wirelength and less congestion than other mixed-size placers.
  • the MPT-base macro placer can also easily function within various placement constraints, such as pre-placed blocks, corner blocks, and placement blockages.
  • the MPT-base macro placer can be combined with state-of-the-art standard cell placers to obtain better mixed-size placement solutions based on a two-stage mixed-size placement flow.
  • FIG. 1 shows a mixed size placement flow chart
  • FIG. 2 shows a Packing-Tree with its four types of packing
  • FIG. 3 shows a general Multi-Packing-Tree
  • FIG. 4 shows an example of packing for a Multi-Packing-tree with a BL-Packing-tree and a BR-Packing-tree
  • FIG. 5A shows a Multi-Packing-tree with four packing sub-trees
  • FIG. 6 shows three dimensions of the cluster matrices
  • FIG. 7 shows the process of handling a placement blockage
  • FIG. 8 shows a rectilinear block sliced into several rectangular blocks
  • FIG. 9A shows a macro placement result and its top/bottom contours
  • FIG. 9B shows a macro placement area corresponding FIG. 9A ;
  • FIG. 10 shows a macro placement flow
  • FIG. 1 shows a mixed size placement flow chart.
  • One feature of the design strategy according to this invention is to place macros around the chip and reverse the chip center to place standard cells. Since macros are usually large and there are routing blockages in the macros, if macros are placed in the chip center they will affect routing very much. The traditional floorplanning techniques cannot directly apply to the macro placement problem since it packs all macros to one corner. To overcome this problem, a new Multi-Packing-tree floorplan representation is proposed based on a new Packing-tree representation to place macros around the chip.
  • a Packing-tree is a binary-tree for modeling non-slicing or slicing floorplan. Each node in the Packing-tree corresponds to a macro block. There are four types of packing of a Packing-tree. BL-, TL-, TR-, and BR-packing pack the blocks to the bottom-left, top-left, top-right, and bottom-right corners, respectively.
  • FIG. 2 is a Packing-tree and its corresponding four packing types of placements. Let (x corner , y corner ) as the coordinate of the corner, (x i , y i ) as the bottom-left coordinate of the block b i , and w i (h i ) as the width (height) of the block b i .
  • the root coordinate of a Packing-tree is at
  • the block b j is above the block b i for BL- and BR-packing, while the block b j is below the block b i for TL- and TR-packing. Therefore, given a Packing-tree, the x-coordinate of all blocks can be determined by traversing the tree once in linear time. Further, y-coordinate can be computed by a contour data structure in amortized constant time similar to a known method. See, e.g., Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu.
  • B*-trees A new representation for non-slicing floorplans, in Proceedings of the ACM/IEEE Design Automation Conference, pages 458-463, 2000. So, the complexity of transforming a Packing-tree to the placement is amortized linear time. Note that B*-tree floorplan representation is a BL-type Packing-tree.
  • a Multi-Packing-tree combines several Packing-trees with different packing types at difference corners.
  • An example of a general Multi-Packing-tree is shown in FIG. 3 .
  • a right-skewed stem is used to combine packing sub-trees for convenience and easy implementation, and the order of sub-Packing trees can be determined by the level of the parent node of packing sub-trees. The smaller the level, the earlier the packing sub-tree packs since the DFS order of tree traversal is used for tree packing. If the parent of two packing sub-trees are the same, the packing sub-tree located at the left-child will be packed first.
  • the general Multi-Packing-tree can be used to model any rectilinear floorplan region with each packing sub-tree packs to one convex corner.
  • the x-coordinates of blocks can be determined by a DFS traversal of the Multi-Packing-tree.
  • two contours are kept, bottom-contour and top-contour, which are initialized according to the bottom-side and the top-side of the given rectilinear region, respectively.
  • All BL- and BR-Packing-trees use one bottom-contour data structure, and all TL- and TR-Packing-trees use on top-contour data structure.
  • FIG. 4 shows an example of packing for a Multi-Packing-tree with a BL-Packing-tree and a BR-Packing-tree.
  • a Multi-Packing-tree is used with four packing sub-tree to handle it, as an example shown in FIG. 5A .
  • the tree is traversed in the depth-first search (DFS) order from the root n 0 . Since n 0 is a stem node, nothing is done and the traversal continues. Then, the left-child of n 0 , n 3 , is the root of the BL-Packing-tree, so b 3 is placed on the bottom-left corner. Since n 3 does not have a left child, n 4 is traversed and the traversal continues.
  • DFS depth-first search
  • the packing sub-trees are traversed in the order of BL-Packing-tree, TL-Packing-tree, TR-Packing-tree, and BR-Packing-tree. After all nodes are traversed, the macro placement shown in FIG. 5B is obtained.
  • Macro clustering can be used to reduce the problem size.
  • the macros with the same height/width within the same group of the design hierarchy are clustered. These macros usually have strong correlation. Clustering macros not only utilizes the area better, but also places strongly correlated macros closer. The cluster dimension is only considered when there is no wasted area.
  • FIG. 6 is an example of a cluster of four blocks, and it has 3 possible dimensions of the cluster matrices, 1 ⁇ 4, 2 ⁇ 2, and 4 ⁇ 1.
  • the blocks are placed according to the current cluster matrix.
  • a branch and bound method is applied to find the best ordering of the blocks based on the placement cost.
  • the placement blockages are given by the user, and no macro can be overlap with the blockages.
  • a new macro block is added and checked if it overlaps with blockages. If it overlaps, the y-coordinate of the block is shifted to the position without overlapping.
  • FIG. 7 gives an example. Adding a new block b 2 , it overlaps with the given placement blockage. The block b 2 is shifted up to avoid overlapping, and the contour is updated according to the position of block b 2 .
  • Pre-placed macros are considered as a placement blockage, and no corresponding node will be generated in the Multi-Packing-tree. It can ensure the positions of pre-placed macros.
  • Corner Macros are described as follows.
  • the analog block is usually fixed at the corner as a corner macro.
  • the node corresponding to the corner block is fixed as the root of the packing sub-tree.
  • the corner macro can be fixed at the corner.
  • Rectilinear Macros is described as follows.
  • a known method can be adopted to handle rectilinear macros for tree-based floorplanning. See, e.g., G.-M. Wu, Y.-C. Chang, and Y.-W. Chang. Rectilinear block placement using B*-trees. ACM Trans. on Design Automation of Electronic Systems, 8(2):188-202, 2003.
  • a rectilinear macro is sliced into several rectangular blocks.
  • the location constraint (LC for short) according to the tree topology is created.
  • the mis-alignemnt situations are fixed to maintain the rectilinear block shape.
  • the rectilinear block is sliced into three rectangular blocks, and n 1 , n 2 , and n 3 nodes keep the LC relation.
  • Multi-Packing-tree can be perturbed to get another Multi-Packing-tree by the following operations:
  • Op1 Rotate a block (cluster).
  • Op2 Resize a cluster.
  • Op3 Move a node in a packing sub-tree to another place.
  • Op4 Swap two nodes within one or two packing sub-trees.
  • a block (cluster) is rotated for a tree node.
  • the clustering dimension of a cluster is changed.
  • Op1 and Op2 do not affect the Multi-Packing-tree structure.
  • a node is selected from a packing sub-tree, and moved to another place of the same or different packing sub-tree.
  • two nodes are selected from one (two) packing sub-tree(s), and swapped.
  • two packing sub-trees are swapped, and it makes the packing order of two packing sub-trees exchanged. Note that the stem structure of a Multi-Packing-tree are fixed and does not effect by any type of operation.
  • ⁇ A+ ⁇ W+ ⁇ D+ ⁇ O+ ⁇ T
  • A is the macro placement area
  • W is the total wirelength
  • D is the total macro displacement
  • O is the vertical overlap length
  • ⁇ , ⁇ , ⁇ , and ⁇ are user-specified weighting parameters.
  • the macro placement area, wirelength, macro displacement, and vertical overlap length are explained in the following paragraphs.
  • the macro placement area is the area under the bottom contour plus the area above the top contour. As shown in FIG. 9A , the contours are plotted in bolded-dashed lines, and the corresponding macro-placement area is shown in FIG. 9B . Minimizing the macro placement area can avoid generating too many island-like standard cell regions, which is surrounding by macros. The routing from this kind of regions to the center of the chip is hard since the many routing blockages are above macro blocks. The routing may be more congestive. Further, the standard cells in this kind of regions need to use longer routing paths to connect to the standard cells located in the chip center, and the timing may be worse.
  • the netlist from the circuit cannot be directly used.
  • the design hierarchy is used, and pseudo nets are created between macro blocks that are in the same design hierarchy group. So, minimizing the total wirelength can keep the macro blocks in the same design hierarchy group closer.
  • the macro placement can be guided by a global placement result.
  • the global placement result does not need to be legal.
  • the given macro positions are extracted, and the macro displacement is added as a penalty of the cost function, so that an optimal macro placement with minimum macro displacement can be found.
  • the Multi-Packing-tree presentation can guarantee no overlaps between top/bottom packing sub-trees. However, the there may exist vertical overlaps between the top contour and the bottom contour. Adding a penalty for the vertical overlap can guide the simulated annealing to find a non-overlap solution.
  • FIG. 10 shows an exemplary macro placement flow. After LEF/DEF files are read, the macros with the same height/width and the same design hierarchy level are first clustered. The cluster dimension is initialized with the one most close to the square, and the final dimension will be selected during simulated annealing optimization.
  • a Multi-Packing-tree with the given number of packing sub-trees is created.
  • Each macro/cluster corresponds to a node in a packing sub-tree. If the initial macro placement is given, the initial packing sub-tree can be assigned to which a node belongs according the nearest corner for the macro. Otherwise, the initial packing sub-tree that a node belongs to is randomly set.
  • Each packing sub-tree is initialized as a complete binary tree.
  • Simulated annealing is used to find the optimal macro placement.
  • a Multi-Packing-tree is perturbed to get another Multi-Packing-tree by the aforementioned operations. After perturbation, the designers can fix the tree structure to satisfy the given macro placement constraints, pack the Multi-Packing-tree, evaluate the macro placement, and decide whether the new solution is acceptable according to the macro placement quality difference and the current temperature of simulated annealing. Then, the Multi-Packing-tree is perturbed again. The simulated annealing continues until the solution is good enough or no better solution can be found, and all blocks/clusters positions are determined.
  • the positions of blocks inside a cluster can be computed according to the matrix dimension of the cluster.
  • the spacing between macros is modified. If the routing resource demand between two macros is higher than the original spacing between macros, the spacing between these two macros is added. Otherwise, the original spacing can be decreased to make the macro placement area smaller. Macro orientation can also be set by horizontal/vertical flipping, so that most pins are closer to the chip center. Then, all macro status is set fixed and the final macro placement is outputted.
  • Table II shows the mixed-size placement and routing results for Feng Shei 5.1, Capo 9.4, the MPT (Multi-Packing-tree) macro placer of the invention integrated with Capo, mPL5, APlace 2.0, and the MPT macro placer of the invention integrated with APlace on the Faraday benchmarks.
  • a leading commercial router is used to route all placement solutions. All placers are run on a 3.2 GHz Pentium 4 Linux workstation with 2 GB RAM.
  • the “HPWL” (half-perimeter wirelength) and WL (routing wirelength) are reported in the database unit.
  • “Viol” gives the number of violations in the routing solutions.
  • the MPT macro placer needs only a few seconds for these benchmarks because the number of macros is small, and the runtimes for macro placement alone are thus not reported.
  • the star sign * in Table II indicates that the placement result has many overlaps, or blocks are outside the placement region and cannot be legalized.
  • the word “NR” in Table II means no result is obtained due to no allowable placement.
  • the min cut placer Feng Shui generates results with many macros/cells outside the chip region.
  • mPL5 does not claim to be a mixed-size placer
  • mPL5 generates high quality solutions for IBM-MS/IBM-MSw Pins benchmarks with mixed-size macros and standard cells. Accordingly, mPL5 placement on the Faraday benchmarks is performed for reference. It is found that mPL5 finds allowable solutions but the quality thereof is not good.
  • APlace generates many overlaps between macros for DSP1, RISC1, and RISC2 and cannot be legalized. As a result, only the HPWLs of its global placement solutions are reported.
  • the min-cut floorplacer Capo finds legal solutions and its HPWLs are better than Feng Shui, and mPL5.
  • the two-stage mixed-size placement approaches utilizing the MPT macro placer according to an embodiment of the invention can determine allowable placement solutions for all the circuits.
  • the MPT macro placer integrated with Capo reduces the respective HPWL and routing wirelength by 8% and 12% on average, compared with Capo alone.
  • the MPT macro placer integrated with APlace generates feasible placement for all the circuits, and the quality is superior to all the mixed-size placers.
  • the HPWL's are respectively reduced by 63%, 35%, and 15%, compared with mPL5, Feng Sui, and Capo.
  • the routing wirelengths are respectively 62%, 68%, and 15% shorter than mPL5, Feng Sui, and Capo. It is also found that as the total macro area increases, HPWL reduction of the placement flow utilizing the MPT macro placer according to an embodiment of the invention increases accordingly. Wirelength reduction is summarized in Table III, illustrating effectiveness of the MPT macro placer.
  • Table IV shows statistics of the mchip benchmark suite.
  • the number of cells ranges from 540 k to 1320 k, and the number of macros from 50 to 380. It is known that only Capo can determine allowable placement with good quality for mixed-size placement with large macros, comparisons of macro placement are made with Capo.
  • the experiment is carried out on a dual Opteron 2.6 GHz machine and begins with running the MPT macro placer and Capo to determine the positions of macros. Thereafter, macros are fixed and standard cells placed using a commercial congestion-driven placer in a fast prototyping mode. A commercial router performs global routing. For fair comparison, the standard cells are placed by the same placer.
  • Table V shows the HPWLs, routing wirelengths (WL), GRC overflows, and maximum overflows.
  • the GRC overflow is the percentage of the global routing cells (GRC's) that have overflow. The larger the value, the more congested the placement.
  • Maximum overflow provides the number of extra tracks assigned for the global routing cell with the maximum overflow.
  • NR in Table V indicates no placement result is obtained for routing due to the segmentation faults in Capo.
  • the MPT macro placer consistently obtains much better wirelengths (HPWL and WL) than Capo's macro placement.
  • HPWL and WL wirelengths
  • Capo's macro placement results in larger GRC overflow and maximum overflow and requires more running time for the cell placement and routing than the MPT macro placer.
  • the invention provides a multi-packing tree (MPT)-based macro placer which places macros around a boundary of a placement region and reserves a center thereof for standard cells.
  • the MPT macro placer is very fast for operations and packing of binary trees, with only amortized linear time needed to transform an MPT to its corresponding macro placement. As a result, a solution of macro placement is efficiently searched by simulated annealing.
  • the packing techniques are, further, efficient and effective for area minimization, such that the MPT-base macro placer can solve mixed-size placement problems with very large macros and a large number of macros. Since macro orientations and spacing between macros are considered, the MPT-base macro placer leads to significantly shorter wirelength and less congestion than other mixed-size placers.
  • the MPT-base macro placer can also easily function within various placement constraints, such as pre-placed blocks, corner blocks, and placement blockages.
  • the MPT-base macro placer can be combined with state-of-the-art standard cell placers to obtain better mixed-size placement solutions based on a two-stage mixed-size placement flow.
US11/608,417 2006-01-03 2006-12-08 Method of packing-based macro placement and semiconductor chip using the same Abandoned US20070157146A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/608,417 US20070157146A1 (en) 2006-01-03 2006-12-08 Method of packing-based macro placement and semiconductor chip using the same
US12/571,576 US8661388B2 (en) 2006-01-03 2009-10-01 Method of packing-based macro placement and semiconductor chip using the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75595406P 2006-01-03 2006-01-03
US11/608,417 US20070157146A1 (en) 2006-01-03 2006-12-08 Method of packing-based macro placement and semiconductor chip using the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/571,576 Continuation US8661388B2 (en) 2006-01-03 2009-10-01 Method of packing-based macro placement and semiconductor chip using the same

Publications (1)

Publication Number Publication Date
US20070157146A1 true US20070157146A1 (en) 2007-07-05

Family

ID=38251406

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/608,417 Abandoned US20070157146A1 (en) 2006-01-03 2006-12-08 Method of packing-based macro placement and semiconductor chip using the same
US12/571,576 Expired - Fee Related US8661388B2 (en) 2006-01-03 2009-10-01 Method of packing-based macro placement and semiconductor chip using the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/571,576 Expired - Fee Related US8661388B2 (en) 2006-01-03 2009-10-01 Method of packing-based macro placement and semiconductor chip using the same

Country Status (4)

Country Link
US (2) US20070157146A1 (ja)
JP (1) JP4474404B2 (ja)
CN (1) CN1996318B (ja)
TW (1) TWI390707B (ja)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110202897A1 (en) * 2008-07-07 2011-08-18 Springsoft, Inc. Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit
US20150012901A1 (en) * 2013-07-05 2015-01-08 National Cheng Kung University Fixed-outline floorplanning approach for mixed-size modules
US20160203254A1 (en) * 2015-01-08 2016-07-14 Mediatek Inc. Methods for reducing congestion region in layout area of ic
US9495501B1 (en) * 2016-01-29 2016-11-15 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US20160335386A1 (en) * 2015-05-11 2016-11-17 Mediatek Inc. Methods for providing macro placement of ic
US20180150583A1 (en) * 2016-11-28 2018-05-31 Ncku Research And Development Foundation Method of macro placement and a non-transitory computer readable medium thereof
US10769341B1 (en) * 2019-04-22 2020-09-08 Ncku Research And Development Foundation Method of placing macro cells and a simulated-evolution-based macro refinement method
US10796053B2 (en) * 2013-11-19 2020-10-06 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
CN112511629A (zh) * 2020-11-30 2021-03-16 上海简苏网络科技有限公司 一种mpt结构的账户树的数据压缩方法及系统
US11227084B2 (en) * 2018-11-14 2022-01-18 Taiwan Semiconductor Manufacturing Company Ltd. Multi-bit standard cell
US20220078021A1 (en) * 2020-09-10 2022-03-10 Thales Aerospace advanced chain of trust
US11288432B2 (en) * 2013-11-19 2022-03-29 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
US11392741B2 (en) 2014-01-28 2022-07-19 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381282B (zh) * 2008-11-13 2013-01-01 Mstar Semiconductor Inc 防止壅塞配置方法及裝置
US8656332B2 (en) * 2009-02-26 2014-02-18 International Business Machines Corporation Automated critical area allocation in a physical synthesized hierarchical design
US8219957B1 (en) * 2010-02-02 2012-07-10 Xilinx, Inc. Global placement legalization for complex packing rules
US8332798B2 (en) * 2011-03-08 2012-12-11 Apple Inc. Using synthesis to place macros
US9436796B2 (en) 2015-02-11 2016-09-06 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for determining common node logical connectivity
US9697320B2 (en) 2015-09-24 2017-07-04 Qualcomm Incorporated Rectilinear macros having non-uniform channel spacing
DE102017127276A1 (de) 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek
US10741539B2 (en) 2017-08-30 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells and variations thereof within a standard cell library
CN113919275A (zh) * 2020-09-21 2022-01-11 台积电(南京)有限公司 用于优化集成电路的布局的方法
TWI828362B (zh) * 2021-10-12 2024-01-01 聯發科技股份有限公司 訓練用於巨集佈置的神經網路的方法及系統
WO2023179498A1 (en) * 2022-03-25 2023-09-28 Mediatek Inc. Action masks for macro placement based on density map calculations
KR102597328B1 (ko) * 2023-01-25 2023-11-02 주식회사 마키나락스 반도체 소자의 배치를 평가하기 위해 2중 클러스터링을 수행하는 방법
KR102602254B1 (ko) * 2023-01-25 2023-11-14 주식회사 마키나락스 반도체 설계와 관련하여 데드 스페이스를 제거하는 방법
KR102597811B1 (ko) * 2023-01-25 2023-11-03 주식회사 마키나락스 매크로 소자로부터의 거리 정보를 고려하여 반도체 소자를 배치하는 방법
KR102597210B1 (ko) * 2023-01-26 2023-11-02 주식회사 마키나락스 매크로 셀들을 그룹화하는 것에 기초하여 반도체를 설계하는 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300019A (en) * 1979-01-09 1981-11-10 Victor Company Of Japan, Limited Method and apparatus for multiplying an electrical signal
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US5661663A (en) * 1995-03-24 1997-08-26 Lsi Logic Corporation Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters
US6262628B1 (en) * 1999-06-23 2001-07-17 Mitsubishi Denki Kabushiki Kaisha Differential amplifier circuit
US7308666B1 (en) * 2004-12-16 2007-12-11 Cadence Design Systems, Inc. Method and an apparatus to improve hierarchical design implementation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02297672A (ja) 1989-05-11 1990-12-10 Nec Corp マイクロコンピュータ
JPH0521760A (ja) 1991-07-09 1993-01-29 Ricoh Co Ltd シーオブゲート対応フロアプラン作成方法及び作成装置
US5815398A (en) * 1996-01-16 1998-09-29 Massachusettes Institute Of Technology Method and apparatus for placing parts in a bounded region
US5930499A (en) * 1996-05-20 1999-07-27 Arcadia Design Systems, Inc. Method for mixed placement of structured and non-structured circuit elements
US6002857A (en) * 1996-11-14 1999-12-14 Avant! Corporation Symbolic constraint-based system for preroute reconstruction following floorplan incrementing
JP3063828B2 (ja) * 1997-03-27 2000-07-12 日本電気株式会社 集積回路の自動概略配線方法
JP3389875B2 (ja) * 1999-03-12 2003-03-24 株式会社トッパンエヌイーシー・サーキットソリューションズ 自動部品配置システム並びに自動部品配置プログラムを記録した記録媒体
JP2000276518A (ja) 1999-03-29 2000-10-06 Nec Ic Microcomput Syst Ltd 論理セルブロックの自動動配置方法
US6308309B1 (en) * 1999-08-13 2001-10-23 Xilinx, Inc. Place-holding library elements for defining routing paths
CN1258729C (zh) * 2003-11-14 2006-06-07 清华大学 基于虚拟模块的大规模混合模式布图方法
CN100347709C (zh) * 2004-07-09 2007-11-07 清华大学 基于最小自由度优先原则的非线性规划布局方法
US7665054B1 (en) * 2005-09-19 2010-02-16 Cadence Design Systems, Inc. Optimizing circuit layouts by configuring rooms for placing devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300019A (en) * 1979-01-09 1981-11-10 Victor Company Of Japan, Limited Method and apparatus for multiplying an electrical signal
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US5661663A (en) * 1995-03-24 1997-08-26 Lsi Logic Corporation Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters
US6262628B1 (en) * 1999-06-23 2001-07-17 Mitsubishi Denki Kabushiki Kaisha Differential amplifier circuit
US7308666B1 (en) * 2004-12-16 2007-12-11 Cadence Design Systems, Inc. Method and an apparatus to improve hierarchical design implementation

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8261223B2 (en) * 2008-07-07 2012-09-04 Springsoft Inc. Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit
US20110202897A1 (en) * 2008-07-07 2011-08-18 Springsoft, Inc. Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit
US20150012901A1 (en) * 2013-07-05 2015-01-08 National Cheng Kung University Fixed-outline floorplanning approach for mixed-size modules
US8966428B2 (en) * 2013-07-05 2015-02-24 National Cheng Kung University Fixed-outline floorplanning approach for mixed-size modules
US11288432B2 (en) * 2013-11-19 2022-03-29 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
US10796053B2 (en) * 2013-11-19 2020-10-06 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
US11392741B2 (en) 2014-01-28 2022-07-19 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
US9940422B2 (en) * 2015-01-08 2018-04-10 Mediatek Inc. Methods for reducing congestion region in layout area of IC
US20160203254A1 (en) * 2015-01-08 2016-07-14 Mediatek Inc. Methods for reducing congestion region in layout area of ic
US9892226B2 (en) * 2015-05-11 2018-02-13 Mediatek Inc. Methods for providing macro placement of IC
US20160335386A1 (en) * 2015-05-11 2016-11-17 Mediatek Inc. Methods for providing macro placement of ic
US20170220722A1 (en) * 2016-01-29 2017-08-03 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US10140409B2 (en) * 2016-01-29 2018-11-27 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US20190026418A1 (en) * 2016-01-29 2019-01-24 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US10685160B2 (en) * 2016-01-29 2020-06-16 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US9495501B1 (en) * 2016-01-29 2016-11-15 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US20180150583A1 (en) * 2016-11-28 2018-05-31 Ncku Research And Development Foundation Method of macro placement and a non-transitory computer readable medium thereof
US10372861B2 (en) * 2016-11-28 2019-08-06 Ncku Research And Development Foundation Method of macro placement and a non-transitory computer readable medium thereof
US11227084B2 (en) * 2018-11-14 2022-01-18 Taiwan Semiconductor Manufacturing Company Ltd. Multi-bit standard cell
US10769341B1 (en) * 2019-04-22 2020-09-08 Ncku Research And Development Foundation Method of placing macro cells and a simulated-evolution-based macro refinement method
US20220078021A1 (en) * 2020-09-10 2022-03-10 Thales Aerospace advanced chain of trust
US11876912B2 (en) * 2020-09-10 2024-01-16 Thales Aerospace advanced chain of trust
CN112511629A (zh) * 2020-11-30 2021-03-16 上海简苏网络科技有限公司 一种mpt结构的账户树的数据压缩方法及系统

Also Published As

Publication number Publication date
TW200727453A (en) 2007-07-16
TWI390707B (zh) 2013-03-21
US20100023910A1 (en) 2010-01-28
CN1996318A (zh) 2007-07-11
CN1996318B (zh) 2010-09-08
JP4474404B2 (ja) 2010-06-02
JP2007188488A (ja) 2007-07-26
US8661388B2 (en) 2014-02-25

Similar Documents

Publication Publication Date Title
US8661388B2 (en) Method of packing-based macro placement and semiconductor chip using the same
US6567967B2 (en) Method for designing large standard-cell base integrated circuits
US6480991B1 (en) Timing-driven global placement based on geometry-aware timing budgets
US6370673B1 (en) Method and system for high speed detailed placement of cells within an integrated circuit design
Viswanathan et al. FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control
US7984410B2 (en) Hierarchy-based analytical placement method for an integrated circuit
US7007258B2 (en) Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout
US7921393B2 (en) Tunneling as a boundary congestion relief mechanism
US6543043B1 (en) Inter-region constraint-based router for use in electronic design automation
Huang et al. NTUplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints
Cong et al. Large-scale circuit placement
US20060190889A1 (en) Circuit floorplanning and placement by look-ahead enabled recursive partitioning
US7966595B1 (en) Method and system for approximate placement in electronic designs
Chen et al. MP-trees: A packing-based macro placement algorithm for mixed-size designs
US20020087939A1 (en) Method for designing large standard-cell based integrated circuits
Brenner et al. BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms
US7603640B2 (en) Multilevel IC floorplanner
Zhong et al. Effective partition-driven placement with simultaneous level processing and global net views
Liu et al. MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs
Roy et al. Satisfying whitespace requirements in top-down placement
US9830416B2 (en) Method for analog circuit placement
Yang et al. A standard-cell placement tool for designs with high row utilization
Ji et al. A quasi-Newton-based floorplanner for fixed-outline floorplanning
US9177090B1 (en) In-hierarchy circuit analysis and modification for circuit instances
Torabi et al. A fast hierarchical adaptive analog routing algorithm based on integer linear programming

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, TUNG-CHIEH;YU, PING-HUNG;CHANG, YAO-WEN;AND OTHERS;REEL/FRAME:018603/0694;SIGNING DATES FROM 20061128 TO 20061130

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION