US20070080405A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- US20070080405A1 US20070080405A1 US11/542,269 US54226906A US2007080405A1 US 20070080405 A1 US20070080405 A1 US 20070080405A1 US 54226906 A US54226906 A US 54226906A US 2007080405 A1 US2007080405 A1 US 2007080405A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims description 65
- 238000002955 isolation Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 38
- 239000011229 interlayer Substances 0.000 description 16
- 229910052759 nickel Inorganic materials 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 8
- 230000001133 acceleration Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000012299 nitrogen atmosphere Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates to semiconductor devices and methods for fabricating the devices, and particularly relates to semiconductor devices including fully-silicided (FUSI) gate electrodes and methods for fabricating the devices.
- FUSI fully-silicided
- a film having a high dielectric constant i.e., a high- ⁇ film
- a gate electrode is fully made of a metal so that reduction of gate leakage current and enhancement of transistor driving ability are both achieved.
- FIGS. 16A and 16B illustrate a full silicidation process in a method for fabricating a conventional MIS transistor.
- FIG. 16A is a cross-sectional view in the gate width direction and
- FIG. 16B is a cross-sectional view in the gate length direction (see, for example, International Electron Device Meeting p. 95, 2004).
- an isolation region 102 is selectively formed in a semiconductor substrate 101 , thereby forming an active region 101 a .
- a gate insulating film 103 and a gate electrode film 104 made of polysilicon are deposited.
- the gate electrode film 104 is patterned such that the ends of the gate electrode film 104 in the gate width direction are located inside the isolation region 102 when viewed from above.
- an offset sidewall 105 is formed on the side of the gate electrode film 104 .
- an extension region 106 and a pocket region 107 having a conductivity different from that of the extension region 106 are sequentially formed below the side of the offset sidewall 105 in the active region 101 a .
- a sidewall 108 is formed at the side of the gate electrode film 104 with the offset sidewall 105 interposed therebetween.
- a source/drain region 109 is formed below the side of the sidewall 108 in the active region 101 a . Then, only an upper portion of the source/drain region 109 is selectively silicided, thereby forming a silicide layer 110 . Subsequently, an interlayer insulating film 111 is formed on the semiconductor substrate 101 and then is planarized by chemical mechanical polishing (CMP) until the gate electrode film 104 is exposed. Thereafter, an upper portion of the gate electrode film 104 is selectively removed by etching.
- CMP chemical mechanical polishing
- a nickel film 112 is deposited by sputtering over the interlayer insulating film 111 and the gate electrode film 104 having a reduced thickness. Subsequently, the nickel film 112 is subjected to heat treatment so that reaction occurs between polysilicon forming the gate electrode film 104 and nickel, thereby forming a gate electrode (FUSI gate electrode) in which the entire gate electrode film 104 is silicided.
- FUSI gate electrode gate electrode
- a semiconductor device has a configuration in which silicon is left on purpose in an end (e.g., a contact region) of a gate electrode located above an isolation region, whereas the gate electrode is fully silicided above an active region.
- a semiconductor device is characterized by including: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region, wherein the gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide region in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.
- depletion occurs in the silicon region remaining in the second portion, so that the gate electrode capacitance is reduced, as compared to the case of siliciding the entire gate electrode.
- the silicon region is located above the isolation region and is apart from the boundary between the active region and the isolation region.
- the silicon region is preferably formed across a portion above the active region.
- the length in a gate length direction of the second portion of the gate electrode is preferably larger than that of the first portion of the gate electrode.
- the length in a gate length direction of the first portion of the gate electrode is preferably equal to that of the second portion of the gate electrode.
- the second portion of the gate electrode is preferably a contact region.
- the silicon region is preferably made of one of polysilicon and amorphous silicon.
- the silicide region is preferably made of nickel silicide.
- the gate insulating film is preferably made of a high-dielectric-constant film.
- a method for fabricating a semiconductor device is characterized by including the steps of: (a) forming an isolation region in a semiconductor substrate, thereby forming an active region surrounded by the isolation region; (b) forming a gate insulating film on the active region; (c) forming a gate electrode film made of silicon across the boundary between the active region and the isolation region adjacent to the active region, after the step (b); (d) forming a metal film on the gate electrode film; and (e) performing heat treatment on the semiconductor substrate, thereby siliciding the gate electrode film with the metal film and forming a gate electrode, wherein in the step (e), the entire region in a thickness direction of a first portion of the gate electrode film located above the active region is silicided, whereas a second portion of the gate electrode film located above the isolation region is silicided with a silicon region left in a portion of the second portion.
- the gate electrode is silicided with metal with a silicon region being left in a portion of an end of the gate electrode, so that depletion occurs in the silicon region. Accordingly, the gate electrode capacitance is reduced, as compared to the case of siliciding the entire gate electrode.
- the gate electrode film is preferably formed such that the length in a gate length direction of the second portion of the gate electrode film is larger than that of the first portion of the gate electrode film.
- the gate electrode film is preferably formed such that the length in a gate length direction of the first portion of the gate electrode film is equal to that of the second portion of the gate electrode film.
- the method of the present invention preferably further includes the step (f) of removing an upper portion of the first portion of the gate electrode film, after the step (c) and before the step (d).
- the method of the present invention preferably further includes the step (g) of removing an upper portion of the metal film located on the second portion of the gate electrode film, after the step (d) and before the step (e).
- the method of the present invention preferably further includes, after the step (c) and before the step (d), the steps of: (h) forming a first sidewall made of a first insulating film on a side face of the gate electrode film; and (i) implanting impurity ions in the active region using the gate electrode film and the first sidewall as a mask after the step (h), thereby forming an extension region in the active region.
- the method of the present invention preferably further includes, after the step (i) and before the step (d), the steps of: (j) forming a second sidewall made of a second insulating film at the side face of the gate electrode film with the first sidewall interposed therebetween; and (k) implanting impurity ions in the active region using the gate electrode film, the first sidewall and the second sidewall as a mask after the step (j), thereby forming a source/drain region in the active region.
- the method of the present invention preferably further includes, after the step (k) and before the step (d), the step (i) of forming a silicide layer on the source/drain region.
- FIGS. 1A and 1B illustrate a semiconductor device according to a first embodiment of the present invention.
- FIG. 1A is a plan view and
- FIG. 1B is a cross-sectional view taken along the line Ib-Ib in FIG. 1A .
- FIGS. 2A through 2D illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.
- FIG. 2A is a cross-sectional view taken along the line IIa-IIa in FIG. 2B
- FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. 2A
- FIG. 2C is a cross-sectional view taken along the line IIc-IIc in FIG. 2D
- FIG. 2D is a cross-sectional view taken along the line IId-IId in FIG. 2C .
- FIGS. 3A through 3D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.
- FIG. 3A is a cross-sectional view taken along the line IIIa-IIIa in FIG. 3 B
- FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb in FIG. 3A
- FIG. 3C is a cross-sectional view taken along the line IIIc-IIIc in FIG. 3D
- FIG. 3D is a cross-sectional view taken along the line IIId-IIId in FIG. 3C .
- FIGS. 4A through 4D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.
- FIG. 4A is a cross-sectional view taken along the line IVa-IVa in FIG. 4B
- FIG. 4B is a cross-sectional view taken along the line IVb-IVb in FIG. 4A
- FIG. 4C is a cross-sectional view taken along the line IVc-IVc in FIG. 4D
- FIG. 4D is a cross-sectional view taken along the line IVd-IVd in FIG. 4C .
- FIGS. 5A through 5D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.
- FIG. 5A is a cross-sectional view taken along the line Va-Va in FIG. 5B
- FIG. 5B is a cross-sectional view taken along the line Vb-Vb in FIG. 5A
- FIG. 5C is a cross-sectional view taken along the line Vc-Vc in FIG. 5D
- FIG. 5D is a cross-sectional view taken along the line Vd-Vd in FIG. 5C .
- FIGS. 6A through 6D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.
- FIG. 6A is a cross-sectional view taken along the line VIa-VIa in FIG. 6B
- FIG. 6B is a cross-sectional view taken along the line VIb-VIb in FIG. 6A
- FIG. 6C is a cross-sectional view taken along the line VIc-VIc in FIG. 6D
- FIG. 6D is a cross-sectional view taken along the line VId-VId in FIG. 6C .
- FIGS. 7A and 7B illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment.
- FIG. 7A is a cross-sectional view taken along the line VIIa-VIIa in FIG. 7B and
- FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb in FIG. 7A .
- FIGS. 8A and 8B illustrate a semiconductor device according to a second embodiment of the present invention.
- FIG. 8A is a plan view and
- FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb in FIG. 8A .
- FIGS. 9A through 9D illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.
- FIG. 9A is a cross-sectional view taken along the line IXa-IXa in FIG. 9B
- FIG. 9B is a cross-sectional view taken along the line IXb-IXb in FIG. 9A
- FIG. 9C is a cross-sectional view taken along the line IXc-IXc in FIG. 9D
- FIG. 9D is a cross-sectional view taken along the line IXd-IXd in FIG. 9C .
- FIGS. 10A through 10D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.
- FIG. 10A is a cross-sectional view taken along the line Xa-Xa in FIG. 10B
- FIG. 10B is a cross-sectional view taken along the line Xb-Xb in FIG. 10A
- FIG. 10C is a cross-sectional view taken along the line Xc-Xc in FIG. 10D
- FIG. 10D is a cross-sectional view taken along the line Xd-Xd in FIG. 1C .
- FIGS. 11A through 11D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.
- FIG. 11A is a cross-sectional view taken along the line XIa-XIa in FIG. 11B
- FIG. 11B is a cross-sectional view taken along the line XIb-XIb in FIG. 11A
- FIG. 11C is a cross-sectional view taken along the line XIc-XIc in FIG. 11D
- FIG. 11D is a cross-sectional view taken along the line XId-XId in FIG. 11C .
- FIGS. 12A through 12D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.
- FIG. 12A is a cross-sectional view taken along the line XIIa-XIIa in FIG. 12B
- FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb in FIG. 12A
- FIG. 12C is a cross-sectional view taken along the line XIIc-XIIc in FIG. 12D
- FIG. 12D is a cross-sectional view taken along the line XIId-XIId in FIG. 12C .
- FIGS. 13A and 13B illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment.
- FIG. 13A is a cross-sectional view taken along the line XIIIa-XIIIa in FIG. 13B and
- FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb in FIG. 13A .
- FIGS. 14A and 14B illustrate a semiconductor device according to a modified example of the second embodiment.
- FIG. 14A is a plan view and
- FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb in FIG. 14A .
- FIGS. 15A through 15D illustrate main portions of cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention.
- FIG. 15A is a cross-sectional view taken along the line XVa-XVa in FIG. 15B
- FIG. 15B is a cross-sectional view taken along the line XVb-XVb in FIG. 15A
- FIG. 15C is a cross-sectional view taken along the line XVc-XVc in FIG. 15D
- FIG. 15D is a cross-sectional view taken along the line XVd-XVd in FIG. 15C .
- FIGS. 16A and 16B illustrate a full silicidation process in a method for fabricating a conventional MIS transistor.
- FIG. 16A is a cross-sectional view in the gate width direction taken along the line XVIa-XVIa in FIG. 16A and
- FIG. 16B is a cross-sectional view in the gate length direction and taken along the line XVIb-XVIb in FIG. 16A .
- FIGS. 1A and 1B illustrate a semiconductor device according to the first embodiment.
- FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line Ib-Ib in FIG. 1A .
- an isolation region 12 of shallow trench isolation (STI) and an active region 11 a surrounded by the isolation region 12 are formed in an upper portion of a semiconductor substrate 11 made of, for example, silicon (Si).
- a silicided gate electrode 15 is formed over the principal surface of the semiconductor substrate 11 to cover the active region 11 a and the isolation region 12 with a gate insulating film 13 of a high- ⁇ film interposed therebetween.
- the high- ⁇ film may be made of hafnium oxide (HfO 2 ), hafnium silicate (HfSiO) or HfSiON, for example.
- An end of the gate electrode 15 located above the isolation region 12 is wider, in the gate length direction, than the other portion of the gate electrode 15 located above the active region 11 a and serves as a contact region 15 a , for example.
- an offset sidewall 16 made of silicon dioxide (SiO 2 ) and a sidewall 17 made of silicon nitride (Si 3 N 4 ) are stacked in this order on the side of the gate electrode 15 .
- This embodiment is characterized in that the entire portion of the gate electrode 15 located above the active region 11 a is silicided, i.e., has a FUSI (fully silicided) structure, and the contact region 15 a is formed above the isolation region 12 with island polysilicon 14 a left in the center thereof.
- the island polysilicon 14 a remains in one end of the gate electrode 15 located above the isolation region 12 , whereas the portion of the gate electrode 15 located above the active region 11 a is fully silicided. Accordingly, depletion occurs in the gate electrode 15 , thus reducing the gate electrode capacitance.
- FIGS. 2A through 2D to FIGS. 7A and 7B illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.
- FIGS. 2A, 2C , 3 A, 3 C, 4 A, 4 C, 5 A, 5 C, 6 A, 6 C and 7 A illustrate cross-sectional structures in the gate width direction.
- FIGS. 2B, 2D , 3 B, 3 D, 4 B, 4 D, 5 B, 5 D, 6 B, 6 D and 7 B illustrate cross-sectional structures in the gate length direction.
- an isolation region 12 of STI is selectively formed in an upper portion of a semiconductor substrate 11 , thereby forming an active region 11 a surrounded by the isolation region 12 .
- a gate insulating film 13 of hafnium oxide with a thickness of 3 nm is formed on the entire principal surface of the semiconductor substrate by, for example, chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- a semiconductor film 14 A of polysilicon with a thickness of 100 nm is formed on the gate insulating film 13 .
- the semiconductor film 14 A may be made of amorphous silicon, instead of polysilicon.
- the semiconductor film 14 A is patterned by lithography and dry etching using an etching gas containing chlorine (Cl 2 ) or hydrogen bromide (HBr) as a main component, thereby forming a gate electrode film 14 .
- the gate electrode film 14 is patterned in such a manner that the middle of the gate electrode film 14 is located above the active region 11 a , both ends thereof are located above the isolation region 12 and the width in the gate length direction of the gate electrode film 14 is large so that one of the ends of the gate electrode film 14 serves as a contact region.
- the width of the contact region of the gate electrode film 14 located above the isolation region 12 is preferably 1.5 times as large as the width of the gate electrode film 14 located above the active region 11 a or more in the gate length direction.
- the width in the gate length direction of the gate electrode film 14 located above the active region 11 a is about 65 nm
- the width of the contact region of the gate electrode film 14 located above the isolation region 12 is set at about 120 nm in consideration of the diameter (e.g., 80 nm) of a contact to be formed and an alignment margin (e.g., 20 nm at each end).
- a TEOS (tetra-ethyl-ortho-silicate) film 16 A with a thickness of 14 nm is formed over the entire surface of the semiconductor substrate 11 including the gate electrode film 14 .
- the TEOS film 16 A is etched by etch back using an etching gas containing fluorocarbon as a main component, thereby forming an offset sidewall 16 out of the TEOS film 16 A on each side of the gate electrode film 14 .
- ions of, for example, arsenic (As) are implanted in the active region 11 a under the conditions that the acceleration energy is 3 keV, the dose is 1.5 ⁇ 10 15 /cm 2 and the tilt angle is 0°, thereby forming an n-type extension region 18 below the side of the offset sidewall 16 in the active region 11 a .
- ions of, for example, boron (B) are implanted in the active region 11 a by four rotation injection under the conditions that the acceleration energy is 10 keV, the dose is 8.0 ⁇ 10 12 /cm 2 and the tile angle of 25°, thereby forming a p-type pocket region 19 under the n-type extension region 18 and below the offset sidewall 16 in the active region 11 a .
- the “four rotation injection” refers to an ion implantation process in which the semiconductor substrate 11 is rotated approximately 90° at each time within the principal surface and ion implantation described above is performed once at every approximately ⁇ 90° rotation.
- a silicon nitride film is deposited by CVD over the entire surface of the semiconductor substrate 11 to cover the gate electrode film 14 and the offset sidewall 16 .
- etch back is performed on the silicon nitride film using an etching gas containing fluorocarbon as a main component, thereby forming a sidewall 17 out of the silicon nitride film at the side of the gate electrode film 14 with the offset sidewall 16 interposed therebetween.
- ions of, for example, arsenic (As) are implanted in the active region 11 a under the conditions that the acceleration energy is 20 keV, the dose is 4.0 ⁇ 10 15 /cm 2 and the tilt angle is 0°.
- ions of, for example, phosphorus (P) are implanted under the conditions that the acceleration energy is 10 keV, the dose is 1.0 ⁇ 10 15 /cm 2 and the tilt angle is 7°, thereby forming an n-type source/drain region 20 below the side of the sidewall 17 in the active region 11 a .
- the n-type source/drain region 20 has an interface deeper than that of the p-type pocket region 19 and is connected to the n-type extension region 18 .
- a protective film 21 made of non-doped silicate glass (NSG) and protecting the gate electrode film 14 is deposited by CVD over the entire surface of the semiconductor substrate 11 to cover the gate electrode film 14 provided with the offset sidewall 16 and the sidewall 17 at its side.
- NSG non-doped silicate glass
- a resist pattern 22 masking the upper surface of the gate electrode film 14 is formed on the protective film 21 by lithography.
- the protective film 21 is removed by etching, thereby exposing the surface of the n-type source/drain region 20 .
- a first metal film made of nickel (Ni) is deposited by sputtering to a thickness of 11 nm over the semiconductor substrate 11 from which the n-type source/drain region 20 is exposed. Then, heat treatment is performed in a nitrogen atmosphere at about 350° C., for example, thereby forming a metal silicide layer 23 made of nickel silicide in an upper portion of the n-type source/drain region 20 . At this time, the gate electrode film 14 made of polysilicon is masked with the protective film 21 , and thus is not silicided.
- the protective film 21 of NSG on the gate electrode film 14 is selectively removed by etching.
- USG undoped silicate glass
- a second metal film 25 made of nickel is deposited by sputtering to a thickness of 95 nm over the interlayer insulating film 24 from which the gate electrode film 14 is exposed.
- the second metal film 25 is subjected to heat treatment in a nitrogen atmosphere at about 520° C., for example, thereby siliciding the gate electrode film 14 .
- a gate electrode 15 formed by fully siliciding a portion of the gate electrode film 14 located above the active region 11 a and made of polysilicon is obtained.
- the width of the contact region 15 a located above the isolation region 12 is larger than the width of the portion of the gate electrode 15 located above the active region 11 a , so that nickel (Ni) is insufficiently supplied.
- island polysilicon 14 a is formed in a self-aligned manner in the contact region 15 a of the gate electrode 15 which is fully silicided above the active region 11 a.
- the island polysilicon 14 a is formed inside the contact region 15 a of the gate electrode 15 located above the isolation region 12 , so that depletion occurs in the gate electrode 15 .
- This depletion reduces the gate electrode capacitance, thus increasing the operation speed of a MIS transistor.
- the thickness (i.e., 95 nm) of the second metal film 25 made of nickel is smaller than the thickness (i.e., 100 nm) of the gate electrode film 14 made of polysilicon.
- nickel (Ni) is insufficient when supplied only from a portion of the second metal film 25 located on the gate electrode film 14 . Therefore, to fully silicide the gate electrode film 14 , it is necessary to also supply nickel from a portion of the second metal film 25 located on the interlayer insulating film 24 .
- the distance from the middle of gate electrode film 14 on the gate insulating film 13 to the portion of the second metal film 25 formed on the interlayer insulating film 24 is short, so that nickel (Ni) is sufficiently supplied from the portion of the second metal film 25 formed on the interlayer insulating film 24 and full silicidation is achieved.
- the distance from the center of the contact region 15 a in the gate electrode film 14 located above the isolation region 12 to the portion of the second metal film 25 formed on the interlayer insulating film 24 is long, so that nickel (Ni) is insufficiently supplied from the portion of the second metal film 25 formed on the interlayer insulating film 24 . Accordingly, the island polysilicon 14 a remains in a lower portion of the center of the contact region 15 a .
- the thickness of the second metal film 25 for forming the island polysilicon 14 a in the contact region 15 a may be equal to or smaller than the thickness of the gate electrode film 14 and is preferably in the range from 60% to 100%, both inclusive.
- the second metal film 25 and the gate electrode film 14 may have the same thickness. In such a case, the entire portion of the second metal film 25 on the gate electrode film 14 does not contribute to silicidation, so that a structure as shown in FIGS. 1A and 1B is obtained.
- the first metal film and the second metal film 25 for silicidation are not necessarily made of nickel, and may be made of cobalt (Co) or tungsten (W).
- FIGS. 8A and 8B illustrate a semiconductor device according to the second embodiment.
- FIG. 8A is a plan view and FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb in FIG. 8A .
- an isolation region 12 of shallow trench isolation (STI) and an active region 11 a surrounded by the isolation region 12 are formed in an upper portion of a semiconductor substrate 11 made of, for example, silicon (Si).
- a silicided gate electrode 15 is formed over the principal surface of the semiconductor substrate 11 across the boundary between the active region 11 a and the isolation region 12 with a gate insulating film 13 of a high- ⁇ film interposed therebetween.
- the high- ⁇ film may be made of hafnium oxide (HfO 2 ), hafnium silicate (HfSiO) or HfSiON, for example.
- An end of the gate electrode 15 located above the isolation region 12 is equal to, in the gate length direction, that of the other portion of the gate electrode 15 located above the active region 11 a and serves as a contact region 15 b , for example.
- an offset sidewall 16 made of silicon dioxide (SiO 2 ) and a sidewall 17 made of silicon nitride (Si 3 N 4 ) are stacked in this order on the side of the gate electrode 15 .
- This embodiment is characterized in that the entire portion of the gate electrode 15 located above the active region 11 a is silicided, i.e., has a FUSI structure, and the island polysilicon 14 b remains in a lower portion the contact region 15 b located above the isolation region 12 . In this manner, the island polysilicon 14 b remains on one end of the gate electrode 15 located above the isolation region 12 , whereas the portion of the gate electrode 15 located above the active region 11 a is fully silicided. Accordingly, depletion occurs in the gate electrode 15 , thus reducing the gate electrode capacitance.
- FIGS. 9A through 9D to FIGS. 13A and 13B illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.
- FIGS. 9A, 9C , 10 A, 10 C, 11 A, 11 C, 12 A, 12 C and 13 A illustrate cross-sectional structures in the gate width direction.
- FIGS. 9B, 9D , 10 B, 10 D, 11 B, 11 D, 12 B, 12 D and 13 B illustrate cross-sectional structures in the gate length direction.
- an isolation region 12 of STI is selectively formed in an upper portion of a semiconductor substrate 11 , thereby forming an active region 11 a surrounded by the isolation region 12 .
- a gate insulating film 13 made of hafnium oxide and having a thickness of 3 nm is formed on the entire principal surface of the semiconductor substrate by, for example, chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- a semiconductor film 14 A of polysilicon with a thickness of 100 nm is formed on the gate insulating film 13 .
- the semiconductor film 14 A may be made of amorphous silicon, instead of polysilicon.
- an insulating film 26 A made of silicon oxide and having a thickness of 50 nm is formed on the semiconductor film 14 A.
- the insulating film 26 A and the semiconductor film 14 A are patterned by lithography and dry etching, thereby forming a protective film 26 and a gate electrode film 14 .
- the gate electrode film 14 have a shape similar to that of the gate electrode 15 illustrated in FIG. 8A and extends in the gate width direction in such a manner that the middle of the gate electrode film 14 is located above the active region 11 a , both ends thereof are located above the isolation region 12 and one of the ends serves as a contact region.
- a TEOS (tetra-ethyl-ortho-silicate) film 16 A with a thickness of 14 nm is formed over the entire surface of the semiconductor substrate 11 including the gate electrode film 14 .
- the TEOS film 16 A is etched by etch back using an etching gas containing fluorocarbon as a main component, thereby forming an offset sidewall 16 out of the TEOS film 16 A on each side of the gate electrode film 14 .
- ions of, for example, arsenic (As) are implanted in the active region 11 a under the conditions that the acceleration energy is 3 keV, the dose is 1.5 ⁇ 10 15 /cm 2 and the tilt angle is 0°, thereby forming an n-type extension region 18 below the side of the offset sidewall 16 in the active region 11 a .
- ions of, for example, boron (B) are implanted in the active region 11 a by four rotation injection under the conditions that the acceleration energy is 10 keV, the dose is 8.0 ⁇ 10 12 /cm 2 and the tile angle is 25°, thereby forming a p-type pocket region 19 under the n-type extension region 18 in the active region 11 a .
- the “four rotation injection” refers to an ion implantation process in which the semiconductor substrate 11 is rotated approximately 90° at each time within the principal surface and ion implantation described above is performed once at every approximately ⁇ 90° rotation.
- a silicon nitride film is deposited by CVD over the entire surface of the semiconductor substrate 11 to cover the gate electrode film 14 and the offset sidewall 16 .
- etch back is performed on the silicon nitride film using an etching gas containing fluorocarbon as a main component, thereby forming a sidewall 17 out of the silicon nitride film at the side of the gate electrode film 14 with the offset sidewall 16 interposed therebetween.
- ions of, for example, arsenic (As) are implanted in the active region 11 a under the conditions that the acceleration energy is 20 keV, the dose is 4.0 ⁇ 10 15 /cm 2 and the tilt angle is 0°.
- ions of, for example, phosphorus (P) are implanted under the conditions that the acceleration energy is 10 keV, the dose is 1.0 ⁇ 10 15 /cm 2 and the tilt angle is 7°, thereby forming an n-type source/drain region 20 below the side of the sidewall 17 in the active region 11 a .
- the n-type source/drain region 20 has an interface deeper than that of the p-type pocket region 19 and is connected to the n-type extension region 18 .
- a first metal film 27 made of nickel (Ni) is deposited by sputtering to a thickness of 11 nm over the semiconductor substrate 11 from which the n-type source/drain region 20 is exposed.
- heat treatment is performed in a nitrogen atmosphere at about 350° C., for example, thereby forming a metal silicide layer 23 made of nickel silicide in an upper portion of the n-type source/drain region 20 .
- the gate electrode film 14 made of polysilicon is masked with the protective film 26 , and thus is not silicided.
- the remaining unreacted first metal film 27 is selectively removed.
- USG undoped silicate glass
- reactive ion etching in which C 5 F 8 , O 2 and Ar are supplied at flow rates of 15 ml/min (standard condition), 18 ml/min (standard condition) and 950 ml/min (standard condition), respectively, the pressure is 6.7 Pa, the RF outputs (T/B) are 1800 W/1500 W, and the substrate temperature is 0° C. may be adopted.
- a resist (not shown) covering a contact region of the gate electrode film 14 located above the isolation region 12 is formed.
- the gate electrode film 14 is etched by dry etching except for a region thereof covered with the resist so that the resultant thickness of the gate electrode film 14 is 40 nm.
- the thickness of the contact region of the gate electrode film 14 is 100 nm, whereas the thickness of a portion of the gate electrode film 14 located above the active region 11 a is 40 nm.
- a second metal film 25 made of nickel is deposited by sputtering to a thickness of 50 nm over the interlayer insulating film 24 from which the gate electrode film 14 is exposed.
- the second metal film 25 is subjected to heat treatment in a nitrogen atmosphere at about 520° C., for example, thereby siliciding the gate electrode film 14 .
- a gate electrode 15 formed by fully siliciding a portion of the gate electrode film 14 located above the active region 11 a and made of polysilicon is obtained.
- the thickness of the contact region 15 b in a portion of the gate electrode film 14 located above the isolation region 12 is larger than the thickness of a portion of the gate electrode film 14 located above the active region 11 a , so that a portion of polysilicon included in the contact region 15 b is not silicided and remains as island polysilicon 14 b.
- the first metal film 27 and the second metal film 25 for silicidation are not necessarily made of nickel, and may be made of cobalt (Co) or tungsten (W).
- FIGS. 14A and 14B illustrate a semiconductor device according to a modified example of the second embodiment.
- FIG. 14A is a plan view and
- FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb in FIG. 14A .
- island polysilicon 14 b is formed above an isolation regions 12 located at each end of an active region 11 a , and the island polysilicon 14 b is formed across the end of the active region 11 a.
- FIGS. 15A through 15D illustrate cross-sectional structures of a main portion in respective process steps of a method for fabricating a semiconductor device according to the third embodiment.
- FIGS. 15A and 15C are cross-sectional views in the gate width direction.
- FIGS. 15B and 15D are cross-sectional views in the gate length direction.
- FIGS. 15A and 15B the same structure as illustrated in FIGS. 12A and 12B is obtained by a method similar to that shown in FIGS. 9A and 9B to FIGS. 12A and 12B .
- a second metal film 25 made of nickel is deposited by sputtering to a thickness of 95 nm over an interlayer insulating film 24 from which a gate electrode film 14 is exposed. Thereafter, a portion of the second metal film 25 located above a contact region of the gate electrode film 14 is selectively etched using, for example, a chlorine gas so that the thickness of this portion of the second metal film 25 is 40 nm. In this manner, a portion of the second metal film 25 located above an active region 11 a has a thickness of 95 nm, whereas the portion of the second metal film 25 located above the contact region of the gate electrode film 14 is 40 nm.
- the second metal film 25 in which the thickness of a portion above the contact region is reduced is subjected to heat treatment in a nitrogen atmosphere at about 520° C., for example, thereby siliciding the gate electrode film 14 .
- a gate electrode 15 formed by fully siliciding a portion of the gate electrode film 14 located above the active region 11 a and made of polysilicon is obtained.
- the thickness of the portion of the second metal film 25 above the contact region for a gate electrode is smaller than the thickness of the portion of the second metal film 25 located above the active region 11 a . Accordingly, a portion of polysilicon in the contact region of the gate electrode film 14 is not silicided and remains as island polysilicon 14 b .
- an end (e.g., the contact region 15 b ) of the gate electrode 15 located above the isolation region 12 and another portion of the gate electrode 15 located above the active region 11 a have the same width in the gate length direction.
- the length in the gate length direction of the end (e.g., the contact region 15 b ) located above the isolation region 12 may be larger than the other portion above the active region 11 a .
- the length in the gate length direction of a portion to be a contact region formed above the isolation region 12 is larger than that of another portion formed above the active region 11 a.
- silicidation is performed with a silicon region left in a portion of a gate electrode located above an isolation region and the gate electrode is fully silicided above an active region. Accordingly, the capacitance of the FUSI gate electrode is reduced. Therefore, the present invention is useful for semiconductor devices including gate electrodes to be fully silicided and methods for fabricating such devices.
Abstract
Description
- The disclosure of Japanese Patent Applications No. 2005-293268 filed in Japan on Oct. 6, 2005 and No. 2006-175777 filed in Japan on Jun. 26, 2006 including specification, drawings and claims is incorporated herein by reference in its entirety.
- The present invention relates to semiconductor devices and methods for fabricating the devices, and particularly relates to semiconductor devices including fully-silicided (FUSI) gate electrodes and methods for fabricating the devices.
- In the field of semiconductor devices, increase of speed and reduction of power consumption are accelerated because of rapid miniaturization of elements in recent years. Accordingly, enhancement of transistor performance is urgently needed. However, conventional miniaturization of elements alone is now insufficient for enhancement of transistor performance.
- In view of this, in a metal insulator semiconductor (MIS) transistor, a film having a high dielectric constant (i.e., a high-κ film) is used as a gate insulating film and a gate electrode is fully made of a metal so that reduction of gate leakage current and enhancement of transistor driving ability are both achieved.
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FIGS. 16A and 16B illustrate a full silicidation process in a method for fabricating a conventional MIS transistor.FIG. 16A is a cross-sectional view in the gate width direction andFIG. 16B is a cross-sectional view in the gate length direction (see, for example, International Electron Device Meeting p. 95, 2004). As illustrated inFIGS. 16A and 16B , first, anisolation region 102 is selectively formed in asemiconductor substrate 101, thereby forming anactive region 101 a. Then, agate insulating film 103 and agate electrode film 104 made of polysilicon are deposited. Thereafter, thegate electrode film 104 is patterned such that the ends of thegate electrode film 104 in the gate width direction are located inside theisolation region 102 when viewed from above. Subsequently, anoffset sidewall 105 is formed on the side of thegate electrode film 104. Using theoffset sidewall 105 and thegate electrode film 104 as a mask, anextension region 106 and apocket region 107 having a conductivity different from that of theextension region 106 are sequentially formed below the side of theoffset sidewall 105 in theactive region 101 a. Thereafter, asidewall 108 is formed at the side of thegate electrode film 104 with theoffset sidewall 105 interposed therebetween. Using thesidewall 108, theoffset sidewall 105 and thegate electrode film 104 as a mask, a source/drain region 109 is formed below the side of thesidewall 108 in theactive region 101 a. Then, only an upper portion of the source/drain region 109 is selectively silicided, thereby forming asilicide layer 110. Subsequently, an interlayerinsulating film 111 is formed on thesemiconductor substrate 101 and then is planarized by chemical mechanical polishing (CMP) until thegate electrode film 104 is exposed. Thereafter, an upper portion of thegate electrode film 104 is selectively removed by etching. Then, anickel film 112 is deposited by sputtering over the interlayerinsulating film 111 and thegate electrode film 104 having a reduced thickness. Subsequently, thenickel film 112 is subjected to heat treatment so that reaction occurs between polysilicon forming thegate electrode film 104 and nickel, thereby forming a gate electrode (FUSI gate electrode) in which the entiregate electrode film 104 is silicided. - However, in the method for fabricating a conventional semiconductor device, full silicidation, i.e., silicidation of the entire gate electrode, causes a problem in which the capacitance of the gate electrode increases.
- It is therefore an object of the present invention to reduce the capacitance of a fully-silicided gate electrode.
- To achieve the object, according to the present invention, a semiconductor device has a configuration in which silicon is left on purpose in an end (e.g., a contact region) of a gate electrode located above an isolation region, whereas the gate electrode is fully silicided above an active region.
- Specifically, a semiconductor device according to the present invention is characterized by including: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region, wherein the gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide region in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.
- In the semiconductor device of the present invention, depletion occurs in the silicon region remaining in the second portion, so that the gate electrode capacitance is reduced, as compared to the case of siliciding the entire gate electrode.
- In the semiconductor device of the present invention, it is preferable that the silicon region is located above the isolation region and is apart from the boundary between the active region and the isolation region.
- In the semiconductor device of the present invention, the silicon region is preferably formed across a portion above the active region.
- In the semiconductor device of the present invention, the length in a gate length direction of the second portion of the gate electrode is preferably larger than that of the first portion of the gate electrode.
- In the semiconductor device of the present invention, the length in a gate length direction of the first portion of the gate electrode is preferably equal to that of the second portion of the gate electrode.
- In the semiconductor device of the present invention, the second portion of the gate electrode is preferably a contact region.
- In the semiconductor device of the present invention, the silicon region is preferably made of one of polysilicon and amorphous silicon.
- In the semiconductor device of the present invention, the silicide region is preferably made of nickel silicide.
- In the semiconductor device of the present invention, the gate insulating film is preferably made of a high-dielectric-constant film.
- A method for fabricating a semiconductor device according to the present invention is characterized by including the steps of: (a) forming an isolation region in a semiconductor substrate, thereby forming an active region surrounded by the isolation region; (b) forming a gate insulating film on the active region; (c) forming a gate electrode film made of silicon across the boundary between the active region and the isolation region adjacent to the active region, after the step (b); (d) forming a metal film on the gate electrode film; and (e) performing heat treatment on the semiconductor substrate, thereby siliciding the gate electrode film with the metal film and forming a gate electrode, wherein in the step (e), the entire region in a thickness direction of a first portion of the gate electrode film located above the active region is silicided, whereas a second portion of the gate electrode film located above the isolation region is silicided with a silicon region left in a portion of the second portion.
- With the method for fabricating a semiconductor device according to the present invention, the gate electrode is silicided with metal with a silicon region being left in a portion of an end of the gate electrode, so that depletion occurs in the silicon region. Accordingly, the gate electrode capacitance is reduced, as compared to the case of siliciding the entire gate electrode.
- In the method of the present invention, in the step (c), the gate electrode film is preferably formed such that the length in a gate length direction of the second portion of the gate electrode film is larger than that of the first portion of the gate electrode film.
- In the method of the present invention, in the step (c), the gate electrode film is preferably formed such that the length in a gate length direction of the first portion of the gate electrode film is equal to that of the second portion of the gate electrode film.
- The method of the present invention preferably further includes the step (f) of removing an upper portion of the first portion of the gate electrode film, after the step (c) and before the step (d).
- The method of the present invention preferably further includes the step (g) of removing an upper portion of the metal film located on the second portion of the gate electrode film, after the step (d) and before the step (e).
- The method of the present invention preferably further includes, after the step (c) and before the step (d), the steps of: (h) forming a first sidewall made of a first insulating film on a side face of the gate electrode film; and (i) implanting impurity ions in the active region using the gate electrode film and the first sidewall as a mask after the step (h), thereby forming an extension region in the active region.
- The method of the present invention preferably further includes, after the step (i) and before the step (d), the steps of: (j) forming a second sidewall made of a second insulating film at the side face of the gate electrode film with the first sidewall interposed therebetween; and (k) implanting impurity ions in the active region using the gate electrode film, the first sidewall and the second sidewall as a mask after the step (j), thereby forming a source/drain region in the active region.
- The method of the present invention preferably further includes, after the step (k) and before the step (d), the step (i) of forming a silicide layer on the source/drain region.
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FIGS. 1A and 1B illustrate a semiconductor device according to a first embodiment of the present invention.FIG. 1A is a plan view andFIG. 1B is a cross-sectional view taken along the line Ib-Ib inFIG. 1A . -
FIGS. 2A through 2D illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.FIG. 2A is a cross-sectional view taken along the line IIa-IIa inFIG. 2B ,FIG. 2B is a cross-sectional view taken along the line IIb-IIb inFIG. 2A ,FIG. 2C is a cross-sectional view taken along the line IIc-IIc inFIG. 2D , andFIG. 2D is a cross-sectional view taken along the line IId-IId inFIG. 2C . -
FIGS. 3A through 3D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.FIG. 3A is a cross-sectional view taken along the line IIIa-IIIa in FIG. 3B,FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb inFIG. 3A ,FIG. 3C is a cross-sectional view taken along the line IIIc-IIIc inFIG. 3D , andFIG. 3D is a cross-sectional view taken along the line IIId-IIId inFIG. 3C . -
FIGS. 4A through 4D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.FIG. 4A is a cross-sectional view taken along the line IVa-IVa inFIG. 4B ,FIG. 4B is a cross-sectional view taken along the line IVb-IVb inFIG. 4A ,FIG. 4C is a cross-sectional view taken along the line IVc-IVc inFIG. 4D , andFIG. 4D is a cross-sectional view taken along the line IVd-IVd inFIG. 4C . -
FIGS. 5A through 5D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.FIG. 5A is a cross-sectional view taken along the line Va-Va inFIG. 5B ,FIG. 5B is a cross-sectional view taken along the line Vb-Vb inFIG. 5A ,FIG. 5C is a cross-sectional view taken along the line Vc-Vc inFIG. 5D , andFIG. 5D is a cross-sectional view taken along the line Vd-Vd inFIG. 5C . -
FIGS. 6A through 6D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.FIG. 6A is a cross-sectional view taken along the line VIa-VIa inFIG. 6B ,FIG. 6B is a cross-sectional view taken along the line VIb-VIb inFIG. 6A ,FIG. 6C is a cross-sectional view taken along the line VIc-VIc inFIG. 6D , andFIG. 6D is a cross-sectional view taken along the line VId-VId inFIG. 6C . -
FIGS. 7A and 7B illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the first embodiment.FIG. 7A is a cross-sectional view taken along the line VIIa-VIIa inFIG. 7B andFIG. 7B is a cross-sectional view taken along the line VIIb-VIIb inFIG. 7A . -
FIGS. 8A and 8B illustrate a semiconductor device according to a second embodiment of the present invention.FIG. 8A is a plan view andFIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb inFIG. 8A . -
FIGS. 9A through 9D illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.FIG. 9A is a cross-sectional view taken along the line IXa-IXa inFIG. 9B ,FIG. 9B is a cross-sectional view taken along the line IXb-IXb inFIG. 9A ,FIG. 9C is a cross-sectional view taken along the line IXc-IXc inFIG. 9D , andFIG. 9D is a cross-sectional view taken along the line IXd-IXd inFIG. 9C . -
FIGS. 10A through 10D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.FIG. 10A is a cross-sectional view taken along the line Xa-Xa inFIG. 10B ,FIG. 10B is a cross-sectional view taken along the line Xb-Xb inFIG. 10A ,FIG. 10C is a cross-sectional view taken along the line Xc-Xc inFIG. 10D , andFIG. 10D is a cross-sectional view taken along the line Xd-Xd inFIG. 1C . -
FIGS. 11A through 11D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.FIG. 11A is a cross-sectional view taken along the line XIa-XIa inFIG. 11B ,FIG. 11B is a cross-sectional view taken along the line XIb-XIb inFIG. 11A ,FIG. 11C is a cross-sectional view taken along the line XIc-XIc inFIG. 11D , andFIG. 11D is a cross-sectional view taken along the line XId-XId inFIG. 11C . -
FIGS. 12A through 12D illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.FIG. 12A is a cross-sectional view taken along the line XIIa-XIIa inFIG. 12B ,FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb inFIG. 12A ,FIG. 12C is a cross-sectional view taken along the line XIIc-XIIc inFIG. 12D , andFIG. 12D is a cross-sectional view taken along the line XIId-XIId inFIG. 12C . -
FIGS. 13A and 13B illustrate cross-sectional structures in respective process steps of the method for fabricating a semiconductor device according to the second embodiment.FIG. 13A is a cross-sectional view taken along the line XIIIa-XIIIa inFIG. 13B andFIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb inFIG. 13A . -
FIGS. 14A and 14B illustrate a semiconductor device according to a modified example of the second embodiment.FIG. 14A is a plan view andFIG. 14B is a cross-sectional view taken along the line XIVb-XIVb inFIG. 14A . -
FIGS. 15A through 15D illustrate main portions of cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention.FIG. 15A is a cross-sectional view taken along the line XVa-XVa inFIG. 15B ,FIG. 15B is a cross-sectional view taken along the line XVb-XVb inFIG. 15A ,FIG. 15C is a cross-sectional view taken along the line XVc-XVc inFIG. 15D , andFIG. 15D is a cross-sectional view taken along the line XVd-XVd inFIG. 15C . -
FIGS. 16A and 16B illustrate a full silicidation process in a method for fabricating a conventional MIS transistor.FIG. 16A is a cross-sectional view in the gate width direction taken along the line XVIa-XVIa inFIG. 16A andFIG. 16B is a cross-sectional view in the gate length direction and taken along the line XVIb-XVIb inFIG. 16A . -
Embodiment 1 - A first embodiment of the present invention will be described with reference to the drawings.
-
FIGS. 1A and 1B illustrate a semiconductor device according to the first embodiment.FIG. 1A is a plan view andFIG. 1B is a cross-sectional view taken along the line Ib-Ib inFIG. 1A . As illustrated inFIGS. 1A and 1B , anisolation region 12 of shallow trench isolation (STI) and anactive region 11 a surrounded by theisolation region 12 are formed in an upper portion of asemiconductor substrate 11 made of, for example, silicon (Si). - As illustrated in
FIG. 1B , asilicided gate electrode 15 is formed over the principal surface of thesemiconductor substrate 11 to cover theactive region 11 a and theisolation region 12 with agate insulating film 13 of a high-κ film interposed therebetween. The high-κ film may be made of hafnium oxide (HfO2), hafnium silicate (HfSiO) or HfSiON, for example. - An end of the
gate electrode 15 located above theisolation region 12 is wider, in the gate length direction, than the other portion of thegate electrode 15 located above theactive region 11 a and serves as acontact region 15 a, for example. - As illustrated in
FIGS. 1A and 1B , an offsetsidewall 16 made of silicon dioxide (SiO2) and asidewall 17 made of silicon nitride (Si3N4) are stacked in this order on the side of thegate electrode 15. - This embodiment is characterized in that the entire portion of the
gate electrode 15 located above theactive region 11 a is silicided, i.e., has a FUSI (fully silicided) structure, and thecontact region 15 a is formed above theisolation region 12 withisland polysilicon 14 a left in the center thereof. In this manner, theisland polysilicon 14 a remains in one end of thegate electrode 15 located above theisolation region 12, whereas the portion of thegate electrode 15 located above theactive region 11 a is fully silicided. Accordingly, depletion occurs in thegate electrode 15, thus reducing the gate electrode capacitance. - Hereinafter, a method for fabricating a semiconductor device thus configured will be described with reference to the drawings.
-
FIGS. 2A through 2D toFIGS. 7A and 7B illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the first embodiment in the order of fabrication.FIGS. 2A, 2C , 3A, 3C, 4A, 4C, 5A, 5C, 6A, 6C and 7A illustrate cross-sectional structures in the gate width direction.FIGS. 2B, 2D , 3B, 3D, 4B, 4D, 5B, 5D, 6B, 6D and 7B illustrate cross-sectional structures in the gate length direction. - First, as illustrated in
FIGS. 2A and 2B , anisolation region 12 of STI is selectively formed in an upper portion of asemiconductor substrate 11, thereby forming anactive region 11 a surrounded by theisolation region 12. Thereafter, agate insulating film 13 of hafnium oxide with a thickness of 3 nm is formed on the entire principal surface of the semiconductor substrate by, for example, chemical vapor deposition (CVD). Subsequently, asemiconductor film 14A of polysilicon with a thickness of 100 nm is formed on thegate insulating film 13. Thesemiconductor film 14A may be made of amorphous silicon, instead of polysilicon. - Next, as illustrated in
FIGS. 2C and 2D , thesemiconductor film 14A is patterned by lithography and dry etching using an etching gas containing chlorine (Cl2) or hydrogen bromide (HBr) as a main component, thereby forming agate electrode film 14. As illustrated inFIG. 1A , thegate electrode film 14 is patterned in such a manner that the middle of thegate electrode film 14 is located above theactive region 11 a, both ends thereof are located above theisolation region 12 and the width in the gate length direction of thegate electrode film 14 is large so that one of the ends of thegate electrode film 14 serves as a contact region. In this case, the width of the contact region of thegate electrode film 14 located above theisolation region 12 is preferably 1.5 times as large as the width of thegate electrode film 14 located above theactive region 11 a or more in the gate length direction. For example, if the width in the gate length direction of thegate electrode film 14 located above theactive region 11 a is about 65 nm, the width of the contact region of thegate electrode film 14 located above theisolation region 12 is set at about 120 nm in consideration of the diameter (e.g., 80 nm) of a contact to be formed and an alignment margin (e.g., 20 nm at each end). Subsequently, a TEOS (tetra-ethyl-ortho-silicate)film 16A with a thickness of 14 nm is formed over the entire surface of thesemiconductor substrate 11 including thegate electrode film 14. - Then, as illustrated in
FIGS. 3A and 3B , theTEOS film 16A is etched by etch back using an etching gas containing fluorocarbon as a main component, thereby forming an offsetsidewall 16 out of theTEOS film 16A on each side of thegate electrode film 14. Using thegate electrode film 14 and the offsetsidewall 16 as a mask, ions of, for example, arsenic (As) are implanted in theactive region 11 a under the conditions that the acceleration energy is 3 keV, the dose is 1.5×1015/cm2 and the tilt angle is 0°, thereby forming an n-type extension region 18 below the side of the offsetsidewall 16 in theactive region 11 a. Thereafter, ions of, for example, boron (B) are implanted in theactive region 11 a by four rotation injection under the conditions that the acceleration energy is 10 keV, the dose is 8.0×1012/cm2 and the tile angle of 25°, thereby forming a p-type pocket region 19 under the n-type extension region 18 and below the offsetsidewall 16 in theactive region 11 a. The “four rotation injection” refers to an ion implantation process in which thesemiconductor substrate 11 is rotated approximately 90° at each time within the principal surface and ion implantation described above is performed once at every approximately −90° rotation. - Thereafter, as illustrated in
FIGS. 3C and 3D , a silicon nitride film is deposited by CVD over the entire surface of thesemiconductor substrate 11 to cover thegate electrode film 14 and the offsetsidewall 16. Subsequently, etch back is performed on the silicon nitride film using an etching gas containing fluorocarbon as a main component, thereby forming asidewall 17 out of the silicon nitride film at the side of thegate electrode film 14 with the offsetsidewall 16 interposed therebetween. Using thegate electrode film 14, the offsetsidewall 16 and thesidewall 17 as a mask, ions of, for example, arsenic (As) are implanted in theactive region 11 a under the conditions that the acceleration energy is 20 keV, the dose is 4.0×1015/cm2 and the tilt angle is 0°. Subsequently, ions of, for example, phosphorus (P) are implanted under the conditions that the acceleration energy is 10 keV, the dose is 1.0×1015/cm2 and the tilt angle is 7°, thereby forming an n-type source/drain region 20 below the side of thesidewall 17 in theactive region 11 a. The n-type source/drain region 20 has an interface deeper than that of the p-type pocket region 19 and is connected to the n-type extension region 18. - Subsequently, as illustrated in
FIGS. 4A and 4B , aprotective film 21 made of non-doped silicate glass (NSG) and protecting thegate electrode film 14 is deposited by CVD over the entire surface of thesemiconductor substrate 11 to cover thegate electrode film 14 provided with the offsetsidewall 16 and thesidewall 17 at its side. - Then, as illustrated in
FIGS. 4C and 4D , a resistpattern 22 masking the upper surface of thegate electrode film 14 is formed on theprotective film 21 by lithography. Using the resistpattern 22 as a mask, theprotective film 21 is removed by etching, thereby exposing the surface of the n-type source/drain region 20. - Thereafter, as illustrated in
FIGS. 5A and 5B , after the resistpattern 22 is removed, a first metal film made of nickel (Ni) is deposited by sputtering to a thickness of 11 nm over thesemiconductor substrate 11 from which the n-type source/drain region 20 is exposed. Then, heat treatment is performed in a nitrogen atmosphere at about 350° C., for example, thereby forming ametal silicide layer 23 made of nickel silicide in an upper portion of the n-type source/drain region 20. At this time, thegate electrode film 14 made of polysilicon is masked with theprotective film 21, and thus is not silicided. - Subsequently, as illustrated in
FIGS. 5C and 5D , theprotective film 21 of NSG on thegate electrode film 14 is selectively removed by etching. - Then, as illustrated in
FIGS. 6A and 6B , aninterlayer insulating film 24 made of undoped silicate glass (USG), which is undoped silicon oxide, is deposited by plasma CVD over the entire surface of thesemiconductor substrate 11 including thegate electrode film 14. Subsequently, theinterlayer insulating film 24 is planarized by CMP until the upper surface of thegate electrode film 14 is exposed. - Thereafter, as illustrated in
FIGS. 6C and 6D , asecond metal film 25 made of nickel is deposited by sputtering to a thickness of 95 nm over theinterlayer insulating film 24 from which thegate electrode film 14 is exposed. - Then, as illustrated in
FIGS. 7A and 7B , thesecond metal film 25 is subjected to heat treatment in a nitrogen atmosphere at about 520° C., for example, thereby siliciding thegate electrode film 14. In this manner, agate electrode 15 formed by fully siliciding a portion of thegate electrode film 14 located above theactive region 11 a and made of polysilicon is obtained. At this time, as illustrated inFIGS. 1A and 1B , the width of thecontact region 15 a located above theisolation region 12 is larger than the width of the portion of thegate electrode 15 located above theactive region 11 a, so that nickel (Ni) is insufficiently supplied. Accordingly,island polysilicon 14 a is formed in a self-aligned manner in thecontact region 15 a of thegate electrode 15 which is fully silicided above theactive region 11 a. - As described above, in this embodiment, the
island polysilicon 14 a is formed inside thecontact region 15 a of thegate electrode 15 located above theisolation region 12, so that depletion occurs in thegate electrode 15. This depletion reduces the gate electrode capacitance, thus increasing the operation speed of a MIS transistor. - In this embodiment, the thickness (i.e., 95 nm) of the
second metal film 25 made of nickel is smaller than the thickness (i.e., 100 nm) of thegate electrode film 14 made of polysilicon. In this case, nickel (Ni) is insufficient when supplied only from a portion of thesecond metal film 25 located on thegate electrode film 14. Therefore, to fully silicide thegate electrode film 14, it is necessary to also supply nickel from a portion of thesecond metal film 25 located on theinterlayer insulating film 24. In a portion of thegate electrode film 14 having a small patterning width above theactive region 11 a, the distance from the middle ofgate electrode film 14 on thegate insulating film 13 to the portion of thesecond metal film 25 formed on theinterlayer insulating film 24 is short, so that nickel (Ni) is sufficiently supplied from the portion of thesecond metal film 25 formed on theinterlayer insulating film 24 and full silicidation is achieved. On the other hand, in a portion of thegate electrode film 14 to be thecontact region 15 a having a wide patterning width above theisolation region 12, the distance from the center of thecontact region 15 a in thegate electrode film 14 located above theisolation region 12 to the portion of thesecond metal film 25 formed on theinterlayer insulating film 24 is long, so that nickel (Ni) is insufficiently supplied from the portion of thesecond metal film 25 formed on theinterlayer insulating film 24. Accordingly, theisland polysilicon 14 a remains in a lower portion of the center of thecontact region 15 a. Therefore, the thickness of thesecond metal film 25 for forming theisland polysilicon 14 a in thecontact region 15 a may be equal to or smaller than the thickness of thegate electrode film 14 and is preferably in the range from 60% to 100%, both inclusive. Thesecond metal film 25 and thegate electrode film 14 may have the same thickness. In such a case, the entire portion of thesecond metal film 25 on thegate electrode film 14 does not contribute to silicidation, so that a structure as shown inFIGS. 1A and 1B is obtained. - The first metal film and the
second metal film 25 for silicidation are not necessarily made of nickel, and may be made of cobalt (Co) or tungsten (W). - Embodiment 2
- Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
-
FIGS. 8A and 8B illustrate a semiconductor device according to the second embodiment.FIG. 8A is a plan view andFIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb inFIG. 8A . As illustrated inFIGS. 8A and 8B , anisolation region 12 of shallow trench isolation (STI) and anactive region 11 a surrounded by theisolation region 12 are formed in an upper portion of asemiconductor substrate 11 made of, for example, silicon (Si). - As illustrated in
FIG. 8B , asilicided gate electrode 15 is formed over the principal surface of thesemiconductor substrate 11 across the boundary between theactive region 11 a and theisolation region 12 with agate insulating film 13 of a high-κ film interposed therebetween. The high-κ film may be made of hafnium oxide (HfO2), hafnium silicate (HfSiO) or HfSiON, for example. - An end of the
gate electrode 15 located above theisolation region 12 is equal to, in the gate length direction, that of the other portion of thegate electrode 15 located above theactive region 11 a and serves as acontact region 15 b, for example. - As illustrated in
FIGS. 8A and 8B , an offsetsidewall 16 made of silicon dioxide (SiO2) and asidewall 17 made of silicon nitride (Si3N4) are stacked in this order on the side of thegate electrode 15. - This embodiment is characterized in that the entire portion of the
gate electrode 15 located above theactive region 11 a is silicided, i.e., has a FUSI structure, and theisland polysilicon 14 b remains in a lower portion thecontact region 15 b located above theisolation region 12. In this manner, theisland polysilicon 14 b remains on one end of thegate electrode 15 located above theisolation region 12, whereas the portion of thegate electrode 15 located above theactive region 11 a is fully silicided. Accordingly, depletion occurs in thegate electrode 15, thus reducing the gate electrode capacitance. - Hereinafter, a method for fabricating a semiconductor device with the foregoing configuration will be described with reference to the drawings.
-
FIGS. 9A through 9D toFIGS. 13A and 13B illustrate cross-sectional structures in respective process steps of a method for fabricating a semiconductor device according to the second embodiment in the order of fabrication.FIGS. 9A, 9C , 10A, 10C, 11A, 11C, 12A, 12C and 13A illustrate cross-sectional structures in the gate width direction.FIGS. 9B, 9D , 10B, 10D, 11B, 11D, 12B, 12D and 13B illustrate cross-sectional structures in the gate length direction. - First, as illustrated in
FIGS. 9A and 9B , anisolation region 12 of STI is selectively formed in an upper portion of asemiconductor substrate 11, thereby forming anactive region 11 a surrounded by theisolation region 12. Thereafter, agate insulating film 13 made of hafnium oxide and having a thickness of 3 nm is formed on the entire principal surface of the semiconductor substrate by, for example, chemical vapor deposition (CVD). Subsequently, asemiconductor film 14A of polysilicon with a thickness of 100 nm is formed on thegate insulating film 13. Thesemiconductor film 14A may be made of amorphous silicon, instead of polysilicon. Thereafter, an insulatingfilm 26A made of silicon oxide and having a thickness of 50 nm is formed on thesemiconductor film 14A. - Next, as illustrated in
FIGS. 9C and 9D , the insulatingfilm 26A and thesemiconductor film 14A are patterned by lithography and dry etching, thereby forming aprotective film 26 and agate electrode film 14. Thegate electrode film 14 have a shape similar to that of thegate electrode 15 illustrated inFIG. 8A and extends in the gate width direction in such a manner that the middle of thegate electrode film 14 is located above theactive region 11 a, both ends thereof are located above theisolation region 12 and one of the ends serves as a contact region. Subsequently, a TEOS (tetra-ethyl-ortho-silicate)film 16A with a thickness of 14 nm is formed over the entire surface of thesemiconductor substrate 11 including thegate electrode film 14. - Then, as illustrated in
FIGS. 10A and 10B , theTEOS film 16A is etched by etch back using an etching gas containing fluorocarbon as a main component, thereby forming an offsetsidewall 16 out of theTEOS film 16A on each side of thegate electrode film 14. Using thegate electrode film 14 and the offsetsidewall 16 as a mask, ions of, for example, arsenic (As) are implanted in theactive region 11 a under the conditions that the acceleration energy is 3 keV, the dose is 1.5×1015/cm2 and the tilt angle is 0°, thereby forming an n-type extension region 18 below the side of the offsetsidewall 16 in theactive region 11 a. Thereafter, ions of, for example, boron (B) are implanted in theactive region 11 a by four rotation injection under the conditions that the acceleration energy is 10 keV, the dose is 8.0×1012/cm2 and the tile angle is 25°, thereby forming a p-type pocket region 19 under the n-type extension region 18 in theactive region 11 a. The “four rotation injection” refers to an ion implantation process in which thesemiconductor substrate 11 is rotated approximately 90° at each time within the principal surface and ion implantation described above is performed once at every approximately −90° rotation. - Thereafter, as illustrated in
FIGS. 10C and 10D , a silicon nitride film is deposited by CVD over the entire surface of thesemiconductor substrate 11 to cover thegate electrode film 14 and the offsetsidewall 16. Subsequently, etch back is performed on the silicon nitride film using an etching gas containing fluorocarbon as a main component, thereby forming asidewall 17 out of the silicon nitride film at the side of thegate electrode film 14 with the offsetsidewall 16 interposed therebetween. Using thegate electrode film 14, the offsetsidewall 16 and thesidewall 17 as a mask, ions of, for example, arsenic (As) are implanted in theactive region 11 a under the conditions that the acceleration energy is 20 keV, the dose is 4.0×1015/cm2 and the tilt angle is 0°. Subsequently, ions of, for example, phosphorus (P) are implanted under the conditions that the acceleration energy is 10 keV, the dose is 1.0×1015/cm2 and the tilt angle is 7°, thereby forming an n-type source/drain region 20 below the side of thesidewall 17 in theactive region 11 a. The n-type source/drain region 20 has an interface deeper than that of the p-type pocket region 19 and is connected to the n-type extension region 18. - Then, as illustrated in
FIGS. 11A and 11B , afirst metal film 27 made of nickel (Ni) is deposited by sputtering to a thickness of 11 nm over thesemiconductor substrate 11 from which the n-type source/drain region 20 is exposed. - Thereafter, as illustrated in
FIGS. 11C and 11D , heat treatment is performed in a nitrogen atmosphere at about 350° C., for example, thereby forming ametal silicide layer 23 made of nickel silicide in an upper portion of the n-type source/drain region 20. At this time, thegate electrode film 14 made of polysilicon is masked with theprotective film 26, and thus is not silicided. Then, the remaining unreactedfirst metal film 27 is selectively removed. - Then, as illustrated in
FIGS. 12A and 12B , aninterlayer insulating film 24 made of undoped silicate glass (USG), which is undoped silicon oxide, is deposited by plasma CVD over the entire surface of thesemiconductor substrate 11 including thegate electrode film 14. Subsequently, theinterlayer insulating film 24 is planarized by CMP until theprotective film 26 is exposed. Thereafter, theprotective film 26 and theinterlayer insulating film 24 are etched using dry etching or wet etching under conditions for selectively etching silicon oxide with respect to silicon nitride and polysilicon. At this time, theinterlayer insulating film 24 is not necessarily etched, and only theprotective film 26 may be selectively etched. To selectively etch the silicon oxide film, in the case of dry etching, reactive ion etching in which C5F8, O2 and Ar are supplied at flow rates of 15 ml/min (standard condition), 18 ml/min (standard condition) and 950 ml/min (standard condition), respectively, the pressure is 6.7 Pa, the RF outputs (T/B) are 1800 W/1500 W, and the substrate temperature is 0° C. may be adopted. - Thereafter, as illustrated in
FIGS. 12C and 12D , a resist (not shown) covering a contact region of thegate electrode film 14 located above theisolation region 12 is formed. Subsequently, thegate electrode film 14 is etched by dry etching except for a region thereof covered with the resist so that the resultant thickness of thegate electrode film 14 is 40 nm. In this manner, the thickness of the contact region of thegate electrode film 14 is 100 nm, whereas the thickness of a portion of thegate electrode film 14 located above theactive region 11 a is 40 nm. Thereafter, asecond metal film 25 made of nickel is deposited by sputtering to a thickness of 50 nm over theinterlayer insulating film 24 from which thegate electrode film 14 is exposed. - Then, as illustrated in
FIGS. 13A and 13B , thesecond metal film 25 is subjected to heat treatment in a nitrogen atmosphere at about 520° C., for example, thereby siliciding thegate electrode film 14. In this manner, agate electrode 15 formed by fully siliciding a portion of thegate electrode film 14 located above theactive region 11 a and made of polysilicon is obtained. At this time, the thickness of thecontact region 15 b in a portion of thegate electrode film 14 located above theisolation region 12 is larger than the thickness of a portion of thegate electrode film 14 located above theactive region 11 a, so that a portion of polysilicon included in thecontact region 15 b is not silicided and remains asisland polysilicon 14 b. - The
first metal film 27 and thesecond metal film 25 for silicidation are not necessarily made of nickel, and may be made of cobalt (Co) or tungsten (W). - (Modified Example of Embodiment 2)
-
FIGS. 14A and 14B illustrate a semiconductor device according to a modified example of the second embodiment.FIG. 14A is a plan view andFIG. 14B is a cross-sectional view taken along the line XIVb-XIVb inFIG. 14A . - As illustrated in
FIGS. 14A and 14B , in a modified example of the second embodiment,island polysilicon 14 b is formed above anisolation regions 12 located at each end of anactive region 11 a, and theisland polysilicon 14 b is formed across the end of theactive region 11 a. - Embodiment 3
- Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
- In the third embodiment, another example of the method for fabricating a semiconductor device according to the second embodiment is described. In this embodiment, only aspects different from those of the second embodiment are described.
-
FIGS. 15A through 15D illustrate cross-sectional structures of a main portion in respective process steps of a method for fabricating a semiconductor device according to the third embodiment.FIGS. 15A and 15C are cross-sectional views in the gate width direction.FIGS. 15B and 15D are cross-sectional views in the gate length direction. - First, as illustrated in
FIGS. 15A and 15B , the same structure as illustrated inFIGS. 12A and 12B is obtained by a method similar to that shown inFIGS. 9A and 9B toFIGS. 12A and 12B . - Next, as illustrated in
FIGS. 15C and 15D , asecond metal film 25 made of nickel is deposited by sputtering to a thickness of 95 nm over aninterlayer insulating film 24 from which agate electrode film 14 is exposed. Thereafter, a portion of thesecond metal film 25 located above a contact region of thegate electrode film 14 is selectively etched using, for example, a chlorine gas so that the thickness of this portion of thesecond metal film 25 is 40 nm. In this manner, a portion of thesecond metal film 25 located above anactive region 11 a has a thickness of 95 nm, whereas the portion of thesecond metal film 25 located above the contact region of thegate electrode film 14 is 40 nm. - Thereafter, as illustrated in
FIGS. 13A and 13B , thesecond metal film 25 in which the thickness of a portion above the contact region is reduced is subjected to heat treatment in a nitrogen atmosphere at about 520° C., for example, thereby siliciding thegate electrode film 14. In this manner, agate electrode 15 formed by fully siliciding a portion of thegate electrode film 14 located above theactive region 11 a and made of polysilicon is obtained. At this time, the thickness of the portion of thesecond metal film 25 above the contact region for a gate electrode is smaller than the thickness of the portion of thesecond metal film 25 located above theactive region 11 a. Accordingly, a portion of polysilicon in the contact region of thegate electrode film 14 is not silicided and remains asisland polysilicon 14 b. - In the second and third embodiments and the modified example of the second embodiment, an end (e.g., the
contact region 15 b) of thegate electrode 15 located above theisolation region 12 and another portion of thegate electrode 15 located above theactive region 11 a have the same width in the gate length direction. Alternatively, as in the first embodiment, the length in the gate length direction of the end (e.g., thecontact region 15 b) located above theisolation region 12 may be larger than the other portion above theactive region 11 a. In this case, in the process step shown inFIGS. 9C and 9D , the length in the gate length direction of a portion to be a contact region formed above theisolation region 12 is larger than that of another portion formed above theactive region 11 a. - As described above, in a semiconductor device and a method for fabricating the device according to the present invention, silicidation is performed with a silicon region left in a portion of a gate electrode located above an isolation region and the gate electrode is fully silicided above an active region. Accordingly, the capacitance of the FUSI gate electrode is reduced. Therefore, the present invention is useful for semiconductor devices including gate electrodes to be fully silicided and methods for fabricating such devices.
Claims (17)
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