US20070011388A1 - Dual port memory with asymmetric inputs and outputs, device, system - Google Patents
Dual port memory with asymmetric inputs and outputs, device, system Download PDFInfo
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- US20070011388A1 US20070011388A1 US11/519,557 US51955706A US2007011388A1 US 20070011388 A1 US20070011388 A1 US 20070011388A1 US 51955706 A US51955706 A US 51955706A US 2007011388 A1 US2007011388 A1 US 2007011388A1
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- 238000012546 transfer Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 21
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000010076 replication Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 16
- 230000002457 bidirectional effect Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- the present invention relates to a device interface and, more specifically, to systems and methods for improved matching of interfaces with data flow.
- Interfaces provide access points for exchanging data within electronic or computer systems.
- An example of an interface includes the access points associated with, for example, a memory device.
- a memory device includes a specific number of pins that are dedicated or at least shared for accessing and storing information within memory locations of a memory device. To minimize the number of dedicated pins for an interface, access points that function both as data inputs and outputs have been developed.
- FIG. 1 illustrates a pair of devices coupled together according to a shared interface. While electronic devices may incorporate various form factors, the present illustration is drawn to data storage and, more particularly, memory devices.
- An interface system 10 includes a memory controller 12 coupled to a memory device 14 according to a bidirectional interface 16 . Bidirectional interface 16 combines both the “D” inputs and “Q” outputs of memory device 14 into shared pins to reduce the overall interface pin count, X.
- While the pin count of a memory device may be reduced through the use of a bidirectional interface, such a functionally shared interface creates a throughput-bottleneck when, for example, a memory controller and memory device are capable of generating memory access commands for reading and writing to a memory device that is capable of responding thereto in a generally simultaneous manner.
- FIG. 2 illustrates an interface system 20 including a memory controller 22 coupled to a memory device 24 according to a separate symmetric interface 26 .
- Separate symmetric interface 26 includes a symmetric read data interface 28 and a symmetric write data interface 30 .
- Each of the interfaces, symmetric read data interface 28 and symmetric write data interface 30 include an equivalent number of pins, X for interfacing with memory device 24 . Separating the read and write data interfaces provides improved performance including signal integrity, no bus turn-around time, reduced I/O capacitance, etc.
- the present invention is directed to a dual port memory with asymmetric inputs and outputs.
- an asymmetric memory interface is provided.
- the asymmetric memory interface includes an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller.
- the asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width different in size from the read bus width.
- a memory system in another embodiment, includes a memory controller and memory device.
- An asymmetric interface couples the memory controller with the memory device.
- the asymmetric interface includes an asymmetric read data interface of a read bus width configured to transfer data from the memory device to the memory controller and an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device.
- the write bus width is configured to be different in width from the read bus width.
- a memory device in a further embodiment of the present invention, includes a memory array and an interface configured to operably couple with an asymmetric interface for coupling a memory controller with the memory device.
- the interface includes an asymmetric read data interface of a read bus width configured to transfer data from the memory device to the memory controller and an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device.
- the write bus width is different from the read bus width.
- an electronic system in yet a further embodiment of the present invention, includes a processor device, a memory controller coupled to the processor device and an asymmetric memory interface.
- the asymmetric memory interface includes an asymmetric read data interface of a read bus width configured to transfer data from a memory device to a memory controller and an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device, the write bus width being different from the read bus width.
- a method of accessing data in a memory device is provided.
- a memory controller writes data over an asymmetric write data interface of a write bus width to a memory device.
- the data is stored in the memory device.
- the data is read from the memory device over an asymmetric read data interface of a read bus width to the memory controller.
- the write bus width is different from the read bus width.
- FIG. 1 is a block diagram of a memory controller and a memory device coupled via a bidirectional interface
- FIG. 2 is a block diagram of a memory controller and a memory device coupled via a separate symmetric interface
- FIG. 3 is a block diagram of a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention
- FIG. 4 is a block diagram of a memory controller and a double data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention
- FIG. 5 is a timing diagram of a memory controller and a double data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention
- FIG. 6 is a block diagram of a memory controller and a quad data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention
- FIG. 7 is a timing diagram of a memory controller and a quad data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- FIG. 8 is a block diagram of an electronic system including a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- Advancements in integrated circuits generally include miniaturization of circuits and, more particularly, a reduction in the physical line dimensions of the individual printed circuits. While the physical area of a specific integrated circuit may periodically be reduced, the inputs and outputs (I/Os) associated therewith must still retain a form factor that enables the I/Os to be routed to pins on the package for further coupling with other devices via a printed wiring board or the like. Frequently the packaging dimension becomes the limiting factor in further miniaturization of the device.
- the various embodiments of the present invention expand the available bandwidth by separating the interfaces into a separate interface at, for example, a memory device for receiving data from a memory controller during a write operation and for transmitting data from the memory device during a read operation as referenced from the perspective of the memory device.
- the impedance loading of the individual I/Os are reduced since a typical driver for transmitting data exhibits an approximately 35% increase in loading, which when coupled as a shared or bidirectional interface, results in a reduction in speed for writing data to the memory device due to the additional impedance loading of the combined interface.
- the various embodiments of the present invention also reduce the form factor or area impact resulting from otherwise increasing all the I/O proportionally.
- memory devices are read from more predominantly than they are written to.
- a memory device in many applications, is read from approximately four times more often than it is written to. Therefore, the separate interfaces are asymmetrically expanded, rather than symmetrically or proportionally expanded.
- FIG. 3 is a block diagram of a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- a memory system 36 includes a memory controller 40 coupled to a memory device 42 according to an interface system 38 , which includes a separate asymmetric interface 44 .
- Separate asymmetric interface 44 includes an asymmetric read data interface 46 and an asymmetric write data interface 48 .
- the asymmetry of interfaces 46 and 48 is a result of a difference in the width of the interface dimensions, namely the difference in the number of the drivers and receivers of the memory device, which further corresponds to a difference in the number of pins X and Y associated with the respective interfaces.
- the asymmetry may follow a memory device access methodology and include a narrower asymmetric write data interface 48 for writing data to memory device 42 and wider asymmetric read data interface 46 for reading data from memory device 42 .
- Memory controller 40 and memory device 42 further include respective interfaces 54 , 56 configured to provide the physical interface layer, as well as any multiple data rate methodologies incorporated therein.
- Interface system 38 of FIG. 3 further includes a command bus 50 of width/pins Z and an address bus 52 of width/pins W.
- command and address buses 50 , 52 function according to conventional command and address specifications known by those of ordinary skill in the art. Addressing may include the request for multiple data words or blocks of data words for use in data-intensive applications, such as graphic or video processing.
- memory controller 40 and memory device 42 may be configured to operate using additional data rate techniques.
- FIG. 4 is a block diagram of a memory system including a memory controller and a double data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- a memory system 60 includes a memory controller 62 and a memory device 64 coupled together according to an interface system 66 .
- memory device 64 is configured as a Dual Data Rate (DDR) memory device configured to read and/or write two pieces of data on each clock cycle. Specifically, DDR memory devices read or write a first piece of data on one edge of the clock and read or write another piece of data on the opposite edge of the clock.
- DDR Dual Data Rate
- Interface system 66 includes a separate asymmetric interface 68 comprised of an asymmetric read data interface 70 and an asymmetric write data interface 72 .
- Separate asymmetric read and write interfaces 70 , 72 are configured, in one embodiment, with asymmetry according to a memory device access methodology that includes a narrower asymmetric write data interface 72 for writing data to memory device 64 and wider asymmetric read data interface 70 for reading data from memory device 64 .
- Memory controller 62 and memory device 64 further include respective interfaces 86 , 88 configured to provide the physical interface layer, as well as any multiple data rate methodologies, such as DDR techniques, incorporated therein.
- memory controller 62 and memory device 64 are configured to exchange data according to a DDR methodology. While FIG. 4 illustrates DDR capability on both the asymmetric read and write interfaces 70 , 72 , it is also known that the loading of a memory device driver is greater than the loading of a memory device receiver. Accordingly, the performance of writing to a memory device may practically operate at a higher switching rate than the reading operation of the memory device over an asymmetric read data interface. Therefore, it is further contemplated that a memory system may be configured such that only one of the interfaces operates according to dual or other multi-rate techniques, while the other interface operates at a different data rate.
- FIG. 5 is a timing diagram of a memory controller and a double data rate (DDR) memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- Clock signals CK and CK# 80 illustrate a clock interface for synchronizing the exchange of signals between the memory controller 62 ( FIG. 4 ) and the memory device 64 ( FIG. 4 ).
- the timing diagram of FIG. 5 further illustrates a command bus 82 including an exemplary string of read, write and No-OPeration (NOP) commands and further illustrates the accompanying address locations as presented on address bus 84 .
- NOP No-OPeration
- asymmetric read and write data interfaces 70 , 72 data may be simultaneously exchanged over the separate interfaces as illustrated in FIG. 5 . Because of the difference in the width of the asymmetric read data interface 70 and the generally narrower asymmetric write data interface 72 , when the write data interface is configured as a smaller width bus, then the effective bandwidth of the asymmetric read data interface 70 is greater than the effective bandwidth of the asymmetric write data interface 72 . The difference in bandwidth is acceptable because of the statistical reality that data is generally read at a much greater frequency than it is written.
- FIG. 6 is a block diagram of a memory controller and a quad data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- a memory system 90 includes a memory controller 92 and a memory device 94 coupled together according to an interface system 96 .
- memory device 94 is configured as a multi-data rate memory device, which is configured to write data at a Quadrature Data Rate (QDR) and to read data at a Double Data Rate (DDR).
- QDR Quadrature Data Rate
- DDR Double Data Rate
- the QDR capability means that for each complete cycle of the clock, valid data is written on four separate occasions during one complete clock cycle.
- the DDR capability means that for each complete cycle of the clock, valid data is read on two separate occasions during one complete clock cycle.
- Interface system 96 includes a separate asymmetric interface 98 comprised of an asymmetric read data interface 100 and an asymmetric write data interface 102 .
- Separate asymmetric read and write data interfaces 100 , 102 are configured, in one embodiment, with asymmetry according to a memory device access methodology that includes a narrower asymmetric write data interface 102 for writing data to memory device 94 and wider asymmetric read data interface 100 for reading data from memory device 94 .
- Memory controller 92 and memory device 94 further include respective interfaces 116 , 118 configured to provide the physical interface layer, as well as any multiple data rate methodologies, such as DDR/QDR techniques, incorporated therein.
- memory controller 92 and memory device 94 are configured to exchange data according to a QDR/DDR methodology.
- FIG. 7 is a timing diagram of a memory controller and a QDR/DDR memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- Clock signals CK and CK# 110 illustrate a clock interface for synchronizing the exchange of signals between the memory controller 92 ( FIG. 6 ) and the memory device 94 ( FIG. 6 ).
- the timing diagram of FIG. 7 further illustrates a command bus 112 including an exemplary string of read, write and No-OPeration (NOP) commands and further illustrates the accompanying address locations as presented on address bus 114 .
- NOP No-OPeration
- asymmetric write data interface 102 is configured according to QDR principles resulting in an augmentation of the overall bandwidth of the asymmetric write data interface 102 .
- FIG. 8 is a block diagram of an electronic system, including a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention.
- An electronic system 200 such as a computer system, includes input and/or output devices I/O device(s) 202 , a processor device 204 , a memory controller 206 and a memory device 208 .
- Memory device 208 includes a memory array 212 configured for inputting and outputting data stored therein.
- the memory controller 206 and memory device 208 couple via a separate asymmetric interface 210 configured according to one or more of the previously described embodiments of the present invention.
- Memory controller 206 and memory device 208 may be configured as a DRAM controller and DRAM device, respectively.
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Abstract
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs.
Description
- This application is a continuation of application Ser. No. 10/925,255, filed Aug. 23, 2004, pending.
- 1. Field of the Invention
- The present invention relates to a device interface and, more specifically, to systems and methods for improved matching of interfaces with data flow.
- 2. State of the Art
- Interfaces provide access points for exchanging data within electronic or computer systems. An example of an interface includes the access points associated with, for example, a memory device. Generally, a memory device includes a specific number of pins that are dedicated or at least shared for accessing and storing information within memory locations of a memory device. To minimize the number of dedicated pins for an interface, access points that function both as data inputs and outputs have been developed.
FIG. 1 illustrates a pair of devices coupled together according to a shared interface. While electronic devices may incorporate various form factors, the present illustration is drawn to data storage and, more particularly, memory devices. Aninterface system 10 includes amemory controller 12 coupled to amemory device 14 according to abidirectional interface 16.Bidirectional interface 16 combines both the “D” inputs and “Q” outputs ofmemory device 14 into shared pins to reduce the overall interface pin count, X. - While the pin count of a memory device may be reduced through the use of a bidirectional interface, such a functionally shared interface creates a throughput-bottleneck when, for example, a memory controller and memory device are capable of generating memory access commands for reading and writing to a memory device that is capable of responding thereto in a generally simultaneous manner.
- In response to increased memory bandwidth demands, separate input and output interfaces have been proposed and implemented.
FIG. 2 illustrates aninterface system 20 including amemory controller 22 coupled to amemory device 24 according to a separatesymmetric interface 26. Separatesymmetric interface 26 includes a symmetricread data interface 28 and a symmetricwrite data interface 30. Each of the interfaces, symmetricread data interface 28 and symmetricwrite data interface 30, include an equivalent number of pins, X for interfacing withmemory device 24. Separating the read and write data interfaces provides improved performance including signal integrity, no bus turn-around time, reduced I/O capacitance, etc. However, doubling of interface pins resulting from separating the read and write data interfaces creates an increased interface dimension formemory device 24, which increases the overall area required for integratingmemory device 24 into an electronic system. Therefore, there is a need to provide an improved device interface while reducing the overall affect to the form factor of the device and overall system. - The present invention is directed to a dual port memory with asymmetric inputs and outputs. In one embodiment of the present invention, an asymmetric memory interface is provided. The asymmetric memory interface includes an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width different in size from the read bus width.
- In another embodiment of the present invention, a memory system is provided. The memory system includes a memory controller and memory device. An asymmetric interface couples the memory controller with the memory device. The asymmetric interface includes an asymmetric read data interface of a read bus width configured to transfer data from the memory device to the memory controller and an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device. The write bus width is configured to be different in width from the read bus width.
- In a further embodiment of the present invention, a memory device is provided. The memory device includes a memory array and an interface configured to operably couple with an asymmetric interface for coupling a memory controller with the memory device. The interface includes an asymmetric read data interface of a read bus width configured to transfer data from the memory device to the memory controller and an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device. The write bus width is different from the read bus width.
- In yet a further embodiment of the present invention, an electronic system is provided. The electronic system includes a processor device, a memory controller coupled to the processor device and an asymmetric memory interface. The asymmetric memory interface includes an asymmetric read data interface of a read bus width configured to transfer data from a memory device to a memory controller and an asymmetric write data interface of a write bus width configured to transfer data from the memory controller to the memory device, the write bus width being different from the read bus width.
- In an additional embodiment of the present invention, a method of accessing data in a memory device is provided. A memory controller writes data over an asymmetric write data interface of a write bus width to a memory device. The data is stored in the memory device. The data is read from the memory device over an asymmetric read data interface of a read bus width to the memory controller. The write bus width is different from the read bus width.
- In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:
-
FIG. 1 is a block diagram of a memory controller and a memory device coupled via a bidirectional interface; -
FIG. 2 is a block diagram of a memory controller and a memory device coupled via a separate symmetric interface; -
FIG. 3 is a block diagram of a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention; -
FIG. 4 is a block diagram of a memory controller and a double data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention; -
FIG. 5 is a timing diagram of a memory controller and a double data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention; -
FIG. 6 is a block diagram of a memory controller and a quad data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention; -
FIG. 7 is a timing diagram of a memory controller and a quad data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention; and -
FIG. 8 is a block diagram of an electronic system including a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. - Advancements in integrated circuits generally include miniaturization of circuits and, more particularly, a reduction in the physical line dimensions of the individual printed circuits. While the physical area of a specific integrated circuit may periodically be reduced, the inputs and outputs (I/Os) associated therewith must still retain a form factor that enables the I/Os to be routed to pins on the package for further coupling with other devices via a printed wiring board or the like. Frequently the packaging dimension becomes the limiting factor in further miniaturization of the device.
- Additionally, as devices become smaller and functionality increases, there is a demand for additional bandwidth access to and from the device. Specifically, for devices that are configured as a memory device, there is a desire to improve the bandwidth for writing data to the memory device, as well as the desire to improve the bandwidth for reading data from the memory device. One approach for expanding the bandwidth has included expanding the width of the bus delivering and retrieving data from the memory device. While such an approach does in fact result in an increased data bandwidth, the additional width of the data bus (e.g., reading and writing buses) results in a dramatic increase in the packaging size of the device due to the increased number of pins.
- The various embodiments of the present invention expand the available bandwidth by separating the interfaces into a separate interface at, for example, a memory device for receiving data from a memory controller during a write operation and for transmitting data from the memory device during a read operation as referenced from the perspective of the memory device. In addition to increasing data bandwidth, by separating the interfaces, the impedance loading of the individual I/Os are reduced since a typical driver for transmitting data exhibits an approximately 35% increase in loading, which when coupled as a shared or bidirectional interface, results in a reduction in speed for writing data to the memory device due to the additional impedance loading of the combined interface. The various embodiments of the present invention also reduce the form factor or area impact resulting from otherwise increasing all the I/O proportionally. The various embodiments of the present invention recognize that, for example, memory devices are read from more predominantly than they are written to. Specifically, a memory device, in many applications, is read from approximately four times more often than it is written to. Therefore, the separate interfaces are asymmetrically expanded, rather than symmetrically or proportionally expanded.
-
FIG. 3 is a block diagram of a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. Amemory system 36 includes amemory controller 40 coupled to amemory device 42 according to aninterface system 38, which includes a separateasymmetric interface 44. Separateasymmetric interface 44 includes an asymmetricread data interface 46 and an asymmetricwrite data interface 48. The asymmetry ofinterfaces write data interface 48 for writing data tomemory device 42 and wider asymmetric read data interface 46 for reading data frommemory device 42.Memory controller 40 andmemory device 42 further includerespective interfaces -
Interface system 38 ofFIG. 3 further includes acommand bus 50 of width/pins Z and anaddress bus 52 of width/pins W. The specifics and operational configuration of command andaddress buses memory controller 40 andmemory device 42 may be configured to operate using additional data rate techniques. -
FIG. 4 is a block diagram of a memory system including a memory controller and a double data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. Amemory system 60 includes amemory controller 62 and amemory device 64 coupled together according to aninterface system 66. In this exemplary embodiment of the of the present invention,memory device 64 is configured as a Dual Data Rate (DDR) memory device configured to read and/or write two pieces of data on each clock cycle. Specifically, DDR memory devices read or write a first piece of data on one edge of the clock and read or write another piece of data on the opposite edge of the clock.Interface system 66 includes a separateasymmetric interface 68 comprised of an asymmetricread data interface 70 and an asymmetricwrite data interface 72. Separate asymmetric read and writeinterfaces write data interface 72 for writing data tomemory device 64 and wider asymmetric read data interface 70 for reading data frommemory device 64.Memory controller 62 andmemory device 64 further includerespective interfaces - In the present embodiment of the present invention,
memory controller 62 andmemory device 64 are configured to exchange data according to a DDR methodology. WhileFIG. 4 illustrates DDR capability on both the asymmetric read and writeinterfaces -
FIG. 5 is a timing diagram of a memory controller and a double data rate (DDR) memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. Clock signals CK andCK# 80 illustrate a clock interface for synchronizing the exchange of signals between the memory controller 62 (FIG. 4 ) and the memory device 64 (FIG. 4 ). The timing diagram ofFIG. 5 further illustrates acommand bus 82 including an exemplary string of read, write and No-OPeration (NOP) commands and further illustrates the accompanying address locations as presented onaddress bus 84. Those skilled in the art appreciate that DDR memory devices read and/or write data on each edge of the clock signal. As stated, because of the separate asymmetric read and writedata interfaces FIG. 5 . Because of the difference in the width of the asymmetricread data interface 70 and the generally narrower asymmetricwrite data interface 72, when the write data interface is configured as a smaller width bus, then the effective bandwidth of the asymmetricread data interface 70 is greater than the effective bandwidth of the asymmetricwrite data interface 72. The difference in bandwidth is acceptable because of the statistical reality that data is generally read at a much greater frequency than it is written. -
FIG. 6 is a block diagram of a memory controller and a quad data rate memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. Amemory system 90 includes amemory controller 92 and amemory device 94 coupled together according to aninterface system 96. In this exemplary embodiment of the present invention,memory device 94 is configured as a multi-data rate memory device, which is configured to write data at a Quadrature Data Rate (QDR) and to read data at a Double Data Rate (DDR). The QDR capability means that for each complete cycle of the clock, valid data is written on four separate occasions during one complete clock cycle. The DDR capability means that for each complete cycle of the clock, valid data is read on two separate occasions during one complete clock cycle.Interface system 96 includes a separateasymmetric interface 98 comprised of an asymmetricread data interface 100 and an asymmetricwrite data interface 102. Separate asymmetric read and writedata interfaces write data interface 102 for writing data tomemory device 94 and wider asymmetric read data interface 100 for reading data frommemory device 94.Memory controller 92 andmemory device 94 further includerespective interfaces memory controller 92 andmemory device 94 are configured to exchange data according to a QDR/DDR methodology. -
FIG. 7 is a timing diagram of a memory controller and a QDR/DDR memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. Clock signals CK andCK# 110 illustrate a clock interface for synchronizing the exchange of signals between the memory controller 92 (FIG. 6 ) and the memory device 94 (FIG. 6 ). The timing diagram ofFIG. 7 further illustrates acommand bus 112 including an exemplary string of read, write and No-OPeration (NOP) commands and further illustrates the accompanying address locations as presented onaddress bus 114. Those skilled in the art appreciate that QDR memory devices write data four times on each clock cycle. As stated, because of the separate asymmetric read and writedata interfaces FIG. 7 . Because of the difference in the width of the asymmetricread data interface 100 and the generally narrower asymmetricwrite data interface 102, when thewrite data interface 102 is configured as a smaller width bus, then the effective bandwidth of the asymmetricread data interface 100 is greater than the effective bandwidth of the asymmetricwrite data interface 102. The difference in bandwidth is acceptable because of the statistical reality that data is generally read at a much greater frequency than it is written. In the present embodiment of the present invention, asymmetricwrite data interface 102 is configured according to QDR principles resulting in an augmentation of the overall bandwidth of the asymmetricwrite data interface 102. -
FIG. 8 is a block diagram of an electronic system, including a memory controller and a memory device coupled via a separate asymmetric interface, in accordance with an embodiment of the present invention. Anelectronic system 200, such as a computer system, includes input and/or output devices I/O device(s) 202, aprocessor device 204, amemory controller 206 and amemory device 208.Memory device 208 includes amemory array 212 configured for inputting and outputting data stored therein. Thememory controller 206 andmemory device 208 couple via a separateasymmetric interface 210 configured according to one or more of the previously described embodiments of the present invention.Memory controller 206 andmemory device 208 may be configured as a DRAM controller and DRAM device, respectively. - While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims (14)
1. A memory device interface, comprising:
a read data interface of a first bus width;
a write data interface of a second bus width; and
wherein the read data interface and the write data interface transfer data at different data rates.
2. The memory device interface of claim 1 , wherein the first bus width is greater in width than the second bus width.
3. The memory device interface of claim 1 , wherein at least one of the read data interface and the write data interface is configured to operate according to a multi data rate methodology.
4. The memory device interface of claim 1 , wherein the read data interface is configured to operate according to a dual data rate (DDR) methodology.
5. The memory device interface of claim 1 , wherein the write data interface is configured to operate according to a dual data rate (DDR) methodology.
6. The memory device interface of claim 1 , wherein at least one of the read data interface and the write data interface is configured to operate according to a quad data rate (QDR) methodology.
7. The memory device interface of claim 1 , further comprising at least one of a command and address interface configured for coupling with a memory controller.
8. A memory system, comprising:
a memory controller; and
a memory device including a memory device interface, the memory device interface comprising:
a read data interface of a first bus width;
a write data interface of a second bus width; and
wherein the read data interface and the write data interface transfer data at different data rates.
9. The memory system of claim 8 , wherein the first bus width is greater in width than the second bus width.
10. The memory system of claim 8 , wherein the read data interface, the memory controller and the memory device are configured to operate according to a dual data rate (DDR) methodology.
11. The memory system of claim 8 , wherein the write data interface, the memory controller and the memory device are configured to operate according to a dual data rate (DDR) methodology.
12. The memory system of claim 8 , wherein the memory controller, the memory device and at least one of the read data interface and the write data interface are configured to operate according to a quad data rate (QDR) methodology.
13. The memory system of claim 8 , further comprising at least one of a command and address bus coupled between the memory controller and the memory device.
14. A memory device, comprising:
a memory array; and
a memory device interface, comprising:
a read data interface of a first bus width;
a write data interface of a second bus width; and
wherein the read data interface and the write data interface transfer data at different data rates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/519,557 US20070011388A1 (en) | 2004-08-23 | 2006-09-12 | Dual port memory with asymmetric inputs and outputs, device, system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/925,255 US7171508B2 (en) | 2004-08-23 | 2004-08-23 | Dual port memory with asymmetric inputs and outputs, device, system and method |
US11/519,557 US20070011388A1 (en) | 2004-08-23 | 2006-09-12 | Dual port memory with asymmetric inputs and outputs, device, system |
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US20060041704A1 (en) | 2006-02-23 |
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