US20060286754A1 - Semiconductor device with interface circuit and method of configuring semiconductor devices - Google Patents
Semiconductor device with interface circuit and method of configuring semiconductor devices Download PDFInfo
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- US20060286754A1 US20060286754A1 US11/154,150 US15415005A US2006286754A1 US 20060286754 A1 US20060286754 A1 US 20060286754A1 US 15415005 A US15415005 A US 15415005A US 2006286754 A1 US2006286754 A1 US 2006286754A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Definitions
- the invention relates in general to methods and devices for semiconductors. More specifically, it relates to configuration of semiconductor devices having Input/Output (I/O) interface circuits.
- I/O Input/Output
- microelectronic architectures form the electronic circuits of semiconductor devices.
- Semiconductor devices are manufactured on silicon wafers using a process of adding layers and selectively removing parts of the layers. The wafers are cut into individual dies upon the completion of the manufacturing process. Each individual die includes a semiconductor device having a core area, where logical computations are made.
- semiconductor devices typically include at least one I/O (input/output) interface circuit enabling communication with other devices.
- I/O circuits, or cells are typically arranged at the periphery of each individual die. This peripheral area may be referred to as the I/O ring.
- lithography In the manufacture of semiconductor devices, the selective removal of layers is enabled by a process called lithography. Through lithography, ever smaller features are imaged on the wafer surface. Increasingly smaller gate transistors are required to satisfy the increasingly higher speed requirements of microelectronic devices. However, as just one example, factors such as the wavelength of light place limitations on minimum resolvable feature sizes. Further, semiconductor devices and their I/O rings are becoming more complex due to their increasing compaction of functionality. Consequently, improvements to lithographic processes are continually sought to enable production of continually shrinking features. It follows that it is desirable to reduce semiconductor processing variation. Therefore, a need exists for improved methods for semiconductor devices, improved semiconductor devices, and improved lithographic patterning devices.
- a method of configuring a semiconductor device having a uniform I/O cell layout, and/or a majority of core area device features and/or I/O cell device features arranged in parallel.
- the features may be critically-dimensioned.
- Such parallel arrangement reduces process-induced variation, not only during the fabrication of the semiconductor device, but also during the manufacture of the patterning device used to fabricate the semiconductor device.
- parallel device feature e.g., gate
- a patterning device which may be used to produce parallel semiconductor features.
- Such a patterning device may be configured for use with any of a variety of semiconductor patterning systems.
- I/O cells performing like functions may be arranged either horizontally or vertically while maintaining similar orientations and feature layouts. For example, horizontal I/O cells are not rotated with respect to vertical I/O cells.
- Such I/O cell configuration may utilize space typically unused in prior art semiconductor device configurations.
- the improved I/O cell configuration may allow increased device complexity and may also provide increased signal density.
- a circuit cell having randomly-arranged device features may be arranged within the semiconductor device.
- Such a circuit cell may be arranged within the core or within a corresponding I/O cell.
- FIG. 1 depicts a semiconductor device having a core area with multi-directional gates and uniform I/O cells with multi-directional gates.
- FIG. 2 depicts one embodiment of a semiconductor device having a core area with unidirectional, or parallel, gates and I/O cells with parallel gates.
- FIG. 3 depicts one embodiment of a semiconductor device having a core area with parallel gates and uniform I/O cells with parallel gates, where the horizontal I/O cells have layouts similar to those of the vertical I/O cells.
- FIG. 4 depicts one embodiment of a semiconductor device having a core area with parallel gates and uniform I/O cells with parallel gates, where the horizontal I/O cells have layouts similar to those of the vertical I/O cells, where the I/O cells are arranged to have a substantially fully populated I/O cell layout.
- FIG. 5 depicts one embodiment of a semiconductor device having a core area with parallel gates and uniform I/O cells with parallel gates, where the horizontal I/O cells are similar to the vertical I/O cells and where the I/O cells are square.
- FIG. 6 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the core area includes circuit cells.
- FIG. 7 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the I/O cells include circuit cells and where the I/O cells are substantially matching and translationally disposed.
- FIG. 8 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the I/O cells include circuit cells and where the I/O cells are reflexively matching.
- FIG. 9 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the I/O cells include circuit cells and where the I/O cells are in point symmetry.
- Embodiments of the present invention provide semiconductors with device features (e.g., I/O gates or core gates) laid out in parallel. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another.
- device features e.g., I/O gates or core gates
- Device features are those features on a semiconductor device which are functional and which may be required for device functionality.
- a semiconductor device may have elements that are inoperable, such as alpha-numerics indicating device ID and/or layer ID, as well as alignment and/or registration verniers. These inoperable elements are not generally considered device features.
- a semiconductor integrated circuit device according to the present invention can have a common layer in which the core and the I/O cell both reside and such common layer can be a conductive layer or a polysilicon layer.
- Device features are usually created one process layer at a time.
- the polysilicon layer from which transistor gates are typically formed.
- Some of the device features arranged at these layers may be commonly referred to as ‘critically-dimensioned.’
- Critically-dimensioned features may have dimensions at or near the capability of technologies to manufacture a particular microprocessor. Manufacture of critically-dimensioned device features is facilitated by a low level of defectivity and a low level of process-induced variation.
- FIG. 1 depicts a semiconductor device 100 having a uniform I/O cell layout and a uniform cell footprint, but with multi-directional gates within the uniform I/O cells.
- I/O cell footprint or simply “footprint” refers to the size and shape of the overall I/O cell (e.g., the I/O cell boundary) and the term I/O cell layout (or simply “layout”) refers to the positioning and/or size and/or shape of the features (e.g., gates) within the I/O cell.
- Semiconductor device 100 has a core area 130 with multi-directional gates 120 and I/O cells 110 with multi-directional gates 140 .
- Multi-directional gates may include gates that are both substantially horizontal and substantially vertical with respect to an x-axis through core area 130 .
- I/O circuit cell 110 has a rectangular shape or rectangular footprint. As shown, such rectangular I/O cells 110 are arranged such that a shorter edge of the rectangular I/O cell 110 is parallel to an edge of core area 130 .
- I/O cells 110 are shown having substantially similar layouts of I/O gates 140 . I/O cells having similar layouts typically perform similar functions.
- FIG. 1 shows a device 100 having only one type of I/O cell 110 , it is understood that there may be many different types of I/O cells, each performing a different, specific function. Further, it is understood that each device described in this specification may have many different types of I/O cells.
- the same I/O cell 110 for a particular function is used around the periphery of core area 130 . That is, horizontally arranged I/O cells 111 for a particular function have substantially matching layouts as vertically arranged I/O cells 112 for the same function. For example, assuming the two cells perform the same function, the layout of horizontally arranged cell 111 becomes the layout for vertically arranged cell 112 by rotating the horizontal cell layout 90 degrees counter-clockwise.
- Like-functioned circuit cells arranged along the top and bottom edges of core area 130 are symmetric about an x axis through the center of core area 130 .
- like-functioned circuit cells arranged along the right and left edges of core area 130 are symmetric about a y axis through the center of core area 130 .
- FIG. 2 depicts one embodiment of a semiconductor device 200 according to the present invention having uniform gate direction throughout the device, but uses two I/O cell layouts.
- Semiconductor device 200 has a core area 250 with parallel core gates 220 and I/O cells 210 with parallel I/O gates 240 . While shown with all or substantially all parallel gates, some embodiments could have at least 90% of the gates in parallel or even less than 90% of gates in parallel. It should be understood that while in FIGS.
- the device features e.g., gates
- the device features are shown where all or a substantial portion of the gates are substantially parallel within the core areas and I/O cells
- alternative embodiments can include arrangement of the features (e.g., gates) such that at least 90% of the gate are parallel, or even in some embodiments, less than 90% of the gates are arranged substantially parallel to one another.
- core gates 220 can be arranged parallel to one another and at least 90% of I/O gates 240 can be arranged parallel to one another.
- less than 90% of I/O cell gates and/or core gates can be arranged parallel to each other.
- the core gates 220 may be arranged substantially parallel to I/O gates 240 (as shown in FIG. 2 ).
- core gates 220 and/or I/O gates 240 may be critically-dimensioned.
- all or substantially all core gates 220 are arranged in parallel to one another throughout core 250 of semiconductor device 200 , and all or substantially all of I/O gates 240 are arranged in parallel to one another. Further, as shown in the embodiment of FIG. 2 , core gates 220 that are parallel to one another may be arranged in parallel to I/O gates 240 that are parallel to one another. In another embodiment, core gates 220 and/or I/O gates 240 may be critically-dimensioned.
- one or more of I/O gates 240 and/or one or more of core gates 220 may be arranged such that they are not parallel to the parallel I/O gates 240 and/or the parallel core gates 220 .
- such non-parallel gates will be relatively isolated or otherwise distanced from the parallel gates.
- such non-parallel gates may not be critically-dimensioned, (e.g., may be comparatively larger in size than the parallel gates in device 200 .)
- gates which may be properly characterized as non-critically-dimensioned can have minimum dimensions that are approximately 25-35% (or more) larger than the minimum dimensions of critically-dimensioned gates.
- Device features such as gates, that are substantially parallel may be arranged in parallel with the greatest accuracy possible.
- parallel or substantially parallel will be used interchangeably.
- the specification may utilize gates in describing embodiments of the present invention, it is understood that features other than gates may also benefit from the described configurations.
- the same I/O cell footprint is used for each I/O cell 210 around the periphery of the core 250 .
- vertical I/O cells 270 and horizontal I/O cells 260 each have a short edge adjacent the core area 250 , effectively leaving unused several open areas 280 .
- Horizontal I/O cell 260 and vertical I/O cell 270 have respective footprints that are rotationally disposed one from another. Consequently, for a particular function, it is difficult to use the same I/O cell gate layout horizontally and vertically while maintaining parallel gates within each I/O cell as well as among all I/O cells.
- layouts can include both the features and their positions within the cell perimeter defined by the footprint. Therefore, for the embodiment of FIG. 2 , it is desirable to design for each function two different I/O cell layouts, where horizontal I/O cells 260 have a layout which varies from that of vertical I/O cells 270 , as shown.
- FIG. 3 depicts one embodiment of a semiconductor device 300 according to the invention having uniform I/O cell layouts throughout the device and substantially parallel gates throughout the device.
- core area 330 with parallel core gates 320 the same I/O cell layout for a particular function can be used for an I/O cell regardless of I/O cell location.
- horizontal I/O cells 360 are substantially identical in layout and footprint to vertical I/O cells 370 .
- horizontal I/O cells 360 and vertical I/O cells 370 have like orientations. That is, horizontal I/O cells 360 are translationally, but not rotationally, disposed from vertical I/O cells 370 . Therefore, I/O gates 390 are arranged substantially in parallel throughout semiconductor device 300 .
- gates may be arranged substantially in parallel throughout at least a majority of, if not substantially all of, semiconductor device 300 . Additionally, as described above in reference to FIG. 2 , core gates 320 and/or I/O gates 390 may be arranged in various configurations having substantially parallel gates.
- I/O cell gates 390 are critically-dimensioned and arranged in parallel. As shown, I/O cell gates 390 may be parallel to core gates 320 . However, at least one I/O gate 390 may be arranged perpendicularly or otherwise not parallel to a majority of core gates 320 . Such non-parallel gate may be isolated or offset from either I/O gates 390 within the I/O cell, or core gates 320 arranged adjacent the I/O cell.
- the horizontal I/O cells 360 are substantially identical to the vertical I/O cells 370 .
- horizontal I/O cells 360 have a cell size which is substantially the same as the cell size of the vertical I/O cells 370 .
- the orientation of the horizontal I/O cells 360 is substantially the same as the orientation of the vertical I/O cells 370 . That is, the horizontal I/O cells 360 are arranged like the vertical I/O cells 370 in that the shorter edges of all I/O cells are substantially parallel to one another.
- first cell edge 311 is shorter than second cell edge 312 .
- Each I/O cell has a first cell edge 311 arranged perpendicular to a second cell edge 312 .
- a first cell edge 311 of one I/O cell corresponds to a first cell edge 311 of any other I/O cell
- a second cell edge 312 of one I/O cell corresponds to a second cell edge 312 of any other I/O cell.
- Horizontal I/O cell 360 is arranged along horizontal edge 313 of device 300 such that first cell edge 311 is parallel to horizontal edge 313 .
- vertical I/O cell 370 is arranged along vertical edge 314 of device 300 such that second cell edge 312 is parallel to vertical edge 314 .
- Such an I/O cell layout more fully populates the device 300 , allowing utilization of previously unused areas.
- open areas 280 are located in the corners of device 200 .
- I/O cells 380 occupy such previously unused areas.
- I/O cells as described by FIG. 3 may yield other advantages, as described below in reference to FIG. 4 .
- FIG. 4 is one embodiment of semiconductor device 400 according to the invention having a fully populated layout of similarly-oriented I/O cells 410 overlaying the area outside the core area 450 , in which the I/O cells 410 have a uniform cell layout and substantially all of the gates in device 400 are arranged in parallel.
- Similarly-oriented means substantially all short I/O cell edges are arranged parallel to one another and substantially all long I/O cell edges are arranged parallel to one another as shown in FIG. 4 .
- Such a layout includes additional I/O cells 410 as compared to the embodiment of FIG. 3 . As described above in reference to FIGS.
- core device features e.g., gates
- I/O device features e.g., gates
- core device features e.g., gates
- I/O device features e.g., gates
- the I/O cell layouts of FIG. 4 allows for additional I/O cells 410 arranged across the top and bottom edges of the die and/or core. Such a configuration may increase signal density of the semiconductor device. Additional I/O cells 410 may also allow additional functionality to be realized from the semiconductor device. In one embodiment, the additional I/O cells 410 allow a variety of routing options and/or packaging options.
- FIG. 5 depicts one embodiment of a semiconductor device according to the invention having a core area 550 with parallel gates and uniform I/O cells 510 (e.g., parallel gates, where the horizontal I/O cells 510 substantially match the vertical I/O cells 510 ), and where all I/O cells 510 have a substantially square footprint. Similar to embodiments previously discussed, I/O cells 510 having similar functionality are used in the x and y direction, and such I/O cells 510 have matching layouts. As described above in reference to FIGS. 2-4 , core device features (e.g., gates) and I/O device features (e.g., gates) may be arranged in various configurations, including for example, where a majority of device features are substantially parallel.
- core device features e.g., gates
- I/O device features e.g., gates
- aligning in parallel critically-dimensioned features may be useful in reducing process variation.
- process variation for example, in the case of gate width variation among critically-dimensioned gates arranged within arrays.
- some circuits within the semiconductor device such as analog circuits, may have wider gates.
- some gate widths may not be critically-dimensioned and such gate widths may not necessarily benefit from parallel arrangement.
- FIG. 6 depicts one embodiment of a semiconductor device 600 according to the invention having layout uniform I/O cells 620 with gates parallel to a majority of the gates in core area 610 of device 600 .
- semiconductor device 600 includes core area 610 and I/O cells 620 , where the core area 610 includes circuit cells 690 .
- core features 640 and I/O features 630 may be arranged in various configurations, including for example, where a majority of device features are substantially parallel.
- core area 610 has a majority of parallel features (e.g., gates), except for some features (e.g., gates) in circuit cells 690 , which are not parallel.
- gate width variation may not be critical to the performance or yield of the semiconductor device 600 .
- circuit cell 690 may contain analog circuits, which have relatively wide gates or relatively long gates. Consequently, gate orientation in circuit cells 690 may be arbitrary.
- circuit cell 690 has gates oriented both horizontally and vertically.
- circuit cell 690 may have no critically-dimensioned features.
- the features of circuit cell 690 may be at least 25-35% larger than any of the critically dimensioned features of device 600 .
- circuit cells can also be arranged within I/O cells.
- the circuit cells may be arranged in a number of configurations. Further, the circuit cells may have comparatively large features, for example long gate transistors (or conversely, wide gate transistors (not shown)). Consequently, circuit cells may have features which are not arranged in parallel.
- core device features and I/O device features may be arranged in various configurations where a majority of device features are substantially parallel.
- FIG. 7 depicts one embodiment of semiconductor device 700 according to the present invention with uniform I/O cells 710 , but where such I/O cells 710 include circuit cells 790 that can have gates that are not parallel to the other gates in semiconductor device 700 (as shown).
- Semiconductor device 700 has a core area 720 and I/O cells 710 where each I/O cell 710 includes a circuit cell 790 .
- Circuit cells 790 may have at least one non-critically dimensioned feature, whereas, the remaining features in I/O cell 710 may be critically dimensioned. Further, there may be a number of different circuit cells 790 in I/O cells 710 , each having a particular function. As shown in FIG. 7 , I/O cells 710 are substantially uniform.
- I/O cells 710 have substantially the same I/O cell footprint and layout including placement of circuit cell 790 within I/O cell 710 .
- I/O cells 710 are translationally disposed from each other.
- the non-circuit cell gates 730 are all arranged in parallel to each other, and are arranged in parallel to core area gates 790 .
- substantially all core gates 790 can be parallel to one another, and in yet another alternative embodiment at least 90% of all core gates can be parallel to one another. It should be understood that various percentages of gates within I/O cells and cores of semiconductor devices can be parallel come within the scope of this invention.
- FIG. 8 depicts one embodiment of a semiconductor device 800 having a core area 820 and uniform I/O cells 810 that include circuit cells 890 .
- I/O cells 810 including placement of circuit cells 890 , are arranged in a substantially reflexively matching manner. That is, the horizontally and vertically arranged same-function I/O cells 810 with circuit cells 890 are symmetric about x and y axes, respectively. Thus, they may be described as reflexively matching. However, in one embodiment, circuit cells 890 may not necessarily be symmetric. Features within the respective circuit cells 890 are not necessarily reflexively matching.
- FIG. 9 depicts one embodiment of a semiconductor device 900 having core area 920 and uniform I/O cells 910 that include circuit cells 990 , where and I/O cells 910 are in point symmetry.
- semiconductor device 900 has circuit cells 990 arranged within each I/O cell 910 .
- I/O cells 910 are in point symmetry from top to bottom and from side to side. That is, the top row I/O cell layouts, including placement of circuit cell 990 , are rotated 180 degrees from the bottom row I/O cell layouts, including placement of circuit cell 990 .
- the left and right columns of I/O cell layouts, including placement of circuit cell 990 are similarly rotated with respect to one another.
- I/O cells 910 are in point symmetry.
- patterning devices are created through the use of patterning devices.
- Each patterning device typically contains pattern images for a single processing layer.
- Pattern images are comprised of individual features, such as the individual features shown in FIGS. 1 through 9 . Consequently, FIGS. 1 through 9 may also be representative of corresponding patterning devices instead of merely resultant semiconductor devices.
- patterning devices may be used with any one of a variety of lithographic systems including, but not limited to, contact, g-line, i-line, duv, euv, x-ray, and imprint systems.
- patterning devices may be any one of a variety of devices including, but not limited to, photomasks, reticles, and imprint templates.
- such a patterning device may not be limited solely to the manufacture of semiconductor devices.
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Abstract
Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.
Description
- The invention relates in general to methods and devices for semiconductors. More specifically, it relates to configuration of semiconductor devices having Input/Output (I/O) interface circuits.
- The demand for faster and smaller microelectronic devices is driving continual shrinks of microelectronic architectures. Such microelectronic architectures form the electronic circuits of semiconductor devices. Semiconductor devices are manufactured on silicon wafers using a process of adding layers and selectively removing parts of the layers. The wafers are cut into individual dies upon the completion of the manufacturing process. Each individual die includes a semiconductor device having a core area, where logical computations are made.
- Individual dies are not typically directly integrated into electronic devices, such as, for example, cel phones. Thus, semiconductor devices typically include at least one I/O (input/output) interface circuit enabling communication with other devices. I/O circuits, or cells, are typically arranged at the periphery of each individual die. This peripheral area may be referred to as the I/O ring.
- In the manufacture of semiconductor devices, the selective removal of layers is enabled by a process called lithography. Through lithography, ever smaller features are imaged on the wafer surface. Increasingly smaller gate transistors are required to satisfy the increasingly higher speed requirements of microelectronic devices. However, as just one example, factors such as the wavelength of light place limitations on minimum resolvable feature sizes. Further, semiconductor devices and their I/O rings are becoming more complex due to their increasing compaction of functionality. Consequently, improvements to lithographic processes are continually sought to enable production of continually shrinking features. It follows that it is desirable to reduce semiconductor processing variation. Therefore, a need exists for improved methods for semiconductor devices, improved semiconductor devices, and improved lithographic patterning devices.
- Methods and devices yielding improved semiconductor devices are disclosed. In particular, process-induced variation is reduced by arranging critically-dimensioned features in parallel.
- Accordingly, a method of configuring a semiconductor device is disclosed having a uniform I/O cell layout, and/or a majority of core area device features and/or I/O cell device features arranged in parallel. In an embodiment, the features may be critically-dimensioned. Such parallel arrangement reduces process-induced variation, not only during the fabrication of the semiconductor device, but also during the manufacture of the patterning device used to fabricate the semiconductor device. Thus, embodiments of the invention having parallel device feature (e.g., gate) layout can significantly reduce yield loss for the semiconductor device.
- Consequently, also disclosed is a patterning device which may be used to produce parallel semiconductor features. Such a patterning device may be configured for use with any of a variety of semiconductor patterning systems.
- Also disclosed is a method of configuring a semiconductor device which may have a majority of features on at least one processing layer arranged substantially in parallel. In the embodiment, I/O cells performing like functions may be arranged either horizontally or vertically while maintaining similar orientations and feature layouts. For example, horizontal I/O cells are not rotated with respect to vertical I/O cells. Such I/O cell configuration may utilize space typically unused in prior art semiconductor device configurations. Thus, the improved I/O cell configuration may allow increased device complexity and may also provide increased signal density.
- In an embodiment, a circuit cell having randomly-arranged device features may be arranged within the semiconductor device. Such a circuit cell may be arranged within the core or within a corresponding I/O cell.
- These, and other, aspects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. The following description, while indicating various embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many substitutions, modifications, additions or rearrangements may be made within the scope of the invention, and the invention includes all such substitutions, modifications, additions or rearrangements.
- The drawings accompanying and forming part of this specification are included to depict certain aspects of the invention. A clearer impression of the invention, and of the components and operation of systems provided with the invention, will become more readily apparent by referring to the exemplary, and therefore nonlimiting, embodiments illustrated in the drawings, wherein identical reference numerals designate the same components. Note that the features illustrated in the drawings are not necessarily drawn to scale.
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FIG. 1 depicts a semiconductor device having a core area with multi-directional gates and uniform I/O cells with multi-directional gates. -
FIG. 2 depicts one embodiment of a semiconductor device having a core area with unidirectional, or parallel, gates and I/O cells with parallel gates. -
FIG. 3 depicts one embodiment of a semiconductor device having a core area with parallel gates and uniform I/O cells with parallel gates, where the horizontal I/O cells have layouts similar to those of the vertical I/O cells. -
FIG. 4 depicts one embodiment of a semiconductor device having a core area with parallel gates and uniform I/O cells with parallel gates, where the horizontal I/O cells have layouts similar to those of the vertical I/O cells, where the I/O cells are arranged to have a substantially fully populated I/O cell layout. -
FIG. 5 depicts one embodiment of a semiconductor device having a core area with parallel gates and uniform I/O cells with parallel gates, where the horizontal I/O cells are similar to the vertical I/O cells and where the I/O cells are square. -
FIG. 6 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the core area includes circuit cells. -
FIG. 7 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the I/O cells include circuit cells and where the I/O cells are substantially matching and translationally disposed. -
FIG. 8 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the I/O cells include circuit cells and where the I/O cells are reflexively matching. -
FIG. 9 depicts one embodiment of a semiconductor device having a core area and uniform I/O cells, where the I/O cells include circuit cells and where the I/O cells are in point symmetry. - The invention and the various features and advantageous details thereof are explained more fully with reference to the nonlimiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well known starting materials, processing techniques, components and equipment are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only and not by way of limitation. After reading the specification, various substitutions, modifications, additions and rearrangements will become apparent to those skilled in the art from this disclosure which do not depart from the scope of the appended claims.
- Embodiments of the present invention provide semiconductors with device features (e.g., I/O gates or core gates) laid out in parallel. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another.
- Device features are those features on a semiconductor device which are functional and which may be required for device functionality. A semiconductor device may have elements that are inoperable, such as alpha-numerics indicating device ID and/or layer ID, as well as alignment and/or registration verniers. These inoperable elements are not generally considered device features. A semiconductor integrated circuit device according to the present invention can have a common layer in which the core and the I/O cell both reside and such common layer can be a conductive layer or a polysilicon layer.
- Device features are usually created one process layer at a time. For example, the polysilicon layer, from which transistor gates are typically formed. Some of the device features arranged at these layers may be commonly referred to as ‘critically-dimensioned.’ Critically-dimensioned features may have dimensions at or near the capability of technologies to manufacture a particular microprocessor. Manufacture of critically-dimensioned device features is facilitated by a low level of defectivity and a low level of process-induced variation.
-
FIG. 1 depicts asemiconductor device 100 having a uniform I/O cell layout and a uniform cell footprint, but with multi-directional gates within the uniform I/O cells. As used herein, the term I/O cell footprint (or simply “footprint”) refers to the size and shape of the overall I/O cell (e.g., the I/O cell boundary) and the term I/O cell layout (or simply “layout”) refers to the positioning and/or size and/or shape of the features (e.g., gates) within the I/O cell.Semiconductor device 100 has acore area 130 withmulti-directional gates 120 and I/O cells 110 withmulti-directional gates 140. Multi-directional gates may include gates that are both substantially horizontal and substantially vertical with respect to an x-axis throughcore area 130. As shown inFIG. 1 , I/O circuit cell 110 has a rectangular shape or rectangular footprint. As shown, such rectangular I/O cells 110 are arranged such that a shorter edge of the rectangular I/O cell 110 is parallel to an edge ofcore area 130. For simplicity, I/O cells 110 are shown having substantially similar layouts of I/O gates 140. I/O cells having similar layouts typically perform similar functions. AlthoughFIG. 1 shows adevice 100 having only one type of I/O cell 110, it is understood that there may be many different types of I/O cells, each performing a different, specific function. Further, it is understood that each device described in this specification may have many different types of I/O cells. - As shown in
FIG. 1 , the same I/O cell 110 for a particular function is used around the periphery ofcore area 130. That is, horizontally arranged I/O cells 111 for a particular function have substantially matching layouts as vertically arranged I/O cells 112 for the same function. For example, assuming the two cells perform the same function, the layout of horizontally arrangedcell 111 becomes the layout for vertically arrangedcell 112 by rotating the horizontal cell layout 90 degrees counter-clockwise. Like-functioned circuit cells arranged along the top and bottom edges ofcore area 130 are symmetric about an x axis through the center ofcore area 130. Similarly, like-functioned circuit cells arranged along the right and left edges ofcore area 130 are symmetric about a y axis through the center ofcore area 130. -
FIG. 2 depicts one embodiment of asemiconductor device 200 according to the present invention having uniform gate direction throughout the device, but uses two I/O cell layouts.Semiconductor device 200 has acore area 250 withparallel core gates 220 and I/O cells 210 with parallel I/O gates 240. While shown with all or substantially all parallel gates, some embodiments could have at least 90% of the gates in parallel or even less than 90% of gates in parallel. It should be understood that while inFIGS. 2-9 , the device features (e.g., gates) are shown where all or a substantial portion of the gates are substantially parallel within the core areas and I/O cells, alternative embodiments can include arrangement of the features (e.g., gates) such that at least 90% of the gate are parallel, or even in some embodiments, less than 90% of the gates are arranged substantially parallel to one another. - For example, in an alternative embodiment for
FIG. 2 , at least 90% ofcore gates 220 can be arranged parallel to one another and at least 90% of I/O gates 240 can be arranged parallel to one another. In yet another alternative embodiment, less than 90% of I/O cell gates and/or core gates can be arranged parallel to each other. In addition, thecore gates 220 may be arranged substantially parallel to I/O gates 240 (as shown inFIG. 2 ). In another embodiment,core gates 220 and/or I/O gates 240 may be critically-dimensioned. - In an alternate embodiment, all or substantially all
core gates 220 are arranged in parallel to one another throughoutcore 250 ofsemiconductor device 200, and all or substantially all of I/O gates 240 are arranged in parallel to one another. Further, as shown in the embodiment ofFIG. 2 ,core gates 220 that are parallel to one another may be arranged in parallel to I/O gates 240 that are parallel to one another. In another embodiment,core gates 220 and/or I/O gates 240 may be critically-dimensioned. - In some embodiments, one or more of I/
O gates 240 and/or one or more ofcore gates 220 may be arranged such that they are not parallel to the parallel I/O gates 240 and/or theparallel core gates 220. In one embodiment, such non-parallel gates will be relatively isolated or otherwise distanced from the parallel gates. Also, such non-parallel gates may not be critically-dimensioned, (e.g., may be comparatively larger in size than the parallel gates indevice 200.) In one embodiment, gates which may be properly characterized as non-critically-dimensioned can have minimum dimensions that are approximately 25-35% (or more) larger than the minimum dimensions of critically-dimensioned gates. - Device features, such as gates, that are substantially parallel may be arranged in parallel with the greatest accuracy possible. However, the terms parallel or substantially parallel will be used interchangeably. Furthermore, although the specification may utilize gates in describing embodiments of the present invention, it is understood that features other than gates may also benefit from the described configurations.
- Referring again to
FIG. 2 , the same I/O cell footprint is used for each I/O cell 210 around the periphery of thecore 250. As shown in the embodiment ofFIG. 2 , vertical I/O cells 270 and horizontal I/O cells 260 each have a short edge adjacent thecore area 250, effectively leaving unused severalopen areas 280. Horizontal I/O cell 260 and vertical I/O cell 270 have respective footprints that are rotationally disposed one from another. Consequently, for a particular function, it is difficult to use the same I/O cell gate layout horizontally and vertically while maintaining parallel gates within each I/O cell as well as among all I/O cells. As discussed, layouts can include both the features and their positions within the cell perimeter defined by the footprint. Therefore, for the embodiment ofFIG. 2 , it is desirable to design for each function two different I/O cell layouts, where horizontal I/O cells 260 have a layout which varies from that of vertical I/O cells 270, as shown. -
FIG. 3 depicts one embodiment of asemiconductor device 300 according to the invention having uniform I/O cell layouts throughout the device and substantially parallel gates throughout the device. As shown,core area 330 withparallel core gates 320. In this embodiment, the same I/O cell layout for a particular function can be used for an I/O cell regardless of I/O cell location. Thus, for a particular function, horizontal I/O cells 360 are substantially identical in layout and footprint to vertical I/O cells 370. Further, horizontal I/O cells 360 and vertical I/O cells 370 have like orientations. That is, horizontal I/O cells 360 are translationally, but not rotationally, disposed from vertical I/O cells 370. Therefore, I/O gates 390 are arranged substantially in parallel throughoutsemiconductor device 300. Consequently, gates may be arranged substantially in parallel throughout at least a majority of, if not substantially all of,semiconductor device 300. Additionally, as described above in reference toFIG. 2 ,core gates 320 and/or I/O gates 390 may be arranged in various configurations having substantially parallel gates. - In one embodiment, I/
O cell gates 390 are critically-dimensioned and arranged in parallel. As shown, I/O cell gates 390 may be parallel tocore gates 320. However, at least one I/O gate 390 may be arranged perpendicularly or otherwise not parallel to a majority ofcore gates 320. Such non-parallel gate may be isolated or offset from either I/O gates 390 within the I/O cell, orcore gates 320 arranged adjacent the I/O cell. - As noted, the horizontal I/
O cells 360 are substantially identical to the vertical I/O cells 370. Thus, horizontal I/O cells 360 have a cell size which is substantially the same as the cell size of the vertical I/O cells 370. Furthermore, the orientation of the horizontal I/O cells 360 is substantially the same as the orientation of the vertical I/O cells 370. That is, the horizontal I/O cells 360 are arranged like the vertical I/O cells 370 in that the shorter edges of all I/O cells are substantially parallel to one another. - In the embodiment shown in
FIG. 3 ,first cell edge 311 is shorter thansecond cell edge 312. Each I/O cell has afirst cell edge 311 arranged perpendicular to asecond cell edge 312. Afirst cell edge 311 of one I/O cell corresponds to afirst cell edge 311 of any other I/O cell, and asecond cell edge 312 of one I/O cell corresponds to asecond cell edge 312 of any other I/O cell. - Horizontal I/
O cell 360 is arranged alonghorizontal edge 313 ofdevice 300 such thatfirst cell edge 311 is parallel tohorizontal edge 313. Similarly, vertical I/O cell 370 is arranged alongvertical edge 314 ofdevice 300 such thatsecond cell edge 312 is parallel tovertical edge 314. Such an I/O cell layout more fully populates thedevice 300, allowing utilization of previously unused areas. - For example, depicted in
FIG. 2 areopen areas 280.Open areas 280 are located in the corners ofdevice 200. As shown inFIG. 3 , I/O cells 380 occupy such previously unused areas. In addition to more fully utilizing available area, I/O cells as described byFIG. 3 may yield other advantages, as described below in reference toFIG. 4 . -
FIG. 4 is one embodiment ofsemiconductor device 400 according to the invention having a fully populated layout of similarly-oriented I/O cells 410 overlaying the area outside thecore area 450, in which the I/O cells 410 have a uniform cell layout and substantially all of the gates indevice 400 are arranged in parallel. Similarly-oriented means substantially all short I/O cell edges are arranged parallel to one another and substantially all long I/O cell edges are arranged parallel to one another as shown inFIG. 4 . Such a layout includes additional I/O cells 410 as compared to the embodiment ofFIG. 3 . As described above in reference toFIGS. 2 and 3 , core device features (e.g., gates) and I/O device features (e.g., gates) may be arranged in various configurations such that all or substantially all the device features are substantially parallel to one another. As discussed previously, in an alternative embodiment, at least 90% of all device features ofsemiconductor device 400 can be arranged to be substantially parallel, while in yet another embodiment, there may less than 90% of all device features ofsemiconductor device 400 arranged in parallel. - As compared to
FIG. 3 , the I/O cell layouts ofFIG. 4 allows for additional I/O cells 410 arranged across the top and bottom edges of the die and/or core. Such a configuration may increase signal density of the semiconductor device. Additional I/O cells 410 may also allow additional functionality to be realized from the semiconductor device. In one embodiment, the additional I/O cells 410 allow a variety of routing options and/or packaging options. -
FIG. 5 depicts one embodiment of a semiconductor device according to the invention having acore area 550 with parallel gates and uniform I/O cells 510 (e.g., parallel gates, where the horizontal I/O cells 510 substantially match the vertical I/O cells 510), and where all I/O cells 510 have a substantially square footprint. Similar to embodiments previously discussed, I/O cells 510 having similar functionality are used in the x and y direction, and such I/O cells 510 have matching layouts. As described above in reference toFIGS. 2-4 , core device features (e.g., gates) and I/O device features (e.g., gates) may be arranged in various configurations, including for example, where a majority of device features are substantially parallel. - As noted above, aligning in parallel critically-dimensioned features may be useful in reducing process variation. For example, in the case of gate width variation among critically-dimensioned gates arranged within arrays. However, some circuits within the semiconductor device, such as analog circuits, may have wider gates. Thus, some gate widths may not be critically-dimensioned and such gate widths may not necessarily benefit from parallel arrangement.
-
FIG. 6 depicts one embodiment of asemiconductor device 600 according to the invention having layout uniform I/O cells 620 with gates parallel to a majority of the gates incore area 610 ofdevice 600. As shown,semiconductor device 600 includescore area 610 and I/O cells 620, where thecore area 610 includescircuit cells 690. As described above in reference to other FIGURES, core features 640 and I/O features 630 may be arranged in various configurations, including for example, where a majority of device features are substantially parallel. - In the embodiment of
FIG. 6 ,core area 610 has a majority of parallel features (e.g., gates), except for some features (e.g., gates) incircuit cells 690, which are not parallel. Incircuit cell 690, gate width variation may not be critical to the performance or yield of thesemiconductor device 600. As an example,circuit cell 690 may contain analog circuits, which have relatively wide gates or relatively long gates. Consequently, gate orientation incircuit cells 690 may be arbitrary. As shown,circuit cell 690 has gates oriented both horizontally and vertically. In this embodiment,circuit cell 690 may have no critically-dimensioned features. For example, the features ofcircuit cell 690 may be at least 25-35% larger than any of the critically dimensioned features ofdevice 600. - As shown in
FIGS. 7-9 , circuit cells can also be arranged within I/O cells. The circuit cells may be arranged in a number of configurations. Further, the circuit cells may have comparatively large features, for example long gate transistors (or conversely, wide gate transistors (not shown)). Consequently, circuit cells may have features which are not arranged in parallel. As described above in reference to other FIGURES, core device features and I/O device features may be arranged in various configurations where a majority of device features are substantially parallel. -
FIG. 7 depicts one embodiment ofsemiconductor device 700 according to the present invention with uniform I/O cells 710, but where such I/O cells 710 includecircuit cells 790 that can have gates that are not parallel to the other gates in semiconductor device 700 (as shown).Semiconductor device 700 has acore area 720 and I/O cells 710 where each I/O cell 710 includes acircuit cell 790.Circuit cells 790 may have at least one non-critically dimensioned feature, whereas, the remaining features in I/O cell 710 may be critically dimensioned. Further, there may be a number ofdifferent circuit cells 790 in I/O cells 710, each having a particular function. As shown inFIG. 7 , I/O cells 710 are substantially uniform. That is, I/O cells 710 have substantially the same I/O cell footprint and layout including placement ofcircuit cell 790 within I/O cell 710. As shown, I/O cells 710 are translationally disposed from each other. Furthermore, as shown inFIG. 7 , the non-circuit cell gates 730 are all arranged in parallel to each other, and are arranged in parallel tocore area gates 790. In an alternative embodiment, substantially allcore gates 790 can be parallel to one another, and in yet another alternative embodiment at least 90% of all core gates can be parallel to one another. It should be understood that various percentages of gates within I/O cells and cores of semiconductor devices can be parallel come within the scope of this invention. -
FIG. 8 depicts one embodiment of asemiconductor device 800 having acore area 820 and uniform I/O cells 810 that includecircuit cells 890. I/O cells 810, including placement ofcircuit cells 890, are arranged in a substantially reflexively matching manner. That is, the horizontally and vertically arranged same-function I/O cells 810 withcircuit cells 890 are symmetric about x and y axes, respectively. Thus, they may be described as reflexively matching. However, in one embodiment,circuit cells 890 may not necessarily be symmetric. Features within therespective circuit cells 890 are not necessarily reflexively matching. -
FIG. 9 depicts one embodiment of asemiconductor device 900 havingcore area 920 and uniform I/O cells 910 that includecircuit cells 990, where and I/O cells 910 are in point symmetry. In the embodiment,semiconductor device 900 hascircuit cells 990 arranged within each I/O cell 910. I/O cells 910 are in point symmetry from top to bottom and from side to side. That is, the top row I/O cell layouts, including placement ofcircuit cell 990, are rotated 180 degrees from the bottom row I/O cell layouts, including placement ofcircuit cell 990. The left and right columns of I/O cell layouts, including placement ofcircuit cell 990, are similarly rotated with respect to one another. Thus, in this embodiment, I/O cells 910 are in point symmetry. - As described above, lithographic images are created through the use of patterning devices. Each patterning device typically contains pattern images for a single processing layer. Pattern images are comprised of individual features, such as the individual features shown in
FIGS. 1 through 9 . Consequently,FIGS. 1 through 9 may also be representative of corresponding patterning devices instead of merely resultant semiconductor devices. Further, patterning devices may be used with any one of a variety of lithographic systems including, but not limited to, contact, g-line, i-line, duv, euv, x-ray, and imprint systems. As such, patterning devices may be any one of a variety of devices including, but not limited to, photomasks, reticles, and imprint templates. Furthermore, such a patterning device may not be limited solely to the manufacture of semiconductor devices. - In the foregoing specification, the invention has been described with reference to specific embodiments. For example, any time a Figure illustrates a uniform I/O cell with uniform feature layout and the same footprint, it should be understood that the footprint can vary from I/O cell to I/O cell (e.g., wider) without departing from the scope of the invention. One of ordinary skill in the art appreciates that various additional modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any component(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all the claims.
Claims (31)
1. A semiconductor integrated circuit device, comprising:
a core area; and
a plurality of I/O cells surrounding the core area, wherein each I/O cell comprises a plurality of features, wherein substantially all of the plurality of features are parallel to one another.
2. The device of claim 1 , wherein each of said I/O cells comprises a first cell edge arranged substantially perpendicular to a second cell edge, and further wherein at least one of said I/O cells has its first cell edge oriented substantially parallel to a horizontal edge of the device; and further wherein at least one other of said I/O cells has its second cell edge oriented substantially parallel to a vertical edge of the device.
3. The device claim 1 , wherein the I/O cell plurality of features comprise a plurality of I/O cell gates, and wherein at least 90% of said I/O cell gates are substantially parallel.
4. The device of claim 3 , wherein the plurality of I/O cells surround the core, and wherein the core comprises a plurality of core gates such that at least 90% of said core gates are substantially parallel to each other.
5. The device of claim 4 , wherein the at least 90% of said I/O cell gates are substantially parallel to at least 90% of said core gates.
6. The device claim 5 , wherein the plurality of core gates and the plurality of I/O cell gates comprise critically-dimensioned features.
7. The device of claim 6 , further comprising at least one circuit cell, wherein the at least one circuit cell comprises at least one circuit-cell feature, and wherein the at least one circuit cell is arranged within the core or within at least one of the I/O cells.
8. A method of configuring a semiconductor integrated circuit comprising:
providing a core area comprising a plurality of core features; and
arranging a plurality of uniform I/O cells surrounding the core area, wherein each uniform I/O cell has substantially all features parallel to one another.
9. The method of claim 8 , wherein the I/O cell plurality of features comprise a plurality of I/O cell gates and the plurality of core features comprise a plurality of core gates, and further comprising:
arranging at least 90% of the I/O cell gates substantially parallel to one another; and
arranging at least 90% of the core gates substantially parallel to one other and further substantially parallel to the substantially parallel I/O cell gates.
10. A semiconductor integrated circuit comprising:
a core, comprising a plurality of core device features arranged such that a majority of the plurality of core device features are substantially parallel; and
a plurality of I/O cells, each I/O cell comprising a plurality of I/O cell device features arranged such that a majority of the plurality of I/O cell device features in each I/O cell are substantially parallel.
11. The circuit of claim 10 , wherein substantially all of said core device features are substantially parallel and substantially all of said I/O cell device features are substantially parallel, and further wherein said core device features are substantially parallel to said I/O cell device features.
12. The circuit of claim 11 , wherein said substantially all of the plurality of core device features and substantially all of the plurality of I/O cell device features comprise critically-dimensioned features.
13. The circuit of 12, further comprising at least one circuit cell, wherein the at least one circuit cell comprises circuit cell device features, and wherein the at least one circuit cell is arranged within the core or within at least one I/O cell.
14. The circuit of claim 11 , wherein the plurality of I/O cells further comprise comprises a plurality of horizontal I/O cells and a plurality of vertical I/O cells, wherein said plurality of horizontal I/O cells and said plurality of vertical I/O cells have dissimilar layouts.
15. The circuit of claim 13 , wherein the circuit cell device features comprise at least one feature arranged perpendicular to said core device features or to said I/O cell device features.
16. The circuit of claim 11 , wherein the plurality of I/O cells further comprise a plurality of horizontal I/O cells and a plurality of vertical I/O cells, and wherein said plurality of horizontal I/O cells are translationally disposed with respect to said plurality of vertical I/O cells.
17. The circuit of claim 10 , wherein said core device features and said I/O cell device features comprise gates.
18. The circuit of claim 11 , wherein said I/O cells have a substantially square footprint.
19. A method of configuring a semiconductor integrated circuit device, comprising:
orienting a plurality of core device features in a core substantially parallel to one another; and
orienting a plurality of I/O cell device features in an I/O cell substantially parallel to one another, wherein said core device features and said I/O cell device features are arranged within a common layer.
20. A semiconductor integrated circuit device, comprising:
a core comprising a plurality of core device features arranged such that at least 90% of said core device features are substantially parallel; and
a plurality of I/O cells having substantially matching device feature layouts, each I/O cell comprising a plurality of I/O cell device features arranged such that at least 90% of said I/O cell device features are substantially parallel.
21. The device of claim 20 , wherein each I/O cells comprises a first cell edge arranged substantially perpendicular to a second cell edge, wherein a first cell edge of a first I/O cell corresponds to a first cell edge of a second I/O cell, wherein at least one of said I/O cells is oriented along a horizontal edge of the device such that a first cell edge of said at least one horizontal I/O cell is substantially parallel to a horizontal edge of the device; and wherein at least one of said I/O cells along a vertical edge of the device is oriented such that a second cell edge of said at least one vertical I/O cell is substantially parallel to a vertical edge of the device.
22. The device of claim 21 , wherein said parallel core device features are parallel to said parallel I/O device features, and wherein said parallel features are arranged on a common layer.
23. The device of claim 22 , further comprising at least two circuit cells, wherein the at least two circuit cells comprise circuit-cell device features, wherein at least one circuit cell is arranged within a horizontal I/O cell, and wherein at least one circuit cell is arranged within a vertical I/O cell.
24. The device of claim 23 , wherein said horizontal I/O cell and said vertical I/O cell are symmetrically disposed or translationally disposed.
25. The device of claim 24 , further comprising at least one circuit cell, wherein the at least one circuit cell comprises at least one circuit-cell device feature, and wherein the at least one circuit cell is arranged within the core.
26. A patterning device used to produce layer-specific semiconductor device features, said patterning device comprising:
a core area, comprising a plurality of critically-dimensioned core features, wherein at least 90% of said critically-dimensioned core features are configured in parallel; and
an I/O cell area bordering the core area, wherein the I/O cell area comprises a plurality of critically-dimensioned I/O cell features, wherein substantially all critically-dimensioned I/O cell features are configured in parallel.
27. The patterning device of claim 26 , wherein substantially all critically-dimensioned core features are configured in parallel and substantially all critically-dimensioned I/O cell features are configured in parallel.
28. The patterning device of claim 27 , wherein the critically-dimensioned core features are substantially parallel to the critically-dimensioned I/O cell features.
29. The patterning of claim 28 , further comprising at least one circuit cell, wherein the at least one circuit cell has at least one non-critically-dimensioned device feature.
30. The patterning device of claim 29 , wherein the I/O cell area comprises at least one horizontal I/O cell and at least one vertical I/O cell, wherein each I/O cell comprises a circuit cell, and wherein said I/O cells have substantially matching feature layouts such that the at least one horizontal I/O cell layout is translationally disposed from the at least one vertical I/O cell layout.
31. The patterning device as recited in claim 29 , wherein the I/O cell area comprises at least one horizontal I/O cell and at least one vertical I/O cell, wherein each I/O cell comprises a circuit cell, and wherein said I/O cells have substantially matching feature layouts such that the at least one horizontal I/O cell layout is in point symmetry with the at least one vertical I/O cell layout.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20110089470A1 (en) * | 2009-10-20 | 2011-04-21 | Mutsumi Aoki | Semiconductor device having layout of logic cell and interface cell with unification of transistor orientation |
US9281362B2 (en) | 2013-09-27 | 2016-03-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
WO2016039848A1 (en) * | 2014-09-08 | 2016-03-17 | Qualcomm Incorporated | Half-node scaling for vertical structures |
US9478541B2 (en) | 2014-09-08 | 2016-10-25 | Qualcomm Incorporated | Half node scaling for vertical structures |
FR3028351A1 (en) * | 2014-11-12 | 2016-05-13 | St Microelectronics Sa | INTEGRATED MULTI-ORIENTATION CELL, IN PARTICULAR INPUT / INPUT CIRCUIT INLET CELL |
US9735772B2 (en) | 2014-11-12 | 2017-08-15 | Stmicroelectronics Sa | Multi-orientation integrated cell, in particular input/output cell of an integrated circuit |
US11482517B2 (en) * | 2015-10-22 | 2022-10-25 | United Microelectronics Corp. | Integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
US7910956B2 (en) | 2011-03-22 |
US20110133252A1 (en) | 2011-06-09 |
US8183599B2 (en) | 2012-05-22 |
US20100096670A1 (en) | 2010-04-22 |
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