US20060283915A1 - Positioning flowable solder for bonding integrated circuit elements - Google Patents
Positioning flowable solder for bonding integrated circuit elements Download PDFInfo
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- US20060283915A1 US20060283915A1 US11/506,241 US50624106A US2006283915A1 US 20060283915 A1 US20060283915 A1 US 20060283915A1 US 50624106 A US50624106 A US 50624106A US 2006283915 A1 US2006283915 A1 US 2006283915A1
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/30105—Capacitance
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A solder mask defined bond pad or a non-solder mask defined bond pad may be configured to center the solder over the bond pad using either surface attractive forces or capillary action. In some embodiments, a stub trace may be provided, for example, in opposition to the real trace to provide a capillary counter-attractive force on the solder. In other embodiments, the surface attractive action of the edge of the solder mask may be utilized to center the solder. In still other embodiments, the natural attractive force of a trace on solder may be utilized to appropriately position solder where desired, for example, to line up with other solder deposits.
Description
- This application is a divisional of U.S. patent application Ser. No. 09/377,286, filed on Aug. 18, 1999.
- This invention relates generally to solder bonding techniques for integrated circuit devices.
- Referring to
FIG. 10 , commonly solder is deposited on asolder pad 62 which is coupled to other electrical components on an integrated circuit by atrace 60. The solder deposition area is defined by theinwardmost edge 64 of a solder mask. Thus, in the embodiment illustrated inFIG. 10 , the solder is deposited inside thecircle 64. The solder mask prevents solder outflow over the mask thereby preventing the solder from moving outwardly beyond theedge 64. - The solder may be in the form of conventional solder balls which are deposited in a solid configuration and then reflowed thereafter. Alternating the solder may be a liquid or paste upon deposition.
- Referring to
FIG. 11 , one problem with existing techniques for depositing solder is that when soft thesolder 66 tends to wick along thetrace 60. Without limitation, it is believed that the wicking is a result of capillary attraction between thesolder 66 and thetrace 60. As a result, thesolder 66 ends up being displaced with respect to thepad 62, as indicated inFIG. 11 . In particular, the solder may abut thesolder mask edge 64. Generally, the solder does not extend onto the solder mask since the mask functions to control solder flow. - Thus, improper contact may result between the solder and the
solder pad 62 as a result of the wicking action of the solder. Of course, this problem may be reduced by decreasing the diameter of the opening 64 in the solder mask. However, this creates tighter tolerances in the process flow. One adverse result may be that the solder mask opening is misaligned to thepad 62 to such an extent that the solder mask opening does not permit the solder to be placed on the pad. - In ball grid array (BGA) packaging techniques an array of solder pads may be aligned with an array of solder balls. If the balls tend to wick away from their solder pads, the balls may become misaligned with other balls in the array. Thus, there may be no way to cause an integrated circuit connector to appropriately connect to all the balls because all the balls have been randomly misaligned. Referring to
FIG. 12 , theball 68 on the top has wicked to the right because itstrace 60 extends to the right whereas theball 76 on the bottom has wicked to the left because of the leftward extension of itstrace 70. The center line “CL” of thepads - Still another problem that may arise in the prior art is the surface action effects of the edge of the solder resist mask.
FIG. 13 illustrates a conventional solder mask defined pad (SDP). In this case, the useful portion of thepad 80 is effectively defined by the opening 82 in the solder mask. This is because the size of the opening 82 is less than the size of thepad 80. Thus, wicking along thetrace 78 may be prevented. However, the mask may tend to attract thesolder 84 to its edge, for example as a result of surface attraction effects. Again, the problem is similar to the problem described previously in that the solder tends to be attracted away from its desired location. - Thus, there is a need for better ways to appropriately position solder on bond pads coupled to conductive traces.
- In accordance with one embodiment, a bond pad assembly may include a bond pad and a trace coupled to the pad. The trace extends away from the pad in a first direction. A trace stub is coupled to the pad and extends away from the pad in a direction other than the first direction.
- Other aspects are set forth in the ensuing detailed description and claims.
-
FIG. 1 is an enlarged top plan view of one embodiment to the present invention; -
FIG. 2 is a cross-sectional view taken generally along the line 2-2 shown inFIG. 1 after solder has been placed on the pad; -
FIG. 3 is an enlarged top plan view of another embodiment of the present invention; -
FIG. 4 is a cross-sectional view taken generally along the line 4-4 shown inFIG. 3 after solder has been placed on the pad; -
FIG. 5 is an enlarged top plan view of still another embodiment to the present invention; -
FIG. 6 is a cross-sectional view taken generally along the line 6-6 inFIG. 5 ; -
FIG. 7 is an enlarged top plan view of still another embodiment of the present invention; -
FIG. 8 is a cross-sectional view taken generally along the line 8-8 inFIG. 7 after the solder has been placed on the pads; -
FIG. 9 is an enlarged top plan view of another embodiment of the present invention; -
FIG. 10 is an enlarged top plan view of an embodiment in accordance with the prior art; -
FIG. 11 is an enlarged top plan view of another embodiment in accordance with the prior art; -
FIG. 12 is an enlarged top plan view of still another embodiment in accordance with the prior art; and -
FIG. 13 is an enlarged top plan view of still another embodiment in accordance with the prior art. - Referring to
FIG. 1 , abond assembly 10 includes abond pad 14 coupled to atrace 12 extending away from thebond pad 14 in a first direction. The bond assembly may be formed on a support which may be, for example, an integrated circuit die, an interposer, or-a printed circuit board. While thebond pad 14 is illustrated as being circular other shapes can be used as well. Thebond pad 14 may be utilized in connection with packaging a variety of different integrated circuit devices. - In one application, the
bond pad 14 may be arranged to interact with solder balls to implement a flip chip bonding technique, a ball grid array bonding technique or any of the variations of bump-type interconnections which may be known to those skilled in the art. In ball grid array packaging techniques, a relatively solid ball is positioned on the bond pad and subsequently reflowed. In other techniques, liquid or semi-liquid solder may be utilized which may flow upon deposition without the application of heat. - A
trace stub 16 extends away from thebond pad 12 in a second direction. Advantageously, thestub 16 may be made of the same material and may be of the same width and thickness as thetrace 12. The first and second directions may be diametrically opposed. - The region which may receive the solder may be greater than the size of the
bond pad 14. Conveniently, the potential solder receiving area may be defined by a solder mask whose inward extent is marked by thesolder mask edge 18. Thus, solder is masked away from the remainder of the device with the exception of the area inside theedge 18. - Referring to
FIG. 2 , asolder ball 20 has been reflowed over thepad 14. As shown inFIG. 2 , thesolder mask edge 18 actually overlaps thetrace stub 16. This provides greater tolerances and ensures that thestub 16 will extend beyond thesolder mask edge 18. With this configuration, if the solder attempts to wick to the left to follow thetrace 12 due to capillary action or any other reason, it will be pulled back to the right by the action of thestub 16. Thus, the forces applied by thestub 16 counteract the wicking action of thetrace 12. In some embodiments, it may be desirable to make thesolder pad 14 relatively small so that thesolder ball 20 is acted upon simultaneously by both thetrace 12 andstub 16. - In another embodiment of the present invention, shown in
FIG. 3 , abond assembly 20 includes an enlarged elliptical or teardrop-shapedbond pad portion 24 which is designed to reduce the capacitance caused by the bond pad maincircular section 26. Thus, thebond pad portion 24 has a elliptical configuration of smaller size than that the maincircular section 26. Theportion 24 is coupled to thetrace 22 on one end. In the embodiment illustrated inFIG. 3 , a matching or mirror image portion orstub 28 is formed on the other side of thesection 26. The function of thestub 28 is to counteract any wicking action resulting from theportion 24. In some embodiments an additional stub, like thestub 16, may be caused to extend outwardly from thestub 28 in opposition to thetrace 22. - In the embodiment illustrated in
FIG. 3 , the matchingstub 28 does not extend outside of the boundary defined by thesolder mask edge 18. Thus, in some embodiments it may be preferable to cause the matching portion to extend beyond the solder mask edge and in other cases this may not be desirable. - Referring to
FIG. 4 , when asolder ball 20 is positioned on thesection 26, it is equally attracted to the left and to the right by theopposed portions solder ball 20 may center on thesection 26. - The embodiment in
FIG. 1 illustrates a non-solder mask defined pad (NSDP). However, as explained in more detail hereinafter, the present invention is also applicable to solder mask defined pads (SDP). Referring now toFIG. 5 , showing an SDP embodiment of the present invention, a solder mask has a cloverleaf-shapededge 32 which extends inwardly of thebond pad 34 and itstrace 30. Each of thelobes 33 of the cloverleaf-shapededge 32 may have a surface action attraction on thesolder ball 36. - By providing four sets of identically shaped clover leaf shaped lobes, the action of the
edges 32 on the solder may be neutralized. One force on the solder is believed to be due to surface tension effects. Moreover, by having the convex edges 35 of thesolder mask 32 substantially spaced apart by a diameter approximately equally the diameter of thesolder 36, the solder tends to be maintained substantially centrally, as illustrated inFIG. 6 . - Referring now to
FIGS. 7 and 8 , an embodiment in which the wicking action of atraces solder balls 20 and 20A is illustrated in an NSDP arrangement. In this case, thebond pads bond pad 50 to overlap with thetrace 40 coupled to thebond pad 42 so that a nested configuration may be achieved. In each case, asolder mask edge solder ball - After being deposited on the
pad 42 and reflowed, thesolder ball 20 may tend to move to the left due to the wicking action of thetrace 40. Similarly, when thesolder ball 20 a is placed on thepad 50, it tends to wick to the right. As a result of the wicking action, thesolder balls - Turning now to
FIG. 9 , still another embodiment of a non-solder mask defined pad is illustrated. In this case, thepad 102 is coupled to atrace 100. A solder receiving area is defined by theedge 110 of the solder mask. Atrace stub 104 is provided as illustrated previously in connection withFIG. 1 . In addition, a pair oftrace stubs trace 100 and thestub 104. Thestubs trace 100 and thestub 104. Thestubs FIG. 9 , while thestub 104 together with thetrace 100 provide horizontal centering. Thus, the embodiment shown inFIG. 9 prevents the solder from moving up or down. The solder may move up and down, not because of the wicking action of the trace, but for some other reason such as other attractive forces, or tilting of the pad supporting surface. - While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims (9)
1. A method of positioning solder on bond pads: coupled to traces, said bond pads being surrounded by solder mask material, said method comprising:
depositing solder on a first bond pad having a trace extending in a first direction;
depositing solder on a second bond pad having a trace extending in a second direction, said first and second directions being different; and
causing said solder deposited on said first bond pad to move to a displaced position with respect to said first bond pad, such that said solder aligns with said solder deposited on said second bond pad.
2. The method of claim 1 including nesting said first bond pad with a trace coupled to said second bond pad, and nesting said second bond pad with a trace coupled to said first bond pad.
3. The method of claim 1 wherein causing includes wicking said solder towards a trace coupled to said first bond pad.
4. A method of forming solder connections in integrated circuits comprising:
depositing solder on a bond pad;
counteracting an attractive force supplied by a bond pad trace to the solder by providing a similar and opposite force on the solder.
5. The method of claim 4 wherein counteracting includes forming a trace-like portion which extends away from said bond pad in a direction opposite to the direction that the trace extends away from said bond pad.
6. The method of claim 5 wherein counteracting includes forming a solder mask around said bond pad and causing said trace-like element to extend outwardly from said bond pad into said solder mask.
7. The method of claim 4 wherein counteracting includes forming tear-drop shaped portions on two opposed sides of a bond pad.
8. The method of claim 4 further including providing elements which tend to cause said solder to center on said bond pad.
9. The method of claim 8 further including providing a set of three elements coupled to said bond pad and oriented at approximately 90° to an adjacent element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/506,241 US20060283915A1 (en) | 1999-08-18 | 2006-08-17 | Positioning flowable solder for bonding integrated circuit elements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/377,286 US7115819B1 (en) | 1999-08-18 | 1999-08-18 | Positioning flowable solder for bonding integrated circuit elements |
US11/506,241 US20060283915A1 (en) | 1999-08-18 | 2006-08-17 | Positioning flowable solder for bonding integrated circuit elements |
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Application Number | Title | Priority Date | Filing Date |
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US09/377,286 Division US7115819B1 (en) | 1999-08-18 | 1999-08-18 | Positioning flowable solder for bonding integrated circuit elements |
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US20060283915A1 true US20060283915A1 (en) | 2006-12-21 |
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US09/377,286 Expired - Fee Related US7115819B1 (en) | 1999-08-18 | 1999-08-18 | Positioning flowable solder for bonding integrated circuit elements |
US11/506,241 Abandoned US20060283915A1 (en) | 1999-08-18 | 2006-08-17 | Positioning flowable solder for bonding integrated circuit elements |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20130099370A1 (en) * | 2011-10-20 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7340181B1 (en) * | 2002-05-13 | 2008-03-04 | National Semiconductor Corporation | Electrical die contact structure and fabrication method |
TWI278081B (en) * | 2005-12-22 | 2007-04-01 | Siliconware Precision Industries Co Ltd | Electronic carrier board and package structure thereof |
TWI488272B (en) * | 2009-02-23 | 2015-06-11 | Advanced Semiconductor Eng | Circuit board and chip package structure |
US9935038B2 (en) * | 2012-04-11 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company | Semiconductor device packages and methods |
US8900911B2 (en) | 2012-05-29 | 2014-12-02 | Essence Solar Solutions Ltd. | Frame holder |
US10192840B2 (en) * | 2015-09-25 | 2019-01-29 | Intel Corporation | Ball pad with a plurality of lobes |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3537176A (en) * | 1969-04-01 | 1970-11-03 | Lockheed Aircraft Corp | Interconnection of flexible electrical circuits |
US5519580A (en) * | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
US5585162A (en) * | 1995-06-16 | 1996-12-17 | Minnesota Mining And Manufacturing Company | Ground plane routing |
JP3037222B2 (en) * | 1997-09-11 | 2000-04-24 | 九州日本電気株式会社 | BGA type semiconductor device |
-
1999
- 1999-08-18 US US09/377,286 patent/US7115819B1/en not_active Expired - Fee Related
-
2006
- 2006-08-17 US US11/506,241 patent/US20060283915A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130099370A1 (en) * | 2011-10-20 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package |
US9786622B2 (en) * | 2011-10-20 | 2017-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package |
Also Published As
Publication number | Publication date |
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US7115819B1 (en) | 2006-10-03 |
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