US20060283915A1 - Positioning flowable solder for bonding integrated circuit elements - Google Patents

Positioning flowable solder for bonding integrated circuit elements Download PDF

Info

Publication number
US20060283915A1
US20060283915A1 US11/506,241 US50624106A US2006283915A1 US 20060283915 A1 US20060283915 A1 US 20060283915A1 US 50624106 A US50624106 A US 50624106A US 2006283915 A1 US2006283915 A1 US 2006283915A1
Authority
US
United States
Prior art keywords
solder
bond pad
trace
pad
bond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/506,241
Inventor
Brad Rumsey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/506,241 priority Critical patent/US20060283915A1/en
Publication of US20060283915A1 publication Critical patent/US20060283915A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09381Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989Coating free areas, e.g. areas other than pads or lands free of solder resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/043Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A solder mask defined bond pad or a non-solder mask defined bond pad may be configured to center the solder over the bond pad using either surface attractive forces or capillary action. In some embodiments, a stub trace may be provided, for example, in opposition to the real trace to provide a capillary counter-attractive force on the solder. In other embodiments, the surface attractive action of the edge of the solder mask may be utilized to center the solder. In still other embodiments, the natural attractive force of a trace on solder may be utilized to appropriately position solder where desired, for example, to line up with other solder deposits.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 09/377,286, filed on Aug. 18, 1999.
  • BACKGROUND
  • This invention relates generally to solder bonding techniques for integrated circuit devices.
  • Referring to FIG. 10, commonly solder is deposited on a solder pad 62 which is coupled to other electrical components on an integrated circuit by a trace 60. The solder deposition area is defined by the inwardmost edge 64 of a solder mask. Thus, in the embodiment illustrated in FIG. 10, the solder is deposited inside the circle 64. The solder mask prevents solder outflow over the mask thereby preventing the solder from moving outwardly beyond the edge 64.
  • The solder may be in the form of conventional solder balls which are deposited in a solid configuration and then reflowed thereafter. Alternating the solder may be a liquid or paste upon deposition.
  • Referring to FIG. 11, one problem with existing techniques for depositing solder is that when soft the solder 66 tends to wick along the trace 60. Without limitation, it is believed that the wicking is a result of capillary attraction between the solder 66 and the trace 60. As a result, the solder 66 ends up being displaced with respect to the pad 62, as indicated in FIG. 11. In particular, the solder may abut the solder mask edge 64. Generally, the solder does not extend onto the solder mask since the mask functions to control solder flow.
  • Thus, improper contact may result between the solder and the solder pad 62 as a result of the wicking action of the solder. Of course, this problem may be reduced by decreasing the diameter of the opening 64 in the solder mask. However, this creates tighter tolerances in the process flow. One adverse result may be that the solder mask opening is misaligned to the pad 62 to such an extent that the solder mask opening does not permit the solder to be placed on the pad.
  • In ball grid array (BGA) packaging techniques an array of solder pads may be aligned with an array of solder balls. If the balls tend to wick away from their solder pads, the balls may become misaligned with other balls in the array. Thus, there may be no way to cause an integrated circuit connector to appropriately connect to all the balls because all the balls have been randomly misaligned. Referring to FIG. 12, the ball 68 on the top has wicked to the right because its trace 60 extends to the right whereas the ball 76 on the bottom has wicked to the left because of the leftward extension of its trace 70. The center line “CL” of the pads 62 and 72 may have been the projected alignment between the balls. In fact the balls are substantially misaligned.
  • Still another problem that may arise in the prior art is the surface action effects of the edge of the solder resist mask. FIG. 13 illustrates a conventional solder mask defined pad (SDP). In this case, the useful portion of the pad 80 is effectively defined by the opening 82 in the solder mask. This is because the size of the opening 82 is less than the size of the pad 80. Thus, wicking along the trace 78 may be prevented. However, the mask may tend to attract the solder 84 to its edge, for example as a result of surface attraction effects. Again, the problem is similar to the problem described previously in that the solder tends to be attracted away from its desired location.
  • Thus, there is a need for better ways to appropriately position solder on bond pads coupled to conductive traces.
  • SUMMARY
  • In accordance with one embodiment, a bond pad assembly may include a bond pad and a trace coupled to the pad. The trace extends away from the pad in a first direction. A trace stub is coupled to the pad and extends away from the pad in a direction other than the first direction.
  • Other aspects are set forth in the ensuing detailed description and claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an enlarged top plan view of one embodiment to the present invention;
  • FIG. 2 is a cross-sectional view taken generally along the line 2-2 shown in FIG. 1 after solder has been placed on the pad;
  • FIG. 3 is an enlarged top plan view of another embodiment of the present invention;
  • FIG. 4 is a cross-sectional view taken generally along the line 4-4 shown in FIG. 3 after solder has been placed on the pad;
  • FIG. 5 is an enlarged top plan view of still another embodiment to the present invention;
  • FIG. 6 is a cross-sectional view taken generally along the line 6-6 in FIG. 5;
  • FIG. 7 is an enlarged top plan view of still another embodiment of the present invention;
  • FIG. 8 is a cross-sectional view taken generally along the line 8-8 in FIG. 7 after the solder has been placed on the pads;
  • FIG. 9 is an enlarged top plan view of another embodiment of the present invention;
  • FIG. 10 is an enlarged top plan view of an embodiment in accordance with the prior art;
  • FIG. 11 is an enlarged top plan view of another embodiment in accordance with the prior art;
  • FIG. 12 is an enlarged top plan view of still another embodiment in accordance with the prior art; and
  • FIG. 13 is an enlarged top plan view of still another embodiment in accordance with the prior art.
  • DETAILED DESCRIPTION
  • Referring to FIG. 1, a bond assembly 10 includes a bond pad 14 coupled to a trace 12 extending away from the bond pad 14 in a first direction. The bond assembly may be formed on a support which may be, for example, an integrated circuit die, an interposer, or-a printed circuit board. While the bond pad 14 is illustrated as being circular other shapes can be used as well. The bond pad 14 may be utilized in connection with packaging a variety of different integrated circuit devices.
  • In one application, the bond pad 14 may be arranged to interact with solder balls to implement a flip chip bonding technique, a ball grid array bonding technique or any of the variations of bump-type interconnections which may be known to those skilled in the art. In ball grid array packaging techniques, a relatively solid ball is positioned on the bond pad and subsequently reflowed. In other techniques, liquid or semi-liquid solder may be utilized which may flow upon deposition without the application of heat.
  • A trace stub 16 extends away from the bond pad 12 in a second direction. Advantageously, the stub 16 may be made of the same material and may be of the same width and thickness as the trace 12. The first and second directions may be diametrically opposed.
  • The region which may receive the solder may be greater than the size of the bond pad 14. Conveniently, the potential solder receiving area may be defined by a solder mask whose inward extent is marked by the solder mask edge 18. Thus, solder is masked away from the remainder of the device with the exception of the area inside the edge 18.
  • Referring to FIG. 2, a solder ball 20 has been reflowed over the pad 14. As shown in FIG. 2, the solder mask edge 18 actually overlaps the trace stub 16. This provides greater tolerances and ensures that the stub 16 will extend beyond the solder mask edge 18. With this configuration, if the solder attempts to wick to the left to follow the trace 12 due to capillary action or any other reason, it will be pulled back to the right by the action of the stub 16. Thus, the forces applied by the stub 16 counteract the wicking action of the trace 12. In some embodiments, it may be desirable to make the solder pad 14 relatively small so that the solder ball 20 is acted upon simultaneously by both the trace 12 and stub 16.
  • In another embodiment of the present invention, shown in FIG. 3, a bond assembly 20 includes an enlarged elliptical or teardrop-shaped bond pad portion 24 which is designed to reduce the capacitance caused by the bond pad main circular section 26. Thus, the bond pad portion 24 has a elliptical configuration of smaller size than that the main circular section 26. The portion 24 is coupled to the trace 22 on one end. In the embodiment illustrated in FIG. 3, a matching or mirror image portion or stub 28 is formed on the other side of the section 26. The function of the stub 28 is to counteract any wicking action resulting from the portion 24. In some embodiments an additional stub, like the stub 16, may be caused to extend outwardly from the stub 28 in opposition to the trace 22.
  • In the embodiment illustrated in FIG. 3, the matching stub 28 does not extend outside of the boundary defined by the solder mask edge 18. Thus, in some embodiments it may be preferable to cause the matching portion to extend beyond the solder mask edge and in other cases this may not be desirable.
  • Referring to FIG. 4, when a solder ball 20 is positioned on the section 26, it is equally attracted to the left and to the right by the opposed portions 24 and 28. Thus, the solder ball 20 may center on the section 26.
  • The embodiment in FIG. 1 illustrates a non-solder mask defined pad (NSDP). However, as explained in more detail hereinafter, the present invention is also applicable to solder mask defined pads (SDP). Referring now to FIG. 5, showing an SDP embodiment of the present invention, a solder mask has a cloverleaf-shaped edge 32 which extends inwardly of the bond pad 34 and its trace 30. Each of the lobes 33 of the cloverleaf-shaped edge 32 may have a surface action attraction on the solder ball 36.
  • By providing four sets of identically shaped clover leaf shaped lobes, the action of the edges 32 on the solder may be neutralized. One force on the solder is believed to be due to surface tension effects. Moreover, by having the convex edges 35 of the solder mask 32 substantially spaced apart by a diameter approximately equally the diameter of the solder 36, the solder tends to be maintained substantially centrally, as illustrated in FIG. 6.
  • Referring now to FIGS. 7 and 8, an embodiment in which the wicking action of a traces 40 and 46 may be used to achieve a desired orientation for solder balls 20 and 20A is illustrated in an NSDP arrangement. In this case, the bond pads 42 and 50 may be placed relatively closer together than is normally the case. This may be done by causing the bond pad 50 to overlap with the trace 40 coupled to the bond pad 42 so that a nested configuration may be achieved. In each case, a solder mask edge 44 or 48 is defined which delimits the extent to which the solder ball 20 or 20 a may move.
  • After being deposited on the pad 42 and reflowed, the solder ball 20 may tend to move to the left due to the wicking action of the trace 40. Similarly, when the solder ball 20 a is placed on the pad 50, it tends to wick to the right. As a result of the wicking action, the solder balls 20 and 20 a line up one above the other exactly as desired. Thus, in this case, the adverse effect of trace wicking is used to obtain the desired alignment between the balls. The desired ball alignment may be useful in causing the balls to interact with other contacts on another device. In some cases, this technique may enable the bond pads to be nested and thereby packed together more closely.
  • Turning now to FIG. 9, still another embodiment of a non-solder mask defined pad is illustrated. In this case, the pad 102 is coupled to a trace 100. A solder receiving area is defined by the edge 110 of the solder mask. A trace stub 104 is provided as illustrated previously in connection with FIG. 1. In addition, a pair of trace stubs 108 and 106 extend transversely to the lengths of the trace 100 and the stub 104. The stubs 106 and 108 center the solder (not shown) along the axis transverse to the axis of the trace 100 and the stub 104. The stubs 106 and 108 provide effectively vertical centering in the orientation shown in FIG. 9, while the stub 104 together with the trace 100 provide horizontal centering. Thus, the embodiment shown in FIG. 9 prevents the solder from moving up or down. The solder may move up and down, not because of the wicking action of the trace, but for some other reason such as other attractive forces, or tilting of the pad supporting surface.
  • While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (9)

1. A method of positioning solder on bond pads: coupled to traces, said bond pads being surrounded by solder mask material, said method comprising:
depositing solder on a first bond pad having a trace extending in a first direction;
depositing solder on a second bond pad having a trace extending in a second direction, said first and second directions being different; and
causing said solder deposited on said first bond pad to move to a displaced position with respect to said first bond pad, such that said solder aligns with said solder deposited on said second bond pad.
2. The method of claim 1 including nesting said first bond pad with a trace coupled to said second bond pad, and nesting said second bond pad with a trace coupled to said first bond pad.
3. The method of claim 1 wherein causing includes wicking said solder towards a trace coupled to said first bond pad.
4. A method of forming solder connections in integrated circuits comprising:
depositing solder on a bond pad;
counteracting an attractive force supplied by a bond pad trace to the solder by providing a similar and opposite force on the solder.
5. The method of claim 4 wherein counteracting includes forming a trace-like portion which extends away from said bond pad in a direction opposite to the direction that the trace extends away from said bond pad.
6. The method of claim 5 wherein counteracting includes forming a solder mask around said bond pad and causing said trace-like element to extend outwardly from said bond pad into said solder mask.
7. The method of claim 4 wherein counteracting includes forming tear-drop shaped portions on two opposed sides of a bond pad.
8. The method of claim 4 further including providing elements which tend to cause said solder to center on said bond pad.
9. The method of claim 8 further including providing a set of three elements coupled to said bond pad and oriented at approximately 90° to an adjacent element.
US11/506,241 1999-08-18 2006-08-17 Positioning flowable solder for bonding integrated circuit elements Abandoned US20060283915A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/506,241 US20060283915A1 (en) 1999-08-18 2006-08-17 Positioning flowable solder for bonding integrated circuit elements

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/377,286 US7115819B1 (en) 1999-08-18 1999-08-18 Positioning flowable solder for bonding integrated circuit elements
US11/506,241 US20060283915A1 (en) 1999-08-18 2006-08-17 Positioning flowable solder for bonding integrated circuit elements

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/377,286 Division US7115819B1 (en) 1999-08-18 1999-08-18 Positioning flowable solder for bonding integrated circuit elements

Publications (1)

Publication Number Publication Date
US20060283915A1 true US20060283915A1 (en) 2006-12-21

Family

ID=37037253

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/377,286 Expired - Fee Related US7115819B1 (en) 1999-08-18 1999-08-18 Positioning flowable solder for bonding integrated circuit elements
US11/506,241 Abandoned US20060283915A1 (en) 1999-08-18 2006-08-17 Positioning flowable solder for bonding integrated circuit elements

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/377,286 Expired - Fee Related US7115819B1 (en) 1999-08-18 1999-08-18 Positioning flowable solder for bonding integrated circuit elements

Country Status (1)

Country Link
US (2) US7115819B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130099370A1 (en) * 2011-10-20 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7340181B1 (en) * 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
TWI278081B (en) * 2005-12-22 2007-04-01 Siliconware Precision Industries Co Ltd Electronic carrier board and package structure thereof
TWI488272B (en) * 2009-02-23 2015-06-11 Advanced Semiconductor Eng Circuit board and chip package structure
US9935038B2 (en) * 2012-04-11 2018-04-03 Taiwan Semiconductor Manufacturing Company Semiconductor device packages and methods
US8900911B2 (en) 2012-05-29 2014-12-02 Essence Solar Solutions Ltd. Frame holder
US10192840B2 (en) * 2015-09-25 2019-01-29 Intel Corporation Ball pad with a plurality of lobes

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3537176A (en) * 1969-04-01 1970-11-03 Lockheed Aircraft Corp Interconnection of flexible electrical circuits
US5519580A (en) * 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
US5585162A (en) * 1995-06-16 1996-12-17 Minnesota Mining And Manufacturing Company Ground plane routing
JP3037222B2 (en) * 1997-09-11 2000-04-24 九州日本電気株式会社 BGA type semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130099370A1 (en) * 2011-10-20 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US9786622B2 (en) * 2011-10-20 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package

Also Published As

Publication number Publication date
US7115819B1 (en) 2006-10-03

Similar Documents

Publication Publication Date Title
US20060283915A1 (en) Positioning flowable solder for bonding integrated circuit elements
JP2746035B2 (en) Semiconductor device assembly with controlled expansion of polymer underfill
JP3080607B2 (en) Method of controlling solder bump shape and standoff height
US8318537B2 (en) Flip chip interconnection having narrow interconnection sites on the substrate
US6418033B1 (en) Microelectronic packages in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles
EP0971569A1 (en) Enhanced mounting pads for printed circuit boards
KR970078788A (en) Microelectronic Mounting Using Arc Solder Columns
CN100423248C (en) Semiconductor device and unit equipped with the same
US7368666B2 (en) Surface-mounting type electronic circuit unit without detachment of solder
JP2000312072A (en) Method of soldering electronic component with lead
JP2003142174A (en) Conductive member
US7309924B2 (en) UBM for fine pitch solder ball and flip-chip packaging method using the same
JP2702839B2 (en) Wiring board electrode structure
US4728305A (en) Solder-bearing leads
JP2924844B2 (en) Semiconductor device and manufacturing method thereof
US4891472A (en) Interconnects on a printed circuit board having connecting points for an electronic component with a plurality of terminals
US10201086B2 (en) Electronic device
US6424049B1 (en) Semiconductor device having chip-on-chip structure and semiconductor chip used therefor
JP3410199B2 (en) Device for preventing bridging of connection member, semiconductor integrated circuit having the same, and mounting substrate
JP2002246512A (en) Structure of bga package and structure of mount substrate
KR100393096B1 (en) Joining structure of semiconductor package and mother board and its method
JP2001094227A (en) Semiconductor chip mounting wiring board and semiconductor chip mounting method using the board
JP2961839B2 (en) Integrated circuit device
JPH0453102B2 (en)
US4778099A (en) Soldering method and apparatus

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION