US20060222760A1 - Process for producing a multifunctional dielectric layer on a substrate - Google Patents

Process for producing a multifunctional dielectric layer on a substrate Download PDF

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Publication number
US20060222760A1
US20060222760A1 US11/386,075 US38607506A US2006222760A1 US 20060222760 A1 US20060222760 A1 US 20060222760A1 US 38607506 A US38607506 A US 38607506A US 2006222760 A1 US2006222760 A1 US 2006222760A1
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layer
metal
interconnects
metal layer
substrate
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US11/386,075
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Johann Helneder
Markus Schwerd
Thomas Goebel
Andrea Mitchell
Heinrich Koerner
Martina Hommel
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Infineon Technologies AG
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Infineon Technologies AG
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SCHWERD, MARKUS, HOMMEL, MARTINA, GOEBEL, THOMAS, MITCHELL, ANDREA, HELNEDER, JOHANN, KOERNER, HEINRICH
Publication of US20060222760A1 publication Critical patent/US20060222760A1/en
Priority to US13/402,890 priority Critical patent/US9269669B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a process for producing a multifunctional dielectric layer on a substrate, in particular on uncovered metallic interconnect systems on a substrate.
  • substrates such as glass, GaAs, InP, circuit boards, printed wiring boards, etc.
  • substrates such as glass, GaAs, InP, circuit boards, printed wiring boards, etc.
  • diffusion barriers which are introduced at the side walls of the Cu interconnects, i.e., are introduced between the Cu interconnect and the surrounding dielectric (SiO 2 ) and consist, for example, of Ta(N).
  • the term Ta(N) used below is in the present context to be understood as meaning a compound with any desired stoichiometry comprising tantalum and any desired proportion of nitrogen. This ensures sufficient protection against diffusion.
  • the copper layer is uncovered at the top following the patterning of the copper interconnects by means of the standard CMP (chemical mechanical polishing) processing, this copper layer has to be passivated in order to prevent any oxidation. This is achieved by the uncovered interconnect surface (Cu layer) being provided with a suitable dielectric layer, e.g., SiN-PECVD layer.
  • a suitable dielectric layer e.g., SiN-PECVD layer.
  • the invention is now based on the object of providing a process that is simple to implement for the production of a multifunctional passivation layer for copper interconnects with improved electromigration and stress migration and improved bonding of the applied dielectric layer.
  • the object on which the invention is based is achieved, in a process of the type described in the introduction, by virtue of the fact that a further metal layer is deposited over the entire surface of the uncovered metal interconnects, and this further metal layer is then at least partially converted into a nonconducting metal oxide, i.e., into an insulator.
  • the metal interconnects have been embedded in an insulator on a substrate and have been provided with a diffusion barrier at the side walls.
  • the further metal layer was applied to the uncovered metal interconnect, which may consist of copper, after the chemical mechanical polishing (CMP).
  • the metal interconnects have a subtractive architecture, by virtue of the fact that a metal layer, which has been deposited over the entire surface of an insulator on the substrate, has been subsequently patterned, for example by RIE (reactive ion etching) or a lift-off process or the like, and the further metal layer has been deposited thereon.
  • the metal interconnects in this case consist of, for example, aluminum.
  • a third configuration of the invention is characterized in that the further metal layer is applied to metal interconnects that have been produced by “pattern plating” (i.e., electrolytic deposition of metal into a resist mask and subsequent removal of the resist mask) on an insulator on the substrate.
  • pattern plating i.e., electrolytic deposition of metal into a resist mask and subsequent removal of the resist mask
  • the further metal layer prefferably be converted into a nonconducting metal oxide by anodic, thermal or plasma-chemical oxidation in a back-end-compatible temperature range between 20-500° C.
  • the further metal layer is produced by a PVD process.
  • tantalum or tantalum nitride It is preferable to deposit tantalum or tantalum nitride.
  • a layer sequence of Ta(N)/Ta or Ta/Ta(N) is deposited.
  • Further materials and material combinations such as Ti, Al, Ti/Al, Zr, Hf, Nb, Ru, Rh, Ir, are possible.
  • a nonconducting metal oxide layer is produced, for example from tantalum pentoxide (Ta 2 O 5 ) when using Ta(N), the aim being to achieve a higher density and quality of the layer, good bonding and a clear, defined interface.
  • a resistor made from Ta(N) is formed and is contact-connected via the metal layer (e.g., Cu) below.
  • parts of the further metal layer prefferably be covered with an SiO 2 or Si 3 N 4 layer.
  • the tantalum pentoxide is formed partly as a MIM dielectric for integration of a MIM capacitor.
  • the Ta(N) resistor and the MIM capacitor can be integrated individually or simultaneously.
  • FIG. 1 shows a Cu level located on a substrate following the CMP, and a PVD-Ta(N) layer deposited thereon as further metal layer;
  • FIG. 2 shows the substrate from FIG. 1 following the deposition of a delimited SiO 2 layer on the Ta(N) layer;
  • FIG. 3 shows the substrate following the oxidation of the free Ta(N) layer to form tantalum pentoxide, with the layer of the Ta(N) layer that has been covered with SiO 2 remaining unchanged and subsequently forming a Ta(N) resistor;
  • FIG. 4 shows the substrate following the deposition of a further metal layer and patterning of the latter to form the upper electrode of a MIM capacitor together with a Ta(N) resistor, which has previously been produced;
  • FIG. 5 shows the substrate following the deposition of a further SiO 2 layer, which serves as an intermetal dielectric
  • FIG. 6 shows the substrate after processing of a further interconnect level and of through-contacts between the two levels.
  • FIG. 1 shows a substrate 1 , for example made from silicon, with a Cu metallization 3 , which has been embedded in an SiO 2 layer 2 (Damascene) and has been electrically connected to a lower-lying Cu level via through-contacts 4 made from Cu or another metal, such as tungsten.
  • the uncovered Cu metallization 3 following a CMP (chemical mechanical polishing) process, has been covered with a further metal layer 5 , e.g., a Ta(N) layer, by a PVD process.
  • a further metal layer 5 e.g., a Ta(N) layer
  • the bonding of a PVD-Ta(N) metal layer is generally better than when using layer systems that have been produced using CVD processes, since, for example, undesirable chemical processes at the interfaces are eliminated in the PVD process and the kinetic energy of the sputtered particles is higher when they first strike the surface on which they are to be deposited.
  • the boundary layer which is in this case produced, corresponds to the surrounding barrier and means that a comparable resistance to electromigration can be expected.
  • PVD Ta, PVD Ta(N), PVD Ta(N)/Ta, PVD Ta/Ta(N) or other materials and material combinations, such as Ti, Al, Ti/Al, Zr, Hf, Nb, Ru, Rh, Ir, is suitable for the further metal layer 5 .
  • this further metal layer 5 as a metallic covering layer, would short-circuit all the interconnects in this level, this layer is completely converted into a nonconducting layer of a metal oxide 7 , such as for example tantalum pentoxide. This can easily be achieved for example by thermal oxidation, which can take place in a back-end-compatible temperature range between 20 and 500° C.
  • a corresponding metal oxide i.e., a dielectric, such as for example Ta 2 O 5 , Al 2 O 3 , HfO 2 , Nb 2 O 5 , RuO 2 , Rh 2 O 3 , Ir 2 O 3 , etc. ( FIG. 2 ).
  • Ta(N) resistor 8 TFR resistor
  • the corresponding region of the further metal layer 5 is covered with SiO 2 prior to the oxidation ( FIG. 3 ).
  • MIM metal, insulator, metal
  • the Ta(N) which has been deposited over a large area, is not protected in the region where the MIM capacitor is to be formed, so that this region is oxidized to form Ta 2 O 5 and serves as dielectric for the MIM capacitor ( FIGS. 4, 5 ).
  • FIG. 6 shows a Cu level that has been passivated with tantalum pentoxide and includes a Ta(N) resistor 8 and a MIM capacitor 9 with Ta 2 O 5 as dielectric.
  • the invention makes it possible to produce a significantly improved barrier interface for metallic interconnect systems by means of a metallic coating, which is substantially completely oxidized in the following process, so as to form a nonconducting metal oxide.
  • the underlying idea of the invention is in converting an applied metal layer (further metal layer 5 ) into a dielectric (metal oxide 7 ) and using the dielectric layer produced in this way for various applications (passivation, stop layer, MIM dielectric, etc.).
  • Al 2 O 3 , HfO 2 , Nb 2 O 5 , etc. can also be used as MIM dielectric.

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Abstract

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

Description

  • This application is a continuation of co-pending International Application No. PCT/DE2004/001948, filed Sep. 3, 2004, which designated the United States and was not published in English, and which is based on German Application No. 103 44 389.4, filed Sep. 25, 2003, both of which applications are incorporated herein by reference.
    • TECHNICAL FIELD
  • The invention relates to a process for producing a multifunctional dielectric layer on a substrate, in particular on uncovered metallic interconnect systems on a substrate.
    • BACKGROUND
  • In the semiconductor components that have been disclosed to date, based on Si substrates, it is predominantly copper interconnects that are responsible for the electrical contact-connection of the individual functional layers or functional elements of a level and also between the levels. A particular problem that has emerged with the use of copper interconnects is that Cu atoms can diffuse into the surrounding dielectric and can, therefore, alter the electrical properties of the semiconductor component, even to the extent of rendering it unable to function.
  • Of course, other substrates, such as glass, GaAs, InP, circuit boards, printed wiring boards, etc., can also be considered as substrates in addition to Si substrates.
  • To prevent Cu atoms from diffusing into the dielectric, it is customary to use diffusion barriers, which are introduced at the side walls of the Cu interconnects, i.e., are introduced between the Cu interconnect and the surrounding dielectric (SiO2) and consist, for example, of Ta(N). The term Ta(N) used below is in the present context to be understood as meaning a compound with any desired stoichiometry comprising tantalum and any desired proportion of nitrogen. This ensures sufficient protection against diffusion.
  • However, since the copper layer is uncovered at the top following the patterning of the copper interconnects by means of the standard CMP (chemical mechanical polishing) processing, this copper layer has to be passivated in order to prevent any oxidation. This is achieved by the uncovered interconnect surface (Cu layer) being provided with a suitable dielectric layer, e.g., SiN-PECVD layer.
  • However, drawbacks of this interface are the weak point in terms of electromigration and stress migration, and the fact that the bonding is less than optimum. By way of example, selective deposition of cobalt on the uncovered metal surfaces by means of electroless electrolysis processes has been attempted with a view to achieving an improvement in this respect, but this has not to date led to the desired level of success.
    • SUMMARY OF THE INVENTION
  • The invention is now based on the object of providing a process that is simple to implement for the production of a multifunctional passivation layer for copper interconnects with improved electromigration and stress migration and improved bonding of the applied dielectric layer.
  • The object on which the invention is based is achieved, in a process of the type described in the introduction, by virtue of the fact that a further metal layer is deposited over the entire surface of the uncovered metal interconnects, and this further metal layer is then at least partially converted into a nonconducting metal oxide, i.e., into an insulator.
  • It is in this way possible to achieve significantly improved bonding of the dielectric layer to the metal interconnect, in particular to the Cu layer, and an improved electromigration and stress migration.
  • In a first configuration of the invention, the metal interconnects have been embedded in an insulator on a substrate and have been provided with a diffusion barrier at the side walls. The further metal layer was applied to the uncovered metal interconnect, which may consist of copper, after the chemical mechanical polishing (CMP).
  • In a second configuration of the invention, the metal interconnects have a subtractive architecture, by virtue of the fact that a metal layer, which has been deposited over the entire surface of an insulator on the substrate, has been subsequently patterned, for example by RIE (reactive ion etching) or a lift-off process or the like, and the further metal layer has been deposited thereon. The metal interconnects in this case consist of, for example, aluminum.
  • A third configuration of the invention is characterized in that the further metal layer is applied to metal interconnects that have been produced by “pattern plating” (i.e., electrolytic deposition of metal into a resist mask and subsequent removal of the resist mask) on an insulator on the substrate.
  • It is expedient for the further metal layer to be converted into a nonconducting metal oxide by anodic, thermal or plasma-chemical oxidation in a back-end-compatible temperature range between 20-500° C.
  • In one particular configuration of the invention, the further metal layer is produced by a PVD process.
  • It is preferable to deposit tantalum or tantalum nitride.
  • According to a further configuration of the invention, a layer sequence of Ta(N)/Ta or Ta/Ta(N) is deposited. Further materials and material combinations, such as Ti, Al, Ti/Al, Zr, Hf, Nb, Ru, Rh, Ir, are possible.
  • Finally, it is provided that during the subsequent oxidation a nonconducting metal oxide layer is produced, for example from tantalum pentoxide (Ta2O5) when using Ta(N), the aim being to achieve a higher density and quality of the layer, good bonding and a clear, defined interface.
  • In a variant of the invention, it is possible to remove regions of the further metal layer during the subsequent oxidation, so that at this location a resistor made from Ta(N) is formed and is contact-connected via the metal layer (e.g., Cu) below.
  • It is preferable for parts of the further metal layer to be covered with an SiO2 or Si3N4 layer.
  • Finally, in a further configuration of the invention, it is provided that the tantalum pentoxide is formed partly as a MIM dielectric for integration of a MIM capacitor.
  • The Ta(N) resistor and the MIM capacitor can be integrated individually or simultaneously.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is to be explained in more detail below on the basis of an exemplary embodiment using Ta(N). In the associated drawings:
  • FIG. 1 shows a Cu level located on a substrate following the CMP, and a PVD-Ta(N) layer deposited thereon as further metal layer;
  • FIG. 2 shows the substrate from FIG. 1 following the deposition of a delimited SiO2 layer on the Ta(N) layer;
  • FIG. 3 shows the substrate following the oxidation of the free Ta(N) layer to form tantalum pentoxide, with the layer of the Ta(N) layer that has been covered with SiO2 remaining unchanged and subsequently forming a Ta(N) resistor;
  • FIG. 4 shows the substrate following the deposition of a further metal layer and patterning of the latter to form the upper electrode of a MIM capacitor together with a Ta(N) resistor, which has previously been produced;
  • FIG. 5 shows the substrate following the deposition of a further SiO2 layer, which serves as an intermetal dielectric; and
  • FIG. 6 shows the substrate after processing of a further interconnect level and of through-contacts between the two levels.
  • The following list of reference symbols can be used in conjunction with the figures:
    • 1 Substrate
    • 6 SiN layer
    • 2 SiO2
    • 7 Metal oxide
    • 3 Cu metallization/metal interconnect
    • 8 Ta(N) resistor
    • 4 Through-contacts
    • 9 MIM capacitor
    • 5 Further metal layer
    DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • FIG. 1 shows a substrate 1, for example made from silicon, with a Cu metallization 3, which has been embedded in an SiO2 layer 2 (Damascene) and has been electrically connected to a lower-lying Cu level via through-contacts 4 made from Cu or another metal, such as tungsten. The uncovered Cu metallization 3, following a CMP (chemical mechanical polishing) process, has been covered with a further metal layer 5, e.g., a Ta(N) layer, by a PVD process. The bonding of a PVD-Ta(N) metal layer is generally better than when using layer systems that have been produced using CVD processes, since, for example, undesirable chemical processes at the interfaces are eliminated in the PVD process and the kinetic energy of the sputtered particles is higher when they first strike the surface on which they are to be deposited.
  • The boundary layer, which is in this case produced, corresponds to the surrounding barrier and means that a comparable resistance to electromigration can be expected. Beneath the Cu metallization 3 there is also an optional SiN layer 6 as a diffusion barrier and etching stop layer.
  • The deposition of, for example, PVD Ta, PVD Ta(N), PVD Ta(N)/Ta, PVD Ta/Ta(N) or other materials and material combinations, such as Ti, Al, Ti/Al, Zr, Hf, Nb, Ru, Rh, Ir, is suitable for the further metal layer 5. However, since this further metal layer 5, as a metallic covering layer, would short-circuit all the interconnects in this level, this layer is completely converted into a nonconducting layer of a metal oxide 7, such as for example tantalum pentoxide. This can easily be achieved for example by thermal oxidation, which can take place in a back-end-compatible temperature range between 20 and 500° C.
  • The above-mentioned materials are in this case converted into a corresponding metal oxide, i.e., a dielectric, such as for example Ta2O5, Al2O3, HfO2, Nb2O5, RuO2, Rh2O3, Ir2O3, etc. (FIG. 2).
  • However, if for example a Ta(N) resistor 8 (TFR resistor) is to be produced between two through-contacts 4, the corresponding region of the further metal layer 5 is covered with SiO2 prior to the oxidation (FIG. 3).
  • Another option is to use and integrate anodically/thermally oxidized Ta/N for MIM capacitors 9 (MIM=metal, insulator, metal). To achieve this, the Ta(N), which has been deposited over a large area, is not protected in the region where the MIM capacitor is to be formed, so that this region is oxidized to form Ta2O5 and serves as dielectric for the MIM capacitor (FIGS. 4, 5).
  • FIG. 6 shows a Cu level that has been passivated with tantalum pentoxide and includes a Ta(N) resistor 8 and a MIM capacitor 9 with Ta2O5 as dielectric.
  • The invention makes it possible to produce a significantly improved barrier interface for metallic interconnect systems by means of a metallic coating, which is substantially completely oxidized in the following process, so as to form a nonconducting metal oxide.
  • The underlying idea of the invention is in converting an applied metal layer (further metal layer 5) into a dielectric (metal oxide 7) and using the dielectric layer produced in this way for various applications (passivation, stop layer, MIM dielectric, etc.).
  • Al2O3, HfO2, Nb2O5, etc. can also be used as MIM dielectric.

Claims (18)

1. A process for producing a multifunctional dielectric layer on a substrate, the process comprising:
forming a plurality of metal interconnects that are embedded in an insulator and have been provided with a diffusion barrier at the side walls;
applying a further metal layer to uncovered portions of the metal interconnects as a metallic covering, the further metal layer comprising a metal, a metal nitride or a layer sequence of these materials; and
converting the further metal layer into a nonconducting metal oxide thereby forming a dielectric layer.
2. The process as claimed in claim 1, wherein the dielectric layer comprises a barrier layer on at least some interconnects.
3. The process as claimed in claim 1, wherein the dielectric layer comprises a capacitor dielectric for at least one of the interconnects.
4. The process as claimed in claim 1, further comprising covering parts of the further metal layer such that the covered parts form resistors.
5. The process as claimed in claim 1, wherein the metal interconnects comprise a material selected from the group consisting of copper, aluminum, tungsten, and gold.
6. The process as claimed in claim 1, wherein the further metal layer is deposited on the metal interconnects, which have a subtractive architecture, by virtue of a metal layer that has been deposited over the entire surface of an insulator on the substrate having subsequently been patterned.
7. The process as claimed in claim 6, wherein the metal interconnects comprise aluminum, copper, tungsten, silicides, or nitrides.
8. The process as claimed in claim 1, wherein the further metal layer is applied to metal interconnects that have been produced by pattern plating on an insulator on the substrate.
9. The process as claimed in claim 1, wherein converting the further metal layer into a nonconducting metal oxide is carried out by a thermal and/or anodic and/or plasma-chemical oxidation.
10. The process as claimed in claim 1, wherein the oxidation takes place in a temperature range between 20-500° C.
11. The process as claimed in claim 1, wherein the further metal layer is formed by a PVD process.
12. The process as claimed in claim 1, wherein the diffusion barrier is formed by depositing tantalum.
13. The process as claimed in claim 1, wherein the diffusion barrier is formed by depositing Ta(N).
14. The process as claimed in claim 1, wherein the diffusion barrier comprises Ti, Al, Zr, Hf. Nb, Ru, Rh, and/or Ir.
15. The process as claimed in claim 1, wherein regions of the further metal layer are removed during the converting.
16. The process as claimed in claim 1, wherein parts of the further metal layer are covered with an SiO2 or Si3N4 layer during the converting.
17. The process as claimed in claim 1, wherein a metal thin film resistor and a MIM capacitor are at least partially formed by the steps of forming a further metal layer and converting the further metal layer.
18. A process for producing a multifunctional dielectric layer on an uncovered metallic interconnect system on a substrate, the interconnect system including metal interconnects that have been embedded in an insulator on a substrate and have been provided with a diffusion barrier at side walls, the method comprising:
performing a chemical mechanical polishing process to expose an upper surface of the metal interconnects;
applying a further metal layer, formed from a metal, a metal nitride or a layer sequence of these materials, to the uncovered metal interconnects as a metallic covering layer following the chemical mechanical polishing process; and
converting portions of the further metal layer into a nonconducting metal oxide thereby forming a dielectric layer as a barrier layer on some interconnects and as a capacitor dielectric on other interconnects, wherein portions of the further metal layer, which have been covered, are not converted and form resistors.
US11/386,075 2003-09-25 2006-03-21 Process for producing a multifunctional dielectric layer on a substrate Abandoned US20060222760A1 (en)

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