US20060138084A1 - Selective reactive ion etching of wafers - Google Patents

Selective reactive ion etching of wafers Download PDF

Info

Publication number
US20060138084A1
US20060138084A1 US11/022,014 US2201404A US2006138084A1 US 20060138084 A1 US20060138084 A1 US 20060138084A1 US 2201404 A US2201404 A US 2201404A US 2006138084 A1 US2006138084 A1 US 2006138084A1
Authority
US
United States
Prior art keywords
wafer
strips
reactive ion
base plate
ion etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/022,014
Inventor
Sim Ye
Tan Tong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Systems on Silicon Manufacturing Co Pte Ltd
Original Assignee
Systems on Silicon Manufacturing Co Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Systems on Silicon Manufacturing Co Pte Ltd filed Critical Systems on Silicon Manufacturing Co Pte Ltd
Priority to US11/022,014 priority Critical patent/US20060138084A1/en
Assigned to SYSTEMS ON SILICON MANUFACTURING CO., PTE. LTD. reassignment SYSTEMS ON SILICON MANUFACTURING CO., PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOK TONG, TAN, KWANG YE, SIM
Publication of US20060138084A1 publication Critical patent/US20060138084A1/en
Priority to US11/642,049 priority patent/US20070095786A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching

Definitions

  • the present invention relates to selective reactive ion etching of wafers and in particular to selective reactive ion etching of wafers where the etching site can be any site on the wafer.
  • Reactive ion etchers can be used for dry isotropic etching of dielectrics (for example, polyimides, oxides, SiO 2 , and nitrides Si 3 N 4 ). Reactive ion etchers can also be used for employing reactive ion etching for the de-processing of silicon chips.
  • a graphite shield with an opening the size of the die is used to cover the wafer as shown in FIG. 1 .
  • the target wafer 1 is sandwiched between a chuck platen 2 and a graphite shield 3 .
  • the graphite shield 3 includes an opening through which etching will take place. Plasma is then formed in the reactive ion etcher and isotropic reactive ion etching begins. Only the portion of the wafer directly under the opening of the graphite shield will be etched and the graphite shield prevents etching of the rest of the wafer.
  • a device for assisting in the selective reactive ion etching of wafers comprising a base plate including an opening for housing a wafer and a plurality of strips that can be arranged over the base plate to select a site of a wafer housed in the base plate for etching.
  • the strips and base plate are formed from graphite.
  • the strips and base plate may be formed from aluminium.
  • the strips are all the same length.
  • the strips can have different widths. If the strips have different widths, preferably the widths are multiples of a unit dimension.
  • the opening in the base plate is circular.
  • the site selected for reactive ion etching is opened to reactive ion etching by arranging the strips in two dimensions.
  • a method of selectively reactive ion etching a portion of a wafer including the step of placing the wafer in a base plate, identifying the portion of the wafer to be etched, arranging a plurality of strips over the wafer and base plate to cover all portions of the wafer that are not to be etched and leave exposed the portion of the wafer to be etched and performing a reactive ion etch on the wafer.
  • FIG. 1 is a view of a reactive ion etching process using a currently used graphite shield
  • FIG. 2 is a view of one embodiment of the invention showing the layering of graphite strips over a graphite base plate and wafer, and
  • FIG. 3 is a view of a second embodiment of the invention showing the layering of graphite strips over a graphite base plate and wafer.
  • the strips are referred to as graphite strips. This is by way of example only and is not intended to limit the invention to graphite strips.
  • the strips may be any suitable material as described below. In some embodiments the strips may be aluminium.
  • FIG. 2 there is shown therein an assembly of a wafer 11 , graphite base plate 12 , and plurality of graphite strips 13 . For clarity some portions of the strips are shaded and others are not to show the wafer and graphite base plate beneath the strips.
  • the graphite base plate provides a base on which the wafer sits.
  • the graphite base plate includes a central aperture in which the wafer is positioned.
  • This aperture can a circular opening be of any suitable diameter.
  • the opening can be 6 inches in diameter, 8 inches in diameter, or 12 inches in diameter.
  • the graphite base plate may include a base portion onto which the wafer is set and side portions that extend from the base portion.
  • the surrounds of the graphite base plate around the central aperture or sides of the base plate extend to at least the height of the wafer and preferably beyond the height of the wafer to provide surfaces on which the graphite strips rest.
  • the graphite base plate is formed from graphite and is about half an inch think between the wafer and one quarter of an inch thick around the central aperture.
  • the base plate and strips are formed from graphite. In alternative embodiments the base plate and strips may be formed from aluminium.
  • the base plate must be formed from a highly conductive material so as not to interfere with the reactive ion etching.
  • the base plate material must not be reactive to the gas species used in the reactive ion etching. These gases are mainly CHF 3 , C 2 F 6 , CF 4 , and O 2 .
  • the temperature within the reactive ion etch chamber can be as high as 100° C. so the melting point of the base plate material must be a few hundred degrees Celsius.
  • One material that meets all of these requirements is graphite.
  • Another suitable base plate material is aluminium. Either of these materials may be used for the base plate and strips.
  • Graphite strips 13 are positioned on the graphite base plate after a wafer is placed on the graphite base plate.
  • graphite strips 13 are all the same length.
  • the graphite strips are laid out parallel to the x axis and y axis as shown in FIG. 2 .
  • the graphite strips may have different widths.
  • the widths of the graphite strips are multiples of a unit dimension.
  • the unit dimension may be the typical width of a die within the wafer.
  • strips 13 a and 13 b are twice the width of the remaining graphite strips. In other embodiments some graphite strips may be 3 or more times as wide as the least wide graphite strip.
  • the strips form a straightened Z shape with parallel upper and lower members and a connecting member between the upper and lower members.
  • the connecting member is an overlap between the upper and lower members.
  • the connecting member may be a separate member and is preferably at right angles to the upper and lower members. This arrangement of the strips allows the strips to overlap when arranged around a target site. The overlapping arrangement assists in protecting the wafer under the strips from the etching process.
  • the wafer In use when a wafer is to be selectively etched the wafer is first placed on the graphite base plate. If the graphite base plate includes a circular aperture the wafer should be placed in the aperture. After this the portion of the wafer to be etched is identified. If the wafer if circular and placed in a circular aperture in the graphite base plate preferably the wafer is aligned within the base plate so that the sides of the portion of the wafer to be etched are parallel to the sides of the base plate (as shown in FIG. 2 ). The graphite strips are then placed over the wafer and base plate to cover all areas of the wafer that are not to be etched and leave exposed the portion of the wafer to be etched. In FIG. 2 this is shown by the different shading on the strips.
  • the shaded areas show the intersection every second x-axis strip with every second y-axis strip.
  • the clear areas are covered by strips by have been left clear to show the wafer and graphite base plate below the graphite strips. Only portion 14 is left exposed. A reactive ion etch is then performed. This etch will only affect the exposed portion of the wafer.
  • the graphite strips are preferably laid in one direction and then the other.
  • the wafer strips may be laid parallel to the x-axis and then a second layer may be laid parallel to the y-axis.
  • the axes chosen for laying the graphite strips may be different.
  • the lengths of the graphite strips may be different. It should also be noted that the axes along which the strips are laid are orthogonal in the preferred embodiment but need not be so long as the wafer is covered leaving only the selected portion to be etched.
  • FIG. 3 shows another embodiment of the invention.
  • the width of the strips parallel to the y-axis range from unit dimension width, strip 17 a , to three times the unit dimension width, strips 17 e, f , and h .
  • the width of the strips parallel to the x-axis range from twice the unit dimension width, 16 a , to seven times the unit dimension width, 16 e .
  • the strips along one axis are laid first omitting a strip that will cover the target site. Then the strips along the other axis are laid, again omitting a strip that will cover the target site. This means that all areas of the wafer are covered by two strips except the areas in line with the target site on the x and y axes and the target site. It should be noted that in this embodiment the size of the target site is not the same as the minimum width of the graphite strips.
  • the advantages of the present invention include that it provides the flexibility to perform a reactive ion etch on any selected site or location on the target wafer.
  • the present invention also allows target sites of differing sizes, in fact the target site can be any size required.
  • the invention also protects the unexposed areas of the wafer from the reactive ion etch to allow further testing. Another advantage is that the invention is simple to implement and is highly effective.
  • etch species or compounds can be re-deposited back onto the surface of the wafer.
  • Use of the strips of the invention prevents re-deposition of etched species or compounds onto the non-selected areas.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention comprises a device for assisting in the selective reactive ion etching of wafers comprising, a graphite base plate including an opening for housing a wafer, and a plurality of graphite strips that can be arranged over the graphite base plate to select a site of a wafer housed in the base plate for etching.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to selective reactive ion etching of wafers and in particular to selective reactive ion etching of wafers where the etching site can be any site on the wafer.
  • 2. Description of the Prior Art
  • Reactive ion etchers can be used for dry isotropic etching of dielectrics (for example, polyimides, oxides, SiO2, and nitrides Si3N4). Reactive ion etchers can also be used for employing reactive ion etching for the de-processing of silicon chips.
  • If selective etching of a particular site on a wafer is required there are two approaches that are currently used. In the first approach the wafer is diced by wafer cleaving or wafer sawing. The die to be etched is then extracted from the diced wafer and etched. This approach has the disadvantage of destroying the wafer and all the good dies on the wafer near the die to be etched.
  • In the second approach a graphite shield with an opening the size of the die is used to cover the wafer as shown in FIG. 1. As can be seen in this Figure the target wafer 1 is sandwiched between a chuck platen 2 and a graphite shield 3. The graphite shield 3 includes an opening through which etching will take place. Plasma is then formed in the reactive ion etcher and isotropic reactive ion etching begins. Only the portion of the wafer directly under the opening of the graphite shield will be etched and the graphite shield prevents etching of the rest of the wafer.
  • There are problems with the second approach including that only the centre die can be etched using the graphite shield. The shape and size of the hole in the graphite shield determines the size and shape of wafer that will be etched using the shield. If another shape and size wafer is to be etched another shield is needed. Further if the wafer to be etched is not in the centre of the die another shield will be needed. These expensive and heavy graphite shields require fabrication with the vendor. Using this second approach a number of different shields may be required which is costly and inefficient.
  • BRIEF SUMMARY OF THE INVENTION
  • Accordingly in the present invention there is provided a device for assisting in the selective reactive ion etching of wafers comprising a base plate including an opening for housing a wafer and a plurality of strips that can be arranged over the base plate to select a site of a wafer housed in the base plate for etching.
  • Preferably the strips and base plate are formed from graphite. Alternatively the strips and base plate may be formed from aluminium.
  • Preferably the strips are all the same length.
  • Preferably the strips can have different widths. If the strips have different widths, preferably the widths are multiples of a unit dimension.
  • Preferably the opening in the base plate is circular.
  • Preferably the site selected for reactive ion etching is opened to reactive ion etching by arranging the strips in two dimensions.
  • In another embodiment there is provided a method of selectively reactive ion etching a portion of a wafer including the step of placing the wafer in a base plate, identifying the portion of the wafer to be etched, arranging a plurality of strips over the wafer and base plate to cover all portions of the wafer that are not to be etched and leave exposed the portion of the wafer to be etched and performing a reactive ion etch on the wafer.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The invention will be further described by way of example only and without intending to be limiting with reference to the following drawings, wherein:
  • FIG. 1 is a view of a reactive ion etching process using a currently used graphite shield;
  • FIG. 2 is a view of one embodiment of the invention showing the layering of graphite strips over a graphite base plate and wafer, and
  • FIG. 3 is a view of a second embodiment of the invention showing the layering of graphite strips over a graphite base plate and wafer.
  • DETAILED DESCRIPTION OF THE INVENTION
  • It should be noted the throughout the detailed description the strips are referred to as graphite strips. This is by way of example only and is not intended to limit the invention to graphite strips. The strips may be any suitable material as described below. In some embodiments the strips may be aluminium.
  • Referring now to FIG. 2 there is shown therein an assembly of a wafer 11, graphite base plate 12, and plurality of graphite strips 13. For clarity some portions of the strips are shaded and others are not to show the wafer and graphite base plate beneath the strips.
  • The graphite base plate provides a base on which the wafer sits. In preferred embodiment the graphite base plate includes a central aperture in which the wafer is positioned. This aperture can a circular opening be of any suitable diameter. For example the opening can be 6 inches in diameter, 8 inches in diameter, or 12 inches in diameter. In alternative embodiments the graphite base plate may include a base portion onto which the wafer is set and side portions that extend from the base portion.
  • The surrounds of the graphite base plate around the central aperture or sides of the base plate extend to at least the height of the wafer and preferably beyond the height of the wafer to provide surfaces on which the graphite strips rest.
  • In preferred embodiments the graphite base plate is formed from graphite and is about half an inch think between the wafer and one quarter of an inch thick around the central aperture.
  • In preferred embodiments the base plate and strips are formed from graphite. In alternative embodiments the base plate and strips may be formed from aluminium. The base plate must be formed from a highly conductive material so as not to interfere with the reactive ion etching. The base plate material must not be reactive to the gas species used in the reactive ion etching. These gases are mainly CHF3, C2F6, CF4, and O2. The temperature within the reactive ion etch chamber can be as high as 100° C. so the melting point of the base plate material must be a few hundred degrees Celsius. One material that meets all of these requirements is graphite. Another suitable base plate material is aluminium. Either of these materials may be used for the base plate and strips.
  • Graphite strips 13 are positioned on the graphite base plate after a wafer is placed on the graphite base plate. In the preferred embodiment graphite strips 13 are all the same length. In this embodiment the graphite strips are laid out parallel to the x axis and y axis as shown in FIG. 2. The graphite strips may have different widths. In this embodiment it is preferred that the widths of the graphite strips are multiples of a unit dimension. For example the unit dimension may be the typical width of a die within the wafer. In FIG. 2 strips 13 a and 13 b are twice the width of the remaining graphite strips. In other embodiments some graphite strips may be 3 or more times as wide as the least wide graphite strip.
  • In one embodiment in a cross-sectional or side view the strips form a straightened Z shape with parallel upper and lower members and a connecting member between the upper and lower members. In preferred embodiments the connecting member is an overlap between the upper and lower members. In alternative embodiments the connecting member may be a separate member and is preferably at right angles to the upper and lower members. This arrangement of the strips allows the strips to overlap when arranged around a target site. The overlapping arrangement assists in protecting the wafer under the strips from the etching process.
  • In use when a wafer is to be selectively etched the wafer is first placed on the graphite base plate. If the graphite base plate includes a circular aperture the wafer should be placed in the aperture. After this the portion of the wafer to be etched is identified. If the wafer if circular and placed in a circular aperture in the graphite base plate preferably the wafer is aligned within the base plate so that the sides of the portion of the wafer to be etched are parallel to the sides of the base plate (as shown in FIG. 2). The graphite strips are then placed over the wafer and base plate to cover all areas of the wafer that are not to be etched and leave exposed the portion of the wafer to be etched. In FIG. 2 this is shown by the different shading on the strips. The shaded areas show the intersection every second x-axis strip with every second y-axis strip. The clear areas are covered by strips by have been left clear to show the wafer and graphite base plate below the graphite strips. Only portion 14 is left exposed. A reactive ion etch is then performed. This etch will only affect the exposed portion of the wafer.
  • The graphite strips are preferably laid in one direction and then the other. For example, the wafer strips may be laid parallel to the x-axis and then a second layer may be laid parallel to the y-axis.
  • In alternative embodiments the axes chosen for laying the graphite strips may be different. In these alternative embodiments the lengths of the graphite strips may be different. It should also be noted that the axes along which the strips are laid are orthogonal in the preferred embodiment but need not be so long as the wafer is covered leaving only the selected portion to be etched.
  • FIG. 3 shows another embodiment of the invention. In this embodiment there are five strips 16 a-16 e that run parallel to the x-axis and eight strips 17 a-17 h that run parallel to the y-axis to expose target site 15.
  • As can be seen in FIG. 3, the width of the strips parallel to the y-axis range from unit dimension width, strip 17 a, to three times the unit dimension width, strips 17 e, f, and h. The width of the strips parallel to the x-axis range from twice the unit dimension width, 16 a, to seven times the unit dimension width, 16 e. The strips along one axis are laid first omitting a strip that will cover the target site. Then the strips along the other axis are laid, again omitting a strip that will cover the target site. This means that all areas of the wafer are covered by two strips except the areas in line with the target site on the x and y axes and the target site. It should be noted that in this embodiment the size of the target site is not the same as the minimum width of the graphite strips.
  • The advantages of the present invention include that it provides the flexibility to perform a reactive ion etch on any selected site or location on the target wafer. The present invention also allows target sites of differing sizes, in fact the target site can be any size required. The invention also protects the unexposed areas of the wafer from the reactive ion etch to allow further testing. Another advantage is that the invention is simple to implement and is highly effective.
  • During reactive ion etching chemical etching and physical ion sputtering occurs. Some of the etch species or compounds can be re-deposited back onto the surface of the wafer. Use of the strips of the invention prevents re-deposition of etched species or compounds onto the non-selected areas.
  • The foregoing describes the invention including preferred forms thereof. Alterations and modifications as will be obvious to those skilled in the art are intended to be incorporated in the scope hereof as defined by the accompanying claims.

Claims (12)

1. A device for assisting in the selective reactive ion etching of wafers comprising,
a base plate including an opening for housing a wafer, and
a plurality of strips that can be arranged over the graphite base plate to select a site of a wafer housed in the base plate for etching.
2. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the strips are all the same length.
3. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the strips can have different widths.
4. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 3 wherein the widths of the strips are multiples of a unit dimension.
5. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the opening in the base plate is circular.
6. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the site selected for reactive ion etching is opened to reactive ion etching by arranging the strips in two dimensions.
7. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the base plate is formed from graphite.
8. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the base plate is formed from aluminium.
9. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the strips are formed from graphite.
10. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the strips are formed from aluminium.
11. A device for assisting in the selective reactive ion etching of wafers as claimed in claim 1 wherein the strips overlap.
12. A method of selectively reactive ion etching a portion of a wafer comprising the steps of,
placing the wafer in a base plate,
identifying the portion of the wafer to be etched,
arranging a plurality of strips over the wafer and base plate to cover all portions of the wafer that are not to be etched and leave exposed the portion of the wafer to be etched, and
performing a reactive ion etch on the wafer.
US11/022,014 2004-12-23 2004-12-23 Selective reactive ion etching of wafers Abandoned US20060138084A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/022,014 US20060138084A1 (en) 2004-12-23 2004-12-23 Selective reactive ion etching of wafers
US11/642,049 US20070095786A1 (en) 2004-12-23 2006-12-19 Selective reactive ion etching of wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/022,014 US20060138084A1 (en) 2004-12-23 2004-12-23 Selective reactive ion etching of wafers

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/642,049 Division US20070095786A1 (en) 2004-12-23 2006-12-19 Selective reactive ion etching of wafers

Publications (1)

Publication Number Publication Date
US20060138084A1 true US20060138084A1 (en) 2006-06-29

Family

ID=36610175

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/022,014 Abandoned US20060138084A1 (en) 2004-12-23 2004-12-23 Selective reactive ion etching of wafers
US11/642,049 Abandoned US20070095786A1 (en) 2004-12-23 2006-12-19 Selective reactive ion etching of wafers

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/642,049 Abandoned US20070095786A1 (en) 2004-12-23 2006-12-19 Selective reactive ion etching of wafers

Country Status (1)

Country Link
US (2) US20060138084A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3484165A (en) * 1966-03-09 1969-12-16 Howson Ltd W H Means for and method of applying flash and main exposures
US4157221A (en) * 1978-03-08 1979-06-05 Guardian Industries Corporation Strip printer adjustable mask and marker
US5855687A (en) * 1990-12-05 1999-01-05 Applied Materials, Inc. Substrate support shield in wafer processing reactors
US6093445A (en) * 1998-08-12 2000-07-25 Shimane University Microscopic element manufacturing method and equipment for carrying out the same
US20040079725A1 (en) * 2002-08-28 2004-04-29 Kyocera Corporation Dry etching apparatus, dry etching method, and plate and tray used therein
USRE38937E1 (en) * 1997-02-07 2006-01-24 Sumitomo Mitsubishi Silicon Corporation Susceptor for vapor-phase growth apparatus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3484165A (en) * 1966-03-09 1969-12-16 Howson Ltd W H Means for and method of applying flash and main exposures
US4157221A (en) * 1978-03-08 1979-06-05 Guardian Industries Corporation Strip printer adjustable mask and marker
US5855687A (en) * 1990-12-05 1999-01-05 Applied Materials, Inc. Substrate support shield in wafer processing reactors
USRE38937E1 (en) * 1997-02-07 2006-01-24 Sumitomo Mitsubishi Silicon Corporation Susceptor for vapor-phase growth apparatus
US6093445A (en) * 1998-08-12 2000-07-25 Shimane University Microscopic element manufacturing method and equipment for carrying out the same
US20040079725A1 (en) * 2002-08-28 2004-04-29 Kyocera Corporation Dry etching apparatus, dry etching method, and plate and tray used therein

Also Published As

Publication number Publication date
US20070095786A1 (en) 2007-05-03

Similar Documents

Publication Publication Date Title
KR100628014B1 (en) Gas distribution plate electrode for a plasma reactor
KR20010029813A (en) Self-Supported Ultra Thin Silicon Wafer Process
US6642127B2 (en) Method for dicing a semiconductor wafer
US20080277659A1 (en) Test structure for semiconductor chip
US7786014B2 (en) Electronic device and method for making the same
US6521910B1 (en) Structure of a test key for monitoring salicide residue
US6709547B1 (en) Moveable barrier for multiple etch processes
EP0395017A2 (en) Plasma etching method
CN102460661A (en) Finfet structures with stress-inducing source/drain-forming spacers and methods for fabricating same
US7989803B2 (en) Manufacturing method for semiconductor chips and semiconductor wafer
US20060096704A1 (en) Dry etching apparatus
US20080227234A1 (en) Method of manufacturing a semiconductor device
US7112288B2 (en) Methods for inspection sample preparation
KR100924611B1 (en) Method of forming a micro pattern in a semiconductor device
US7015567B2 (en) Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure
US20060138084A1 (en) Selective reactive ion etching of wafers
US11631813B2 (en) Deposition mask and methods of manufacturing and using a deposition mask
US5910679A (en) Method for fabricating semiconductor device having a crack resistant contact hole and a semiconductor device having a crack resistant hole
US20070015317A1 (en) Method of forming metal line and contact plug of flash memory device
US6143579A (en) Efficient method for monitoring gate oxide damage related to plasma etch chamber processing history
KR960005099B1 (en) Inter layer defect analysis method of multipoly structure
US20090212794A1 (en) Test key for semiconductor structure
JPS6226839A (en) Semiconductor substrate
CN109659296B (en) Test key for monitoring etching depth of O L ED panel and O L ED large panel
KR100468699B1 (en) Overlay Keys for Overlap Measurement in Semiconductor Manufacturing Processes

Legal Events

Date Code Title Description
AS Assignment

Owner name: SYSTEMS ON SILICON MANUFACTURING CO., PTE. LTD., S

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KWANG YE, SIM;KOK TONG, TAN;REEL/FRAME:016129/0900

Effective date: 20041215

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION