US20060075086A1 - Method and system between subnetwork operation and full network operation - Google Patents
Method and system between subnetwork operation and full network operation Download PDFInfo
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- US20060075086A1 US20060075086A1 US10/517,474 US51747405A US2006075086A1 US 20060075086 A1 US20060075086 A1 US 20060075086A1 US 51747405 A US51747405 A US 51747405A US 2006075086 A1 US2006075086 A1 US 2006075086A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40039—Details regarding the setting of the power status of a node according to activity on the bus
Definitions
- the present invention relates to a method for changing over a serially networked system, in particular a serial databus system, from subnetwork operation, in which at least one node and/or at least one user of the system is in a state of reduced current consumption and is not addressed and/or not activated by the signal level of the data traffic on the system, to full network operation, in which all the nodes and/or all the users of the system are addressed and/or activated by the signal level of the data traffic on the system.
- the present invention also relates to a serially networked system, which is intended to be changed over from subnetwork operation, in which at least one node and/or at least one user of the system is in a state of reduced current consumption and cannot be addressed and/or activated by the signal level of the data traffic on the system, to full network operation, in which all the nodes and/or all the users of the system may be addressed and/or activated by the signal level of the data traffic on the system.
- a disadvantage of this known principle is that the second level scheme used for waking is associated with markedly increased bus system noise emission; in particular, cyclic wake-up events lead for this reason to undesirable disturbances in the motor vehicle, wherein E[lectro]M[agnetic]C[ompatibility] emissions also play a part; moreover, a second driver stage is necessary, to generate the other level scheme.
- This waking mechanism may be implemented both in system chips and in other networking products, such as for instance in simple transceiver modules.
- the rest phase or critical period should preferably be so set that the normal time gaps between the subnetwork operation messages are insufficient for detecting the end of subnetwork operation.
- the nodes or users in subnetwork operation appropriately send cyclic messages, so as to ensure that the “selectively sleeping” nodes or users are not woken (such cyclic messages are conventionally a constituent of a network management system, as in standard use in automobile technology, and thus require no separate effort).
- This signal level pattern which advantageously does not otherwise occur in the data traffic, may appropriately be detected by at least one node in the reduced current consumption state and/or by at least one user in the reduced current consumption state.
- the present invention further relates to a transceiver unit, in particular for carrying out a method of the type described above and/or in particular associated with at least one system of the type described above; the transceiver unit is connected to at least one serial databus, in particular to at least one C[ontroller]A[rea]N[etwork] bus, and is in communication with at least one microcontroller unit which is provided to carry out at least one application.
- At least one control logic is associated with the transceiver unit and/or at least one control logic is implemented in the transceiver unit.
- the present invention further relates to a voltage regulator which is connected to at least one battery unit, and which is in communication with at least one transceiver unit, in particular of the type described above, which voltage regulator is intended to supply a voltage to at least one microcontroller unit, provided to execute at least one application, if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected by the transceiver unit in at least one incoming message associated with at least one application and occurring on at least one serial databus, in particular on at least one C[ontroller]A[rea]N[etwork] bus.
- the present invention further relates to a chip unit, in particular a system chip unit, for addressing and/or activating at least one microcontroller unit which is provided to carry out at least one application and which is associated with at least one serial databus, in particular at least one C[ontroller]A[rea]N[etwork]bus; which chip unit comprises at least one transceiver unit of the type described above, and at least one voltage regulator of the type described above.
- a chip unit in particular a system chip unit, for addressing and/or activating at least one microcontroller unit which is provided to carry out at least one application and which is associated with at least one serial databus, in particular at least one C[ontroller]A[rea]N[etwork]bus; which chip unit comprises at least one transceiver unit of the type described above, and at least one voltage regulator of the type described above.
- the present invention further relates to a microcontroller unit provided to carry out at least one application and associated with at least one serial data bus, in particular at least one C[ontroller]A[rea]N[etwork] bus, which microcontroller unit is to be supplied with a voltage only if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected in at least one incoming message associated with at least one application and occurring on the databus, by at least one transceiver unit, in particular according to the type described above.
- the microcontroller unit can be activated by the transceiver unit
- the present invention finally relates to the use of
- FIG. 1 is a schematic block diagram of an example of embodiment of a system according to the present invention based on the method of the present invention
- FIG. 2 is a schematic block diagram of a detailed section of the system shown in FIG. 1 .
- FIG. 3 shows, in a schematic time sequence, an example of embodiment of a changeover, according to the method, of the system of FIG. 1 and 2 from subnetwork operation to full network operation;
- FIG. 4 is a schematic representation of an example of embodiment of a defined signal level pattern not otherwise occurring in the ongoing data traffic.
- FIG. 1 shows an exemplary implementation of a serially networked CAN system 100 provided for C[ontroller]A[rea]N[etwork] applications in automobile electronics, namely in motor vehicle electronics.
- This serially networked system 100 comprises five users 30 , 32 , 34 , 36 , 38 , which are connected to a serial C[ontroller]A[rea]N[etwork] databus 10 via respective associated nodes 20 , 22 , 24 , 26 , 28 and which take the form, for example, of a system chip unit (optionally including transceiver unit) and/or of a microcontroller unit, for instance an application controller unit or a protocol controller unit.
- FIG. 2 the build-up, the function and the structure of the users 30 , 32 , 34 , 36 , 38 provided to execute applications are explained in an exemplary manner by means of a detailed description of the first user 30 , which is connected to the node 20 of the CAN databus 10 and which can be addressed and/or activated via this CAN databus 10 .
- the operating principle is as follows:
- the transceiver unit 84 equipped with a control logic and connected to the data bus 10 and/or by a system chip unit 80 which accommodates the transceiver unit 84 and which is permanently supplied from a battery unit 70 , then the transceiver unit 84 switches on a voltage regulator 86 which is connected to the battery unit 70 via a supply line 76 and which is in communication 886 with the transceiver unit 84 .
- connection line 984 in that the voltage regulator 86 supplies a voltage to the application user which takes the form of a microcontroller unit 90 with integrated CAN control unit; as shown in FIG. 2 , between the voltage regulator 86 and the (application) microcontroller unit 90 there is also a reset line 986 (“reset”).
- the pattern detector (or transceiver 84 ) does not detect the presence of any message on the CAN data bus 10 , then the voltage regulator 86 is not switched on.
- the system 100 may be configured and controlled via a mode control interface 982 between the transceiver unit 84 (or the system chip unit 80 ) and the microcontroller unit 90 .
- two users 32 , 38 are in a low current consumption state, in which these two users 32 , 38 are not addressed and thus also not activated by the signal level 40 , 42 , 44 (cf. FIG. 3 ) of the data traffic on the system 100 .
- the remaining three active users 30 , 34 , 36 define subnetwork operation T, i.e. the three users 30 , 34 , 36 communicate with one another (this is symbolized by the double-headed arrow between the active user 30 and the active user 34 and by the double-headed arrow between the active user 34 and the active user 36 ) and are addressed by the signal level 40 , 42 , 44 of the data traffic on the system 100 .
- this critical period ⁇ t k is in turn set to be greater than the interval ⁇ t d between the individual messages and data packets of the data traffic on the system 100 , such that the normal time gaps ⁇ t d between the messages and data packets of subnetwork operation T are insufficient for detecting the end of subnetwork operation T.
- the nodes 20 , 24 , 26 or the users 30 , 34 , 36 send messages and data packets during subnetwork operation T at cyclic intervals which are smaller than the critical value ⁇ t k , so as to ensure that the “selectively sleeping” nodes 22 , 28 or the “selectively sleeping” users 32 , 38 are not woken during subnetwork operation T.
- a special waking data packet (c.f. FIG. 3 ) may be used according to a further development essential to the invention.
- This “global waking message” or “global waking data packet” uses the same nominal level scheme but is distinguished by a special bit sequence, which does not arise in normal communication operation and which may be freely defined in the data field of any desired message or any desired data packet.
- the nodes 22 , 28 in the low current consumption state and/or the users 32 , 38 in the low current consumption state of the serially networked system 100 may examine the ongoing data traffic on the CAN system bus 10 for a continuous symmetrical data pattern and interpret the detection of this data pattern as a waking event.
- a symmetrical data pattern 62 or 64 which is linked to any identifier 60 (address/header), of which there is at least one, and which may be simply detected by simple hardware, specifically without the need for a protocol controller.
- a decisive advantage consists in the fact that the protocol used does not have to be tracked in bit-accurate manner and that, moreover, it is not essential to use a special message identifier (address/header), but rather any desired message identifier 60 (address/header) may be used; all that is needed is detection of a symmetrical pattern which may be repeated appropriately frequently in the data field of the message or of the data packet.
- the data patterns used may be of any desired type and are distinguished merely by the frequent repetition of identical bit phases. To filter such data patterns, it is possible to use both per se known analog circuits and per se known digital circuits.
- the method illustrated in FIG. 3 allows the implementation of subnetwork operation T within a serial bus system 10 .
- a certain time period ⁇ t> ⁇ t k without communication on the databus 10 is used to allow waking of these “sleeping” nodes 22 , 28 or “sleeping” users 32 , 38 by a normal message or data packet; the criterion for addressing all the nodes 20 , 22 , 24 , 26 , 28 or all the users 30 , 32 , 34 , 36 , 38 on the databus 10 is thus that a bus system rest phase ⁇ t was present beforehand which is greater than the settable critical period ⁇ t k .
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Abstract
In order further to develop a method for changing over a serially networked system (100), in particular a serial databus system, from subnetwork operation (T), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and is not addressed and/or not activated by the signal level (40, 42, 44) of the data traffic on the system (100), to full network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) are addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), together with a corresponding system (100) in such a way that the nodes (22, 28) and/or the users (32, 38) in the network, i.e. on the databus (10), may be simply yet effectively woken, it is proposed that the system (100) be changed over from subnetwork operation (T) to full network operation (G) if a signal rest level (50) and/or no change in the signal level is noted on the system (100) for a period (Δt) which is greater than a critical period (Δtk) of definable or settable length.
Description
- The present invention relates to a method for changing over a serially networked system, in particular a serial databus system, from subnetwork operation, in which at least one node and/or at least one user of the system is in a state of reduced current consumption and is not addressed and/or not activated by the signal level of the data traffic on the system, to full network operation, in which all the nodes and/or all the users of the system are addressed and/or activated by the signal level of the data traffic on the system.
- The present invention also relates to a serially networked system, which is intended to be changed over from subnetwork operation, in which at least one node and/or at least one user of the system is in a state of reduced current consumption and cannot be addressed and/or activated by the signal level of the data traffic on the system, to full network operation, in which all the nodes and/or all the users of the system may be addressed and/or activated by the signal level of the data traffic on the system.
- With increasingly complex serial networking in particular of automobiles, the energy requirement of the electronic components used in serial networking is also constantly on the increase. Added to this is the fact that ever more comfort functions are also active when the motor vehicle is switched off, having then to be operated directly from the vehicle battery.
- Due to the serial networking of a large number of functions by means, for example, of the C[ontroller]A[rea]N[etwork] bus, the entire bus system is always activated even when only a few vehicle functions are in operation, since each bus user is “woken” or “kept awake” by data transmission involving a few users; this leads to undesirably high system current consumption, which, in view of the fact that only a few vehicle functions are in operation, is also wholly unnecessary.
- According to the prior art, users in a serially networked system are transferred into a low current consumption state in which the normal bus traffic at normal bus levels does not cause waking. These users are thus in a “selective sleep state”, while the remaining users maintain “subnetwork operation”.
- In order to be able to wake the sleeping nodes or the sleeping users, in the prior art a second level scheme with a markedly different potential is used on the databus, with which the users may be “globally woken”; only when this second level scheme is used for transmission do all the nodes globally wake up. This known principle is used for example in a “Single Wire C[ontroller]A[rea]N[etwork]”.
- However, a disadvantage of this known principle is that the second level scheme used for waking is associated with markedly increased bus system noise emission; in particular, cyclic wake-up events lead for this reason to undesirable disturbances in the motor vehicle, wherein E[lectro]M[agnetic]C[ompatibility] emissions also play a part; moreover, a second driver stage is necessary, to generate the other level scheme.
- Taking as basis the above-described disadvantages and shortcomings and acknowledging the outlined prior art, it is an object of the present invention so to develop a method of the above-mentioned type and a system of the above-mentioned type that the nodes and/or users in the network, i.e. on the databus, may be woken simply yet effectively.
- This object is achieved by a method having the features indicated in claim 1 and by a system having the features indicated in claim 4. Advantageous embodiments and expedient further developments of the present invention are identified in the respective dependent claims.
- It is therefore proposed according to the invention to use a different waking mechanism instead of the second level scheme in a system which finds itself selectively asleep in subnetwork operation, which different waking mechanism does not exhibit the above-described disadvantages of the prior art. This waking mechanism may be implemented both in system chips and in other networking products, such as for instance in simple transceiver modules.
- With regard to the present invention, it is first of all assumed that a number of nodes or a number of users are in a state of reduced current consumption and are thus not woken by the ongoing bus traffic.
- If, for a settable time designated rest phase or critical period for the purposes of the present invention, no more changes in level are noted on the databus, i.e. if the databus undergoes a relatively long, defined rest phase, it is assumed that subnetwork operation has been terminated.
- Once this critical period has passed, the next level change which occurs, for instance another user's new message, is again interpreted as a normal waking event and thus leads to the waking of all the users in the network (=“global waking” or full network operation).
- The rest phase or critical period should preferably be so set that the normal time gaps between the subnetwork operation messages are insufficient for detecting the end of subnetwork operation.
- The nodes or users in subnetwork operation appropriately send cyclic messages, so as to ensure that the “selectively sleeping” nodes or users are not woken (such cyclic messages are conventionally a constituent of a network management system, as in standard use in automobile technology, and thus require no separate effort).
- According to a particularly inventive further development of the present method and of the present system, a changeover from subnetwork operation to full network operation may also occur through the detection of at least one defined, especially continuous and/or especially symmetrical signal level pattern (=so-called “data pattern”) in the data traffic on the system.
- This signal level pattern, which advantageously does not otherwise occur in the data traffic, may appropriately be detected by at least one node in the reduced current consumption state and/or by at least one user in the reduced current consumption state.
- The present invention further relates to a transceiver unit, in particular for carrying out a method of the type described above and/or in particular associated with at least one system of the type described above; the transceiver unit is connected to at least one serial databus, in particular to at least one C[ontroller]A[rea]N[etwork] bus, and is in communication with at least one microcontroller unit which is provided to carry out at least one application.
- According to a preferred further development of the present invention, at least one control logic is associated with the transceiver unit and/or at least one control logic is implemented in the transceiver unit.
- The present invention further relates to a voltage regulator which is connected to at least one battery unit, and which is in communication with at least one transceiver unit, in particular of the type described above, which voltage regulator is intended to supply a voltage to at least one microcontroller unit, provided to execute at least one application, if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected by the transceiver unit in at least one incoming message associated with at least one application and occurring on at least one serial databus, in particular on at least one C[ontroller]A[rea]N[etwork] bus.
- The present invention further relates to a chip unit, in particular a system chip unit, for addressing and/or activating at least one microcontroller unit which is provided to carry out at least one application and which is associated with at least one serial databus, in particular at least one C[ontroller]A[rea]N[etwork]bus; which chip unit comprises at least one transceiver unit of the type described above, and at least one voltage regulator of the type described above.
- The present invention further relates to a microcontroller unit provided to carry out at least one application and associated with at least one serial data bus, in particular at least one C[ontroller]A[rea]N[etwork] bus, which microcontroller unit is to be supplied with a voltage only if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected in at least one incoming message associated with at least one application and occurring on the databus, by at least one transceiver unit, in particular according to the type described above.
- According to a preferred further development of the present invention, the microcontroller unit can be activated by the transceiver unit
- The present invention finally relates to the use of
-
- a method of the type described above and/or
- at least one system of the type described above and/or
- at least one chip unit of the type described above and/or
- at least one microcontroller unit of the type described above in automobile electronics, in particular in motor vehicle electronics.
- As has already been described above, there are various possible ways in which the teaching of the present invention may advantageously be embodied and refined. On the one hand, reference can be made in this connection to the claims dependent on claims 1, 4, 9 and 13, and on the other, further aspects, features and advantages of the present invention are apparent from and will be elucidated with reference to the illustrative embodiment shown in FIGS. 1 to 4.
- In the Figures:
-
FIG. 1 is a schematic block diagram of an example of embodiment of a system according to the present invention based on the method of the present invention; -
FIG. 2 is a schematic block diagram of a detailed section of the system shown inFIG. 1 . -
FIG. 3 shows, in a schematic time sequence, an example of embodiment of a changeover, according to the method, of the system ofFIG. 1 and 2 from subnetwork operation to full network operation; and -
FIG. 4 is a schematic representation of an example of embodiment of a defined signal level pattern not otherwise occurring in the ongoing data traffic. -
FIG. 1 shows an exemplary implementation of a serially networkedCAN system 100 provided for C[ontroller]A[rea]N[etwork] applications in automobile electronics, namely in motor vehicle electronics. - This serially networked
system 100 comprises fiveusers databus 10 via respective associatednodes - Next, in
FIG. 2 the build-up, the function and the structure of theusers first user 30, which is connected to thenode 20 of theCAN databus 10 and which can be addressed and/or activated via thisCAN databus 10. The operating principle is as follows: - If, in the case of a
system 100 changeover (cf.FIG. 1 ) according to the method from subnetwork operation to full network operation (cf.FIG. 3 ), a defined, for example continuous and/or for example symmetrical signal level pattern (=so-termed “data pattern” cf.FIG. 4 ) is detected in the data or message traffic on the CAN data bus line which otherwise does not occur in the data or message traffic, by thenode 20 which is in a state of reduced current consumption and/or by theuser 30 which is in a state of reduced current consumption, and in this regard in particular by atransceiver unit 84 equipped with a control logic and connected to thedata bus 10 and/or by asystem chip unit 80 which accommodates thetransceiver unit 84 and which is permanently supplied from abattery unit 70, then thetransceiver unit 84 switches on avoltage regulator 86 which is connected to thebattery unit 70 via asupply line 76 and which is incommunication 886 with thetransceiver unit 84. - After that, the application is stated completely via a
connection line 984 in that thevoltage regulator 86 supplies a voltage to the application user which takes the form of amicrocontroller unit 90 with integrated CAN control unit; as shown inFIG. 2 , between thevoltage regulator 86 and the (application)microcontroller unit 90 there is also a reset line 986 (“reset”). - If, however, the pattern detector (or transceiver 84) does not detect the presence of any message on the
CAN data bus 10, then thevoltage regulator 86 is not switched on. - The
system 100 may be configured and controlled via amode control interface 982 between the transceiver unit 84 (or the system chip unit 80) and themicrocontroller unit 90. - In addition, it is noted in respect of the example of embodiment of the present invention illustrated by means of
FIG. 2 that for the change-over it is not important whether use is made of an integratedsystem chip 80 or of discrete components such astransceiver 84 andvoltage regulator 86. - Of the five
users first user 30 of which has been described by way of example hereinabove with reference toFIG. 2 , twousers FIG. 1 , are in a low current consumption state, in which these twousers signal level FIG. 3 ) of the data traffic on thesystem 100. - The remaining three
active users users active user 30 and theactive user 34 and by the double-headed arrow between theactive user 34 and the active user 36) and are addressed by thesignal level system 100. - The
system 100 is now changed over from subnetwork operation T to fill network operation G, in which all thenodes users signal level system 100, in that asignal rest level 50 is noted on thesystem 100, i.e. in particular no change is noted in the signal level (=so-called rest phase), for a period Δt; this rest phase period Δt is greater than a critical period Δtk of definable and settable length. - On the other hand, this critical period Δtk is in turn set to be greater than the interval Δtd between the individual messages and data packets of the data traffic on the
system 100, such that the normal time gaps Δtd between the messages and data packets of subnetwork operation T are insufficient for detecting the end of subnetwork operation T. - Accordingly, the
nodes users nodes users - So that the
present system 100 also has the option, in ongoing subnetwork operation T (c.f.FIG. 3 ), of waking the “sleeping”nodes users FIG. 3 ) may be used according to a further development essential to the invention. - This “global waking message” or “global waking data packet” uses the same nominal level scheme but is distinguished by a special bit sequence, which does not arise in normal communication operation and which may be freely defined in the data field of any desired message or any desired data packet.
- In this context, the
nodes users system 100 may examine the ongoing data traffic on the CANsystem bus 10 for a continuous symmetrical data pattern and interpret the detection of this data pattern as a waking event. - As a particularly suitable bit sequence, there is provided a
symmetrical data pattern - Thus, a decisive advantage consists in the fact that the protocol used does not have to be tracked in bit-accurate manner and that, moreover, it is not essential to use a special message identifier (address/header), but rather any desired message identifier 60 (address/header) may be used; all that is needed is detection of a symmetrical pattern which may be repeated appropriately frequently in the data field of the message or of the data packet.
- The more data bytes are used, the more frequently this pattern may be present therein and the better it may be filtered for. The data patterns used may be of any desired type and are distinguished merely by the frequent repetition of identical bit phases. To filter such data patterns, it is possible to use both per se known analog circuits and per se known digital circuits.
- To summarize, it may thus be stated that the method illustrated in
FIG. 3 allows the implementation of subnetwork operation T within aserial bus system 10. Parts (=“selectively sleeping”nodes users 32, 38) of thenetworked system 100 shown inFIGS. 1 and 2 may remain in a reduced current consumption state, whereas other parts (=“active”nodes users - In order to wake these “sleeping”
nodes users databus 10 is used to allow waking of these “sleeping”nodes users nodes users databus 10 is thus that a bus system rest phase Δt was present beforehand which is greater than the settable critical period Δtk. - Alternatively or in addition thereto, an appropriately designed
symmetrical data pattern 62, 64 (c.f.FIG. 4 ) may be used within any desired messages or data packets, so as to “wake” the “sleeping”nodes users -
- 100 serially networked system, in particular serial databus system
- 10 serial databus, in particular C[ontroller]A[rea]N[etwork] bus
- 20 first node of the
system 100 - 22 second node of the
system 100 - 24 third node of the
system 100 - 26 fourth node of the
system 100 - 28 fifth node of the
system 100 - 30 first user of the
system 100 - 32 second user of the
system 100 - 34 third user of the
system 100 - 36 fourth user of the
system 100 - 38 fifth user of the
system 100 - 40 first signal level on
databus 10 - 42 second signal level on
databus 10 - 44 third signal level on
databus 10 - 46 fourth signal level on
databus 10 - 48 fifth signal level on
databus 10 - 50 signal rest level on
databus 10 - 60 identifier (address/header)
- 62 first symmetrical data pattern
- 64 second symmetrical data pattern
- 70 battery unit
- 76 connection between
battery unit 70 andvoltage regulator 86 - 80 chip unit, in particular system chip unit
- 84 transceiver unit of the
chip unit 80 - 86 voltage regulator of the
chip unit 80 - 886 connection between
transceiver unit 84 andvoltage regulator 86 - 90 microcontroller unit
- 982 interface between
transceiver unit 84 andmicrocontroller unit 90 - 984 connection between
voltage regulator 86 andmicrocontroller unit 90 - 986 reset line between
voltage regulator 86 andmicrocontroller unit 90 - G full network operation
- T subnetwork operation
- Δt time period
- Δtd interval
- Δtk critical period
Claims (15)
1. A method for changing over a serially networked system (100), in particular a serial databus system, from subnetwork operation (1), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and is not addressed and/or not activated by the signal level (40, 42, 44) of the data traffic on the system (100), to fill network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) are addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), characterized in that the system (100) is changed over from subnetwork operation (T) to fill network operation (G) if a signal rest level (50) and/or no change in the signal level is noted on the system (100) for a period (Δt) which is greater than a critical period (Δtk) of definable or settable length.
2. A method as claimed in claim 1 , characterized in that the critical period (Δtk) is selected to be greater than the interval (Δtd) between the individual messages or data packets of the data traffic on the system (100).
3. A method as claimed in claim 1 or 2 , characterized in that messages or data packets are sent by at least one of the nodes (20, 24, 26) and/or users (30, 34, 36) participating in subnetwork operation (T) at cyclic intervals which are smaller than the critical period (Δtk).
4. A serially networked system (100), which is intended to be changed over from subnetwork operation (T), in which at least one node (22, 28) and/or at least one user (32, 38) of the system (100) is in a state of reduced current consumption and cannot be addressed and/or activated by the signal level (40, 42, 44) of the data traffic on the system (100), to full network operation (G), in which all the nodes (20, 22, 24, 26, 28) and/or all the users (30, 32, 34, 36, 38) of the system (100) may be addressed and/or activated by the signal level (46, 48) of the data traffic on the system (100), characterized in that the changeover from subnetwork operation (T) to full network operation (G) takes place if the system (100) is in the signal rest level (50) state and/or an unchanged signal level state for a period (Δt) which is greater than a critical period (Δtk) of definable or settable length.
5. A system as claimed in claim 4 , characterized in that the critical period (Δtk) is greater than the interval (Δtd) between the individual messages or data packets of the data traffic on the system (100).
6. A system as claimed in claim 4 or 5 , characterized in that at least one of the nodes (20, 24, 26) and/or users (30, 34, 36) participating in subnetwork operation (T) sends messages or data packets at cyclic intervals which are smaller than the critical period (Δtk).
7. A system as claimed in at least one of claims 4 to 6 , characterized in that the system (100) comprises at least one serial databus (10), in particular at least one C[ontroller]A[rea]N[etwork] bus.
8. A system as claimed in at least one of claims 4 to 7 , characterized in that the user (30, 32, 34, 36, 38) takes the form of
at least one system chip unit (80), in particular at least one system chip unit,
and/or at least one microcontroller (90) unit provided for carrying out at least one application.
9. A transceiver unit (84), in particular for carrying out a method as claimed in at least one of claims 1 to 3 and/or in particular associated with at least one system (100) as claimed in at least one of claims 4 to 8 , characterized in that the transceiver unit (84)
is connected to at least one serial databus (10), in particular to at least one C[ontroller]A[rea]N[etwork] bus, and
is in communication (982) with at least one microcontroller unit (90) which is provided to carry out at least one application.
10. A transceiver unit as claimed in claim 9 , characterized by at least one control logic associated with the transceiver unit (84) and/or implemented in the transceiver unit (84).
11. A voltage regulator (86) which is connected to at least one battery unit (70), and which is in communication (886) with at least one transceiver unit (84), in particular as claimed in claim 9 or 10 , which voltage regulator is intended to supply a voltage to at least one microcontroller unit (90), provided to execute at least one application, in the event of detection, by the transceiver unit (84), of at least one defined, in particular continuous and/or in particular symmetrical signal level pattern in at least one incoming message associated with at least one application and occurring on at least one serial databus (10), in particular on at least one C[ontroller]A[rea]N[etwork] bus.
12. A chip unit (80), in particular a system chip unit, for addressing and/or activating at least one microcontroller unit (90) which is provided to carry out at least one application and which is associated with at least one serial databus (10), in particular at least one C[ontroller]A[rea]N[etwork] bus; characterized by
at least one transceiver unit (84) as claimed in claim 9 or 10 , and
at least one voltage regulator (86) as claimed in claim 11 .
13. A microcontroller unit (90) provided to carry out at least one application and associated with at least one serial data bus (10), in particular at least one C[ontroller]A[rea]N[etwork] bus, which microcontroller unit is to be supplied with a voltage only if at least one defined, in particular continuous and/or in particular symmetrical signal level pattern is detected in at least one incoming message associated with at least one application and occurring on the databus (10), by at least one transceiver unit (84), in particular as claimed in claim 9 or 10 .
14. A microcontroller unit (90) as claimed in claim 13 , characterized in that the microcontroller unit (90) may be activated by the transceiver unit (84).
15. The use of
a method as claimed in at least one of claims 1 to 3 and/or
at least one system (100) as claimed in at least one of claims 4 to 8 and/or
at least one chip unit (80) as claimed in claim 12 and/or
at least one microcontroller unit (90) as claimed in claim 13 or 14 in automobile electronics, in particular in motor vehicle electronics.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10225775.2 | 2002-06-10 | ||
DE10225776.0 | 2002-06-10 | ||
DE10225775A DE10225775A1 (en) | 2002-06-10 | 2002-06-10 | Connection system for network with several subscribers each connected to data bus and each providing signals in given time periods, with partial net period followed by full net period |
DE2002125776 DE10225776A1 (en) | 2002-06-10 | 2002-06-10 | Method of switching a serial networked system from partial to full network operation in which definite continual or symmetrical signal level pattern can be recognized in the data on the system |
PCT/IB2003/002116 WO2003104036A1 (en) | 2002-06-10 | 2003-06-05 | Method and system for switching between subnetwork operation and full network operation |
Publications (1)
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US20060075086A1 true US20060075086A1 (en) | 2006-04-06 |
Family
ID=29737586
Family Applications (2)
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US10/517,474 Abandoned US20060075086A1 (en) | 2002-06-10 | 2003-06-05 | Method and system between subnetwork operation and full network operation |
US10/517,246 Active 2028-07-08 US8566466B2 (en) | 2002-06-10 | 2003-06-05 | Method and system for switching between subnetwork operation and full network operation |
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US10/517,246 Active 2028-07-08 US8566466B2 (en) | 2002-06-10 | 2003-06-05 | Method and system for switching between subnetwork operation and full network operation |
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US (2) | US20060075086A1 (en) |
EP (2) | EP1517813A1 (en) |
JP (2) | JP2005529517A (en) |
CN (2) | CN100414915C (en) |
AU (2) | AU2003232391A1 (en) |
WO (2) | WO2003104037A1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
CN100414915C (en) | 2008-08-27 |
EP1515873A1 (en) | 2005-03-23 |
WO2003104036A1 (en) | 2003-12-18 |
US8566466B2 (en) | 2013-10-22 |
EP1517813A1 (en) | 2005-03-30 |
CN1659065A (en) | 2005-08-24 |
WO2003104037A1 (en) | 2003-12-18 |
JP2005529517A (en) | 2005-09-29 |
AU2003232391A1 (en) | 2003-12-22 |
AU2003232392A1 (en) | 2003-12-22 |
CN1659066A (en) | 2005-08-24 |
US20050204204A1 (en) | 2005-09-15 |
JP2005529516A (en) | 2005-09-29 |
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STCB | Information on status: application discontinuation |
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