US20060027934A1 - Silicon chip carrier with conductive through-vias and method for fabricating same - Google Patents
Silicon chip carrier with conductive through-vias and method for fabricating same Download PDFInfo
- Publication number
- US20060027934A1 US20060027934A1 US11/242,221 US24222105A US2006027934A1 US 20060027934 A1 US20060027934 A1 US 20060027934A1 US 24222105 A US24222105 A US 24222105A US 2006027934 A1 US2006027934 A1 US 2006027934A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- conductive
- vias
- carrier structure
- semiconductor carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the invention relates generally to a carrier for mounting and packaging multiple integrated circuit chips; and, more particularly, to a self-supporting semiconductor or insulator carrier substrate with conductive through-vias.
- a carrier for integrated circuit devices is typically fabricated of semiconductor, glass, or glass-ceramic material as a freestanding substrate, chip or wafer having conductive through-vias.
- the through-vias are exposed on the top and underside of the carrier and are insulated from each other. Multiple levels of carrier material with metallic or semi-metallic vias are often required to obtain the necessary conductive paths between chips and other devices mounted with respect to the carrier.
- the carrier having through-vias provides chip input/output terminals (I/O), with the chips typically mounted in the “flip chip” manner, and other device I/O through the carrier from the surface at which the chip or device is mounted to the other side of the carrier, which may include a next level of packaging, a board, or additional flip-chips mounted on that side of the carrier.
- FIG. 1 provides a representative illustration of a carrier in accordance with this invention.
- Carrier 102 comprises a layer 104 of insulative or semiconductive material, for example silicon, fused silica (“glass”, “quartz”), ceramic, or another semiconductor or insulator.
- the carrier 102 has multiple through-vias, shown as 105 representatively, which extend from the upper or top surface of the carrier layer 104 to the bottom surface of the carrier layer 104 .
- the through-vias are filled with a metallic or semi-metallic conductive via material, shown as conductor 115 , to provide conductive paths through the carrier.
- Solder bumps, C4s, or the like, shown as 114 are disposed at the bottom surface of carrier layer 104 in electrical contact with the conductive via material 115 in order to join the carrier to a next level.
- the conductive material 115 in the through-vias may be placed in electrical contact with additional multilevel wiring, integrated circuits or associated devices, optical or optoelectronic elements, microelectromechanical elements, etc. disposed in layers 106 which are, in turn, connected to the chip connectors, shown as microjoints 125 , of chip 120 .
- Semiconductor devices may also be embedded in the substrate and electrically incorporated into the aforementioned integrated circuits. Should additional multilevel wiring not be needed, the microjoints of chip 120 can be bonded directly to the conductive via material 115 .
- SOC System-on-a-Chip
- Black's method involves etching so-called blind holes only partially through the semiconductor substrate, insulating the holes' sidewalls, filling the insulated holes with metal selected from tungsten, chromium, copper, aluminum, nickel, indium, gold, and mixtures or alloys thereof, planarizing the top surface and removing excess metal, and then grinding away the bottom semiconductor material to expose the bottom of the filled vias (i.e., to open the blind holes).
- metal selected from tungsten, chromium, copper, aluminum, nickel, indium, gold, and mixtures or alloys thereof
- Table 1 provides a listing of commonly used materials, namely silicon for substrates, and copper, tungsten, and nickel for the metal, and their mechanical properties. YOUNG'S POISSON MATERIAL MODULUS (GPa) RATIO CTE (ppm/° C.) Silicon 170 0.28 3 doped 170 0.28 2 polysilicon Copper 130 0.34 16.5 Tungsten 411 0.28 4.5 Nickel 200 0.31 13.4
- tungsten With a CTE of ⁇ 5 ppm/° C. approaches the CTE of silicon (Si).
- the modulus of W is so high (>400 GPa) compared to that of silicon ( ⁇ 170 GPa) that brittle fracture of the Si and/or delamination of via sidewalls are likely, given the finite but small thermal expansion mismatch.
- the typical processes used to grow or deposit poly-Si are only practical for thicknesses up to ⁇ 1 or several single ⁇ m, and often are limited to deposition temperatures above the maximum temperatures that can be tolerated by integrated circuit components or wiring on the substrate above (if these are to be fabricated prior to filling the through-vias).
- the vertical extrusion due to sidewall stresses is determined by the thermal expansion mismatch, the modulus, and the Poisson ratio.
- the forces resulting from the extrusion and acting on the overlying or underlying structures or thin films increase with the modulus of the through-vias.
- the piston-like failures can be avoided by minimizing the thermal expansion mismatch, the Poisson ratio, and the modulus of the through-vias. If a conductive material has a CTE which is exactly the same as that of the substrate materials, then the modulus and Poisson ratio of the conductive material would not be an issue.
- What is needed, therefore, and what is an object of the present invention is to provide a carrier structure which can be fabricated at the desired dimensions and which can withstand thermal cycling experienced during production, joining processing, and use.
- Another object of the present invention is to provide a through-via structure including conductive material having a coefficient of thermal expansion which closely matches the substrate material, a reduced modulus and a reduced Poisson ratio in order to minimize the negative effects of thermal mismatch.
- Yet another object of the present invention is to provide a through-via structure which includes multiple differing materials having different coefficients of thermal expansion, to result in a through-via having an effective coefficient of thermal expansion which most closely matches that of the substrate, to minimize the negative effects of thermal mismatch.
- Another object of the invention is to provide a through-via structure which includes multiple differing materials having different coefficients of thermal expansion, to result in a through-via having an effective coefficient of thermal expansion which closely matches that of the substrate material and an effective modulus which most closely matches that of the substrate, or which is reduced to be less than that of the substrate, to reduce mechanical stresses encountered in processing and use.
- Yet another object of the invention is to provide ultrahigh density multi-chip packaging with through-vias, facilitating the inclusion of discrete or passive devices, to enable ultrahigh density system-on-package integration.
- Another object of the invention is to provide ultrahigh density multi-chip packaging with edge connectors to bring all wiring out for connection to a carrier or other level of packaging.
- the foregoing and other objects are realized by the present invention which provides a carrier structure and method for fabricating a carrier structure having through-vias which are filled with a composite conductive material having a coefficient of thermal expansion which closely matches that of the substrate and having a modulus value which matches or is less than that of the substrate.
- the composite conductive material may be a conducting metal, a conducting metal ceramic, a conducting mixture of metals and ceramics, or a metal with a sealed void.
- One embodiment of the invention includes a structure and method for fabricating a carrier structure having through-vias comprising concentric via fill areas each having differing materials disposed therein, wherein the via structure has an effective thermal coefficient of expansion and an effective modulus which are matched more closely to that of the carrier substrate material.
- each via structure is patterned as a annulus about a post “via” of the carrier material.
- the annulus is patterned to a depth which is the same as the desired length of the via and is less than the overall depth of the carrier layer.
- the conductor-lined, carrier-material-filled via is then exposed by polishing back the surface of the carrier having the base of the post to expose the conductive ring.
- ultrahigh density packages can be provided to enable ultrahigh density system-on-package integration.
- the ultrahigh density package is preferably provided with an integrated edge connector for connection to a carrier.
- System-on-chip is realized when multiple devices are connected to both sides of the ultrahigh density package.
- FIG. 1 is a side view of the carrier of the instant invention
- FIGS. 2A, 2B , 2 C, and 2 D are perspective views of carriers having through-vias with matched mechanical properties formed in accordance with different embodiments of the present invention.
- FIG. 3 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2A , in accordance with one embodiment of the present invention
- FIGS. 4A through 4K illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 3 with further backside processing;
- FIG. 5 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2B , in accordance with a second embodiment of the present invention
- FIGS. 6A through 6F illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 5 ;
- FIG. 7 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2C , in accordance with another embodiment of the present invention.
- FIGS. 8A through 8E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 7 ;
- FIG. 9 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2D , in accordance with another embodiment of the present invention.
- FIGS. 10A through 10E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 9 ;
- FIGS. 11A through 11C illustrate the formation of a collar about the top opening of the through-via to facilitate optimal electrical contact
- FIGS. 12A through 12C illustrate steps and the resulting structures for capping the through-vias
- FIGS. 13A and 13B provide side and top views of a system-on-chip mounted on an ultrahigh density package with an integrated edge connector in accordance with the present invention.
- FIGS. 14A and 14B illustrate two arrays of ultrahigh density packages bearing system-on-chip and edge connectors connected to a carrier.
- the invention addresses the shortcomings of the prior art by providing metal-ceramic materials, or multiple materials in through-vias, wherein the materials are chosen to reduce the negative effects of thermal mismatch by achieving an effective thermal expansion coefficient and an effective modulus which more closely matches those of the carrier substrate material.
- a carrier substrate of silicon which has a CTE of 3 ppm/° C. and an elastic modulus of 170 GPa
- FIGS. 2A, 2B , 2 C, and 2 D are perspective views of carriers having through-vias with matched mechanical properties formed in accordance with different embodiments of the present invention.
- FIG. 2A shows a side view of one carrier embodiment 200 of the invention wherein an annular ring 215 of a first via material, comprising a desired conductor, is disposed about the periphery of the via hole in the carrier substrate material 204 , lining the cylinder, with the inner volume of the lined cylinder being filled with a second via material 210 .
- the second via material is chosen to have a CTE which is close to the CTE of the carrier substrate material 204 , so that undesirable effects of thermal mismatch will be minimized while still realizing the desired conductive properties in the through-via.
- An additional insulating ring 203 or liner may be disposed between the annular ring 215 and the carrier substrate material 204 to act as an additional insulator or diffusion barrier or both.
- FIG. 3 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2A , in accordance with one embodiment of the present invention.
- the carrier substrate made of a semiconductor or insulative material, silicon for example, is etched at step 300 to form blind vias.
- Blind vias are defined as vias which extend to a desired depth into the carrier substrate layer, which desired depth is less than the thickness or depth of the initial carrier substrate.
- the desired depth is defined as the depth of the cylindrical through-vias which will result from the process, also defined for most resulting structures as the desired overall thickness of the end-product carrier substrate with through-vias.
- the blind vias are etched into the silicon, or other carrier material, at step 300 , using standard etching techniques known in the art.
- a suitable deep etch method is described in co-pending patent application Ser. No. 10/639,989, entitled “Deep Filled Vias”, which was filed on Aug. 13, 2003 (Docket YOR920030048US1), and is assigned to the present assignee, the teachings of which are incorporated herein by reference.
- the substrate comprises silicon and the pattern transfer can be accomplished using silicon etching by fluorine radicals generated in a plasma, as is known in the art.
- Deep silicon structures can be patterned using commercially-available, deep reactive ion etch (RIE) systems such as the A601E, available from Alcatel.
- RIE deep reactive ion etch
- the deep RIE dry etching method uses time-multiplexed deep etching (TMDE), a variation of sidewall passivation, wherein etching and deposition cycles are performed sequentially.
- TMDE time-multiplexed deep etching
- sidewalls are passivated by a polymer deposited from a plasma, formed from the deposition precursor.
- both the polymer and the silicon are preferentially etched from the bottom of the trench by ion bombardment.
- a backside oxide or metal layer may optionally be used as a stopping layer for the deep Si etch. If a semiconductor or other conductive substrate is used, the exposed surfaces of the cylindrical blind vias must then be insulated at step 302 to avoid electrical grounding, shorting, or crosstalk through the substrate of signals that will be carried by the conductive through-vias.
- Insulation of the via sidewalls may be achieved through any number of standards techniques including, but not limited to, thermal oxidation in a tube furnace in an oxygen or steam environment at between 900° C. and 1100° C., low-pressure chemical vapor deposition (LPCVD) using TEOS at temperatures between 700° C. and 900° C., or plasma-enhanced chemical vapor deposition (PECVD) using silane or TEOS and oxygen or nitrous oxide, at temperatures between 300° C. and 600° C.
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma-enhanced chemical vapor deposition
- Silane or TEOS and oxygen or nitrous oxide at temperatures between 300° C. and 600° C.
- Nitrides may be deposited using silane, ammonia, and nitrogen precursors. The time is determined by the desired oxide or nitride thickness, such as 0.5-2.0 ⁇ m.
- Oxide, nitride, or bilayers of the two materials are all used to insulate the exposed sidewalls and floor of the blind vias.
- this step may not be necessary; however, a layer of an insulating material such as Si 3 N 4 may still be desired to act as a diffusion barrier.
- annular deposition is conducted to form an annular ring of the desired conductor along the exposed insulated surfaces of the blind via.
- the annular deposition may consist of a PVD barrier layer, a seed layer, and a plated metal, for example, PVD TaN/Ta/Cu plus plated Cu.
- the PVD barrier layer aids in adhesion of the filling metal, as well as protecting it from corrosion or thermal diffusion into the outlying carrier substrate material.
- the remaining volume of the cylindrical blind via is filled with a second via material, which is either conducting or insulating, comprising material such as poly-Si, SiO 2 , Si 3 N 4 , CVD-W, an inorganic oxide (e.g., glass, ceramic or glass ceramic compounds), a metal ceramic compound such as Cu-cordierite, or other suitable materials having CTE in the range of ⁇ 0 to ⁇ 5 ppm/° C., wherein the second via material has a thermal coefficient of expansion which matches or more closely approximates the CTE of the carrier substrate material (e.g., Si).
- the carrier substrate material e.g., Si
- Fill methods may include PECVD, PVD, plating, spin-on, sol-gel, bladder fill, or squeegee application with doctor blade.
- Some materials such as spin-on, sol-gel, and pastes may require a subsequent thermal cure and sinter.
- the deposition method used is preferably a vacuum assisted infiltration technique. A carrier with blind-etched through-vias is placed within a chamber and a mechanical vacuum is drawn. The Cu/Cordierite paste is introduced and a squeegee or doctor blade is used to extrude the paste into the evacuated via holes.
- a preferred process incorporates screening from a pressurized nozzle under vacuum to achieve voidless fill at room temperature.
- the filling step is followed by a drying bakeout step and then removal of residual paste from the top surface. Thereafter a multistep sintering process is conducted, first under steam (400° C. to 650° C.) to burn out any organics from the paste, and then is followed by a higher temperature (650° C. to 800° C.) sintering step under forming gas to reduce any oxide in the metal system and assure good interlinking of the Cu particles.
- the structure is planarized back to the top surface of the carrier substrate at step 308 to remove any materials deposited thereon.
- IC circuits and components may be fabricated on the top surface at some point, with care being taken to make electrical contact with the conductive annulus of the through-via. It may additionally be desirable to cap the second via vill material as detailed below with reference to FIGS. 12A through 12C .
- the bottom surface of the structure is subjected to a grinding and polishing step at 310 to expose the conductive annular ring material and second via fill material, resulting in the structure of FIG. 2A at the desired thickness for the end product carrier substrate with through-vias.
- FIGS. 4A through 4K illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 3 with further detail regarding the backside processing.
- Substrate 404 in FIG. 4A comprises the silicon substrate having etched blind vias.
- the blind vias have been provided with an insulating layer 403 , followed by the annular fill illustrated as 415 in FIG. 4C .
- the CTE-matched fill material 410 is then provided, overfilling the vias as shown in FIG. 4D .
- FIG. 4D After planarization of the top surface, and any optional processing to fabricate IC devices or circuits on the top surface, the structure of FIG.
- the backside grind and polish is preferably done to within 10-20 ⁇ m of the via bottoms, after which they are exposed by using a wet etch to recess the remaining silicon as shown in FIG. 4H . Care is taken to protect the frontside of the structure (wafer) from the wet etch chemistry. This can be done through a number of methods, representatively illustrated as layer 420 in FIG. 4F , including but not limited to a) a sacrificial protective coating such as a deposited oxide, nitride, or polyimide spin-on; b) a protective tape that is impervious to backside wet processing chemistry; or c) a fixture which creates a seal at the wafer edge and covers the frontside.
- a sacrificial protective coating such as a deposited oxide, nitride, or polyimide spin-on
- a protective tape that is impervious to backside wet processing chemistry
- a fixture which creates a seal at the wafer edge and
- the frontside protection is removed after all backside wet processing is complete.
- Wet etch of the silicon to reveal the vias can be done with etches such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). Concentrations of these chemistries can range from 10-50% by weight.
- KOH or TMAH is typically heated to 50° C.-80° C. which results in faster etching of the silicon.
- a timed etch is used to etch the silicon and recess the surface below the via tops by 5-10 ⁇ m.
- a blanket layer 423 of oxide, or other insulating material such as polyimide, is deposited as shown in FIG. 4I .
- any remaining oxide cap or oxide/nitride cap that surrounds the exposed via bottoms is briefly polished by CMP to expose the conductive material in the via cores as illustrated in 4 J, while leaving the bulk of the thicker backside wafer insulation in place.
- the back surface of the silicon wafer is thus completely insulated except over the conductive through-vias, so that metal pads or C4s, 425 , can be deposited over the via tips without shorting to the substrate as shown in FIG. 4K .
- the structure of FIG. 2B comprises a substrate 224 in which the through-via comprises an annular ring of insulating material 223 within which is disposed a conductive via of metal (e.g., copper) 225 having a void 220 at its core.
- the top and bottom surfaces of the through-via are copper, and copper covers the insulated sidewalls of the through-via.
- a void filled with a gas such as air, an inert gas, or N 2 , or alternatively a vacuum, is disposed at the center of the through-via and provides an effective modulus which is more nearly matched to the substrate 224 .
- the through-via becomes compliant when voided, resulting in a lower effective modulus and a lower effective Poisson ratio, and therefore exhibiting lower stresses and forces due to surrounding structures.
- the effective Poisson ratio here is defined as the ratio of out-of-plane displacement to in-plane displacement due to in-plane stress to reduce mechanical stresses encountered in processing and use.
- the effective Poisson ratio can be reduced to about 0.22 with the introduction of a percolated network of through-voids with an effective radius of three quarters of the through-via radius when a through-void of radius of three quarters of the via radius is introduced in the through-via.
- the introduction of a void or voids reduces the effective modulus and Poisson ratio of the through-via, resulting in a compliant through-via that exerts much less stress and force on the surrounding structures. In other words it behaves on a whole as if it had a much smaller thermal expansion mismatch with the substrate, thereby reducing piston-like deviations at the top during thermal cycling.
- FIG. 5 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2B , in accordance with a second embodiment of the present invention.
- blind vias are etched into the substrate, as above, to a depth which is slightly greater than the desired depth of the through-vias in the finished product.
- the sidewalls of the blind vias are insulated (as above), preferably by oxidizing silicon to form a thin layer of SiO 2 or PECVD oxide or nitride or both.
- An annular fill is conducted at step 504 to provide metal (e.g., PVD TaN/Ta/Cu plus plated Cu to thickness ⁇ 1/10 to ⁇ 1 ⁇ 5 of the via diameter) along the exposed insulated surfaces of the blind via.
- the top of the via is then capped with metal by either an overfilling, burnishing, or similar technique.
- the void in the center of the via will contain the ambient of the capping process, typically N2 or a vacuum.
- Overfilling is achieved by a PVD, CVD, evaporation, or sputtering process for metal deposition that will enclose and pinch off the via top.
- a polishing step may be needed to restore planarity.
- the top of the structure is planarized at step 508 to remove excess metal at the top surface and to expose the substrate between the vias.
- the planarization step must leave the top via surfaces of metal disposed in the top surface of the substrate material. Fabrication of IC circuits or components, etc. on the top surface may be done at some point, as above.
- the bottom substrate surfaces are exposed to the backside processing steps to expose the blind vias and remove the excess substrate material and insulating layer and insulate the substrate bottom surface, as above. Care must be taken at both the top and bottom surfaces to leave metal across the entire via surface in order to preserve the void within.
- FIGS. 6A through 6F illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 5 .
- the blind vias are etched in substrate 604 .
- the insulating layer 603 is formed in the blind vias of the structure in FIG. 6B .
- the annular fill is conducted to provide metal 615 along the exposed insulated surfaces of the vias to yield the structure of FIG. 6C .
- the sealing or burnishing step provides additional metal 625 at the top surface of the vias, in conductive contact with the metal 615 and seals void 620 within, as shown in FIG. 6D .
- Planarization is done to remove the excess metal and expose the substrate 604 and metal vias at the top surface as shown in FIG. 6E .
- IC circuits or components may be fabricated on the top surface, as above.
- the bottom of the structure is exposed to the backside processing steps to remove the excess substrate material and insulating layer at the bottom of the vias, while leaving metal at the via bottom, as illustrated in FIG. 6F .
- the structure of FIG. 2C comprises a substrate 234 in which the through-vias each comprise an annular ring of insulating material 233 within which is disposed concentric circles comprising conductive via metal (e.g., copper) 235 , inner insulating ring 236 , and a core post 230 of substrate material.
- conductive via metal e.g., copper
- inner insulating ring 236 inner insulating ring 236
- a core post 230 of substrate material This differs from the coaxial through-via of the aforementioned Gaul patent in that the center post here is an insulator or semiconductor and does not carry the electrical signal. The center post is not contacted by the IC circuitry on the top or on the bottom of the carrier. The post is effectively a hollow waveguide, and could even be used for optical conductance through the Si substrate.
- the inner core of substrate material will necessarily be a thermal and modulus match to the outer substrate material, thereby reducing the mechanical effects of the overall via structure on the substrate.
- FIG. 7 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown in FIG. 2C , in accordance with a third embodiment of the present invention.
- blind vias are etched into the substrate to a depth which is the desired depth of the through-vias in the finished product.
- the vias are etched in a pattern whereby each is an annular via of thickness ⁇ 1/10 to ⁇ 1 ⁇ 5 of the via diameter etched about a post of substrate material which will remain as the core of the via.
- the sidewalls of the blind vias are insulated, preferably by oxidizing silicon to form a thin layer of SiO 2 (see above) on both the outer sidewalls and the post sidewalls.
- the annular vias are then overfilled with the desired conductive material at step 704 .
- the top of the structure is planarized at step 708 to remove excess metal at the top surface and to expose the substrate between the annular metal rings of the vias.
- IC circuits or components may be fabricated on top surface, as above.
- the bottom substrate surfaces are exposed to the backside processing steps to expose the blind vias and remove the excess substrate material and insulating layer.
- FIGS. 8A through 8E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 7 .
- the annular vias are etched in substrate 804 .
- the insulating layer 803 is formed on the sidewalls of the annular vias of the structure in FIG. 8B .
- the annular fill is conducted to provide metal 815 along the exposed insulated surfaces of the vias to completely fill the vias and yield the structure of FIG. 8C .
- Planarization is done to remove the excess metal and expose the substrate 804 and annular metal vias at the top surface as shown in FIG. 8D .
- IC circuits or components may be built on top surface, as above, with care taken to contact the conductive annulus.
- the bottom of the structure is exposed to the backside processing steps to remove the excess substrate material and insulating layer at the bottom of the vias, as illustrated in FIG. 8E .
- the structure of FIG. 2D comprises substrate 244 having vias of metal-ceramic core 245 surrounded by an annular insulating ring 243 .
- the metal-ceramic is chosen to have a coefficient of thermal expansion which is closely matched to the CTE of the substrate material, as well as a modulus which is close to that of the substrate or which is less than that of the substrate, with enough porosity to decrease the effective modulus and Poisson ratio.
- suitable materials include a copper cordierite metal-ceramic, surrounded by an SiO 2 or SiO 2 /Si 3 N 4 insulating layer in a silicon substrate.
- Additional materials of interest would be other low CTE materials, such as, but not limited to, glass ceramic, beta-Eucryptite, Enstatite, Fosterite, millite, Zircon, and fused silica.
- Metals in addition to copper, such as gold and silver, would be suitable candidate conductors due to their excellent conductivities. Additionally, alloys of the above metals as well as solid solution alloys such as Cu—Ni are of interest.
- a suitable fill material consists of fine particles of a low-CTE core material coated with a thin layer of linking metal such as copper.
- the low CTE core can consist of a wide range of materials from low CTE metals or alloys such as molybdenum, tungsten or Invar to nonmetals such as SiO2, silicon and silicon carbide.
- the coating material must consist of a metal for electrical conductivity, and should be able to form metallurgical joins at temperatures compatible with other structures already built on the wafer. Copper is a particularly desirable material because it is highly conducting and can form joins by Cu surface diffusion at temperatures considerably below its melting point. Other metals or alloys are also suitable such as thin layers of solder.
- heterogeneous mixtures of particles with the same outer layer (joining metal) but with different cores could be utilized to advantage.
- a mixture of copper coated tungsten (Cu/W) could be mixed with copper coated SiO2 (Cu/SiO2).
- Cu/W copper coated tungsten
- Cu/SiO2 copper coated SiO2
- the combination would lower the average CTE compared to Cu/W alone (which is already low CTE relative to Cu alone) while maintaining enough Cu/W to ensure outstanding electrical conductivity as well as ensuring mechanical and electrical connectivity between all outer shells.
- two particle types could be coated with metals A and B, where a low melting AB eutectic could form upon contact and mild heating.
- FIG. 9 is a representative flow chart for fabricating the structure of FIG. 2D .
- the blind vias are etched into the substrate.
- an insulating layer is formed along the exposed surfaces of the blind vias, typically by exposing the structure to an oxidizing atmosphere or PECVD, etc. as above.
- PECVD oxidizing atmosphere
- the remaining via volume is filled with the metal-ceramic.
- a metal-ceramic paste may be spread in the insulated vias at step 904 , followed by a sintering step to cure the via fill.
- a four stage cleaning method was developed including a first rinse step, a first coarse wiping step, a second fine wiping step, and a spin dry step.
- Planarization at step 908 will remove any excess conductive material from the backside processing at step 910 will expose the through-vias.
- FIGS. 10A through 10E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow of FIG. 9 .
- the vias are etched in substrate 1004 .
- the insulating layer 1003 is formed on the sidewalls of the vias of the structure in FIG. 10B .
- the fill is conducted to provide metal-ceramic 1015 along the exposed insulated surfaces of the vias to completely fill the vias and yield the structure of FIG. 10C .
- Planarization is done to remove the excess metal and expose the substrate 1004 and metal vias at the top surface as shown in FIG. 10D .
- IC circuits or components may be added as above. Special care must be taken to make electrical contact the top surface of the metal-ceramic filled through-vias.
- the bottom of the structure is exposed to grinding and polishing and etching to remove the excess substrate material and then adding an insulating layer to the exposed silicon substrate and subsequently removing the insulator only over the raised via bottoms by selective polishing, as illustrated in FIG. 10E .
- An effective method for ensuring good electrical contact to the surface of a partially plated through-via is to etch a shallow, concentric collar of suitably larger diameter in substrate 1104 around the top of the through-vias as shown in FIGS. 11A-11C .
- Such a structure adds a mask step, but greatly enhances the chances of achieving a good contact to subsequent levels of wiring as long as the collar depth is set to be no greater than the sidewall plating thickness.
- the collar effectively extends the annulus 1115 of FIG. 11C outward, offering a larger capture surface on which to drop contact vias, while moving these contacts further away from the central area of the deep via, filled with conductive material 1110 , where filling is most challenging.
- the fill material and processing described above may be tailored to leave the filled vias with an intentionally porous internal structure and/or with a controlled recess between the surface of the fill material and the top of the via.
- An intentionally porous and/or recessed surface must be effectively capped and sealed before the via planarization step to enable subsequent processing of the substrate.
- a number of metals and deposition methods can be used to seal effectively seal and cap such vias, including but not limited to tungsten, tantalum, or copper.
- Deposition methods may include sputtering, plasma jet deposition, thermal or laser-assisted CVD, molten liquid, metal infiltration via capillary action, or bumping with solder.
- Cap thickness may vary between about 0.5 to 10 microns depending on the size of the surface pores and/or the depth of the recess.
- insulators An alternative approach for metal capping of the filled porous via is the use of insulators. This is particularly practical with the partially plated vias where the electrical connection through the carrier is not counting on the via fill.
- any number of high temperature (> or ⁇ 400 C) stable insulating materials including but not limited to silicon dioxide, silicon nitride, silicon oxynitride, ceramics or high temperature polymers can be used.
- the inorganic material may be deposited using thermally activated or plasma-enhanced CVD, sputtering, or other such techniques known in the microelectronics field as well as plasma jet deposition.
- Photolithography may be used to remove insulator from the field areas, leaving it only on the via surface to seal pores and/or fill any recess.
- Final surface planarization after capping is done using CMP to expose the partially plated via sidewall top surface, or planarizing to the level of desired insulator thickness for electrical connection of the overlying build to the deep via.
- High temperature polymers including but not limited to polyimides or photosensitive polyimides (PSPI) may be spin applied from solution, laminated, or vapor deposited onto the surface of the substrate 1204 , as shown at 1220 of FIGS. 12A-12C , having through-vias including insulative via liner 1203 , conducting material 1215 , and via fill 1210 .
- the liquid polyimide precursor may not significantly penetrate into the porous via, thus largely preserving the thermal properties of said via.
- the negatively or positively working PSPI is exposed and developed to remove the unwanted material, FIG. 12B .
- a touch-up polish can be applied to improve further the planarity of the surface.
- the electrical connection after insulator capping is done at the partially plated via sidewalls, or a conductive cap, shown as 1225 in FIG. 12C , can be deposited to connect electrically the via sidewalls.
- All of the embodiments of the present invention provide conductive through-vias having effective CTEs and modulus values which are more closely matched to the CTE and modulus of the substrate materials than pure metal or metal compound vias. As well some have reduced Poisson ratios.
- the finished supporting substrate has a thickness of 300 ⁇ m, with via aspect ratios of less than or equal to 4:1, such that the through-via diameter must be greater than or about equal to 75 ⁇ m.
- a system-on-chip 1300 can be realized by connecting multiple devices to the ultrahigh density package.
- Silicon carrier 1304 with metallized through-vias 1315 provides connection through intermediate multilevel wiring layer 1306 for chips 1320 and 1340 mounted on C4s 1325 on one side of the carrier and for chip 1360 on the other side of the carrier.
- the Si carrier is built from a semiconductor, it is possible to include all types of active and passive devices on the carrier, such as are conventionally built in integrated circuits.
- Multiple chips and discrete devices including, but not limited to, optical modulators, FET transistors, thin oxide trench or surface capacitors, varactors, logic or analog integrated circuits, resistors, inductors, transmission lines, can be mounted to the package.
- the multiple chips and discrete devices may be mounted in very close proximity (e.g., 5-10 ⁇ m) on one or both sides of the Si carrier. Mounting is done by conventional techniques.
- Dual heat spreaders 1350 and 1370 can be provided on the backside of the mounted chips, using thermal paste or other conventional heat-sinking interface, to dissipate heat generated by the chips.
- the silicon carrier preferably includes one or more levels of wiring, preferably Cu wiring at single ⁇ m dimensions for optimum density and bandwidth.
- the wiring 1355 may be provided on one or both sides of the package, with connection through the through-vias if wiring is only formed on one side of the package. Dual-damascene processing for Cu wiring, as is well known in the art, may be used to form the wiring. Pitches for the wiring are preferably no greater than approximately 5 ⁇ m to allow parallel memory bussing between chips for terabit per second data processing. For a Si carrier with chips or chip stacks mounted on both sides, the external I/O would be provided near one or more edges of the Si carrier top or bottom surface, shown as 1365 .
- linear or staggered arrays of bonding pads along one or both surfaces could be bonded to a lead frame or wire bonded to the inner leads of a socket or edge connector 1365 which would ultimately mate to an outside socket on a printed circuit board.
- the entire assembly is enclosed in a metal, plastic, ceramic, or other material package enclosure, illustratively shown as 1380 , so that all of the electronics are enclosed, with the lead frame or edge connector leads being exposed and the outer surfaces of the heat spreaders remaining exposed for thermal contact with suitable mating structures or materials for external heat sinking.
- Heat fins may additionally be provided at the assembly edge not occupied by the edge connector.
- Single or multiple ultrahigh density system-on-chip packages 1400 A, 1400 B, 1400 C, 1400 D . . . 1400 N and 1410 A, 1410 B, 1410 C, 1410 D through 1410 N may now be plugged in via their respective edge connectors 1465 A- 1465 N and 1475 A through 1475 N to mating connectors on a printed circuit board 1490 , rack, backplane or the like, as shown in FIGS. 14A and 14B .
- Heat sink fins or other devices shown illustratively as 1450 D and 1450 N, may be attached to the outside or outer edges of the ultrahigh density packages.
- air 1492 , or coolant 1494 such as water, could be circulated through the compartment 1490 to cool the packages, thereby extracting heat directly from the mounted chips inside the ultrahigh density package arrays.
- a complete ultrahigh performance computer system such as a PC or portable gaming system (e.g., 4 or more chips) could be packaged in an ultrahigh density package with an edge connector in such a manner as to comply with the “Compact Flash” format.
- an entire supercomputer node (CPU, memory communications interfaces) could be packaged in a similar Compact Flash format and plugged vertically into a PC board or backplane so that it is, itself, a heat-sink cooling fin.
- the supercomputer node could be bolted into a cold plate that has internal coolant circulation (need illustrations of the latter two).
Abstract
Description
- The invention relates generally to a carrier for mounting and packaging multiple integrated circuit chips; and, more particularly, to a self-supporting semiconductor or insulator carrier substrate with conductive through-vias.
- A carrier for integrated circuit devices is typically fabricated of semiconductor, glass, or glass-ceramic material as a freestanding substrate, chip or wafer having conductive through-vias. The through-vias are exposed on the top and underside of the carrier and are insulated from each other. Multiple levels of carrier material with metallic or semi-metallic vias are often required to obtain the necessary conductive paths between chips and other devices mounted with respect to the carrier. The carrier having through-vias provides chip input/output terminals (I/O), with the chips typically mounted in the “flip chip” manner, and other device I/O through the carrier from the surface at which the chip or device is mounted to the other side of the carrier, which may include a next level of packaging, a board, or additional flip-chips mounted on that side of the carrier.
-
FIG. 1 provides a representative illustration of a carrier in accordance with this invention.Carrier 102 comprises alayer 104 of insulative or semiconductive material, for example silicon, fused silica (“glass”, “quartz”), ceramic, or another semiconductor or insulator. Thecarrier 102 has multiple through-vias, shown as 105 representatively, which extend from the upper or top surface of thecarrier layer 104 to the bottom surface of thecarrier layer 104. The through-vias are filled with a metallic or semi-metallic conductive via material, shown asconductor 115, to provide conductive paths through the carrier. Solder bumps, C4s, or the like, shown as 114, are disposed at the bottom surface ofcarrier layer 104 in electrical contact with the conductive viamaterial 115 in order to join the carrier to a next level. At the upper surface ofcarrier layer 104, theconductive material 115 in the through-vias may be placed in electrical contact with additional multilevel wiring, integrated circuits or associated devices, optical or optoelectronic elements, microelectromechanical elements, etc. disposed inlayers 106 which are, in turn, connected to the chip connectors, shown asmicrojoints 125, ofchip 120. Semiconductor devices may also be embedded in the substrate and electrically incorporated into the aforementioned integrated circuits. Should additional multilevel wiring not be needed, the microjoints ofchip 120 can be bonded directly to the conductive viamaterial 115. - Problems have arisen in carriers of the prior art due to limitations in materials, deposition methods, control of dimensional tolerances, and mechanical stresses encountered during processing of the materials. Traditional substrate thicknesses are in the range of 0.5 mm to 20 mm with through-via aspect ratios in the range of 1:1 to 2:1. Through-vias may be tapered or vertical as dictated by the forming technology. For instance, vias formed by a punch technique display a breakout region and laser vias can be tapered depending upon the aspect ratio. Typical pitches may be 225 μm for glass ceramic or plastic substrates at the present, and 150 μm for ceramic substrates. Depending upon the desired via density, given the number of chips or other devices to be joined to the carrier and the number of desired bonding sites, the via diameters would accordingly range from 25 to 300 μm.
- There is a need to miniaturize such carriers to accommodate single or multiple flip-chips and micro-components with I/O densities of from 1,000 to 10,000 per cm2, with overall physical dimensions being in the single cm range for length and width and in the range of a single μm to a few 100 μms in thickness. For high speed and low power, the through-vias and associated connections must present series resistances lower than several 100 mΩs to several tens of mΩs, or else signal risetimes will be degraded. This in turn specifies that through-vias filled with typical conductive materials be of a height in the range of a single μm to several hundred μms with diameters of several 10's to ˜100 μm.
- As computing performance continues to improve, geometrically by Moore's Law, at the same time as physical limits to semiconductor device scaling impede continued improvements of the integrated device, increasingly higher levels of system integration are needed. Just as multiple transistors and circuits are integrated in a monolithic manner for LSI, VLSI, and USLI, it is desirable to integrate entire computer system blocks on single chips, for so-called “System-on-a-Chip” (SOC). For example, multiple CPU cores plus multiple levels of cache memory are now integrated within a single multiprocessor chip, along with off-chip memory and other logic units. As SOC integration density demands increase and speed continues to increase, power densities become untenable. Current packaging technologies are limited in interconnect density, I/O density, interconnect bandwidth, and chip-to-chip spacing required to reach the ultrahigh performance levels needed, including greater than 10 GHz chip-to-chip communications with full memory bandwidth for >1000 I/Os per chip-to-chip edge interconnection. Finally, there is a need for ultrahigh speed discrete devices and passive components such as massive decoupling capacitors to address noise and other issues that are on-chip. It is not possible for current off-chip devices to respond at the on-chip frequencies needed, due to excessive distances from the chip, high parasitic impedance, and slow characteristics of the devices themselves. A carrier package with conductive through-vias, enabling connection of devices on both sides of the package, would allow the desired device densities.
- Filling high aspect ratio vias, with a height in the range of a single μm to several hundred μms with diameters of several 10's to ˜100 μm, to provide packages with through-vias, is challenging. A popular technique for filling blind vias or through-vias of micro-scale diameters is electroplating of Cu. However, the hydrodynamics, the ionic concentrations, and the diffusivities limit the filling of deep blind holes. Authors Tomisaka et al. (ECTC 2002) did extensive plating optimization and were still not able to eliminate voids in vias of only 70 μm deep. Methods for filling large blind holes which are to be opened later break down or become impractical at such dimensions. The U.S. Pat. No. 5,998,292 of Black, et al details a method for creating insulated conductive through-holes in a semiconductor wafer for 3-dimensional wafer joining. Black's method involves etching so-called blind holes only partially through the semiconductor substrate, insulating the holes' sidewalls, filling the insulated holes with metal selected from tungsten, chromium, copper, aluminum, nickel, indium, gold, and mixtures or alloys thereof, planarizing the top surface and removing excess metal, and then grinding away the bottom semiconductor material to expose the bottom of the filled vias (i.e., to open the blind holes). U.S. Pat. Nos. 5,646,067 and 5,814,889 and 5,618,752 of Gaul use the Black approach applied to a silicon carrier layer with tungsten or polysilicon through vias. Chiu et al. (U.S. Pat. No. 6,593,644) describe a similar process to create a Si-based chip carrier, with through-vias filled by Cu, Ni, or Al. The Black method provides adequate fill of the through-vias (for some of the listed materials); however, given the materials used, the resulting structure will experience the mechanical failures described below with reference to Table 1. Gaul utilizes materials that are more closely thermally matched, namely W and poly-Si, but would not have practical deposition methods for multi-10's of pin and would have vastly differing values for modulus. It is also to be noted that incorporation of embedded components into present carriers is difficult due to processing limitations, such as high temperature sintering conditions for ceramic carriers, as well as limitations with embedded component material systems.
- At the above-stated diameters, most metals which are commonly used for integrated circuit interconnect vias generate unacceptable stress levels on the carrier layer material (e.g., Si or glass) due to thermal expansion mismatch. In addition, the metal structures exhibit top surface extrusions, ruptures, or expansions during and after typical thermal cycling. For carrier substrates and integrated devices that are comprised of brittle materials, such as semiconductors, glass, or ceramics, the risk of mechanical failure by brittle fracture is significant given the thermal expansion mismatches and the fragility of the carrier materials. In addition to brittle fracture, interfacial delamination is likely when employing standard materials and combinations of materials at the stated dimensions. Table 1 provides a listing of commonly used materials, namely silicon for substrates, and copper, tungsten, and nickel for the metal, and their mechanical properties.
YOUNG'S POISSON MATERIAL MODULUS (GPa) RATIO CTE (ppm/° C.) Silicon 170 0.28 3 doped 170 0.28 2 polysilicon Copper 130 0.34 16.5 Tungsten 411 0.28 4.5 Nickel 200 0.31 13.4 - Of the metals commonly used for substrate metallization, only tungsten (W), with a CTE of ˜5 ppm/° C. approaches the CTE of silicon (Si). However, the modulus of W is so high (>400 GPa) compared to that of silicon (˜170 GPa) that brittle fracture of the Si and/or delamination of via sidewalls are likely, given the finite but small thermal expansion mismatch. Like W, the typical processes used to grow or deposit poly-Si are only practical for thicknesses up to ˜1 or several single μm, and often are limited to deposition temperatures above the maximum temperatures that can be tolerated by integrated circuit components or wiring on the substrate above (if these are to be fabricated prior to filling the through-vias).
- Three potential problems associated with large CTE mismatches between vias and the Si substrate include delamination at the via sidewalls (resulting in so-called “rattling vias” that exhibit compromised conductivity and mechanical stability), cracking of the Si substrate between vias, and piston-like ruptures of any overlying or underlying structures or thin films in contact with the top and bottom surfaces of the vias. The following reference discusses via cracking issues: “Fiber-End Cracking in Brittle-Matrix Composites: A Model Study”, J. A. Casey, D. R. Clarke and Y. Fu, in Metal-Ceramic Interfaces, Proceedings of an International Workshop, ACTA Met, 1990.
- The vertical extrusion due to sidewall stresses is determined by the thermal expansion mismatch, the modulus, and the Poisson ratio. The forces resulting from the extrusion and acting on the overlying or underlying structures or thin films increase with the modulus of the through-vias. The piston-like failures can be avoided by minimizing the thermal expansion mismatch, the Poisson ratio, and the modulus of the through-vias. If a conductive material has a CTE which is exactly the same as that of the substrate materials, then the modulus and Poisson ratio of the conductive material would not be an issue.
- What is needed, therefore, and what is an object of the present invention is to provide a carrier structure which can be fabricated at the desired dimensions and which can withstand thermal cycling experienced during production, joining processing, and use.
- Another object of the present invention is to provide a through-via structure including conductive material having a coefficient of thermal expansion which closely matches the substrate material, a reduced modulus and a reduced Poisson ratio in order to minimize the negative effects of thermal mismatch.
- Yet another object of the present invention is to provide a through-via structure which includes multiple differing materials having different coefficients of thermal expansion, to result in a through-via having an effective coefficient of thermal expansion which most closely matches that of the substrate, to minimize the negative effects of thermal mismatch.
- Another object of the invention is to provide a through-via structure which includes multiple differing materials having different coefficients of thermal expansion, to result in a through-via having an effective coefficient of thermal expansion which closely matches that of the substrate material and an effective modulus which most closely matches that of the substrate, or which is reduced to be less than that of the substrate, to reduce mechanical stresses encountered in processing and use.
- Yet another object of the invention is to provide ultrahigh density multi-chip packaging with through-vias, facilitating the inclusion of discrete or passive devices, to enable ultrahigh density system-on-package integration.
- Another object of the invention is to provide ultrahigh density multi-chip packaging with edge connectors to bring all wiring out for connection to a carrier or other level of packaging.
- The foregoing and other objects are realized by the present invention which provides a carrier structure and method for fabricating a carrier structure having through-vias which are filled with a composite conductive material having a coefficient of thermal expansion which closely matches that of the substrate and having a modulus value which matches or is less than that of the substrate. The composite conductive material may be a conducting metal, a conducting metal ceramic, a conducting mixture of metals and ceramics, or a metal with a sealed void.
- One embodiment of the invention includes a structure and method for fabricating a carrier structure having through-vias comprising concentric via fill areas each having differing materials disposed therein, wherein the via structure has an effective thermal coefficient of expansion and an effective modulus which are matched more closely to that of the carrier substrate material.
- In another embodiment, each via structure is patterned as a annulus about a post “via” of the carrier material. The annulus is patterned to a depth which is the same as the desired length of the via and is less than the overall depth of the carrier layer. Upon filling the annulus with the desired conductive material, the conductor-lined, carrier-material-filled via is then exposed by polishing back the surface of the carrier having the base of the post to expose the conductive ring.
- Using the inventive carrier structure having through-vias which are filled with a composite conductive material having a coefficient of thermal expansion which closely matches that of the substrate, ultrahigh density packages can be provided to enable ultrahigh density system-on-package integration. The ultrahigh density package is preferably provided with an integrated edge connector for connection to a carrier. System-on-chip is realized when multiple devices are connected to both sides of the ultrahigh density package.
- The invention will now be described in greater detail with specific reference to the appended drawings wherein:
-
FIG. 1 is a side view of the carrier of the instant invention; -
FIGS. 2A, 2B , 2C, and 2D are perspective views of carriers having through-vias with matched mechanical properties formed in accordance with different embodiments of the present invention; -
FIG. 3 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2A , in accordance with one embodiment of the present invention; -
FIGS. 4A through 4K illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 3 with further backside processing; -
FIG. 5 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2B , in accordance with a second embodiment of the present invention; -
FIGS. 6A through 6F illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 5 ; -
FIG. 7 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2C , in accordance with another embodiment of the present invention; -
FIGS. 8A through 8E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 7 ; -
FIG. 9 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2D , in accordance with another embodiment of the present invention; -
FIGS. 10A through 10E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 9 ; -
FIGS. 11A through 11C illustrate the formation of a collar about the top opening of the through-via to facilitate optimal electrical contact; -
FIGS. 12A through 12C illustrate steps and the resulting structures for capping the through-vias, and -
FIGS. 13A and 13B provide side and top views of a system-on-chip mounted on an ultrahigh density package with an integrated edge connector in accordance with the present invention; and -
FIGS. 14A and 14B illustrate two arrays of ultrahigh density packages bearing system-on-chip and edge connectors connected to a carrier. - The invention addresses the shortcomings of the prior art by providing metal-ceramic materials, or multiple materials in through-vias, wherein the materials are chosen to reduce the negative effects of thermal mismatch by achieving an effective thermal expansion coefficient and an effective modulus which more closely matches those of the carrier substrate material. For a carrier substrate of silicon, which has a CTE of 3 ppm/° C. and an elastic modulus of 170 GPa, it is preferable to fill the through-via with a material or a combination of materials that yield an effective CTE of less than 8 ppm/° C. and an effective elastic modulus of less than or equal to 170 GPa.
FIGS. 2A, 2B , 2C, and 2D are perspective views of carriers having through-vias with matched mechanical properties formed in accordance with different embodiments of the present invention. -
FIG. 2A shows a side view of one carrier embodiment 200 of the invention wherein an annular ring 215 of a first via material, comprising a desired conductor, is disposed about the periphery of the via hole in thecarrier substrate material 204, lining the cylinder, with the inner volume of the lined cylinder being filled with a second viamaterial 210. The second via material is chosen to have a CTE which is close to the CTE of thecarrier substrate material 204, so that undesirable effects of thermal mismatch will be minimized while still realizing the desired conductive properties in the through-via. An additional insulatingring 203 or liner may be disposed between the annular ring 215 and thecarrier substrate material 204 to act as an additional insulator or diffusion barrier or both. -
FIG. 3 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2A , in accordance with one embodiment of the present invention. The carrier substrate, made of a semiconductor or insulative material, silicon for example, is etched atstep 300 to form blind vias. Blind vias are defined as vias which extend to a desired depth into the carrier substrate layer, which desired depth is less than the thickness or depth of the initial carrier substrate. The desired depth is defined as the depth of the cylindrical through-vias which will result from the process, also defined for most resulting structures as the desired overall thickness of the end-product carrier substrate with through-vias. The blind vias are etched into the silicon, or other carrier material, atstep 300, using standard etching techniques known in the art. A suitable deep etch method is described in co-pending patent application Ser. No. 10/639,989, entitled “Deep Filled Vias”, which was filed on Aug. 13, 2003 (Docket YOR920030048US1), and is assigned to the present assignee, the teachings of which are incorporated herein by reference. In the presently preferred embodiment, the substrate comprises silicon and the pattern transfer can be accomplished using silicon etching by fluorine radicals generated in a plasma, as is known in the art. Deep silicon structures can be patterned using commercially-available, deep reactive ion etch (RIE) systems such as the A601E, available from Alcatel. The deep RIE dry etching method uses time-multiplexed deep etching (TMDE), a variation of sidewall passivation, wherein etching and deposition cycles are performed sequentially. During the deposition step, sidewalls are passivated by a polymer deposited from a plasma, formed from the deposition precursor. During the subsequent etching cycle, both the polymer and the silicon are preferentially etched from the bottom of the trench by ion bombardment. By switching between etching and deposition cycles, deep, anisotropic structures having vertical sidewalls can be realized with very high etching rates in silicon substrates. A backside oxide or metal layer may optionally be used as a stopping layer for the deep Si etch. If a semiconductor or other conductive substrate is used, the exposed surfaces of the cylindrical blind vias must then be insulated atstep 302 to avoid electrical grounding, shorting, or crosstalk through the substrate of signals that will be carried by the conductive through-vias. - Insulation of the via sidewalls may be achieved through any number of standards techniques including, but not limited to, thermal oxidation in a tube furnace in an oxygen or steam environment at between 900° C. and 1100° C., low-pressure chemical vapor deposition (LPCVD) using TEOS at temperatures between 700° C. and 900° C., or plasma-enhanced chemical vapor deposition (PECVD) using silane or TEOS and oxygen or nitrous oxide, at temperatures between 300° C. and 600° C. Nitrides may be deposited using silane, ammonia, and nitrogen precursors. The time is determined by the desired oxide or nitride thickness, such as 0.5-2.0 μm. Oxide, nitride, or bilayers of the two materials are all used to insulate the exposed sidewalls and floor of the blind vias. For insulating substrates such as glass this step may not be necessary; however, a layer of an insulating material such as Si3N4 may still be desired to act as a diffusion barrier.
- Thereafter, at
step 304, annular deposition is conducted to form an annular ring of the desired conductor along the exposed insulated surfaces of the blind via. The annular deposition may consist of a PVD barrier layer, a seed layer, and a plated metal, for example, PVD TaN/Ta/Cu plus plated Cu. The PVD barrier layer aids in adhesion of the filling metal, as well as protecting it from corrosion or thermal diffusion into the outlying carrier substrate material. As noted above, it is preferable not to fill the entire via with the desired metal, since unacceptable thermal mismatch will result in breakage or delamination. Therefore, a controlled deposition is conducted to result in a thin annular ring of the conductive material. - At
step 306, the remaining volume of the cylindrical blind via is filled with a second via material, which is either conducting or insulating, comprising material such as poly-Si, SiO2, Si3N4, CVD-W, an inorganic oxide (e.g., glass, ceramic or glass ceramic compounds), a metal ceramic compound such as Cu-cordierite, or other suitable materials having CTE in the range of ˜0 to ˜5 ppm/° C., wherein the second via material has a thermal coefficient of expansion which matches or more closely approximates the CTE of the carrier substrate material (e.g., Si). In the example of Cu fill in a 100 μm diameter Si through-via, it has been calculated that a Cu plating thickness equal to 1/10 of the via diameter and filled with SiO2 will lead to the desired thermal and conductive properties. - Fill methods may include PECVD, PVD, plating, spin-on, sol-gel, bladder fill, or squeegee application with doctor blade. Some materials such as spin-on, sol-gel, and pastes may require a subsequent thermal cure and sinter. For example, for a Cu/Cordierite paste the deposition method used is preferably a vacuum assisted infiltration technique. A carrier with blind-etched through-vias is placed within a chamber and a mechanical vacuum is drawn. The Cu/Cordierite paste is introduced and a squeegee or doctor blade is used to extrude the paste into the evacuated via holes. A preferred process incorporates screening from a pressurized nozzle under vacuum to achieve voidless fill at room temperature. The filling step is followed by a drying bakeout step and then removal of residual paste from the top surface. Thereafter a multistep sintering process is conducted, first under steam (400° C. to 650° C.) to burn out any organics from the paste, and then is followed by a higher temperature (650° C. to 800° C.) sintering step under forming gas to reduce any oxide in the metal system and assure good interlinking of the Cu particles.
- After the filling of the remaining volume has been completed, the structure is planarized back to the top surface of the carrier substrate at
step 308 to remove any materials deposited thereon. IC circuits and components may be fabricated on the top surface at some point, with care being taken to make electrical contact with the conductive annulus of the through-via. It may additionally be desirable to cap the second via vill material as detailed below with reference toFIGS. 12A through 12C . Finally, the bottom surface of the structure is subjected to a grinding and polishing step at 310 to expose the conductive annular ring material and second via fill material, resulting in the structure ofFIG. 2A at the desired thickness for the end product carrier substrate with through-vias. -
FIGS. 4A through 4K illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 3 with further detail regarding the backside processing.Substrate 404 inFIG. 4A comprises the silicon substrate having etched blind vias. InFIG. 4B , the blind vias have been provided with an insulatinglayer 403, followed by the annular fill illustrated as 415 inFIG. 4C . The CTE-matchedfill material 410 is then provided, overfilling the vias as shown inFIG. 4D . After planarization of the top surface, and any optional processing to fabricate IC devices or circuits on the top surface, the structure ofFIG. 4E is then subjected to the grinding and polishing step at the bottom surface to remove the excess substrate material and bottom via fill materials (i.e., the insulatinglayer 403 andmetal 415 which line the bottom of the blind vias) to expose the through vias as shown inFIG. 4G . - The backside grind and polish is preferably done to within 10-20 μm of the via bottoms, after which they are exposed by using a wet etch to recess the remaining silicon as shown in
FIG. 4H . Care is taken to protect the frontside of the structure (wafer) from the wet etch chemistry. This can be done through a number of methods, representatively illustrated aslayer 420 inFIG. 4F , including but not limited to a) a sacrificial protective coating such as a deposited oxide, nitride, or polyimide spin-on; b) a protective tape that is impervious to backside wet processing chemistry; or c) a fixture which creates a seal at the wafer edge and covers the frontside. The frontside protection is removed after all backside wet processing is complete. Wet etch of the silicon to reveal the vias can be done with etches such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). Concentrations of these chemistries can range from 10-50% by weight. The KOH or TMAH is typically heated to 50° C.-80° C. which results in faster etching of the silicon. A timed etch is used to etch the silicon and recess the surface below the via tops by 5-10 μm. After etching the carrier material as shown inFIG. 4H , ablanket layer 423 of oxide, or other insulating material such as polyimide, is deposited as shown inFIG. 4I . Any remaining oxide cap or oxide/nitride cap that surrounds the exposed via bottoms is briefly polished by CMP to expose the conductive material in the via cores as illustrated in 4J, while leaving the bulk of the thicker backside wafer insulation in place. The back surface of the silicon wafer is thus completely insulated except over the conductive through-vias, so that metal pads or C4s, 425, can be deposited over the via tips without shorting to the substrate as shown inFIG. 4K . - The structure of
FIG. 2B comprises asubstrate 224 in which the through-via comprises an annular ring of insulatingmaterial 223 within which is disposed a conductive via of metal (e.g., copper) 225 having a void 220 at its core. The top and bottom surfaces of the through-via are copper, and copper covers the insulated sidewalls of the through-via. However, a void filled with a gas such as air, an inert gas, or N2, or alternatively a vacuum, is disposed at the center of the through-via and provides an effective modulus which is more nearly matched to thesubstrate 224. The through-via becomes compliant when voided, resulting in a lower effective modulus and a lower effective Poisson ratio, and therefore exhibiting lower stresses and forces due to surrounding structures. The effective Poisson ratio here is defined as the ratio of out-of-plane displacement to in-plane displacement due to in-plane stress to reduce mechanical stresses encountered in processing and use. For a through-via material with high Poisson ratio of 0.4, the effective Poisson ratio can be reduced to about 0.22 with the introduction of a percolated network of through-voids with an effective radius of three quarters of the through-via radius when a through-void of radius of three quarters of the via radius is introduced in the through-via. Although it does not change the thermal expansion coefficient, the introduction of a void or voids reduces the effective modulus and Poisson ratio of the through-via, resulting in a compliant through-via that exerts much less stress and force on the surrounding structures. In other words it behaves on a whole as if it had a much smaller thermal expansion mismatch with the substrate, thereby reducing piston-like deviations at the top during thermal cycling. -
FIG. 5 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2B , in accordance with a second embodiment of the present invention. Atstep 500, blind vias are etched into the substrate, as above, to a depth which is slightly greater than the desired depth of the through-vias in the finished product. Atstep 502, the sidewalls of the blind vias are insulated (as above), preferably by oxidizing silicon to form a thin layer of SiO2 or PECVD oxide or nitride or both. An annular fill is conducted atstep 504 to provide metal (e.g., PVD TaN/Ta/Cu plus plated Cu to thickness ˜ 1/10 to ·⅕ of the via diameter) along the exposed insulated surfaces of the blind via. The top of the via is then capped with metal by either an overfilling, burnishing, or similar technique. The void in the center of the via will contain the ambient of the capping process, typically N2 or a vacuum. Overfilling is achieved by a PVD, CVD, evaporation, or sputtering process for metal deposition that will enclose and pinch off the via top. A polishing step may be needed to restore planarity. In the alternative, burnishing a conformally-plated blanket copper layer (which partially fills the through-via) with a blunt-tipped tool can also be used to smear the ductile copper from the wafer surface into and over the via hole, thus creating a sealed cavity within the via. The void will not introduce mechanical stress upon the substrate during subsequent processing or use. Thereafter, the top of the structure is planarized atstep 508 to remove excess metal at the top surface and to expose the substrate between the vias. The planarization step must leave the top via surfaces of metal disposed in the top surface of the substrate material. Fabrication of IC circuits or components, etc. on the top surface may be done at some point, as above. Finally, atstep 510, the bottom substrate surfaces are exposed to the backside processing steps to expose the blind vias and remove the excess substrate material and insulating layer and insulate the substrate bottom surface, as above. Care must be taken at both the top and bottom surfaces to leave metal across the entire via surface in order to preserve the void within. -
FIGS. 6A through 6F illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 5 . AtFIG. 6A , the blind vias are etched insubstrate 604. The insulatinglayer 603 is formed in the blind vias of the structure inFIG. 6B . Thereafter, the annular fill is conducted to providemetal 615 along the exposed insulated surfaces of the vias to yield the structure ofFIG. 6C . The sealing or burnishing step providesadditional metal 625 at the top surface of the vias, in conductive contact with themetal 615 and seals void 620 within, as shown inFIG. 6D . Planarization is done to remove the excess metal and expose thesubstrate 604 and metal vias at the top surface as shown inFIG. 6E . IC circuits or components may be fabricated on the top surface, as above. Finally, the bottom of the structure is exposed to the backside processing steps to remove the excess substrate material and insulating layer at the bottom of the vias, while leaving metal at the via bottom, as illustrated inFIG. 6F . - The structure of
FIG. 2C comprises asubstrate 234 in which the through-vias each comprise an annular ring of insulatingmaterial 233 within which is disposed concentric circles comprising conductive via metal (e.g., copper) 235, inner insulatingring 236, and acore post 230 of substrate material. This differs from the coaxial through-via of the aforementioned Gaul patent in that the center post here is an insulator or semiconductor and does not carry the electrical signal. The center post is not contacted by the IC circuitry on the top or on the bottom of the carrier. The post is effectively a hollow waveguide, and could even be used for optical conductance through the Si substrate. The inner core of substrate material will necessarily be a thermal and modulus match to the outer substrate material, thereby reducing the mechanical effects of the overall via structure on the substrate. -
FIG. 7 is a flow chart of a representative process flow for fabricating a carrier with through-vias, as shown inFIG. 2C , in accordance with a third embodiment of the present invention. Atstep 700, blind vias are etched into the substrate to a depth which is the desired depth of the through-vias in the finished product. The vias are etched in a pattern whereby each is an annular via of thickness ˜ 1/10 to ˜⅕ of the via diameter etched about a post of substrate material which will remain as the core of the via. Atstep 702, the sidewalls of the blind vias are insulated, preferably by oxidizing silicon to form a thin layer of SiO2 (see above) on both the outer sidewalls and the post sidewalls. The annular vias are then overfilled with the desired conductive material atstep 704. Thereafter, the top of the structure is planarized atstep 708 to remove excess metal at the top surface and to expose the substrate between the annular metal rings of the vias. IC circuits or components may be fabricated on top surface, as above. Finally, atstep 710, the bottom substrate surfaces are exposed to the backside processing steps to expose the blind vias and remove the excess substrate material and insulating layer. -
FIGS. 8A through 8E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 7 . AtFIG. 8A , the annular vias are etched insubstrate 804. The insulatinglayer 803 is formed on the sidewalls of the annular vias of the structure inFIG. 8B . Thereafter, the annular fill is conducted to providemetal 815 along the exposed insulated surfaces of the vias to completely fill the vias and yield the structure ofFIG. 8C . Planarization is done to remove the excess metal and expose thesubstrate 804 and annular metal vias at the top surface as shown inFIG. 8D . IC circuits or components may be built on top surface, as above, with care taken to contact the conductive annulus. Finally, the bottom of the structure is exposed to the backside processing steps to remove the excess substrate material and insulating layer at the bottom of the vias, as illustrated inFIG. 8E . - The structure of
FIG. 2D comprisessubstrate 244 having vias of metal-ceramic core 245 surrounded by an annularinsulating ring 243. The metal-ceramic is chosen to have a coefficient of thermal expansion which is closely matched to the CTE of the substrate material, as well as a modulus which is close to that of the substrate or which is less than that of the substrate, with enough porosity to decrease the effective modulus and Poisson ratio. Examples of suitable materials include a copper cordierite metal-ceramic, surrounded by an SiO2 or SiO2/Si3N4 insulating layer in a silicon substrate. Additional materials of interest would be other low CTE materials, such as, but not limited to, glass ceramic, beta-Eucryptite, Enstatite, Fosterite, millite, Zircon, and fused silica. Metals in addition to copper, such as gold and silver, would be suitable candidate conductors due to their excellent conductivities. Additionally, alloys of the above metals as well as solid solution alloys such as Cu—Ni are of interest. - Another example of a suitable fill material consists of fine particles of a low-CTE core material coated with a thin layer of linking metal such as copper. The low CTE core can consist of a wide range of materials from low CTE metals or alloys such as molybdenum, tungsten or Invar to nonmetals such as SiO2, silicon and silicon carbide. The coating material must consist of a metal for electrical conductivity, and should be able to form metallurgical joins at temperatures compatible with other structures already built on the wafer. Copper is a particularly desirable material because it is highly conducting and can form joins by Cu surface diffusion at temperatures considerably below its melting point. Other metals or alloys are also suitable such as thin layers of solder.
- Further, heterogeneous mixtures of particles with the same outer layer (joining metal) but with different cores, could be utilized to advantage. For instance a mixture of copper coated tungsten (Cu/W) could be mixed with copper coated SiO2 (Cu/SiO2). The combination would lower the average CTE compared to Cu/W alone (which is already low CTE relative to Cu alone) while maintaining enough Cu/W to ensure outstanding electrical conductivity as well as ensuring mechanical and electrical connectivity between all outer shells. In addition there may be advantages in some cases to mixing particles with dissimilar outer layers. For instance, two particle types could be coated with metals A and B, where a low melting AB eutectic could form upon contact and mild heating.
- Calculations suggest that a greater than 2000 Angstrom coating is desirable for high electrical conductivity if the outer layer alone were the only contributor to conductivity as would be the case of Cu coated SiO2. For particles with conducting cores, the thickness of the Cu outer layer should be as thin as possible to keep the net CTE low while maintaining good joining characteristics.
-
FIG. 9 is a representative flow chart for fabricating the structure ofFIG. 2D . Atstep 900 the blind vias are etched into the substrate. At step 902, an insulating layer is formed along the exposed surfaces of the blind vias, typically by exposing the structure to an oxidizing atmosphere or PECVD, etc. as above. Thereafter, the remaining via volume is filled with the metal-ceramic. As illustrated, a metal-ceramic paste may be spread in the insulated vias atstep 904, followed by a sintering step to cure the via fill. To remove excess paste overburden and particle residue a four stage cleaning method was developed including a first rinse step, a first coarse wiping step, a second fine wiping step, and a spin dry step. Details of an apparatus and method for applying paste into blind vias in a wafer are described in a separate patent application Ser. No. 10/700,327, entitled “Method and Apparatus for Filling Vias”, (YOR920030196US1), which was filed on Nov. 3, 2003, the teachings of which are herein incorporated by reference. A low-temperature bake (between 100° C. and 200° C.) in nitrogen or an inert ambient or vacuum may be used to drive off volatile components in the paste before high temperature sintering begins. This low temperature step may be tailored to allow controlled shrinkage of the paste compound, thus affording the possibility of using multiple filling steps to achieve a precise level of fill or a controlled recess. Multistep sintering between 400° C. and about 900° C. can be used in a variety of ambients (including nitrogen or steam ending with forming gas) to achieve complete burnout of any organic components at lower temperatures, and to achieve complete reduction of any oxide and good linking of metal particles at higher temperatures. This will result is a connected network of metal particles within a porous cordierite/glass phase. Planarization atstep 908 will remove any excess conductive material from the backside processing atstep 910 will expose the through-vias. -
FIGS. 10A through 10E illustrate the structures obtained at each step of processing a carrier with through-vias in accordance with the process flow ofFIG. 9 . AtFIG. 10A , the vias are etched insubstrate 1004. The insulatinglayer 1003 is formed on the sidewalls of the vias of the structure inFIG. 10B . Thereafter, the fill is conducted to provide metal-ceramic 1015 along the exposed insulated surfaces of the vias to completely fill the vias and yield the structure ofFIG. 10C . Planarization is done to remove the excess metal and expose thesubstrate 1004 and metal vias at the top surface as shown inFIG. 10D . IC circuits or components may be added as above. Special care must be taken to make electrical contact the top surface of the metal-ceramic filled through-vias. - Finally, the bottom of the structure is exposed to grinding and polishing and etching to remove the excess substrate material and then adding an insulating layer to the exposed silicon substrate and subsequently removing the insulator only over the raised via bottoms by selective polishing, as illustrated in
FIG. 10E . - An effective method for ensuring good electrical contact to the surface of a partially plated through-via is to etch a shallow, concentric collar of suitably larger diameter in
substrate 1104 around the top of the through-vias as shown inFIGS. 11A-11C . Such a structure adds a mask step, but greatly enhances the chances of achieving a good contact to subsequent levels of wiring as long as the collar depth is set to be no greater than the sidewall plating thickness. During final planarization, the collar effectively extends theannulus 1115 ofFIG. 11C outward, offering a larger capture surface on which to drop contact vias, while moving these contacts further away from the central area of the deep via, filled withconductive material 1110, where filling is most challenging. - The fill material and processing described above may be tailored to leave the filled vias with an intentionally porous internal structure and/or with a controlled recess between the surface of the fill material and the top of the via. An intentionally porous and/or recessed surface must be effectively capped and sealed before the via planarization step to enable subsequent processing of the substrate. A number of metals and deposition methods can be used to seal effectively seal and cap such vias, including but not limited to tungsten, tantalum, or copper. Deposition methods may include sputtering, plasma jet deposition, thermal or laser-assisted CVD, molten liquid, metal infiltration via capillary action, or bumping with solder. Cap thickness may vary between about 0.5 to 10 microns depending on the size of the surface pores and/or the depth of the recess. In the case of sputtered or jet-deposited copper, it is particularly useful to post-anneal the metal at a temperature above 500 C to assure good pore-sealing prior to final planarization. This anneal can be achieved using standard oven or hot plate anneals or using laser assisted localized heating of the cap metal.
- An alternative approach for metal capping of the filled porous via is the use of insulators. This is particularly practical with the partially plated vias where the electrical connection through the carrier is not counting on the via fill. Thus any number of high temperature (> or ˜400 C) stable insulating materials including but not limited to silicon dioxide, silicon nitride, silicon oxynitride, ceramics or high temperature polymers can be used. The inorganic material may be deposited using thermally activated or plasma-enhanced CVD, sputtering, or other such techniques known in the microelectronics field as well as plasma jet deposition. Co-Pending U.S. patent application Ser. No. ______, filed Oct. 17, 2003, entitled “Silicon Chip Carrier with Through-Vias Using Laser Assisted CVD of Conductor”, provides deposition teachings, which are herein incorporated by reference. Photolithography may be used to remove insulator from the field areas, leaving it only on the via surface to seal pores and/or fill any recess. Final surface planarization after capping is done using CMP to expose the partially plated via sidewall top surface, or planarizing to the level of desired insulator thickness for electrical connection of the overlying build to the deep via.
- High temperature polymers, including but not limited to polyimides or photosensitive polyimides (PSPI), may be spin applied from solution, laminated, or vapor deposited onto the surface of the
substrate 1204, as shown at 1220 ofFIGS. 12A-12C , having through-vias including insulative vialiner 1203, conductingmaterial 1215, and viafill 1210. With appropriate viscosity and surface tension properties the liquid polyimide precursor may not significantly penetrate into the porous via, thus largely preserving the thermal properties of said via. To aid in the removal of the excess polymer in the field area, the negatively or positively working PSPI is exposed and developed to remove the unwanted material,FIG. 12B . A touch-up polish can be applied to improve further the planarity of the surface. The electrical connection after insulator capping is done at the partially plated via sidewalls, or a conductive cap, shown as 1225 inFIG. 12C , can be deposited to connect electrically the via sidewalls. - All of the embodiments of the present invention provide conductive through-vias having effective CTEs and modulus values which are more closely matched to the CTE and modulus of the substrate materials than pure metal or metal compound vias. As well some have reduced Poisson ratios. Optimally, the finished supporting substrate has a thickness of 300 μm, with via aspect ratios of less than or equal to 4:1, such that the through-via diameter must be greater than or about equal to 75 μm.
- Once the supporting carrier has been fabricated, preferably of a thickness of at least 150 μm and ideally 350 μm in thickness, with through-vias filled with conductive material that is thermally matched and modulus matched, multiple devices can be mounted on both sides of the substrate. As illustrated in
FIGS. 13A and 13B , a system-on-chip 1300 can be realized by connecting multiple devices to the ultrahigh density package.Silicon carrier 1304 with metallized through-vias 1315, provides connection through intermediatemultilevel wiring layer 1306 forchips C4s 1325 on one side of the carrier and forchip 1360 on the other side of the carrier. Since the Si carrier is built from a semiconductor, it is possible to include all types of active and passive devices on the carrier, such as are conventionally built in integrated circuits. Multiple chips and discrete devices including, but not limited to, optical modulators, FET transistors, thin oxide trench or surface capacitors, varactors, logic or analog integrated circuits, resistors, inductors, transmission lines, can be mounted to the package. The multiple chips and discrete devices may be mounted in very close proximity (e.g., 5-10 μm) on one or both sides of the Si carrier. Mounting is done by conventional techniques.Dual heat spreaders - The silicon carrier preferably includes one or more levels of wiring, preferably Cu wiring at single μm dimensions for optimum density and bandwidth. The
wiring 1355 may be provided on one or both sides of the package, with connection through the through-vias if wiring is only formed on one side of the package. Dual-damascene processing for Cu wiring, as is well known in the art, may be used to form the wiring. Pitches for the wiring are preferably no greater than approximately 5 μm to allow parallel memory bussing between chips for terabit per second data processing. For a Si carrier with chips or chip stacks mounted on both sides, the external I/O would be provided near one or more edges of the Si carrier top or bottom surface, shown as 1365. For example, linear or staggered arrays of bonding pads along one or both surfaces could be bonded to a lead frame or wire bonded to the inner leads of a socket oredge connector 1365 which would ultimately mate to an outside socket on a printed circuit board. Ideally, the entire assembly is enclosed in a metal, plastic, ceramic, or other material package enclosure, illustratively shown as 1380, so that all of the electronics are enclosed, with the lead frame or edge connector leads being exposed and the outer surfaces of the heat spreaders remaining exposed for thermal contact with suitable mating structures or materials for external heat sinking. Heat fins (not shown) may additionally be provided at the assembly edge not occupied by the edge connector. - Single or multiple ultrahigh density system-on-
chip packages respective edge connectors 1465A-1465N and 1475A through 1475N to mating connectors on a printedcircuit board 1490, rack, backplane or the like, as shown inFIGS. 14A and 14B . Heat sink fins or other devices, shown illustratively as 1450D and 1450N, may be attached to the outside or outer edges of the ultrahigh density packages. As illustrated inFIG. 14B ,air 1492, orcoolant 1494, such as water, could be circulated through thecompartment 1490 to cool the packages, thereby extracting heat directly from the mounted chips inside the ultrahigh density package arrays. - In one embodiment, a complete ultrahigh performance computer system such as a PC or portable gaming system (e.g., 4 or more chips) could be packaged in an ultrahigh density package with an edge connector in such a manner as to comply with the “Compact Flash” format. In another preferred embodiment, an entire supercomputer node (CPU, memory communications interfaces) could be packaged in a similar Compact Flash format and plugged vertically into a PC board or backplane so that it is, itself, a heat-sink cooling fin. Alternatively, the supercomputer node could be bolted into a cold plate that has internal coolant circulation (need illustrations of the latter two). Multiple similar nodes would then be plugged into a PC board or backplane in close proximity to form a composite multi-node heat-sink structure populating the board or plane. An entire supercomputer could be constructed of the PC boards with similar ultrahigh density packing of ultrahigh density integrated nodes. In this manner, there is the potential for orders of magnitude increase in supercomputer power per unit volume of space.
- While the invention has been described with reference to several preferred embodiments, it should be understood that modifications can be made without departing from the spirit and scope of the invention as set forth in the appended claims.
Claims (53)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/242,221 US20060027934A1 (en) | 2003-12-05 | 2005-10-03 | Silicon chip carrier with conductive through-vias and method for fabricating same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/729,254 US7276787B2 (en) | 2003-12-05 | 2003-12-05 | Silicon chip carrier with conductive through-vias and method for fabricating same |
US11/242,221 US20060027934A1 (en) | 2003-12-05 | 2005-10-03 | Silicon chip carrier with conductive through-vias and method for fabricating same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/729,254 Continuation-In-Part US7276787B2 (en) | 2003-12-05 | 2003-12-05 | Silicon chip carrier with conductive through-vias and method for fabricating same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060027934A1 true US20060027934A1 (en) | 2006-02-09 |
Family
ID=34633899
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/729,254 Expired - Fee Related US7276787B2 (en) | 2003-12-05 | 2003-12-05 | Silicon chip carrier with conductive through-vias and method for fabricating same |
US11/242,221 Abandoned US20060027934A1 (en) | 2003-12-05 | 2005-10-03 | Silicon chip carrier with conductive through-vias and method for fabricating same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/729,254 Expired - Fee Related US7276787B2 (en) | 2003-12-05 | 2003-12-05 | Silicon chip carrier with conductive through-vias and method for fabricating same |
Country Status (2)
Country | Link |
---|---|
US (2) | US7276787B2 (en) |
CN (1) | CN100456467C (en) |
Cited By (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050248002A1 (en) * | 2004-05-07 | 2005-11-10 | Michael Newman | Fill for large volume vias |
US20060049335A1 (en) * | 2004-09-09 | 2006-03-09 | Toyoda Gosei Co., Ltd. | Solid state device and light-emitting element |
US20060275946A1 (en) * | 2005-05-04 | 2006-12-07 | Icemos Technology Corporation | Silicon Wafer Having Through-Wafer Vias |
US20070032077A1 (en) * | 2005-08-08 | 2007-02-08 | Tzung-Yu Hung | Method of manufacturing metal plug and contact |
US20070085117A1 (en) * | 2005-10-11 | 2007-04-19 | Icemos Technology Corporation | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US20070111356A1 (en) * | 2005-10-28 | 2007-05-17 | Icemos Technology Corporation | Front Lit PIN/NIP Diode Having a Continuous Anode/Cathode |
US20070138588A1 (en) * | 2005-12-16 | 2007-06-21 | Icemos Technology Corporation | Backlit Photodiode and Method of Manufacturing a Backlit Photodiode |
US20070205478A1 (en) * | 2006-03-02 | 2007-09-06 | Icemos Technology Corporation | Photodiode having increased proportion of light-sensitive area to light-insensitive area |
US20070246821A1 (en) * | 2006-04-20 | 2007-10-25 | Lu Szu W | Utra-thin substrate package technology |
US20070281471A1 (en) * | 2006-06-01 | 2007-12-06 | Dror Hurwitz | Advanced Multilayered Coreless Support Structures and their Fabrication |
US20080036061A1 (en) * | 2006-08-11 | 2008-02-14 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
US20080057691A1 (en) * | 2006-08-29 | 2008-03-06 | Dando Ross S | Methods and systems for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum |
US20080073752A1 (en) * | 2006-09-27 | 2008-03-27 | Nec Electronics Corporation | Semiconductor apparatus |
US20080099870A1 (en) * | 2006-08-10 | 2008-05-01 | Icemos Technology Corporation | Method of manufacturing a photodiode array with through-wafer vias |
US20080099924A1 (en) * | 2005-05-04 | 2008-05-01 | Icemos Technology Corporation | Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape |
US20080119046A1 (en) * | 2006-11-21 | 2008-05-22 | Sparks Terry G | Method of making a contact on a backside of a die |
US20080122040A1 (en) * | 2006-06-29 | 2008-05-29 | Icemos Technology Corporation | Varying Pitch Adapter and a Method of Forming a Varying Pitch Adapter |
US20080138987A1 (en) * | 2004-11-26 | 2008-06-12 | Applied Materials, Inc. | Edge removal of silicon-on-insulator transfer wafer |
US20080137318A1 (en) * | 2006-12-08 | 2008-06-12 | Sudarshan Rangaraj | Compliant structure for an electronic device, method of manufacturing same, and system containing same |
US20080182362A1 (en) * | 2006-03-21 | 2008-07-31 | Paul Stephen Andry | Method for precision assembly of integrated circuit chip packages |
US20080217748A1 (en) * | 2007-03-08 | 2008-09-11 | International Business Machines Corporation | Low cost and low coefficient of thermal expansion packaging structures and processes |
US20080290525A1 (en) * | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
US20080303031A1 (en) * | 2007-06-07 | 2008-12-11 | United Test And Assembly Center Ltd. | Vented die and package |
US20090001598A1 (en) * | 2007-06-27 | 2009-01-01 | Wen-Chih Chiou | Formation of Through Via before Contact Processing |
US20090072374A1 (en) * | 2007-09-17 | 2009-03-19 | Stephan Dobritz | Electric Device, Stack of Electric Devices, and Method of Manufacturing a Stack of Electric Devices |
US20090079059A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Integrated semiconductor substrate structure using incompatible processes |
US20090079056A1 (en) * | 2007-09-25 | 2009-03-26 | Rti International | Large substrate structural vias |
US20090283871A1 (en) * | 2008-05-14 | 2009-11-19 | Hung-Pin Chang | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack |
US20090321861A1 (en) * | 2008-06-26 | 2009-12-31 | Micron Technology, Inc. | Microelectronic imagers with stacked lens assemblies and processes for wafer-level packaging of microelectronic imagers |
US20100078777A1 (en) * | 2008-09-30 | 2010-04-01 | Hans-Joachim Barth | On-Chip Radio Frequency Shield with Interconnect Metallization |
US20100078771A1 (en) * | 2008-09-30 | 2010-04-01 | Hans-Joachim Barth | On-Chip RF Shields with Through Substrate Conductors |
US20100187665A1 (en) * | 2009-01-26 | 2010-07-29 | Sixis, Inc. | Integral metal structure with conductive post portions |
US20100267217A1 (en) * | 2009-04-20 | 2010-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside Process for a Substrate |
US20100301477A1 (en) * | 2006-07-26 | 2010-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-Based Thin Substrate and Packaging Schemes |
US20110042820A1 (en) * | 2009-08-18 | 2011-02-24 | International Business Machines Corporation | 3d silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
US20110074040A1 (en) * | 2009-09-29 | 2011-03-31 | Manfred Frank | Semiconductor Device And Method For Making Same |
US20110097853A1 (en) * | 2009-10-28 | 2011-04-28 | Electronics And Telecommunications Research Institute | Via forming method and method of manufacturing multi-chip package using the same |
US20110201175A1 (en) * | 2008-09-30 | 2011-08-18 | Hans-Joachim Barth | System on a Chip with On-Chip RF Shield |
US8012796B2 (en) | 2007-05-15 | 2011-09-06 | International Business Machines Corporation | Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers |
US20110266674A1 (en) * | 2010-04-28 | 2011-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser Etch Via Formation |
US20120251783A1 (en) * | 2011-04-01 | 2012-10-04 | Seiko Epson Corporation | Base surface processing method and mems device |
US20120273926A1 (en) * | 2011-04-30 | 2012-11-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die |
US20120314384A1 (en) * | 2011-06-09 | 2012-12-13 | Tessera, Inc. | Low-stress tsv design using conductive particles |
US20130015585A1 (en) * | 2011-07-12 | 2013-01-17 | Valentin Kosenko | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US8456017B2 (en) * | 2011-04-27 | 2013-06-04 | Industrial Technology Research Institute | Filled through-silicon via with conductive composite material |
US20130319738A1 (en) * | 2012-05-30 | 2013-12-05 | Dror Hurwitz | Multilayer electronic structure with through thickness coaxial structures |
US8617929B2 (en) | 2008-09-30 | 2013-12-31 | Infineon Technologies Ag | On-Chip RF shields with front side redistribution lines |
US20140070423A1 (en) * | 2012-09-13 | 2014-03-13 | Invensas Corporation | Tunable composite interposer |
US8889548B2 (en) | 2008-09-30 | 2014-11-18 | Infineon Technologies Ag | On-chip RF shields with backside redistribution lines |
US20150130077A1 (en) * | 2010-09-17 | 2015-05-14 | Tessera, Inc. | Staged via formation from both sides of chip |
KR20150092182A (en) * | 2012-12-04 | 2015-08-12 | 엘타 시스템즈 리미티드 | An integrated electronic device including an interposer structure and a method for fabricating the same |
US9238593B2 (en) * | 2010-07-14 | 2016-01-19 | Nhk Spring Co., Ltd. | Ceramic member, probe holder, and manufacturing method of ceramic member |
US20160359044A1 (en) * | 2015-06-04 | 2016-12-08 | International Business Machines Corporation | FORMATION OF DISLOCATION-FREE SiGe FINFET USING POROUS SILICON |
US9589879B2 (en) | 2011-03-07 | 2017-03-07 | Invensas Corporation | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates |
US9659844B2 (en) * | 2015-08-31 | 2017-05-23 | Texas Instruments Incorporated | Semiconductor die substrate with integral heat sink |
Families Citing this family (190)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7831151B2 (en) | 2001-06-29 | 2010-11-09 | John Trezza | Redundant optical device array |
US7397067B2 (en) | 2003-12-31 | 2008-07-08 | Intel Corporation | Microdisplay packaging system |
US7202154B2 (en) * | 2004-01-05 | 2007-04-10 | International Business Machines Corporation | Suspension for filling via holes in silicon and method for making the same |
JP4179186B2 (en) * | 2004-02-25 | 2008-11-12 | ソニー株式会社 | WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE |
US7105918B2 (en) * | 2004-07-29 | 2006-09-12 | Micron Technology, Inc. | Interposer with flexible solder pad elements and methods of manufacturing the same |
JP4387269B2 (en) * | 2004-08-23 | 2009-12-16 | 株式会社テクニスコ | Glass substrate with vias and method for forming vias |
US7109068B2 (en) * | 2004-08-31 | 2006-09-19 | Micron Technology, Inc. | Through-substrate interconnect fabrication methods |
TWI254425B (en) * | 2004-10-26 | 2006-05-01 | Advanced Semiconductor Eng | Chip package structure, chip packaging process, chip carrier and manufacturing process thereof |
JP4795677B2 (en) * | 2004-12-02 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | Semiconductor device, semiconductor module using the same, and manufacturing method of semiconductor device |
JP4502820B2 (en) * | 2005-01-05 | 2010-07-14 | 日本電気株式会社 | Semiconductor chip and semiconductor device |
US8456015B2 (en) * | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US7521806B2 (en) * | 2005-06-14 | 2009-04-21 | John Trezza | Chip spanning connection |
US7534722B2 (en) * | 2005-06-14 | 2009-05-19 | John Trezza | Back-to-front via process |
US7786592B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US7781886B2 (en) * | 2005-06-14 | 2010-08-24 | John Trezza | Electronic chip contact structure |
US7838997B2 (en) | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US20060278996A1 (en) * | 2005-06-14 | 2006-12-14 | John Trezza | Active packaging |
US7215032B2 (en) | 2005-06-14 | 2007-05-08 | Cubic Wafer, Inc. | Triaxial through-chip connection |
US7482272B2 (en) | 2005-06-14 | 2009-01-27 | John Trezza | Through chip connection |
US7687400B2 (en) | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7560813B2 (en) * | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
WO2006138424A2 (en) * | 2005-06-14 | 2006-12-28 | Cubic Wafer, Inc. | Through chip connection |
US7402515B2 (en) * | 2005-06-28 | 2008-07-22 | Intel Corporation | Method of forming through-silicon vias with stress buffer collars and resulting devices |
US7528006B2 (en) * | 2005-06-30 | 2009-05-05 | Intel Corporation | Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion |
US9601474B2 (en) * | 2005-07-22 | 2017-03-21 | Invensas Corporation | Electrically stackable semiconductor wafer and chip packages |
US7429529B2 (en) | 2005-08-05 | 2008-09-30 | Farnworth Warren M | Methods of forming through-wafer interconnects and structures resulting therefrom |
DE102005039068A1 (en) * | 2005-08-11 | 2007-02-15 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Semiconductor substrate and method of manufacture |
CN100559574C (en) * | 2005-08-26 | 2009-11-11 | 皇家飞利浦电子股份有限公司 | Electric screen through-wafer interconnect and its manufacture method and detecting element and checkout equipment |
US7488680B2 (en) * | 2005-08-30 | 2009-02-10 | International Business Machines Corporation | Conductive through via process for electronic device carriers |
US7517798B2 (en) * | 2005-09-01 | 2009-04-14 | Micron Technology, Inc. | Methods for forming through-wafer interconnects and structures resulting therefrom |
JP4609317B2 (en) * | 2005-12-28 | 2011-01-12 | カシオ計算機株式会社 | Circuit board |
US7626257B2 (en) * | 2006-01-18 | 2009-12-01 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US9312217B2 (en) * | 2006-02-01 | 2016-04-12 | Silex Microsystems Ab | Methods for making a starting substrate wafer for semiconductor engineering having wafer through connections |
JP5431918B2 (en) * | 2006-03-27 | 2014-03-05 | コーニンクレッカ フィリップス エヌ ヴェ | Low resistance through-substrate interconnects for semiconductor carriers |
US7687397B2 (en) | 2006-06-06 | 2010-03-30 | John Trezza | Front-end processed wafer having through-chip connections |
US20080067665A1 (en) * | 2006-09-20 | 2008-03-20 | Azniza Binti Abd Aziz | Via structure |
CN101553903B (en) * | 2006-10-17 | 2012-08-29 | 丘费尔资产股份有限公司 | Wafer via formation |
US7705613B2 (en) * | 2007-01-03 | 2010-04-27 | Abhay Misra | Sensitivity capacitive sensor |
US7803693B2 (en) * | 2007-02-15 | 2010-09-28 | John Trezza | Bowed wafer hybridization compensation |
US7598163B2 (en) * | 2007-02-15 | 2009-10-06 | John Callahan | Post-seed deposition process |
US7705632B2 (en) * | 2007-02-15 | 2010-04-27 | Wyman Theodore J Ted | Variable off-chip drive |
US7670874B2 (en) * | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
US7747223B2 (en) * | 2007-03-29 | 2010-06-29 | Research In Motion Limited | Method, system and mobile device for prioritizing a discovered device list |
US7850060B2 (en) * | 2007-04-05 | 2010-12-14 | John Trezza | Heat cycle-able connection |
US7748116B2 (en) * | 2007-04-05 | 2010-07-06 | John Trezza | Mobile binding in an electronic connection |
US20080261392A1 (en) * | 2007-04-23 | 2008-10-23 | John Trezza | Conductive via formation |
US7960210B2 (en) | 2007-04-23 | 2011-06-14 | Cufer Asset Ltd. L.L.C. | Ultra-thin chip packaging |
KR100856293B1 (en) * | 2007-05-04 | 2008-09-03 | 삼성전기주식회사 | A crystal device fabrication method |
US7553752B2 (en) * | 2007-06-20 | 2009-06-30 | Stats Chippac, Ltd. | Method of making a wafer level integration package |
DE102007039754A1 (en) * | 2007-06-22 | 2008-12-24 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Process for the production of substrates |
JP2009021462A (en) * | 2007-07-13 | 2009-01-29 | Disco Abrasive Syst Ltd | Method for processing wafer |
TWI357118B (en) * | 2007-08-02 | 2012-01-21 | Advanced Semiconductor Eng | Method for forming vias in a substrate |
US7902069B2 (en) * | 2007-08-02 | 2011-03-08 | International Business Machines Corporation | Small area, robust silicon via structure and process |
TWI387019B (en) * | 2007-08-02 | 2013-02-21 | Advanced Semiconductor Eng | Method for forming vias in a substrate |
US8546255B2 (en) * | 2007-08-02 | 2013-10-01 | Advanced Semiconductor Engineering, Inc. | Method for forming vias in a semiconductor substrate and a semiconductor device having the semiconductor substrate |
US7892885B2 (en) * | 2007-10-30 | 2011-02-22 | International Business Machines Corporation | Techniques for modular chip fabrication |
US7741153B2 (en) * | 2007-10-30 | 2010-06-22 | International Business Machines Corporation | Modular chip integration techniques |
US7767486B2 (en) * | 2007-11-21 | 2010-08-03 | Intel Corporation | High-volume on-wafer heterogeneous packaging of optical interconnects |
TWI365483B (en) * | 2007-12-04 | 2012-06-01 | Advanced Semiconductor Eng | Method for forming a via in a substrate |
US8242382B2 (en) * | 2008-01-30 | 2012-08-14 | Innovent Technologies, Llc | Method and apparatus for manufacture of via disk |
US7898063B2 (en) * | 2008-02-16 | 2011-03-01 | International Business Machines Corporation | Through substrate annular via including plug filler |
US8409901B2 (en) | 2008-03-11 | 2013-04-02 | The Royal Institution For The Advancement Of Learning/Mcgill University | Low temperature wafer level processing for MEMS devices |
US20110101531A1 (en) * | 2008-05-30 | 2011-05-05 | Nxp B.V. | Thermo-mechanical stress in semiconductor wafers |
US7772123B2 (en) * | 2008-06-06 | 2010-08-10 | Infineon Technologies Ag | Through substrate via semiconductor components |
US8384224B2 (en) | 2008-08-08 | 2013-02-26 | International Business Machines Corporation | Through wafer vias and method of making same |
US8035198B2 (en) * | 2008-08-08 | 2011-10-11 | International Business Machines Corporation | Through wafer via and method of making same |
US8138036B2 (en) * | 2008-08-08 | 2012-03-20 | International Business Machines Corporation | Through silicon via and method of fabricating same |
US8299566B2 (en) * | 2008-08-08 | 2012-10-30 | International Business Machines Corporation | Through wafer vias and method of making same |
US8097525B2 (en) * | 2008-08-29 | 2012-01-17 | International Business Machines Corporation | Vertical through-silicon via for a semiconductor structure |
US8030780B2 (en) * | 2008-10-16 | 2011-10-04 | Micron Technology, Inc. | Semiconductor substrates with unitary vias and via terminals, and associated systems and methods |
US7893529B2 (en) * | 2009-01-12 | 2011-02-22 | International Business Machines Corporation | Thermoelectric 3D cooling |
TWI387084B (en) * | 2009-01-23 | 2013-02-21 | Advanced Semiconductor Eng | Substrate having vias and package having the same |
JP5330115B2 (en) * | 2009-06-17 | 2013-10-30 | 浜松ホトニクス株式会社 | Multilayer wiring board |
US8471156B2 (en) * | 2009-08-28 | 2013-06-25 | Advanced Semiconductor Engineering, Inc. | Method for forming a via in a substrate and substrate with a via |
FR2951017A1 (en) * | 2009-10-05 | 2011-04-08 | St Microelectronics Crolles 2 | ELECTRICAL CONNECTION VIA FOR SEMICONDUCTOR DEVICE SUBSTRATE |
FR2951018A1 (en) * | 2009-10-05 | 2011-04-08 | St Microelectronics Crolles 2 | ELECTRICAL CONNECTION VIA FOR SEMICONDUCTOR DEVICE SUBSTRATE |
US8242604B2 (en) * | 2009-10-28 | 2012-08-14 | International Business Machines Corporation | Coaxial through-silicon via |
US8492901B2 (en) * | 2009-11-06 | 2013-07-23 | International Business Machines Corporation | Metal oxide semiconductor (MOS)-compatible high-aspect ratio through-wafer vias and low-stress configuration thereof |
TWI392069B (en) * | 2009-11-24 | 2013-04-01 | Advanced Semiconductor Eng | Package structure and packaging process thereof |
US8354736B2 (en) * | 2010-01-14 | 2013-01-15 | Synopsys, Inc. | Reclaiming usable integrated circuit chip area near through-silicon vias |
US20110204517A1 (en) * | 2010-02-23 | 2011-08-25 | Qualcomm Incorporated | Semiconductor Device with Vias Having More Than One Material |
WO2011109648A1 (en) * | 2010-03-03 | 2011-09-09 | Georgia Tech Research Corporation | Through-package-via (tpv) structures on inorganic interposer and methods for fabricating same |
US20110291287A1 (en) * | 2010-05-25 | 2011-12-01 | Xilinx, Inc. | Through-silicon vias with low parasitic capacitance |
US8232648B2 (en) | 2010-06-01 | 2012-07-31 | International Business Machines Corporation | Semiconductor article having a through silicon via and guard ring |
TW201200853A (en) * | 2010-06-18 | 2012-01-01 | Ind Tech Res Inst | Measuring apparatus |
DE102010030760B4 (en) * | 2010-06-30 | 2014-07-24 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Semiconductor device with via contacts with a stress relaxation mechanism and method of making the same |
US8598695B2 (en) * | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
TWI446420B (en) | 2010-08-27 | 2014-07-21 | Advanced Semiconductor Eng | Releasing carrier method for semiconductor process |
TWI445152B (en) | 2010-08-30 | 2014-07-11 | Advanced Semiconductor Eng | Semiconductor structure and method for manufacturing the same |
US9007273B2 (en) | 2010-09-09 | 2015-04-14 | Advances Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US8349735B2 (en) | 2010-09-22 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive TSV with insulating annular ring |
TWI434387B (en) | 2010-10-11 | 2014-04-11 | Advanced Semiconductor Eng | Semiconductor element having a via and package having a semiconductor element with a via and method for making the same |
US8912658B2 (en) * | 2010-10-29 | 2014-12-16 | International Business Machines Corporation | Interconnect structure with enhanced reliability |
TWI527174B (en) * | 2010-11-19 | 2016-03-21 | 日月光半導體製造股份有限公司 | Package having semiconductor device |
US9142665B2 (en) | 2010-12-10 | 2015-09-22 | Infineon Technologies Austria Ag | Semiconductor component with a semiconductor via |
US9396997B2 (en) * | 2010-12-10 | 2016-07-19 | Infineon Technologies Ag | Method for producing a semiconductor component with insulated semiconductor mesas |
US8742535B2 (en) | 2010-12-16 | 2014-06-03 | Lsi Corporation | Integration of shallow trench isolation and through-substrate vias into integrated circuit designs |
US8987137B2 (en) | 2010-12-16 | 2015-03-24 | Lsi Corporation | Method of fabrication of through-substrate vias |
TWI445155B (en) | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | Stacked semiconductor package and method for making the same |
US8853819B2 (en) | 2011-01-07 | 2014-10-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor structure with passive element network and manufacturing method thereof |
TWI459520B (en) * | 2011-01-31 | 2014-11-01 | Xintec Inc | Interposer and method for forming the same |
WO2012115333A1 (en) * | 2011-02-24 | 2012-08-30 | 단국대학교 산학협력단 | Substrate having penetrating structure and manufacturing method thereof, package device including substrate having penetrating structure and manufacturing method thereof |
US20120319293A1 (en) * | 2011-06-17 | 2012-12-20 | Bok Eng Cheah | Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package |
US8487425B2 (en) | 2011-06-23 | 2013-07-16 | International Business Machines Corporation | Optimized annular copper TSV |
US8816505B2 (en) * | 2011-07-29 | 2014-08-26 | Tessera, Inc. | Low stress vias |
US20130062736A1 (en) * | 2011-09-09 | 2013-03-14 | Texas Instruments Incorporated | Post-polymer revealing of through-substrate via tips |
US9147609B2 (en) * | 2011-10-07 | 2015-09-29 | Newport Fab, Llc | Through silicon via structure, method of formation, and integration in semiconductor substrate |
KR101959284B1 (en) * | 2011-11-18 | 2019-03-19 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
US8541883B2 (en) | 2011-11-29 | 2013-09-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having shielded conductive vias |
US8975157B2 (en) | 2012-02-08 | 2015-03-10 | Advanced Semiconductor Engineering, Inc. | Carrier bonding and detaching processes for a semiconductor wafer |
US8963316B2 (en) | 2012-02-15 | 2015-02-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and method for manufacturing the same |
JP5722814B2 (en) * | 2012-03-06 | 2015-05-27 | 日本電信電話株式会社 | Manufacturing method of semiconductor device |
US8786060B2 (en) | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
TW201405737A (en) * | 2012-05-25 | 2014-02-01 | Applied Materials Inc | Polymer hot-wire chemical vapor deposition in chip scale packaging |
US8772946B2 (en) * | 2012-06-08 | 2014-07-08 | Invensas Corporation | Reduced stress TSV and interposer structures |
DE102012209620B4 (en) * | 2012-06-08 | 2023-01-19 | Robert Bosch Gmbh | Method for manufacturing a sensor carrier, sensor carrier and sensor |
US9153542B2 (en) | 2012-08-01 | 2015-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having an antenna and manufacturing method thereof |
US8937387B2 (en) | 2012-11-07 | 2015-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor device with conductive vias |
US8952542B2 (en) | 2012-11-14 | 2015-02-10 | Advanced Semiconductor Engineering, Inc. | Method for dicing a semiconductor wafer having through silicon vias and resultant structures |
US9406552B2 (en) | 2012-12-20 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having conductive via and manufacturing process |
US8916979B2 (en) | 2012-12-28 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-vias and methods of forming the same |
US8841751B2 (en) | 2013-01-23 | 2014-09-23 | Advanced Semiconductor Engineering, Inc. | Through silicon vias for semiconductor devices and manufacturing method thereof |
CN103985666A (en) * | 2013-02-07 | 2014-08-13 | 中芯国际集成电路制造(上海)有限公司 | Annular silicon deep hole and method for preparing annular silicon deep hole electrode |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US8802504B1 (en) | 2013-03-14 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9978688B2 (en) | 2013-02-28 | 2018-05-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a waveguide antenna and manufacturing method thereof |
US9089268B2 (en) | 2013-03-13 | 2015-07-28 | Advanced Semiconductor Engineering, Inc. | Neural sensing device and method for making the same |
US8998509B2 (en) * | 2013-03-14 | 2015-04-07 | Oracle International Corporation | Stackable photonic interconnect module |
US8987734B2 (en) | 2013-03-15 | 2015-03-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor wafer, semiconductor process and semiconductor package |
US9173583B2 (en) | 2013-03-15 | 2015-11-03 | Advanced Semiconductor Engineering, Inc. | Neural sensing device and method for making the same |
US9245824B2 (en) * | 2013-04-18 | 2016-01-26 | Globalfoundries Inc. | Through-vias for wiring layers of semiconductor devices |
CN103258790A (en) * | 2013-04-27 | 2013-08-21 | 江阴长电先进封装有限公司 | Method for revealing inner metal of silicon through holes |
US9099442B2 (en) | 2013-08-05 | 2015-08-04 | Micron Technology, Inc. | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods |
US9666521B2 (en) * | 2013-08-08 | 2017-05-30 | Invensas Corporation | Ultra high performance interposer |
US9082781B2 (en) | 2013-10-03 | 2015-07-14 | International Business Machines Corporation | Semiconductor article having a zig-zag guard ring and method of forming the same |
US9478491B1 (en) * | 2014-01-31 | 2016-10-25 | Altera Corporation | Integrated circuit package substrate with openings surrounding a conductive via |
US10847442B2 (en) * | 2014-02-24 | 2020-11-24 | Micron Technology, Inc. | Interconnect assemblies with through-silicon vias and stress-relief features |
JP6269175B2 (en) * | 2014-03-05 | 2018-01-31 | 株式会社デンソー | Manufacturing method of semiconductor device |
US9123738B1 (en) * | 2014-05-16 | 2015-09-01 | Xilinx, Inc. | Transmission line via structure |
KR101650938B1 (en) * | 2014-09-25 | 2016-08-24 | 코닝정밀소재 주식회사 | Substrate for ic package |
US9324613B2 (en) * | 2014-09-29 | 2016-04-26 | Innovative Micro Technology | Method for forming through substrate vias with tethers |
JP6539992B2 (en) * | 2014-11-14 | 2019-07-10 | 凸版印刷株式会社 | Printed circuit board, semiconductor device, method of manufacturing wired circuit board, method of manufacturing semiconductor device |
JP6390404B2 (en) * | 2014-12-15 | 2018-09-19 | 富士通株式会社 | Electronic device and method of manufacturing electronic device |
US9318376B1 (en) | 2014-12-15 | 2016-04-19 | Freescale Semiconductor, Inc. | Through substrate via with diffused conductive component |
US9907190B1 (en) * | 2015-02-03 | 2018-02-27 | Amazon Technologies, Inc. | Composite structures and methods of making |
US9401323B1 (en) | 2015-04-03 | 2016-07-26 | International Business Machines Corporation | Protected through semiconductor via (TSV) |
KR101644266B1 (en) * | 2015-04-08 | 2016-07-29 | 주식회사 스탠딩에그 | Method of manufacturing cap substrate, method of manufacturing mems device using the same, and mems device |
US9812354B2 (en) * | 2015-05-15 | 2017-11-07 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a material defining a void |
JP6509635B2 (en) | 2015-05-29 | 2019-05-08 | 東芝メモリ株式会社 | Semiconductor device and method of manufacturing semiconductor device |
US9812359B2 (en) | 2015-06-08 | 2017-11-07 | Globalfoundries Inc. | Thru-silicon-via structures |
US10504821B2 (en) * | 2016-01-29 | 2019-12-10 | United Microelectronics Corp. | Through-silicon via structure |
US9807867B2 (en) | 2016-02-04 | 2017-10-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method of manufacturing the same |
TWI601259B (en) * | 2016-02-24 | 2017-10-01 | 矽品精密工業股份有限公司 | Electronic package, semiconductor substrate of the electronic package, and method for manufacturing the electronic package |
JP7011148B2 (en) * | 2016-04-01 | 2022-01-26 | 日亜化学工業株式会社 | A method for manufacturing a light emitting element mounting substrate and a method for manufacturing a light emitting device using the same, and a light emitting element mounting substrate and a light emitting device using the same. |
TWI680535B (en) * | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | Oxidative volumetric expansion of metals and metal containing compounds |
EP3290399B1 (en) * | 2016-08-29 | 2022-03-02 | Infineon Technologies AG | Method for producing a metal-ceramic substrate with a least one via |
TWI719262B (en) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | Deposition and treatment of films for patterning |
CN109923662A (en) | 2016-11-08 | 2019-06-21 | 应用材料公司 | For patterning the geometry control of the bottom-up column of application |
DE102016124646A1 (en) * | 2016-12-16 | 2018-06-21 | Osram Opto Semiconductors Gmbh | Method for producing a semiconductor component |
WO2018156710A1 (en) | 2017-02-22 | 2018-08-30 | Applied Materials, Inc. | Critical dimension control for self-aligned contact patterning |
US10636659B2 (en) | 2017-04-25 | 2020-04-28 | Applied Materials, Inc. | Selective deposition for simplified process flow of pillar formation |
US10840186B2 (en) | 2017-06-10 | 2020-11-17 | Applied Materials, Inc. | Methods of forming self-aligned vias and air gaps |
TW201906035A (en) | 2017-06-24 | 2019-02-01 | 美商微材料有限責任公司 | Method of producing fully self-aligned vias and contacts |
US10510602B2 (en) | 2017-08-31 | 2019-12-17 | Mirocmaterials LLC | Methods of producing self-aligned vias |
US10573555B2 (en) | 2017-08-31 | 2020-02-25 | Micromaterials Llc | Methods of producing self-aligned grown via |
WO2019050735A1 (en) | 2017-09-06 | 2019-03-14 | Micromaterials Llc | Methods of producing self-aligned vias |
JP2019106538A (en) | 2017-12-07 | 2019-06-27 | マイクロマテリアルズ エルエルシー | Methods for controllable metal and barrier-liner recess |
EP3499557A1 (en) | 2017-12-15 | 2019-06-19 | Micromaterials LLC | Selectively etched self-aligned via processes |
IT201800000947A1 (en) * | 2018-01-15 | 2019-07-15 | St Microelectronics Srl | SEMICONDUCTOR PLATE WITH BURIED CONDENSER, AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PLATE |
KR20190104902A (en) | 2018-03-02 | 2019-09-11 | 마이크로머티어리얼즈 엘엘씨 | Methods for removing metal oxides |
CN108538811A (en) * | 2018-03-20 | 2018-09-14 | 杭州电子科技大学 | With the low stopping area differential transfer structure and its interlayer interconnection structure of silicon hole |
FR3080709B1 (en) * | 2018-04-26 | 2023-01-20 | St Microelectronics Grenoble 2 | VIA DRIVERS |
TW202002219A (en) | 2018-05-08 | 2020-01-01 | 美商微材料有限責任公司 | Selective removal process to create high aspect ratio fully self-aligned via |
TW202011547A (en) | 2018-05-16 | 2020-03-16 | 美商微材料有限責任公司 | A method for creating a fully self-aligned via |
US10699953B2 (en) | 2018-06-08 | 2020-06-30 | Micromaterials Llc | Method for creating a fully self-aligned via |
US10707151B2 (en) * | 2018-11-20 | 2020-07-07 | Nanya Technology Corporation | Through silicon via structure and method for manufacturing the same |
CN111508926B (en) | 2019-01-31 | 2022-08-30 | 奥特斯(中国)有限公司 | Component carrier and method for producing a component carrier |
CN109860143B (en) * | 2019-02-27 | 2022-01-14 | 京东方科技集团股份有限公司 | Array substrate, display device, preparation method and splicing display device |
US11164938B2 (en) | 2019-03-26 | 2021-11-02 | Micromaterials Llc | DRAM capacitor module |
JP7302318B2 (en) * | 2019-06-13 | 2023-07-04 | セイコーエプソン株式会社 | Wiring board, wiring board manufacturing method, inkjet head, MEMS device, and oscillator |
CN110391178B (en) * | 2019-07-30 | 2021-09-24 | 河南机电职业学院 | Method for penetrating and filling through hole by jet flow |
US10896848B1 (en) * | 2019-10-15 | 2021-01-19 | Nanya Technology Corporation | Method of manufacturing a semiconductor device |
US11659660B2 (en) | 2019-11-01 | 2023-05-23 | Raytheon Company | Oxide liner stress buffer |
CN111081666A (en) * | 2019-12-12 | 2020-04-28 | 联合微电子中心有限责任公司 | TSV structure capable of reducing thermal stress and forming method thereof |
US11587881B2 (en) * | 2020-03-09 | 2023-02-21 | Advanced Semiconductor Engineering, Inc. | Substrate structure including embedded semiconductor device |
CN111816608B (en) * | 2020-07-09 | 2023-05-09 | 电子科技大学 | Glass blind hole processing method |
CN114361131A (en) * | 2020-10-13 | 2022-04-15 | 长鑫存储技术有限公司 | Conductive structure, semiconductor structure and manufacturing method thereof |
CN112599491A (en) * | 2020-12-15 | 2021-04-02 | 西安电子科技大学 | Silicon substrate based on low thermal stress through silicon via |
CN117153780B (en) * | 2023-10-26 | 2024-01-30 | 甬矽电子(宁波)股份有限公司 | Method for producing a through-silicon-via structure and through-silicon-via structure |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3838381B2 (en) * | 1995-11-22 | 2006-10-25 | 株式会社アドバンテスト | Probe card |
US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
US5780331A (en) * | 1997-01-15 | 1998-07-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making buried contact structure for a MOSFET device in an SRAM cell |
JP4005762B2 (en) * | 1999-06-30 | 2007-11-14 | 株式会社東芝 | Integrated circuit device and manufacturing method thereof |
JP2006210368A (en) * | 1999-07-02 | 2006-08-10 | Toyota Central Res & Dev Lab Inc | Vertical semiconductor device and its fabrication process |
JP2001091544A (en) * | 1999-09-27 | 2001-04-06 | Hitachi Ltd | Method for manufacture of semiconductor inspecting device |
US6693358B2 (en) * | 2000-10-23 | 2004-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
JP3433193B2 (en) * | 2000-10-23 | 2003-08-04 | 松下電器産業株式会社 | Semiconductor chip and manufacturing method thereof |
US6780311B1 (en) * | 2002-03-22 | 2004-08-24 | Thomas L. Haley | Apparatus for supporting a water filter intake |
JP2006019455A (en) * | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
-
2003
- 2003-12-05 US US10/729,254 patent/US7276787B2/en not_active Expired - Fee Related
-
2004
- 2004-11-05 CN CNB2004100906008A patent/CN100456467C/en active Active
-
2005
- 2005-10-03 US US11/242,221 patent/US20060027934A1/en not_active Abandoned
Cited By (162)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050248002A1 (en) * | 2004-05-07 | 2005-11-10 | Michael Newman | Fill for large volume vias |
US8017967B2 (en) | 2004-09-09 | 2011-09-13 | Toyoda Gosei Co., Ltd. | Light-emitting element including a fusion-bonding portion on contact electrodes |
US20060049335A1 (en) * | 2004-09-09 | 2006-03-09 | Toyoda Gosei Co., Ltd. | Solid state device and light-emitting element |
US20080252212A1 (en) * | 2004-09-09 | 2008-10-16 | Toyoda Gosei Co., Ltd. | Solid state device and light-emitting element |
US7417220B2 (en) * | 2004-09-09 | 2008-08-26 | Toyoda Gosei Co., Ltd. | Solid state device and light-emitting element |
US7951718B2 (en) * | 2004-11-26 | 2011-05-31 | Applied Materials, Inc. | Edge removal of silicon-on-insulator transfer wafer |
US20080138987A1 (en) * | 2004-11-26 | 2008-06-12 | Applied Materials, Inc. | Edge removal of silicon-on-insulator transfer wafer |
US20080099924A1 (en) * | 2005-05-04 | 2008-05-01 | Icemos Technology Corporation | Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape |
US7709950B2 (en) | 2005-05-04 | 2010-05-04 | Icemos Technology Ltd. | Silicon wafer having through-wafer vias |
US20090253261A1 (en) * | 2005-05-04 | 2009-10-08 | Icemos Technology Ltd. | Silicon Wafer Having Through-Wafer Vias With A Predetermined Geometric Shape |
US20060275946A1 (en) * | 2005-05-04 | 2006-12-07 | Icemos Technology Corporation | Silicon Wafer Having Through-Wafer Vias |
US20080315368A1 (en) * | 2005-05-04 | 2008-12-25 | Icemos Technology Corporation | Silicon Wafer Having Through-Wafer Vias |
US7553764B2 (en) * | 2005-05-04 | 2009-06-30 | Icemos Technology Ltd. | Silicon wafer having through-wafer vias |
US20070032077A1 (en) * | 2005-08-08 | 2007-02-08 | Tzung-Yu Hung | Method of manufacturing metal plug and contact |
US20080315269A1 (en) * | 2005-10-11 | 2008-12-25 | Icemos Technology Corporation | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US7768085B2 (en) | 2005-10-11 | 2010-08-03 | Icemos Technology Ltd. | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US7972934B2 (en) | 2005-10-11 | 2011-07-05 | Icemos Technology Ltd. | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US7821089B2 (en) | 2005-10-11 | 2010-10-26 | Icemos Technology Ltd. | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US20070085117A1 (en) * | 2005-10-11 | 2007-04-19 | Icemos Technology Corporation | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US20080248606A1 (en) * | 2005-10-11 | 2008-10-09 | Icemos Technology Corporation | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US8058091B2 (en) | 2005-10-28 | 2011-11-15 | Icemos Technology Ltd. | Front lit PIN/NIP diode having a continuous anode/cathode |
US20080299698A1 (en) * | 2005-10-28 | 2008-12-04 | Icemos Technology Corporation | Front Lip PIN/NIP Diode Having a Continuous Anode/Cathode |
US20070111356A1 (en) * | 2005-10-28 | 2007-05-17 | Icemos Technology Corporation | Front Lit PIN/NIP Diode Having a Continuous Anode/Cathode |
US7560791B2 (en) | 2005-10-28 | 2009-07-14 | Icemos Technology Ltd. | Front lit PIN/NIP diode having a continuous anode/cathode |
US7576404B2 (en) | 2005-12-16 | 2009-08-18 | Icemos Technology Ltd. | Backlit photodiode and method of manufacturing a backlit photodiode |
US20070138588A1 (en) * | 2005-12-16 | 2007-06-21 | Icemos Technology Corporation | Backlit Photodiode and Method of Manufacturing a Backlit Photodiode |
US20090176330A1 (en) * | 2006-03-02 | 2009-07-09 | Icemos Technology Ltd. | Photodiode Having Increased Proportion of Light-Sensitive Area to Light-Insensitive Area |
US20070205478A1 (en) * | 2006-03-02 | 2007-09-06 | Icemos Technology Corporation | Photodiode having increased proportion of light-sensitive area to light-insensitive area |
US7528458B2 (en) | 2006-03-02 | 2009-05-05 | Icemos Technology Ltd. | Photodiode having increased proportion of light-sensitive area to light-insensitive area |
US7741141B2 (en) | 2006-03-02 | 2010-06-22 | Icemos Technology Ltd. | Photodiode having increased proportion of light-sensitive area to light-insensitive area |
US20080182362A1 (en) * | 2006-03-21 | 2008-07-31 | Paul Stephen Andry | Method for precision assembly of integrated circuit chip packages |
US7615405B2 (en) * | 2006-03-21 | 2009-11-10 | International Business Machines Corporation | Method for precision assembly of integrated circuit chip packages |
US20070246821A1 (en) * | 2006-04-20 | 2007-10-25 | Lu Szu W | Utra-thin substrate package technology |
US7682972B2 (en) * | 2006-06-01 | 2010-03-23 | Amitec-Advanced Multilayer Interconnect Technoloiges Ltd. | Advanced multilayer coreless support structures and method for their fabrication |
US20070281471A1 (en) * | 2006-06-01 | 2007-12-06 | Dror Hurwitz | Advanced Multilayered Coreless Support Structures and their Fabrication |
US20080122040A1 (en) * | 2006-06-29 | 2008-05-29 | Icemos Technology Corporation | Varying Pitch Adapter and a Method of Forming a Varying Pitch Adapter |
US8704383B2 (en) | 2006-07-26 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-based thin substrate and packaging schemes |
US8174129B2 (en) | 2006-07-26 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon-based thin substrate and packaging schemes |
US20100301477A1 (en) * | 2006-07-26 | 2010-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicon-Based Thin Substrate and Packaging Schemes |
US20090224352A1 (en) * | 2006-08-10 | 2009-09-10 | Icemos Technology Ltd. | Method of Manufacturing a Photodiode Array with Through-Wafer Vias |
US7579273B2 (en) | 2006-08-10 | 2009-08-25 | Icemos Technology Ltd. | Method of manufacturing a photodiode array with through-wafer vias |
US7910479B2 (en) | 2006-08-10 | 2011-03-22 | Icemos Technology Ltd. | Method of manufacturing a photodiode array with through-wafer vias |
US20080099870A1 (en) * | 2006-08-10 | 2008-05-01 | Icemos Technology Corporation | Method of manufacturing a photodiode array with through-wafer vias |
US7473577B2 (en) * | 2006-08-11 | 2009-01-06 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
US7898087B2 (en) | 2006-08-11 | 2011-03-01 | International Business Machines Corporation | Integrated chip carrier with compliant interconnects |
US20080036061A1 (en) * | 2006-08-11 | 2008-02-14 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
US7560371B2 (en) | 2006-08-29 | 2009-07-14 | Micron Technology, Inc. | Methods for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum |
US20080057691A1 (en) * | 2006-08-29 | 2008-03-06 | Dando Ross S | Methods and systems for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum |
US20080073752A1 (en) * | 2006-09-27 | 2008-03-27 | Nec Electronics Corporation | Semiconductor apparatus |
US7834461B2 (en) * | 2006-09-27 | 2010-11-16 | Nec Electronics Corporation | Semiconductor apparatus |
US20080119046A1 (en) * | 2006-11-21 | 2008-05-22 | Sparks Terry G | Method of making a contact on a backside of a die |
US7544605B2 (en) * | 2006-11-21 | 2009-06-09 | Freescale Semiconductor, Inc. | Method of making a contact on a backside of a die |
WO2008063745A1 (en) * | 2006-11-21 | 2008-05-29 | Freescale Semiconductor Inc. | Method of making a contact on a backside of a die |
US7692307B2 (en) * | 2006-12-08 | 2010-04-06 | Intel Corporation | Compliant structure for an electronic device, method of manufacturing same, and system containing same |
US20080137318A1 (en) * | 2006-12-08 | 2008-06-12 | Sudarshan Rangaraj | Compliant structure for an electronic device, method of manufacturing same, and system containing same |
US20080217748A1 (en) * | 2007-03-08 | 2008-09-11 | International Business Machines Corporation | Low cost and low coefficient of thermal expansion packaging structures and processes |
US9159602B2 (en) | 2007-05-15 | 2015-10-13 | International Business Machines Corporation | Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers |
US8012796B2 (en) | 2007-05-15 | 2011-09-06 | International Business Machines Corporation | Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers |
US7645701B2 (en) | 2007-05-21 | 2010-01-12 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
US20080290525A1 (en) * | 2007-05-21 | 2008-11-27 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
US20090315188A1 (en) * | 2007-05-21 | 2009-12-24 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
US8198734B2 (en) | 2007-05-21 | 2012-06-12 | International Business Machines Corporation | Silicon-on-insulator structures for through via in silicon carriers |
US20080303031A1 (en) * | 2007-06-07 | 2008-12-11 | United Test And Assembly Center Ltd. | Vented die and package |
US8426246B2 (en) | 2007-06-07 | 2013-04-23 | United Test And Assembly Center Ltd. | Vented die and package |
US8143719B2 (en) * | 2007-06-07 | 2012-03-27 | United Test And Assembly Center Ltd. | Vented die and package |
US7939941B2 (en) | 2007-06-27 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of through via before contact processing |
US20090001598A1 (en) * | 2007-06-27 | 2009-01-01 | Wen-Chih Chiou | Formation of Through Via before Contact Processing |
US9209157B2 (en) | 2007-06-27 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of through via before contact processing |
US9793192B2 (en) | 2007-06-27 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of through via before contact processing |
US20110177655A1 (en) * | 2007-06-27 | 2011-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of Through Via before Contact Processing |
US7834462B2 (en) * | 2007-09-17 | 2010-11-16 | Qimonda Ag | Electric device, stack of electric devices, and method of manufacturing a stack of electric devices |
US20090072374A1 (en) * | 2007-09-17 | 2009-03-19 | Stephan Dobritz | Electric Device, Stack of Electric Devices, and Method of Manufacturing a Stack of Electric Devices |
US20090079058A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Semiconductor substrate elastomeric stack |
US20090080158A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Comb-shaped power bus bar assembly structure having integrated capacitors |
US20090079059A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Integrated semiconductor substrate structure using incompatible processes |
US8404585B2 (en) * | 2007-09-24 | 2013-03-26 | Research Triangle Institute | Preventing breakage of long metal signal conductors on semiconductor substrates |
US7829994B2 (en) | 2007-09-24 | 2010-11-09 | Sixis, Inc. | Semiconductor substrate elastomeric stack |
US8222086B2 (en) | 2007-09-24 | 2012-07-17 | Research Triangle Institute | Integrated semiconductor substrate structure using incompatible processes |
US20090079084A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Preventing breakage of long metal signal conductors on semiconductor substrates |
US7719844B2 (en) | 2007-09-24 | 2010-05-18 | Sixis, Inc. | Stackable self-aligning insulative guide tray for holding semiconductor substrates |
US7944041B2 (en) * | 2007-09-24 | 2011-05-17 | Research Triangle Institute | Integrated semiconductor substrate structure using incompatible processes |
US20110266034A1 (en) * | 2007-09-24 | 2011-11-03 | Research Triangle Institute | Preventing breakage of long metal signal conductors on semiconductor substrates |
US7831874B2 (en) | 2007-09-24 | 2010-11-09 | Sixis, Inc. | Local defect memories on semiconductor substrates in a stack computer |
US7764498B2 (en) | 2007-09-24 | 2010-07-27 | Sixis, Inc. | Comb-shaped power bus bar assembly structure having integrated capacitors |
US20110183469A1 (en) * | 2007-09-24 | 2011-07-28 | Research Triangle Institute | Integrated semiconductor substrate structure using incompatible processes |
US7999388B2 (en) | 2007-09-24 | 2011-08-16 | Research Triangle Institute | Preventing breakage of long metal signal conductors on semiconductor substrates |
US20090080152A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Stackable self-aligning insulative guide tray for holding semiconductor substrates |
US20090079463A1 (en) * | 2007-09-24 | 2009-03-26 | Research Triangle Institute | Local defect memories on semiconductor substrates in a stack computer |
US7709966B2 (en) | 2007-09-25 | 2010-05-04 | Sixis, Inc. | Large substrate structural vias |
US20100200540A1 (en) * | 2007-09-25 | 2010-08-12 | Sixis, Inc. | Large substrate structural vias |
US20090079056A1 (en) * | 2007-09-25 | 2009-03-26 | Rti International | Large substrate structural vias |
US8008134B2 (en) | 2007-09-25 | 2011-08-30 | Research Triangle Institute | Large substrate structural vias |
US20090283871A1 (en) * | 2008-05-14 | 2009-11-19 | Hung-Pin Chang | System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack |
US10515933B2 (en) | 2008-05-14 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | System, structure, and method of manufacturing a semiconductor substrate stack |
US8853830B2 (en) | 2008-05-14 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | System, structure, and method of manufacturing a semiconductor substrate stack |
US11004832B2 (en) | 2008-05-14 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | System, structure, and method of manufacturing a semiconductor substrate stack |
US9728457B2 (en) | 2008-05-14 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | System, structure, and method of manufacturing a semiconductor substrate stack |
US20090321861A1 (en) * | 2008-06-26 | 2009-12-31 | Micron Technology, Inc. | Microelectronic imagers with stacked lens assemblies and processes for wafer-level packaging of microelectronic imagers |
US8063469B2 (en) | 2008-09-30 | 2011-11-22 | Infineon Technologies Ag | On-chip radio frequency shield with interconnect metallization |
US20100078777A1 (en) * | 2008-09-30 | 2010-04-01 | Hans-Joachim Barth | On-Chip Radio Frequency Shield with Interconnect Metallization |
DE102009044967B4 (en) * | 2008-09-30 | 2018-06-21 | Infineon Technologies Ag | System on a chip with RF shielding on the chip |
US20110201175A1 (en) * | 2008-09-30 | 2011-08-18 | Hans-Joachim Barth | System on a Chip with On-Chip RF Shield |
US8617929B2 (en) | 2008-09-30 | 2013-12-31 | Infineon Technologies Ag | On-Chip RF shields with front side redistribution lines |
US20100078771A1 (en) * | 2008-09-30 | 2010-04-01 | Hans-Joachim Barth | On-Chip RF Shields with Through Substrate Conductors |
US8536683B2 (en) | 2008-09-30 | 2013-09-17 | Infineon Technologies Ag | System on a chip with on-chip RF shield |
US9390973B2 (en) | 2008-09-30 | 2016-07-12 | Infineon Technologies Ag | On-chip RF shields with backside redistribution lines |
US8748287B2 (en) | 2008-09-30 | 2014-06-10 | Infineon Technologies Ag | System on a chip with on-chip RF shield |
US8169059B2 (en) | 2008-09-30 | 2012-05-01 | Infineon Technologies Ag | On-chip RF shields with through substrate conductors |
US8889548B2 (en) | 2008-09-30 | 2014-11-18 | Infineon Technologies Ag | On-chip RF shields with backside redistribution lines |
US20100187665A1 (en) * | 2009-01-26 | 2010-07-29 | Sixis, Inc. | Integral metal structure with conductive post portions |
US8129834B2 (en) | 2009-01-26 | 2012-03-06 | Research Triangle Institute | Integral metal structure with conductive post portions |
US20100267217A1 (en) * | 2009-04-20 | 2010-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside Process for a Substrate |
US8691664B2 (en) | 2009-04-20 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside process for a substrate |
US8048794B2 (en) * | 2009-08-18 | 2011-11-01 | International Business Machines Corporation | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
US20110042820A1 (en) * | 2009-08-18 | 2011-02-24 | International Business Machines Corporation | 3d silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
US20110074040A1 (en) * | 2009-09-29 | 2011-03-31 | Manfred Frank | Semiconductor Device And Method For Making Same |
US8101517B2 (en) * | 2009-09-29 | 2012-01-24 | Infineon Technologies Ag | Semiconductor device and method for making same |
US20110097853A1 (en) * | 2009-10-28 | 2011-04-28 | Electronics And Telecommunications Research Institute | Via forming method and method of manufacturing multi-chip package using the same |
US8486830B2 (en) * | 2009-10-28 | 2013-07-16 | Electronics And Telecommunications Research Institute | Via forming method and method of manufacturing multi-chip package using the same |
US8519538B2 (en) * | 2010-04-28 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser etch via formation |
US20110266674A1 (en) * | 2010-04-28 | 2011-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser Etch Via Formation |
US9238593B2 (en) * | 2010-07-14 | 2016-01-19 | Nhk Spring Co., Ltd. | Ceramic member, probe holder, and manufacturing method of ceramic member |
US20160284627A1 (en) * | 2010-09-17 | 2016-09-29 | Tessera, Inc. | Staged via formation from both sides of chip |
US9362203B2 (en) * | 2010-09-17 | 2016-06-07 | Tessera, Inc. | Staged via formation from both sides of chip |
US20180114743A1 (en) * | 2010-09-17 | 2018-04-26 | Tessera, Inc. | Staged via formation from both sides of chip |
US9847277B2 (en) * | 2010-09-17 | 2017-12-19 | Tessera, Inc. | Staged via formation from both sides of chip |
US10354942B2 (en) * | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
US20150130077A1 (en) * | 2010-09-17 | 2015-05-14 | Tessera, Inc. | Staged via formation from both sides of chip |
US9589879B2 (en) | 2011-03-07 | 2017-03-07 | Invensas Corporation | Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates |
US20120251783A1 (en) * | 2011-04-01 | 2012-10-04 | Seiko Epson Corporation | Base surface processing method and mems device |
US8679360B2 (en) * | 2011-04-01 | 2014-03-25 | Seiko Epson Corporation | Base surface processing method and MEMS device |
US8456017B2 (en) * | 2011-04-27 | 2013-06-04 | Industrial Technology Research Institute | Filled through-silicon via with conductive composite material |
US9437482B2 (en) | 2011-04-30 | 2016-09-06 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming shielding layer over active surface of semiconductor die |
US8791015B2 (en) * | 2011-04-30 | 2014-07-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming shielding layer over active surface of semiconductor die |
US20120273926A1 (en) * | 2011-04-30 | 2012-11-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die |
TWI493670B (en) * | 2011-06-09 | 2015-07-21 | Tessera Inc | Low-stress tsv design using conductive particles |
US20120314384A1 (en) * | 2011-06-09 | 2012-12-13 | Tessera, Inc. | Low-stress tsv design using conductive particles |
US9433100B2 (en) | 2011-06-09 | 2016-08-30 | Tessera, Inc. | Low-stress TSV design using conductive particles |
US8723049B2 (en) * | 2011-06-09 | 2014-05-13 | Tessera, Inc. | Low-stress TSV design using conductive particles |
US20140346646A1 (en) * | 2011-07-12 | 2014-11-27 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US20130015585A1 (en) * | 2011-07-12 | 2013-01-17 | Valentin Kosenko | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US20150348843A1 (en) * | 2011-07-12 | 2015-12-03 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor |
US20130214429A1 (en) * | 2011-07-12 | 2013-08-22 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US8829683B2 (en) * | 2011-07-12 | 2014-09-09 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US8431431B2 (en) * | 2011-07-12 | 2013-04-30 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US9142511B2 (en) * | 2011-07-12 | 2015-09-22 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers |
US9515024B2 (en) * | 2011-07-12 | 2016-12-06 | Invensas Corporation | Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor |
US20130319738A1 (en) * | 2012-05-30 | 2013-12-05 | Dror Hurwitz | Multilayer electronic structure with through thickness coaxial structures |
US9185793B2 (en) * | 2012-05-30 | 2015-11-10 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic structure with through thickness coaxial structures |
US20140070423A1 (en) * | 2012-09-13 | 2014-03-13 | Invensas Corporation | Tunable composite interposer |
US9362204B2 (en) * | 2012-09-13 | 2016-06-07 | Invensas Corporation | Tunable composite interposer |
US20150162216A1 (en) * | 2012-09-13 | 2015-06-11 | Invensas Corporation | Tunable composite interposer |
US9780042B2 (en) | 2012-09-13 | 2017-10-03 | Invensas Corporation | Tunable composite interposer |
US8963335B2 (en) * | 2012-09-13 | 2015-02-24 | Invensas Corporation | Tunable composite interposer |
US9673172B2 (en) * | 2012-12-04 | 2017-06-06 | Elta Systems Ltd. | Integrated electronic device including an interposer structure and a method for fabricating the same |
CN104937715A (en) * | 2012-12-04 | 2015-09-23 | 埃勒塔系统有限公司 | An integrated electronic device including an interposer structure and a method for fabricating the same |
US20150303173A1 (en) * | 2012-12-04 | 2015-10-22 | Elta Systems Ltd. | An integrated electronic device including an interposer structure and a method for fabricating the same |
KR102164533B1 (en) | 2012-12-04 | 2020-10-13 | 엘타 시스템즈 리미티드 | An integrated electronic device including an interposer structure and a method for fabricating the same |
KR20150092182A (en) * | 2012-12-04 | 2015-08-12 | 엘타 시스템즈 리미티드 | An integrated electronic device including an interposer structure and a method for fabricating the same |
US20160359044A1 (en) * | 2015-06-04 | 2016-12-08 | International Business Machines Corporation | FORMATION OF DISLOCATION-FREE SiGe FINFET USING POROUS SILICON |
US10833175B2 (en) * | 2015-06-04 | 2020-11-10 | International Business Machines Corporation | Formation of dislocation-free SiGe finFET using porous silicon |
US9659844B2 (en) * | 2015-08-31 | 2017-05-23 | Texas Instruments Incorporated | Semiconductor die substrate with integral heat sink |
Also Published As
Publication number | Publication date |
---|---|
CN1684256A (en) | 2005-10-19 |
CN100456467C (en) | 2009-01-28 |
US7276787B2 (en) | 2007-10-02 |
US20050121768A1 (en) | 2005-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060027934A1 (en) | Silicon chip carrier with conductive through-vias and method for fabricating same | |
US6593644B2 (en) | System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face | |
US8581392B2 (en) | Silicon based microchannel cooling and electrical package | |
US7935571B2 (en) | Through substrate vias for back-side interconnections on very thin semiconductor wafers | |
TWI511248B (en) | Vias in porous substrates | |
US6535398B1 (en) | Multichip module substrates with buried discrete capacitors and components and methods for making | |
US4774632A (en) | Hybrid integrated circuit chip package | |
US6673698B1 (en) | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers | |
US6300250B1 (en) | Method of forming bumps for flip chip applications | |
TWI819252B (en) | Semiconductor core assembly | |
JP2010538465A (en) | Structures and processes for electrical interconnection and thermal management | |
US7723759B2 (en) | Stacked wafer or die packaging with enhanced thermal and device performance | |
CN110010563B (en) | Bottom heat dissipation type radio frequency chip adapter plate packaging process | |
WO2023122732A1 (en) | Direct bonding on package substrates | |
WO2004047167A1 (en) | Semiconductor device, wiring substrate, and method for manufacturing wiring substrate | |
CN103380496A (en) | Interposers, electronic modules, and methods for forming the same | |
CN111834306A (en) | Semiconductor device and electronic apparatus including the same | |
US20080308303A1 (en) | Chip carrier substrate and production method therefor | |
JP4844392B2 (en) | Semiconductor device and wiring board | |
US20040195669A1 (en) | Integrated circuit packaging apparatus and method | |
US6432724B1 (en) | Buried ground plane for high performance system modules | |
KR102643053B1 (en) | semiconductor device assembly | |
US20240047298A1 (en) | Semiconductor structure | |
US20230108475A1 (en) | Thermal management techniques for high power integrated circuits operating in dry cryogenic environments | |
KR20240032172A (en) | A semiconductor device assembly |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:EDELSTEIN, DANIEL CHARLES;ANDRY, PAUL STEPHEN;BUCHWALTER, LEENA PAIVIKKI;AND OTHERS;REEL/FRAME:017120/0150;SIGNING DATES FROM 20050422 TO 20050516 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |