US20050287749A1 - Methods for forming openings in doped silicon dioxide - Google Patents

Methods for forming openings in doped silicon dioxide Download PDF

Info

Publication number
US20050287749A1
US20050287749A1 US11/214,225 US21422505A US2005287749A1 US 20050287749 A1 US20050287749 A1 US 20050287749A1 US 21422505 A US21422505 A US 21422505A US 2005287749 A1 US2005287749 A1 US 2005287749A1
Authority
US
United States
Prior art keywords
layer
oxide layer
processing chamber
doped oxide
plasma processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/214,225
Inventor
Li Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/214,225 priority Critical patent/US20050287749A1/en
Publication of US20050287749A1 publication Critical patent/US20050287749A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the present invention is directed toward methods of forming openings in doped silicon dioxide.
  • the methods may be used to form self-aligned contact holes and gate structures.
  • SAC self-aligned contact
  • a pair of adjacent gates are utilized to align an etched opening in a doped silicon dioxide layers.
  • the etch used to form the contact opening must often be selective of silicon nitride spacers surrounding the gates.
  • the etch may not be selective of field oxide regions formed to isolate active areas. If the field oxide regions are etched as a result of a slight misalignment of the mask the, overall performance of the semiconductor device may be degraded.
  • the present invention relates to removing doped silicon dioxide from a structure in a process that is selective to undoped silicon dioxide and silicon nitride. More particularly, the present invention is directed to a method of using a plasma formed from at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas to remove doped silicon dioxide.
  • FIGS. 1 a - 1 e illustrate the formation of a gate structure in accordance with the present invention.
  • FIG. 2 is a diagram of a plasma processing chamber that may be used in accordance with the present invention.
  • FIGS. 3 a - 3 b illustrate the formation of an opening in a doped silicon dioxide layer in accordance with the present invention.
  • the present invention is directed toward methods of forming openings in doped silicon dioxide, and the methods may be used to form self-aligned contact holes. Additionally, gate structures may be formed.
  • FIGS. 1 a - 1 e illustrate the formation of a self-aligned contact hole and the formation of a gate structure for a semiconductor device 24 in a stepwise fashion.
  • a semiconductor substrate 26 is generally provided.
  • semiconductor substrate is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials.
  • substrate refers to any supporting structure including but not limited to the semiconductor substrates described above.
  • the substrate 26 may be processed in any suitable manner, and the substrate 26 may have structures such as field oxide regions and well regions formed therein.
  • a pair of gate stacks 27 are formed proximate to the substrate 26 using any suitable process.
  • the gate stacks 27 may be formed from any suitable materials in any suitable configuration.
  • One such configuration includes a gate oxide layer 28 formed proximate to the substrate 26 .
  • a polysilicon layer 30 is formed proximate to the gate oxide layer 28 , and a conductive layer 32 is formed over the polysilicon layer 30 .
  • An insulating layer 34 is formed over the conductive layer 32 , and insulating sidewall spacers 36 are formed on either side of the gate stacks 27 .
  • the insulating layers 34 and sidewall spacer 36 are generally made of silicon nitride or undoped silicon dioxide.
  • unundoped silicon dioxide is defined as including undoped silicon dioxide, undoped silicon dioxide containing impurities that do not act as dopants, tetraethyloxysilicate (TEOS), and field oxide regions.
  • a contact area 38 is defined on the semiconductor substrate 26 between the gate stacks 27 .
  • a doped silicon dioxide layer 40 is formed over the pair of gate stacks 27 and proximate to the substrate 26 and the contact area 38 .
  • the doped silicon dioxide layer 40 may be formed using any suitable method.
  • the doped silicon dioxide layer 40 is generally borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) or combinations thereof.
  • a patterned layer 42 is formed on the doped silicon dioxide layer 40 .
  • the patterned layer 42 may be formed by depositing a photoresist layer, providing a mask, and developing and subsequently removing appropriate photoresist to form the patterned layer 42 .
  • the patterned layer 42 may also be formed in accordance with any suitable method.
  • the pattern layer 42 is formed to leave an area 44 of the doped silicon dioxide layer 40 overlying the contact area 38 exposed.
  • a self-aligned contact hole 46 is formed in the semiconductor device 24 .
  • the self-aligned contact hole 46 is etched so that active area 38 between the pair of gate stacks 27 is exposed.
  • the etch is generally carried out in a plasma processing chamber that is generally programmed to perform in a specified manner.
  • the etch may be carried out in a dual frequency high density plasma processing chamber.
  • FIG. 2 shows one plasma etching system 100 that may be used in accordance with the present invention.
  • the plasma etching system 100 includes a plasma processing chamber 101 , and the plasma processing chamber 101 generally includes bottom electrode 102 and a top electrode 104 .
  • the top electrode 104 may include a shower head for allowing etchant gas chemistries 110 to enter the processing chamber 101 .
  • the top electrode also may include a quartz confinement ring 108 that circles an edge that is under the top electrode 104 .
  • a wafer 106 may be placed on the bottom electrode 102 .
  • the process chamber 101 therefore establishes a dual frequency parallel plate processing arrangement where a first radio frequency (RF) source 114 a is coupled to the top electrode 104 through a first RF matching network 112 a .
  • bottom electrode 102 is coupled to a second RF source 114 b through a second RF matching network 114 b .
  • Each of the RF sources 114 a , 114 b are coupled to ground 116 .
  • the process chamber 101 may exhaust etchant gases through a high conductance pumping network 122 that leads to a VAT valve 124 .
  • the VAT valve 124 is then coupled to a drag pump 126 that assists in channeling the etchant gases to an appropriate storage unit (not shown).
  • the process chamber 101 is generally controlled by a controller 125 that may be programmed to control the chamber 101 in a desired manner.
  • An Exelan 2300 Series EtcherTM from LAM Research Corporation is one example of a suitable dual frequency processing system.
  • the etch that forms the self-aligned contact hole 46 generally uses an etchant gas mixture of at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas.
  • the fluorocarbon gas generally has a carbon to fluorine ration of greater than or equal to about 0.5.
  • suitable fluorocarbon gases include, but are not limited to, CH 3 F, C 4 F 8 , C 4 F 6 , and CH 2 F 2 , and combinations thereof.
  • hydrogen containing gas is defined to mean any gas having a hydrogen species except for gases containing a fluorine species.
  • suitable hydrogen containing gases include, but are not limited to, H 2 , NH 3 , and CH 4 , and combinations thereof.
  • suitable inert gases include, but are not limited to Ar, He, and Ne, and combinations thereof.
  • the etchant gas mixture may comprise C 4 F 8 , NH 3 , and Ar.
  • the etchant gas mixture may comprise C 4 F 6 , H 2 , and Ar.
  • the etchant gases are generally flowed into a plasma processing chamber and a plasma is struck in the plasma processing chamber from the etchant gases.
  • the etchant gases may be flowed through the showerhead of upper electrode 104 in processing chamber 101 .
  • the semiconductor device 24 is then exposed to the plasma and the undoped oxide 40 is etched away in the area 44 exposed by the pattern 42 to form self-aligned contact opening 46 .
  • the etchant gases etch the doped oxide layer 40 , but they generally etch undoped oxide or silicon nitride regions such as the insulating layers 34 and the sidewall spacers 36 much more slowly. Therefore, the etch is relatively highly selective of doped silicon dioxide and relatively minimally selective of undoped oxide and silicon nitride.
  • the etchant gases etch the substrate 26 or other surrounding regions that are comprised of material other than doped oxide much more slowly. Therefore, the insulating layers 34 and sidewall spacers 36 of the gate stacks 27 protect conductive layers from being substantially etched, and the self-aligned contact opening 46 is easily formed without substantially etching into the gate stacks.
  • the fluorocarbon gas will generally be flowed into the processing chamber at a rate of between about 5 to about 50 standard cubic centimeters per minute (sccm).
  • the hydrogen containing gas will generally be flowed into the processing chamber at a rate of about 1 to about 50 sccm.
  • the inert gas will generally be flowed into the chamber at a rate of about 10 to about 1000 sccm, and the inert gas will more generally have a flow rate of about 100 to about 300 sccm.
  • the processing chamber may be maintained at a pressure of about 1 to about 200 milliTorr, and the processing chamber will more generally be maintained at a pressure of about 50 to about 100 milliTorr. Generally, a power of about 10-2000 Watts may be applied to the processing chamber.
  • the etch of the present invention provides a wide process window for the fluorocarbon and hydrogen containing gases. Therefore, the gas flow rates of the fluorocarbon and hydrogen containing gases may fluctuate without adversely affecting the etch of the present invention or causing the etch to stop. Generally, the gas flow rates may fluctuate as much as +/ ⁇ 2 sccm for a given etch.
  • the self-aligned contact hole may be filled with a contact plug to form a gate structure.
  • the pattern 42 is removed as shown in FIG. 1 d .
  • the pattern may be removed by any suitable method.
  • a contact plug 48 formed from conductive material is deposited in contact hole 46 .
  • the contact plug 48 contacts active area 38 and allows the active area 38 to be connected to overlying structures (not shown.)
  • the contact plug may be formed and processed according to any suitable method.
  • the methods of the present invention may also be used to form an opening in a doped oxide layer of a semiconductor device 10 as shown in FIGS. 3 a - 3 b .
  • a semiconductor substrate 12 is provided, and an undoped silicon dioxide or silicon nitride layer 14 is formed proximate to at least a portion of substrate 12 .
  • a doped silicon dioxide layer 16 is formed overlying at least a portion of the layer 14 .
  • the doped oxide layer is generally selected from BPSG and PSG and combinations thereof.
  • a pattern 18 is formed over the doped silicon dioxide layer 16 by masking, and the pattern 18 exposes as etch area 20 of the doped silicon dioxide layer 16 .
  • an opening 22 is formed in the silicon dioxide layer 16 at the etching area 20 by etching the silicon dioxide layer.
  • the etch is generally performed in accordance with the methods described above.
  • the etch is relatively highly selective of doped silicon dioxide and relatively minimally selective of undoped silicon dioxide and silicon nitride. Therefore, the layer 14 acts as an etch stop.
  • the etch may contact the substrate 12 , or the etch may be performed using undoped silicon dioxide or silicon nitride layers as etch stops to form a desired opening in a doped silicon dioxide layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma processing chamber. An etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas is used to strike a plasma. The plasma etches the opening in the doped oxide layer, and the etch is relatively highly selective of the doped oxide layer and relatively minimally selective of undoped oxide and silicon nitride layers.

Description

    CROSS REFERENCE
  • This application is a second division of U.S. patent application Ser. No. 10/218,047 filed Aug. 13, 2002 (docket no. MIO 0101 PA/01-0617).
    • BACKGROUND OF THE INVENTION
  • The present invention is directed toward methods of forming openings in doped silicon dioxide. The methods may be used to form self-aligned contact holes and gate structures.
  • As the size of individual semiconductor devices decreases and packing density increases, the use of self-alignment techniques to relax alignment requirements and improve critical dimension control has become common in semiconductor fabrication. One such technique is called a self-aligned contact (SAC) etch, in which a pair of adjacent gates are utilized to align an etched opening in a doped silicon dioxide layers. The etch used to form the contact opening must often be selective of silicon nitride spacers surrounding the gates. However, when the etch is selective of the silicon nitride spacers, it may not be selective of field oxide regions formed to isolate active areas. If the field oxide regions are etched as a result of a slight misalignment of the mask the, overall performance of the semiconductor device may be degraded.
  • Thus there remains a need in the art for an etch that is relatively highly selective of doped silicon dioxide layers and relatively minimally selective of silicon nitride and undoped silicon dioxide layers.
    • SUMMARY OF THE INVENTION
  • The present invention relates to removing doped silicon dioxide from a structure in a process that is selective to undoped silicon dioxide and silicon nitride. More particularly, the present invention is directed to a method of using a plasma formed from at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas to remove doped silicon dioxide.
  • Accordingly, it is an object of the present invention to provide a method of etching an opening in doped silicon dioxide. Further, it is an object of the present invention to provide a method of forming a SAC opening in a semiconductor device. Additional objects and advantages of the present invention will become apparent from the subsequent drawings and detailed description of the preferred embodiments
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 a-1 e illustrate the formation of a gate structure in accordance with the present invention.
  • FIG. 2 is a diagram of a plasma processing chamber that may be used in accordance with the present invention.
  • FIGS. 3 a-3 b illustrate the formation of an opening in a doped silicon dioxide layer in accordance with the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention is directed toward methods of forming openings in doped silicon dioxide, and the methods may be used to form self-aligned contact holes. Additionally, gate structures may be formed.
  • In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration, and not by way of limitation, specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made without departing from the spirit and scope of the present invention. In the drawings, like numerals describe substantially similar components throughout the several views.
  • FIGS. 1 a-1 e illustrate the formation of a self-aligned contact hole and the formation of a gate structure for a semiconductor device 24 in a stepwise fashion. Referring to FIG. 1 a, a semiconductor substrate 26 is generally provided. As used herein, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. The substrate 26 may be processed in any suitable manner, and the substrate 26 may have structures such as field oxide regions and well regions formed therein.
  • A pair of gate stacks 27 are formed proximate to the substrate 26 using any suitable process. The gate stacks 27 may be formed from any suitable materials in any suitable configuration. One such configuration includes a gate oxide layer 28 formed proximate to the substrate 26. A polysilicon layer 30 is formed proximate to the gate oxide layer 28, and a conductive layer 32 is formed over the polysilicon layer 30. An insulating layer 34 is formed over the conductive layer 32, and insulating sidewall spacers 36 are formed on either side of the gate stacks 27. The insulating layers 34 and sidewall spacer 36 are generally made of silicon nitride or undoped silicon dioxide. For the purposes of describing and defining the present invention, “undoped silicon dioxide” is defined as including undoped silicon dioxide, undoped silicon dioxide containing impurities that do not act as dopants, tetraethyloxysilicate (TEOS), and field oxide regions. A contact area 38 is defined on the semiconductor substrate 26 between the gate stacks 27.
  • Referring to FIG. 1 b, a doped silicon dioxide layer 40 is formed over the pair of gate stacks 27 and proximate to the substrate 26 and the contact area 38. The doped silicon dioxide layer 40 may be formed using any suitable method. The doped silicon dioxide layer 40 is generally borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) or combinations thereof. A patterned layer 42 is formed on the doped silicon dioxide layer 40. The patterned layer 42 may be formed by depositing a photoresist layer, providing a mask, and developing and subsequently removing appropriate photoresist to form the patterned layer 42. The patterned layer 42 may also be formed in accordance with any suitable method. The pattern layer 42 is formed to leave an area 44 of the doped silicon dioxide layer 40 overlying the contact area 38 exposed.
  • Referring to FIG. 1 c, a self-aligned contact hole 46 is formed in the semiconductor device 24. The self-aligned contact hole 46 is etched so that active area 38 between the pair of gate stacks 27 is exposed. The etch is generally carried out in a plasma processing chamber that is generally programmed to perform in a specified manner. For example, the etch may be carried out in a dual frequency high density plasma processing chamber. However, it is to be understood that the present invention is not limited to methods employing dual frequency plasma processing chambers. FIG. 2 shows one plasma etching system 100 that may be used in accordance with the present invention. The plasma etching system 100 includes a plasma processing chamber 101, and the plasma processing chamber 101 generally includes bottom electrode 102 and a top electrode 104. The top electrode 104 may include a shower head for allowing etchant gas chemistries 110 to enter the processing chamber 101. The top electrode also may include a quartz confinement ring 108 that circles an edge that is under the top electrode 104. A wafer 106 may be placed on the bottom electrode 102.
  • The process chamber 101 therefore establishes a dual frequency parallel plate processing arrangement where a first radio frequency (RF) source 114 a is coupled to the top electrode 104 through a first RF matching network 112 a. Similarly, bottom electrode 102 is coupled to a second RF source 114 b through a second RF matching network 114 b. Each of the RF sources 114 a, 114 b are coupled to ground 116.
  • During operation, the process chamber 101 may exhaust etchant gases through a high conductance pumping network 122 that leads to a VAT valve 124. The VAT valve 124 is then coupled to a drag pump 126 that assists in channeling the etchant gases to an appropriate storage unit (not shown). The process chamber 101 is generally controlled by a controller 125 that may be programmed to control the chamber 101 in a desired manner. An Exelan 2300 Series Etcher™ from LAM Research Corporation is one example of a suitable dual frequency processing system.
  • Referring to FIGS. 1 c and 2, the etch that forms the self-aligned contact hole 46 generally uses an etchant gas mixture of at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas. The fluorocarbon gas generally has a carbon to fluorine ration of greater than or equal to about 0.5. Examples of suitable fluorocarbon gases include, but are not limited to, CH3F, C4F8, C4F6, and CH2F2, and combinations thereof. For purposes of describing and defining the present invention, “hydrogen containing gas” is defined to mean any gas having a hydrogen species except for gases containing a fluorine species. Examples of suitable hydrogen containing gases include, but are not limited to, H2, NH3, and CH4, and combinations thereof. Examples of suitable inert gases include, but are not limited to Ar, He, and Ne, and combinations thereof. For example, the etchant gas mixture may comprise C4F8, NH3, and Ar. Alternatively, the etchant gas mixture may comprise C4F6, H2, and Ar.
  • The etchant gases are generally flowed into a plasma processing chamber and a plasma is struck in the plasma processing chamber from the etchant gases. For example, the etchant gases may be flowed through the showerhead of upper electrode 104 in processing chamber 101. The semiconductor device 24 is then exposed to the plasma and the undoped oxide 40 is etched away in the area 44 exposed by the pattern 42 to form self-aligned contact opening 46. The etchant gases etch the doped oxide layer 40, but they generally etch undoped oxide or silicon nitride regions such as the insulating layers 34 and the sidewall spacers 36 much more slowly. Therefore, the etch is relatively highly selective of doped silicon dioxide and relatively minimally selective of undoped oxide and silicon nitride. Additionally, the etchant gases etch the substrate 26 or other surrounding regions that are comprised of material other than doped oxide much more slowly. Therefore, the insulating layers 34 and sidewall spacers 36 of the gate stacks 27 protect conductive layers from being substantially etched, and the self-aligned contact opening 46 is easily formed without substantially etching into the gate stacks.
  • If the etch is performed using a dual frequency plasma processing system such as the system illustrated in FIG. 2, the fluorocarbon gas will generally be flowed into the processing chamber at a rate of between about 5 to about 50 standard cubic centimeters per minute (sccm). The hydrogen containing gas will generally be flowed into the processing chamber at a rate of about 1 to about 50 sccm. The inert gas will generally be flowed into the chamber at a rate of about 10 to about 1000 sccm, and the inert gas will more generally have a flow rate of about 100 to about 300 sccm. The processing chamber may be maintained at a pressure of about 1 to about 200 milliTorr, and the processing chamber will more generally be maintained at a pressure of about 50 to about 100 milliTorr. Generally, a power of about 10-2000 Watts may be applied to the processing chamber.
  • The etch of the present invention provides a wide process window for the fluorocarbon and hydrogen containing gases. Therefore, the gas flow rates of the fluorocarbon and hydrogen containing gases may fluctuate without adversely affecting the etch of the present invention or causing the etch to stop. Generally, the gas flow rates may fluctuate as much as +/−2 sccm for a given etch.
  • Referring to FIGS. 1 d-1 e, the self-aligned contact hole may be filled with a contact plug to form a gate structure. The pattern 42 is removed as shown in FIG. 1 d. The pattern may be removed by any suitable method. Next, a contact plug 48 formed from conductive material is deposited in contact hole 46. The contact plug 48 contacts active area 38 and allows the active area 38 to be connected to overlying structures (not shown.) The contact plug may be formed and processed according to any suitable method.
  • The methods of the present invention may also be used to form an opening in a doped oxide layer of a semiconductor device 10 as shown in FIGS. 3 a-3 b. Referring to FIG. 3 a, a semiconductor substrate 12 is provided, and an undoped silicon dioxide or silicon nitride layer 14 is formed proximate to at least a portion of substrate 12. A doped silicon dioxide layer 16 is formed overlying at least a portion of the layer 14. The doped oxide layer is generally selected from BPSG and PSG and combinations thereof. A pattern 18 is formed over the doped silicon dioxide layer 16 by masking, and the pattern 18 exposes as etch area 20 of the doped silicon dioxide layer 16.
  • Referring to FIG. 3 b, an opening 22 is formed in the silicon dioxide layer 16 at the etching area 20 by etching the silicon dioxide layer. The etch is generally performed in accordance with the methods described above. The etch is relatively highly selective of doped silicon dioxide and relatively minimally selective of undoped silicon dioxide and silicon nitride. Therefore, the layer 14 acts as an etch stop. The etch may contact the substrate 12, or the etch may be performed using undoped silicon dioxide or silicon nitride layers as etch stops to form a desired opening in a doped silicon dioxide layer.
  • It will be obvious to those skilled in the art that various changes may be made without departing from the scope of the invention, which is not to be considered limited to what is described in the specification. It shall be observed that the present invention can be practiced in conjunction with a variety of integrated circuit fabrication techniques, including those techniques currently used in the art and any other suitable, yet to be developed techniques.

Claims (23)

1. A method of forming a self-aligned contact hole, comprising:
providing a pair of gate stacks in spaced relation to one another on a semiconductor substrate, wherein:
each of said gate stacks has at least one conductive layer formed therein and an insulating layer extending over said conductive layer;
said insulating layer is selected from undoped silicon dioxide and silicon nitride and combinations thereof; and
a contact area is defined on said semiconductor substrate between said pair of gate stacks;
forming a spacer composed of a spacer material adjacent to each of side of said gate stacks, wherein said spacer material is selected from undoped silicon dioxide and silicon nitride and combinations thereof;
forming a doped silicon dioxide layer over said pair of gate stacks and over said contact area;
forming a patterned layer on said doped silicon layer, wherein said patterned layer exposes the doped silicon dioxide overlying said contact area; and
etching a self-aligned contact hole through doped silicon dioxide exposed by said patterned layer in a plasma processing chamber, wherein said step of etching a contact hole comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said contact hole in said doped oxide layer, said etch being relatively highly selective of said doped oxide layer and relatively minimally selective of said insulating layer and said spacers, and said self-aligned contact hole extending to said contact area.
2. The method as claimed in claim 1 wherein said silicon dioxide layer is selected from BPSG and PSG and combinations thereof.
3. A method of forming a self-aligned contact hole, comprising:
providing a pair of gate stacks in spaced relation to one another on a semiconductor substrate, wherein:
each of said gate stacks has at least one conductive layer formed therein and an insulating layer extending over said conductive layer;
said insulating layer is selected from undoped silicon dioxide and silicon nitride and combinations thereof; and
a contact area is defined on said semiconductor substrate between said pair of gate stacks;
forming a spacer composed of a spacer material adjacent to each of side of said gate stacks, wherein said spacer material is selected from undoped silicon dioxide and silicon nitride and combinations thereof;
forming a doped silicon dioxide layer over said pair of gate stacks and over said contact area, wherein said doped silicon layer is selected from BPSG, PSG, and combinations thereof;
forming a patterned layer on said doped silicon layer, wherein said patterned layer exposes the doped silicon dioxide overlying said contact area; and
etching a self-aligned contact hole through doped silicon dioxide exposed by said patterned layer in a plasma processing chamber, wherein said step of etching a contact hole comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas selected from CH3F, C4F8 and CH2F2, and combinations thereof, at least one hydrogen containing gas, and at least one inert gas into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said contact hole in said doped oxide layer, said etch being relatively highly selective of said doped oxide layer and relatively minimally selective of said insulating layer and said spacers, and said self-aligned contact hole extending to said contact area.
4. A method of forming a self-aligned contact hole, comprising:
providing a pair of gate stacks in spaced relation to one another on a semiconductor substrate, wherein:
each of said gate stacks has at least one conductive layer formed therein and an insulating layer extending over said conductive layer;
said insulating layer is selected from undoped silicon dioxide and silicon nitride and combinations thereof; and
a contact area is defined on said semiconductor substrate between said pair of gate stacks;
forming a spacer composed of a spacer material adjacent to each of side of said gate stacks, wherein said spacer material is selected from undoped silicon dioxide and silicon nitride and combinations thereof;
forming a doped silicon dioxide layer over said pair of gate stacks and over said contact area, wherein said doped silicon layer is selected from BPSG, PSG, and combinations thereof;
forming a patterned layer on said doped silicon layer, wherein said patterned layer exposes the doped silicon dioxide overlying said contact area; and
etching a self-aligned contact hole through doped silicon dioxide exposed by said patterned layer in a plasma processing chamber, wherein said step of etching a contact hole comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas selected from CH3F, C4F8, C4F6, and CH2F2, and combinations thereof, at least one hydrogen containing gas, and at least one inert gas into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said contact hole in said doped oxide layer, said etch being relatively highly selective of said doped oxide layer and relatively minimally selective of said insulating layer and said spacers, and said self-aligned contact hole extending to said contact area.
5. A method of forming a self-aligned contact hole, comprising:
providing a pair of gate stacks in spaced relation to one another on a semiconductor substrate, wherein:
each of said gate stacks has at least one conductive layer formed therein and an insulating layer extending over said conductive layer;
said insulating layer is selected from undoped silicon dioxide and silicon nitride and combinations thereof; and
a contact area is defined on said semiconductor substrate between said pair of gate stacks;
forming a spacer composed of a spacer material adjacent to each of side of said gate stacks, wherein said spacer material is selected from undoped silicon dioxide and silicon nitride and combinations thereof;
forming a doped silicon dioxide layer over said pair of gate stacks and over said contact area, wherein said doped silicon layer is selected from BPSG, PSG, and combinations thereof; and
forming a patterned layer on said doped silicon layer, wherein said patterned layer exposes the doped silicon dioxide overlying said contact area; and
etching a self-aligned contact hole through doped silicon dioxide exposed by said patterned layer in a plasma processing chamber, wherein said step of etching a contact hole comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas selected from CH3F, C4F8, C4F6, and CH2F2, and combinations thereof, at least one hydrogen containing gas selected from H2, NH3, and CH4, and combinations thereof, and at least one inert gas into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said contact hole in said doped oxide layer, said etch being relatively highly selective of said doped oxide layer and relatively minimally selective of said insulating layer and said spacers, and said self-aligned contact hole extending to said contact area.
6. The method as claimed in claim 5 wherein said fluorocarbon gas is flowed into said plasma processing chamber at a rate of between about 5 to about 50 sccm.
7. The method as claimed in claim 5 wherein said hydrogen containing gas is flowed into said plasma processing chamber at a rate of between about 1 to about 50 sccm.
8. The method as claimed in claim 5 wherein said fluorocarbon gas is flowed into said plasma processing chamber at a rate of between about 5 to about 50 sccm, and wherein said hydrogen containing gas is flowed into said plasma processing chamber at a rate of between about 1 to about 50 sccm.
9. The method as claimed in claim 5 wherein said plasma processing chamber is at a pressure of about 1 milliTorr to about 200 milliTorr.
10. A method of forming a self-aligned contact hole, comprising:
providing a pair of gate stacks in spaced relation to one another on a semiconductor substrate, wherein:
each of said gate stacks has at least one conductive layer formed therein and an insulating layer extending over said conductive layer;
said insulating layer is selected from undoped silicon dioxide and silicon nitride and combinations thereof; and
a contact area is defined on said semiconductor substrate between said pair of gate stacks;
forming a spacer composed of a spacer material adjacent to each of side of said gate stacks, wherein said spacer material is selected from undoped silicon dioxide and silicon nitride and combinations thereof;
forming a doped silicon dioxide layer over said pair of gate stacks and over said contact area, wherein said doped silicon layer is selected from BPSG, PSG, and combinations thereof; and
forming a patterned layer on said doped silicon layer, wherein said patterned layer exposes the doped silicon dioxide overlying said contact area; and
etching a self-aligned contact hole through doped silicon dioxide exposed by said patterned layer in a plasma processing chamber, wherein said step of etching a contact hole comprises;
flowing an etchant gas mixture comprising a fluorocarbon gas comprising C4F6, a hydrogen containing gas comprising H2, and an inert gas comprising Ar into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said contact hole in said doped oxide layer, said etch being relatively highly selective of said doped oxide layer and relatively minimally selective of said insulating layer and said spacers, and said self-aligned contact hole extending to said contact area.
11. A method of etching an opening in a doped oxide layer of a semiconductor device, comprising:
providing a semiconductor structure, wherein:
at least one insulating layer selected from undoped silicon dioxide and silicon nitride and combinations thereof is formed proximate to a semiconductor substrate; and
a doped oxide layer at least partially overlies said at least one insulating layer; and
said doped oxide layer is selected from BPSG and PSG and combinations thereof;
masking said doped oxide layer to provide an etching area on top of said doped oxide layer, wherein said etching area is formed on said doped oxide layer in a region that at least partially overlies said at least one insulating layer;
forming an opening in said doped oxide layer at said etching area in a plasma processing chamber, wherein said step of forming an opening comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas, at least one hydrogen containing gas, and at least one inert gas into said plasma processing chamber, wherein said fluorocarbon gas comprises a gas having a carbon to fluorine ratio greater than or equal to about 0.5;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said opening in said doped oxide layer, wherein said etch is relatively highly selective of said doped oxide layer and relatively minimally selective said at least one insulating layer.
12. The method as claimed in claim 11 wherein said at least one insulating layer is exposed to said plasma.
13. The method as claimed in claim 11 wherein said hydrogen containing gas is selected from H2, NH3, and CH4, and combinations thereof.
14. The method as claimed in claim 15 wherein said plasma processing chamber comprises a dual frequency plasma processing chamber.
15. The method as claimed in claim 14 wherein said fluorocarbon gas is flowed into said plasma processing chamber at a rate of between about 5 to about 50 sccm.
16. The method as claimed in claim 14 wherein said hydrogen containing gas is flowed into said plasma processing chamber at a rate of between about 1 to about 50 sccm.
17. The method as claimed in claim 14 wherein said fluorocarbon gas is flowed into said plasma processing chamber at a rate of between about 5 to about 50 sccm, and wherein said hydrogen containing gas is flowed into said plasma processing chamber at a rate of between about 1 to about 50 sccm.
18. The method as claimed in claim 14 wherein said plasma processing chamber is at a pressure of about 1 milliTorr to about 200 milliTorr.
19. The method as claimed in claim 11 wherein said inert gas comprises argon.
20. A method of etching an opening in a doped oxide layer of a semiconductor device, comprising:
providing a semiconductor structure, wherein:
at least one insulating layer selected from undoped silicon dioxide and silicon nitride and combinations thereof is formed proximate to a semiconductor substrate; and
a doped oxide layer at least partially overlies said at least one insulating layer; and
said doped oxide layer is selected from BPSG and PSG and combinations thereof;
masking said doped oxide layer to provide an etching area on top of said doped oxide layer, wherein said etching area is formed on said doped oxide layer in a region that at least partially overlies said at least one insulating layer;
forming an opening in said doped oxide layer at said etching area in a plasma processing chamber, wherein said step of forming an opening comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas selected from CH3F, C4F8, C4F6, and CH2F2, and combinations thereof, at least one hydrogen containing gas, and at least one inert gas into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said opening in said doped oxide layer, wherein said etch is relatively highly selective of said doped oxide layer and relatively minimally selective of said at least one insulating layer, and wherein said at least one insulating layer is exposed to said plasma.
21. A method of etching an opening in a doped oxide layer of a semiconductor device, comprising:
providing a semiconductor structure, wherein:
at least one insulating layer selected from undoped silicon dioxide and silicon nitride and combinations thereof is formed proximate to a semiconductor substrate; and
a doped oxide layer at least partially overlies said at least one insulating layer; and
said doped oxide layer is selected from BPSG and PSG and combinations thereof;
masking said doped oxide layer to provide an etching area on top of said doped oxide layer, wherein said etching area is formed on said doped oxide layer in a region that at least partially overlies said at least one insulating layer;
forming an opening in said doped oxide layer at said etching area in a plasma processing chamber, wherein said step of forming an opening comprises;
flowing an etchant gas mixture comprising at least one fluorocarbon gas selected from CH3F, C4F8, C4F6, and CH2F2, and combinations thereof, at least one hydrogen containing gas selected from H2, NH3, and CH4, and combinations thereof, and at least one inert gas into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said opening in said doped oxide layer, wherein said etch is relatively highly selective of said doped oxide layer and relatively minimally selective of said at least one insulating layer, and wherein said at least one insulating layer is exposed to said plasma.
22. A method of etching an opening in a doped oxide layer of a semiconductor device, comprising:
providing a semiconductor structure, wherein:
at least one insulating layer selected from undoped silicon dioxide and silicon nitride and combinations thereof is formed proximate to a semiconductor substrate; and
a doped oxide layer at least partially overlies said at least one insulating layer; and
said doped oxide layer is selected from BPSG and PSG and combinations thereof;
masking said doped oxide layer to provide an etching area on top of said doped oxide layer, wherein said etching area is formed on said doped oxide layer in a region that at least partially overlies said at least one insulating layer;
forming an opening in said doped oxide layer at said etching area in a plasma processing chamber, wherein said step of forming an opening comprises;
flowing an etchant gas mixture comprising a fluorocarbon gas comprising C4F8, a hydrogen containing gas comprising NH3, and an inert gas comprising Ar into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said opening in said doped oxide layer, wherein said etch is relatively highly selective of said doped oxide layer and relatively minimally selective of said at least one insulating layer, and wherein said at least one insulating layer is exposed to said plasma.
23. A method of etching an opening in a doped oxide layer of a semiconductor device, comprising:
providing a semiconductor structure, wherein:
at least one insulating layer selected from undoped silicon dioxide and silicon nitride and combinations thereof is formed proximate to a semiconductor substrate; and
a doped oxide layer at least partially overlies said at least one insulating layer; and
said doped oxide layer is selected from BPSG and PSG and combinations thereof;
masking said doped oxide layer to provide an etching area on top of said doped oxide layer, wherein said etching area is formed on said doped oxide layer in a region that at least partially overlies said at least one insulating layer;
forming an opening in said doped oxide layer at said etching area in a plasma processing chamber, wherein said step of forming an opening comprises;
flowing an etchant gas mixture comprising a fluorocarbon gas comprising C4F6, a hydrogen containing gas comprising H2, and an inert gas comprising Ar into said plasma processing chamber;
striking a plasma in said plasma processing chamber from said etchant gas mixture; and
utilizing said plasma to etch said opening in said doped oxide layer, wherein said etch is relatively highly selective of said doped oxide layer and relatively minimally selective of said at least one insulating layer, and wherein said at least one insulating layer is exposed to said plasma.
US11/214,225 2002-08-13 2005-08-29 Methods for forming openings in doped silicon dioxide Abandoned US20050287749A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/214,225 US20050287749A1 (en) 2002-08-13 2005-08-29 Methods for forming openings in doped silicon dioxide

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/218,047 US7541270B2 (en) 2002-08-13 2002-08-13 Methods for forming openings in doped silicon dioxide
US11/214,225 US20050287749A1 (en) 2002-08-13 2005-08-29 Methods for forming openings in doped silicon dioxide

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/218,047 Division US7541270B2 (en) 2002-08-13 2002-08-13 Methods for forming openings in doped silicon dioxide

Publications (1)

Publication Number Publication Date
US20050287749A1 true US20050287749A1 (en) 2005-12-29

Family

ID=31714481

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/218,047 Expired - Lifetime US7541270B2 (en) 2002-08-13 2002-08-13 Methods for forming openings in doped silicon dioxide
US11/214,213 Abandoned US20050280151A1 (en) 2002-08-13 2005-08-29 Methods for forming openings in doped silicon dioxide
US11/214,225 Abandoned US20050287749A1 (en) 2002-08-13 2005-08-29 Methods for forming openings in doped silicon dioxide

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10/218,047 Expired - Lifetime US7541270B2 (en) 2002-08-13 2002-08-13 Methods for forming openings in doped silicon dioxide
US11/214,213 Abandoned US20050280151A1 (en) 2002-08-13 2005-08-29 Methods for forming openings in doped silicon dioxide

Country Status (1)

Country Link
US (3) US7541270B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070207622A1 (en) * 2006-02-23 2007-09-06 Micron Technology, Inc. Highly selective doped oxide etchant
US20090275208A1 (en) * 2008-05-02 2009-11-05 Nishant Sinha Compositions of Matter, and Methods of Removing Silicon Dioxide
CN105355595A (en) * 2015-11-25 2016-02-24 上海华虹宏力半导体制造有限公司 Formation method of semiconductor device

Families Citing this family (119)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
EP2988322B1 (en) * 2014-08-18 2020-06-24 IMEC vzw Method for selective oxide removal
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) * 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10510851B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance contact method and structure
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
TWI716818B (en) 2018-02-28 2021-01-21 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866485A (en) * 1997-09-29 1999-02-02 Siemens Aktiengesellschaft Techniques for etching a silicon dioxide-containing layer
US6090304A (en) * 1997-08-28 2000-07-18 Lam Research Corporation Methods for selective plasma etch
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6117767A (en) * 1995-11-01 2000-09-12 Micron Technology, Inc. Method of forming an integrated circuit structure
US6217766B1 (en) * 1996-07-16 2001-04-17 Biostar Development C.V. Sulphur reducing bacterium and its use in biological desulphurization processes
US6277758B1 (en) * 1998-07-23 2001-08-21 Micron Technology, Inc. Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
US6287905B2 (en) * 1999-12-24 2001-09-11 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor device
US6329292B1 (en) * 1998-07-09 2001-12-11 Applied Materials, Inc. Integrated self aligned contact etch
US6337285B1 (en) * 2000-03-21 2002-01-08 Micron Technology, Inc. Self-aligned contact (SAC) etch with dual-chemistry process
US6346482B2 (en) * 1998-05-08 2002-02-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an improved contact structure and a manufacturing method thereof
US6448140B1 (en) * 1999-02-08 2002-09-10 Taiwan Semiconductor Manufacturing Company Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4324611A (en) * 1980-06-26 1982-04-13 Branson International Plasma Corporation Process and gas mixture for etching silicon dioxide and silicon nitride
US4579618A (en) * 1984-01-06 1986-04-01 Tegal Corporation Plasma reactor apparatus
US6036877A (en) * 1991-06-27 2000-03-14 Applied Materials, Inc. Plasma reactor with heated source of a polymer-hardening precursor material
US6184150B1 (en) * 1992-09-08 2001-02-06 Applied Materials Inc. Oxide etch process with high selectivity to nitride suitable for use on surfaces of uneven topography
US6217786B1 (en) 1998-12-31 2001-04-17 Lam Research Corporation Mechanism for bow reduction and critical dimension control in etching silicon dioxide using hydrogen-containing additive gases in fluorocarbon gas chemistry
US6706138B2 (en) * 2001-08-16 2004-03-16 Applied Materials Inc. Adjustable dual frequency voltage dividing plasma reactor

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6117767A (en) * 1995-11-01 2000-09-12 Micron Technology, Inc. Method of forming an integrated circuit structure
US6217766B1 (en) * 1996-07-16 2001-04-17 Biostar Development C.V. Sulphur reducing bacterium and its use in biological desulphurization processes
US6090304A (en) * 1997-08-28 2000-07-18 Lam Research Corporation Methods for selective plasma etch
US5866485A (en) * 1997-09-29 1999-02-02 Siemens Aktiengesellschaft Techniques for etching a silicon dioxide-containing layer
US6346482B2 (en) * 1998-05-08 2002-02-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an improved contact structure and a manufacturing method thereof
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6121671A (en) * 1998-06-22 2000-09-19 Micron Technology, Inc. Semiconductor device having a substrate, an undoped silicon oxide structure, and an overlying doped silicon oxide structure with a side wall terminating at the undoped silicon oxide structure
US6329292B1 (en) * 1998-07-09 2001-12-11 Applied Materials, Inc. Integrated self aligned contact etch
US6277758B1 (en) * 1998-07-23 2001-08-21 Micron Technology, Inc. Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
US6448140B1 (en) * 1999-02-08 2002-09-10 Taiwan Semiconductor Manufacturing Company Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess
US6287905B2 (en) * 1999-12-24 2001-09-11 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor device
US6337285B1 (en) * 2000-03-21 2002-01-08 Micron Technology, Inc. Self-aligned contact (SAC) etch with dual-chemistry process

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070207622A1 (en) * 2006-02-23 2007-09-06 Micron Technology, Inc. Highly selective doped oxide etchant
US20070262048A1 (en) * 2006-02-23 2007-11-15 Niraj Rana Highly Selective Doped Oxide Etchant
US8512587B2 (en) 2006-02-23 2013-08-20 Micron Technology, Inc. Highly selective doped oxide etchant
US20090275208A1 (en) * 2008-05-02 2009-11-05 Nishant Sinha Compositions of Matter, and Methods of Removing Silicon Dioxide
US8226840B2 (en) 2008-05-02 2012-07-24 Micron Technology, Inc. Methods of removing silicon dioxide
US8580158B2 (en) 2008-05-02 2013-11-12 Micron Technology, Inc. Methods of removing silicon dioxide
US8871120B2 (en) 2008-05-02 2014-10-28 Micron Technology, Inc. Compositions of matter, and methods of removing silicon dioxide
CN105355595A (en) * 2015-11-25 2016-02-24 上海华虹宏力半导体制造有限公司 Formation method of semiconductor device

Also Published As

Publication number Publication date
US20050280151A1 (en) 2005-12-22
US20040033684A1 (en) 2004-02-19
US7541270B2 (en) 2009-06-02

Similar Documents

Publication Publication Date Title
US7541270B2 (en) Methods for forming openings in doped silicon dioxide
US6939806B2 (en) Etching memory
US6589879B2 (en) Nitride open etch process based on trifluoromethane and sulfur hexafluoride
US6015760A (en) Method for enhancing oxide to nitride selectivity through the use of independent heat control
US7273566B2 (en) Gas compositions
US20060051968A1 (en) Self-aligned contact etch with high sensitivity to nitride shoulder
US6716766B2 (en) Process variation resistant self aligned contact etch
JPH04239723A (en) Manufacture of semiconductor device
US20070148965A1 (en) Method and composition for plasma etching of a self-aligned contact opening
KR100743873B1 (en) Techniques for improving etching in a plasma processing chamber
KR100311487B1 (en) Method for etching of oxidation film
US6227211B1 (en) Uniformity improvement of high aspect ratio contact by stop layer
US6117788A (en) Semiconductor etching methods
US6475922B1 (en) Hard mask process to control etch profiles in a gate stack
GB2349505A (en) Method of fabricating a semiconductor device
US5968278A (en) High aspect ratio contact
US5180466A (en) Process for dry etching a silicon nitride layer
US20030096504A1 (en) Method of dry etching for fabricating semiconductor device
US6686294B2 (en) Method and apparatus for etching silicon nitride film and manufacturing method of semiconductor device
EP0933805A2 (en) Process for anisotropic etching of nitride layer with selectivity to oxide
KR20040077272A (en) Method of etching silicon nitride film
KR19990045272A (en) Method for Selectively Etching Silicon Nitride from Silicon Oxide
US20070287286A1 (en) Method for fabricating semiconductor device
KR20050068372A (en) Method for forming contact-hole in semiconductor device
KR20040003474A (en) Method of forming contact of semicontactor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION