US20050263827A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
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- US20050263827A1 US20050263827A1 US11/136,508 US13650805A US2005263827A1 US 20050263827 A1 US20050263827 A1 US 20050263827A1 US 13650805 A US13650805 A US 13650805A US 2005263827 A1 US2005263827 A1 US 2005263827A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to a semiconductor device using a silica film forming coating liquid for forming a silica film and a method of fabricating the same.
- a degree of integration and miniaturization have recently been increased and miniaturization has recently progressed. With this, a size reduction in an element isolation region has been desired strongly.
- a shallow trench isolation (STI) structure has been employed in an increasing number of times to meet the needs.
- the STI structure can sufficiently render the element isolation region sufficiently small.
- methods of burying a silicon oxide film (SiO 2 ) in an isolation groove in the STI methods using a polysilazane film are known.
- Japanese Patent No.3178412 discloses one of the methods using the polysilazane film.
- an SiO 2 film is formed on a surface of a silicon substrate and thereafter, a silicon nitride (SiN) film is formed on the SiO 2 film. Furthermore, an isolation groove is formed in the SiN film.
- a polysilazane solution a solution of a silazane perhydride polymer in the above-noted reference
- oxidation by substitution is carried out using H 2 O (in an atmosphere of steam) so that the polysilazane film is denaturalized to an SiO 2 film.
- an object of the present invention is to provide a semiconductor device in which the silicon substrate can be prevented from oxidation and the silicon oxide film can be prevented from peeling off when the coating film is oxidated and a method of fabricating the same.
- the present invention provides a semiconductor device comprising a silicon substrate, a first silicon oxide film deposited on the silicon substrate, a silicon-rich film deposited on the first silicon oxide film, and a second silicon film deposited on the silicon-rich film and formed by heat-treating a fluid applied for forming a silica coat.
- FIG. 1 is a longitudinal section of a second sample of a semiconductor device of one embodiment in accordance with the present invention
- FIG. 3 is a longitudinal section of a first sample
- FIG. 4 is a longitudinal section of the first sample after heat treatment
- FIG. 5 is a longitudinal section of the second sample after heat treatment
- FIG. 7 is a longitudinal section of a fourth sample
- FIG. 8 is a perspective view of a NAND flash EEPROM
- FIGS. 9A to 9 D are longitudinal sections showing fabricating steps of the NAND flash EEPROM.
- FIGS. 10A and 10B are longitudinal sections showing fabricating steps continuous to the step of FIG. 9D .
- the invention is applied to a technique of burying an element isolation groove of the shallow trench isolation (STI) structure.
- STI shallow trench isolation
- a grooved sample 11 for evaluation is prepared and has such a structure as shown in FIG. 2 .
- the grooved sample 11 includes a silicon substrate 1 having an upper surface on which a silicon nitride (SiN) film 2 is deposited, for example, by 150 nm.
- SiN silicon nitride
- five grooves la are formed by the lithography and dry etching techniques. Three of the five grooves 1 a are shown in FIG. 2 .
- Each groove 1 a has a depth of 450 nm, for example.
- Each groove la has a depth of 300 nm in the substrate 1 .
- the five grooves 1 a have widths of 100 nm, 500 nm, 1000 nm, 5000 nm and 10000 nm respectively.
- a silicon oxide (SiO 2 ) film 3 is deposited on the grooved sample 11 or the substrate 1 , for example, by a high density plasma CVD (HDP) technique.
- the SiO 2 film 3 has a film thickness of 200 nm, for example.
- a polysilazane solution serving as a coating solution for silica film formation is applied to the SiO 2 film 3 by spin coating thereby to be formed into a polysilazane coating film 4 .
- a first sample 12 as shown in FIG. 3 is formed.
- the first sample 12 corresponds to a conventional structure and a compared example to be compared with a sample of the embodiment (a second sample 13 as shown in FIG. 1 ).
- a second sample 13 with a structure as shown in FIG. 1 is then formed.
- the SiO 2 film 3 is deposited by 200 nm on the grooved sample 11 with the foregoing structure using an HDP technique.
- an Si-rich film 14 is deposited by 100 nm, for example.
- a polysilazane solution is applied to the Si-rich film 14 by spin coating, thereby forming a polysilazane coating film 4 .
- a second sample 13 which is a sample of the embodiment, is formed.
- the Si-rich film 14 constitutes a film containing Si.
- the above-described Si-rich film 14 is a stoichiometrically silicon rich film and is composed of an Si-rich insulating film, for example, an Si-rich SiO 2 film.
- the silicon rich insulating film (SiO 2 film) has a refractive index ranging from 1.45 to 1.72. The reason for the setting of this range is that since Si has a refractive index of 1.72 and SiO2 has a refractive index of 1.45, the SiO 2 film becomes rich with Si if the SiO2 film has a refractive index ranges from 1.45 to 1.72.
- a CENTURA-Ultima chamber manufactured by Applied Materials Inc. was used to make the aforesaid SiO 2 film 3 and Si-rich film 14 .
- a film was formed using a bare-Si wafer apart from the aforesaid two samples 12 and 13 .
- a refractive index was measured, and the determination of the SiO 2 film and Si-rich film 14 was made on the basis of the measured refractive index. More specifically, the SiO 2 film and Si-rich film were formed on the bare-Si wafer so as to each have a thickness of 400 nm, and then, the refractive index was measured.
- UV1280 Film Thickness Measurement System produced by KLA-Tencor Corporation was used for measurement of refractive index. Refractive indexes of the formed SiO 2 film and Si-rich film were 1.46 and 1.65 respectively.
- a bare Si wafer 15 was prepared, and the SiO 2 film 3 was formed on the bare Si wafer 15 under the same condition as the above-described first sample 12 .
- a polysilazane solution was applied to the SiO 2 film 3 to be formed into a polysilazane coating film 4 .
- a third sample 16 was formed.
- the bare Si wafer 15 was prepared, and the SiO 2 film 3 and Si-rich film 14 were formed under the same condition as the above-described second sample 13 .
- a polysilazane solution was applied to the SiO 2 film 3 to be formed into a polysilazane coating film 4 .
- a fourth sample 17 was formed.
- the aforesaid four samples 12 , 13 , 16 and 17 of the polysilazane coating film 4 were processed for oxidation by substitution in an atmosphere of H 2 O (steam). More specifically, the four samples 12 , 13 , 16 and 17 were heat-treated as follows. An oxidizing furnace ALPHA-8SE-Z manufactured by Tokyo Electron Ltd. was used for the heat-treatment.
- the samples were heat-treated in an atmosphere of H 2 O at 400° C. for 15 minutes and thereafter, further heat-treated in an atmosphere of O 2 at 800° C. for 30 minutes.
- refractive indexes of the third and fourth samples 16 and 17 were 1.458 and 1.456 respectively. Consequently, it was confirmed that the polysilazane coating film 4 deposited on each of the samples 16 and 17 became an SiO 2 film. From the results of the third and fourth samples 16 and 17 , it was confirmed that the polysilazane coating film 4 deposited on each of the first and second samples 12 and 13 also became an SiO 2 film.
- a section of the first sample 12 was observed using a scanning electron microscope (SEM). Type S-5200 manufactured by Hitachi, Ltd. was used as SEM. As the result of the observation, it was confirmed that the silicon substrate 1 was oxidated in each groove 1 a of the first sample 12 , as shown in FIG. 4 . An oxidated region is shown by oblique lines in FIG. 4 . Furthermore, it was confirmed that peeling occurred in a boundary between high density plasma (HDP)-SiO2 film 3 and the polysilazane coating film 4 (SiO 2 film) in a part of the groove 1 a having a width of 10000 nm.
- HDP high density plasma
- SiO 2 film polysilazane coating film
- a section of the second sample 13 was also observed using SEM. No such fault as found in the first sample 12 was confirmed in the second sample 13 as shown in FIG. 5 .
- the structure of the HDP-SiO2 film 3 , Si-rich film 14 and polysilazane coating film 4 as the second sample 13 causes the following reaction: when H 2 O reaches the Si-rich film in the oxidation of the polysilazane coating film 4 , oxygen of H 2 O reacts with the Si-rich film 14 to form SiO 2 . Since oxygen is thus consumed, H 2 O does not reach the substrate 1 .
- the Si-rich film 14 serves as a film with a function of preventing H 2 O or oxygen from permeation. Accordingly, the substrate 1 can be prevented from oxidation in the second sample 13 .
- the second sample 13 expands when SiO2 is formed by the reaction of oxygen with Si-rich film 14 .
- the expansion compensates for the shrinkage of the second sample 13 when Si—NH of the polysilazane coating film is oxidated by substitution into SiO 2 . Consequently, the peeling does not occur in the boundary between the HDP-SiO2 film 3 and the polysilazane coating film 4 (SiO 2 film).
- the foregoing embodiment includes depositing the SiO 2 film 3 on the silicon substrate 1 , depositing the Si-rich film 14 on the SiO 2 film, applying the polysilazane coating solution on the Si-rich film 14 , and oxidating (heat-treating) the polysilazane coating film 14 by substitution.
- H2O oxidating
- oxygen of H 2 O reacts with Si to form SiO 2 , whereupon oxygen is consumed.
- the substrate 1 can be prevented from oxidation. Furthermore, the cubic volume of the Si-rich film 14 is expanded when oxygen of H 2 O reacts with Si to form the SiO 2 film. The cubic expansion can compensate for cubic shrinkage resulting from film shrinkage of the polysilazane coating film 4 due to oxidation by substitution. Consequently, the peeling of the SiO 2 film can be prevented in the boundary between the HDP-SiO2 film 3 and the polysilazane coating film 4 .
- each one of NAND cells comprises a plurality of series-connected memory cells MC.
- Each NAND cell is isolated by a shallow trench isolation structure including a buried insulating film 22 formed, for example, in a p-type semiconductor substrate 21 .
- a gate oxide film 23 is formed on the surface of a semiconductor substrate 21 .
- a first floating gate 24 a comprising, for example, poly-silicon is formed on the gate oxide film 23 .
- the first floating gage 24 a constitutes a floating gate FG.
- a second floating gate 24 b comprising, for example, poly-silicon is formed on the first floating gate 24 a.
- the second floating gage 24 b also constitutes the floating gate FG.
- an oxygen-nitride-oxygen (ONO) film 25 serving as a composite insulating film is formed on the second floating gate 24 b.
- a control gate 26 comprising poly-silicon is formed on the ONO film 25 .
- a mask 27 comprising a silicon nitride film is formed on the control gate 26 .
- the mask 27 , control gate 26 and first and second floating gates 24 a and 24 b are covered with a silicon nitride film 28 , whereupon a gate structure GS is constituted.
- An n-type diffusion layer 29 is formed in each part of the substrate 21 located between the gate structures GS.
- the diffusion layer 29 and the gate structure GS constitute each memory cell MC.
- the adjacent memory cells MC are connected in series to each other so as to own each diffusion layer jointly.
- the memory cells MC are covered with an interlayer insulating film 30 made from, for example, boro-phospho-silicate glass (BPSG). Wiring 31 made from tungsten, for example, is formed in the interlayer insulating film 30 .
- BPSG boro-phospho-silicate glass
- FIGS. 9A to 10 B The fabrication step of the NAND-type flash EEPROM will be described with reference to FIGS. 9A to 10 B.
- the gate oxide film 23 On the surface of the substrate 1 are formed the gate oxide film 23 , first floating gate 24 a made from poly-silicon and mask 32 made from the silicon nitride film sequentially.
- the mask 32 is patterned, and the first floating gate 24 a, gate oxide film 23 and substrate 21 are etched with the patterned mask 32 serving as a mask so that a plurality of trenches are formed.
- a process for forming a buried insulating film 22 in the trenches 33 or an STI structure forming step is carried out.
- This step is carried out in the same manner as the step of forming and heat-treating the second sample 13 as shown in FIG. 1 .
- the SiO 2 film 3 is deposited on the substrate 1 as shown in FIG. 9B .
- the Si-rich film 14 is deposited on the SiO 2 film 3 .
- the film forming conditions for the SiO 2 film 3 and Si-rich film 14 are the same as described above.
- a polysilazane coating liquid is applied to the Si-rich film 14 by spin coating, thereby forming the polysilazane coating film 4 . Thereafter, the polysilazane coating film 4 is oxidated by way of substitution or heat-treated to be formed into the SiO 2 film.
- the heat-treating conditions are the same as described above.
- the buried insulating film 22 comprising the SiO 2 film is formed, whereby the trenches 33 are filled.
- the aforesaid SiO 2 film (buried insulating film) 22 is flattened by chemical mechanical polishing with the mask 32 serving as a stopper.
- the second floating gate 24 b comprising, the surface of the SiO 2 film 22 in each trench 33 is etched by the dry or wet etching so as to be slightly lower than the surface of the mask 32 .
- a step between the first floating gate 24 a and the surface of the insulating film 22 is reduced.
- the mask 32 is removed.
- the second floating gate 24 b comprising, for example, poly-silicon 8 is formed on the surface of the first floating gate 24 a.
- the second floating gate 24 b is patterned by the dry etching, and a slit 34 is formed in the upper surface of the buried insulating film 22 as shown in FIG. 10B .
- the ONO film 25 , the silicon gate (CG) 26 made from poly-silicon and the mask 27 are formed sequentially as a composite insulating film including the second floating gate.
- the mask 27 is patterned. Using the patterned mask 27 , the poly-silicon composing the control gate 26 and the ONO film 25 are etched using the patterned mask 27 . The mask 27 , control gate 26 and first and second floating gates 24 a and 24 b are covered by the silicon nitride film 28 , whereupon the gate structure GS is formed, as shown in FIG. 8 .
- n-type diffusion layers 29 are formed in parts of the substrate 21 located between the gate structures GS.
- the n-type diffusion layers 29 serve as source or drain regions.
- Each memory cell MC is composed of the diffusion layer 29 and the gate structure GS.
- the memory cells MC are covered with an interlayer insulating film 30 made from, for example, BPSG. Wiring 31 made from tungsten and contact holes (not shown) are formed in the interlayer insulating film 30 , whereupon a NAND-type flash EEPROM is fabricated.
- the invention should not be limited to the foregoing embodiment.
- the embodiment may be modified or expanded as follows. Firstly, although the thickness of the Si-rich film 14 is 100 nm in the foregoing embodiment, the thickness of the Si-rich film may be set to a suitable value ranging from 10 nm to 500 nm according to a thickness of the polysilazane coating film 4 .
- a film containing Si for example, an Si film may be deposited, instead of the Si-rich film 14 .
- An insulating film deposited under the Si-rich film 14 or the SiO 2 film has a thickness of 100 nm in the foregoing embodiment.
- the thickness of the SiO 2 film may be set to a suitable value ranging from 10 nm to 300 nm according to a thickness of the polysilazane coating film 4 .
- the SiO 2 film 3 deposited under the Si-rich film 14 is formed by the high density plasma (HDP) technique in the foregoing embodiment.
- HDP high density plasma
- PECVD plasma enhanced chemical vapor deposition
- reflow burying technique may be employed, instead.
- the invention is applied to a burying technique for element isolation in the foregoing embodiment.
- the invention may be applied to a burying technique for a space between the gate electrodes or for a space between metal wirings.
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Abstract
A semiconductor device includes a silicon substrate, a first silicon oxide film deposited on the silicon substrate, a silicon-rich film deposited on the first silicon oxide film, and a second silicon film deposited on the silicon-rich film and formed by heat-treating a fluid applied for forming a silica coat.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-156214, filed on May 26, 2004, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device using a silica film forming coating liquid for forming a silica film and a method of fabricating the same.
- 2. Description of the Related Art
- A degree of integration and miniaturization have recently been increased and miniaturization has recently progressed. With this, a size reduction in an element isolation region has been desired strongly. A shallow trench isolation (STI) structure has been employed in an increasing number of times to meet the needs. The STI structure can sufficiently render the element isolation region sufficiently small. As one of methods of burying a silicon oxide film (SiO2) in an isolation groove in the STI, methods using a polysilazane film are known. For example, Japanese Patent No.3178412 discloses one of the methods using the polysilazane film.
- In the method disclosed in Japanese Patent No. 3178412, an SiO2 film is formed on a surface of a silicon substrate and thereafter, a silicon nitride (SiN) film is formed on the SiO2 film. Furthermore, an isolation groove is formed in the SiN film. Successively, the surface of the substrate is covered with a polysilazane solution (a solution of a silazane perhydride polymer in the above-noted reference) by spin coating. Subsequently, oxidation by substitution is carried out using H2O (in an atmosphere of steam) so that the polysilazane film is denaturalized to an SiO2 film.
- The following problem arises when the polysilazane film is applied to STI. In the oxidation by substitution in the atmosphere of steam, H2O reaches the substrate, oxidating the same. Oxidation of the substrate increases a thickness of the gate oxide film. Oxidation of the substrate further shrinks the polysilazane film. When the groove has a large width, the SiO2 film peels off.
- Therefore, an object of the present invention is to provide a semiconductor device in which the silicon substrate can be prevented from oxidation and the silicon oxide film can be prevented from peeling off when the coating film is oxidated and a method of fabricating the same.
- The present invention provides a semiconductor device comprising a silicon substrate, a first silicon oxide film deposited on the silicon substrate, a silicon-rich film deposited on the first silicon oxide film, and a second silicon film deposited on the silicon-rich film and formed by heat-treating a fluid applied for forming a silica coat.
- The invention also provides a method of fabricating a semiconductor device, comprising depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.
- Other objects, features and advantages of the present invention will become clear upon reviewing the following description of the embodiment with reference to the accompanying drawings, in which:
-
FIG. 1 is a longitudinal section of a second sample of a semiconductor device of one embodiment in accordance with the present invention; -
FIG. 2 is a longitudinal section of a grooved sample for evaluation; -
FIG. 3 is a longitudinal section of a first sample; -
FIG. 4 is a longitudinal section of the first sample after heat treatment; -
FIG. 5 is a longitudinal section of the second sample after heat treatment; -
FIG. 6 is a longitudinal section of a third sample; -
FIG. 7 is a longitudinal section of a fourth sample; -
FIG. 8 is a perspective view of a NAND flash EEPROM; -
FIGS. 9A to 9D are longitudinal sections showing fabricating steps of the NAND flash EEPROM; and -
FIGS. 10A and 10B are longitudinal sections showing fabricating steps continuous to the step ofFIG. 9D . - One embodiment of the present invention will be described with reference to FIGS. 1 to 7. In the embodiment, the invention is applied to a technique of burying an element isolation groove of the shallow trench isolation (STI) structure.
- Firstly, a
grooved sample 11 for evaluation is prepared and has such a structure as shown inFIG. 2 . Thegrooved sample 11 includes asilicon substrate 1 having an upper surface on which a silicon nitride (SiN)film 2 is deposited, for example, by 150 nm. Thereafter, for example, five grooves la are formed by the lithography and dry etching techniques. Three of the fivegrooves 1 a are shown inFIG. 2 . Eachgroove 1 a has a depth of 450 nm, for example. Each groove la has a depth of 300 nm in thesubstrate 1. Furthermore, the fivegrooves 1 a have widths of 100 nm, 500 nm, 1000 nm, 5000 nm and 10000 nm respectively. - A silicon oxide (SiO2)
film 3 is deposited on thegrooved sample 11 or thesubstrate 1, for example, by a high density plasma CVD (HDP) technique. The SiO2film 3 has a film thickness of 200 nm, for example. Subsequently, a polysilazane solution serving as a coating solution for silica film formation is applied to the SiO2 film 3 by spin coating thereby to be formed into apolysilazane coating film 4. As a result, afirst sample 12 as shown inFIG. 3 is formed. Thefirst sample 12 corresponds to a conventional structure and a compared example to be compared with a sample of the embodiment (asecond sample 13 as shown inFIG. 1 ). - The following is a condition for deposition of the SiO2 film 3 using the HDP technique: the conditions of an SiH4/O2 gas flow and source power/bias power are represented as SiH4/O2=55/110 sccm and SRF/BRF=4400/2600 W.
- A
second sample 13 with a structure as shown inFIG. 1 is then formed. In this case, the SiO2 film 3 is deposited by 200 nm on thegrooved sample 11 with the foregoing structure using an HDP technique. Continually, an Si-rich film 14 is deposited by 100 nm, for example. Subsequently, a polysilazane solution is applied to the Si-rich film 14 by spin coating, thereby forming apolysilazane coating film 4. As a result, asecond sample 13, which is a sample of the embodiment, is formed. The Si-rich film 14 constitutes a film containing Si. - The above-described Si-
rich film 14 is a stoichiometrically silicon rich film and is composed of an Si-rich insulating film, for example, an Si-rich SiO2 film. The silicon rich insulating film (SiO2 film) has a refractive index ranging from 1.45 to 1.72. The reason for the setting of this range is that since Si has a refractive index of 1.72 and SiO2 has a refractive index of 1.45, the SiO2 film becomes rich with Si if the SiO2 film has a refractive index ranges from 1.45 to 1.72. - In the embodiment, the conditions of an SiH4/O2 gas flow and source power/bias power are represented as SiH4/O2=55/110 sccm and SRF/BRF=4400/2600 W. A CENTURA-Ultima chamber manufactured by Applied Materials Inc. was used to make the aforesaid SiO2 film 3 and Si-
rich film 14. - For determination of the SiO2 film 3 and Si-
rich film 14, a film was formed using a bare-Si wafer apart from the aforesaid twosamples rich film 14 was made on the basis of the measured refractive index. More specifically, the SiO2 film and Si-rich film were formed on the bare-Si wafer so as to each have a thickness of 400 nm, and then, the refractive index was measured. UV1280 Film Thickness Measurement System produced by KLA-Tencor Corporation was used for measurement of refractive index. Refractive indexes of the formed SiO2 film and Si-rich film were 1.46 and 1.65 respectively. - Furthermore, as shown in
FIG. 6 , abare Si wafer 15 was prepared, and the SiO2 film 3 was formed on thebare Si wafer 15 under the same condition as the above-describedfirst sample 12. A polysilazane solution was applied to the SiO2 film 3 to be formed into apolysilazane coating film 4. Thus, athird sample 16 was formed. - Additionally, as shown in
FIG. 7 , thebare Si wafer 15 was prepared, and the SiO2 film 3 and Si-rich film 14 were formed under the same condition as the above-describedsecond sample 13. A polysilazane solution was applied to the SiO2 film 3 to be formed into apolysilazane coating film 4. Thus, afourth sample 17 was formed. - Subsequently, the aforesaid four
samples polysilazane coating film 4 were processed for oxidation by substitution in an atmosphere of H2O (steam). More specifically, the foursamples - Firstly, the samples were heat-treated in an atmosphere of H2O at 400° C. for 15 minutes and thereafter, further heat-treated in an atmosphere of O2 at 800° C. for 30 minutes. Subsequently, refractive indexes of the third and
fourth samples polysilazane coating film 4 deposited on each of thesamples fourth samples polysilazane coating film 4 deposited on each of the first andsecond samples - A section of the
first sample 12 was observed using a scanning electron microscope (SEM). Type S-5200 manufactured by Hitachi, Ltd. was used as SEM. As the result of the observation, it was confirmed that thesilicon substrate 1 was oxidated in eachgroove 1 a of thefirst sample 12, as shown inFIG. 4 . An oxidated region is shown by oblique lines inFIG. 4 . Furthermore, it was confirmed that peeling occurred in a boundary between high density plasma (HDP)-SiO2 film 3 and the polysilazane coating film 4 (SiO2 film) in a part of thegroove 1 a having a width of 10000 nm. - A section of the
second sample 13 was also observed using SEM. No such fault as found in thefirst sample 12 was confirmed in thesecond sample 13 as shown inFIG. 5 . - Causes of the fault in the
first sample 12 will be considered. Firstly, a cause of oxidation on thesubstrate 1 of thefirst sample 12 will be described. When thepolysilazane coating film 4 was oxidated, H2O reached thesubstrate 1 and oxygen (O) in H2O reacted with Si to form SiO2. Furthermore, as for a cause of the peeling in the groove part with the width of 10000 nm, thepolysilazane coating film 4 shrinks when Si—NH is oxidized into SiO2. Accordingly, in the wide groove part where an absolute amount of shrinkage is large, the peeling occurs in a boundary between high density plasma (HDP)-SiO2 film 3 and the polysilazane coating film 4 (SiO2 film). - On the other hand, the structure of the HDP-
SiO2 film 3, Si-rich film 14 andpolysilazane coating film 4 as thesecond sample 13 causes the following reaction: when H2O reaches the Si-rich film in the oxidation of thepolysilazane coating film 4, oxygen of H2O reacts with the Si-rich film 14 to form SiO2. Since oxygen is thus consumed, H2O does not reach thesubstrate 1. In this case, the Si-rich film 14 serves as a film with a function of preventing H2O or oxygen from permeation. Accordingly, thesubstrate 1 can be prevented from oxidation in thesecond sample 13. - Furthermore, the
second sample 13 expands when SiO2 is formed by the reaction of oxygen with Si-rich film 14. The expansion compensates for the shrinkage of thesecond sample 13 when Si—NH of the polysilazane coating film is oxidated by substitution into SiO2. Consequently, the peeling does not occur in the boundary between the HDP-SiO2 film 3 and the polysilazane coating film 4 (SiO2 film). - The foregoing embodiment includes depositing the SiO2 film 3 on the
silicon substrate 1, depositing the Si-rich film 14 on the SiO2 film, applying the polysilazane coating solution on the Si-rich film 14, and oxidating (heat-treating) thepolysilazane coating film 14 by substitution. When H2O reaches the Si-rich film 14 in the oxidation of thepolysilazane coating film 4 by substitution, oxygen of H2O reacts with Si to form SiO2, whereupon oxygen is consumed. - Accordingly, since H2O is prevented from reaching the
substrate 1, thesubstrate 1 can be prevented from oxidation. Furthermore, the cubic volume of the Si-rich film 14 is expanded when oxygen of H2O reacts with Si to form the SiO2 film. The cubic expansion can compensate for cubic shrinkage resulting from film shrinkage of thepolysilazane coating film 4 due to oxidation by substitution. Consequently, the peeling of the SiO2 film can be prevented in the boundary between the HDP-SiO2 film 3 and thepolysilazane coating film 4. - The following describes a case where the foregoing fabricating method is applied to fabrication of a NAND-type flash EEPROM. In
FIG. 8 , each one of NAND cells comprises a plurality of series-connected memory cells MC. Each NAND cell is isolated by a shallow trench isolation structure including a buried insulatingfilm 22 formed, for example, in a p-type semiconductor substrate 21. - In each memory cell MC, a
gate oxide film 23 is formed on the surface of asemiconductor substrate 21. A first floatinggate 24 a comprising, for example, poly-silicon is formed on thegate oxide film 23. The first floatinggage 24 a constitutes a floating gate FG. A second floatinggate 24 b comprising, for example, poly-silicon is formed on the first floatinggate 24 a. The second floatinggage 24 b also constitutes the floating gate FG. - For example, an oxygen-nitride-oxygen (ONO)
film 25 serving as a composite insulating film is formed on the second floatinggate 24 b. Acontrol gate 26 comprising poly-silicon is formed on theONO film 25. Amask 27 comprising a silicon nitride film is formed on thecontrol gate 26. Themask 27,control gate 26 and first and second floatinggates silicon nitride film 28, whereupon a gate structure GS is constituted. - An n-
type diffusion layer 29 is formed in each part of thesubstrate 21 located between the gate structures GS. Thediffusion layer 29 and the gate structure GS constitute each memory cell MC. The adjacent memory cells MC are connected in series to each other so as to own each diffusion layer jointly. The memory cells MC are covered with aninterlayer insulating film 30 made from, for example, boro-phospho-silicate glass (BPSG).Wiring 31 made from tungsten, for example, is formed in theinterlayer insulating film 30. - The fabrication step of the NAND-type flash EEPROM will be described with reference to
FIGS. 9A to 10B. Firstly, as shown inFIG. 9A , on the surface of thesubstrate 1 are formed thegate oxide film 23, first floatinggate 24 a made from poly-silicon andmask 32 made from the silicon nitride film sequentially. Subsequently, themask 32 is patterned, and the first floatinggate 24 a,gate oxide film 23 andsubstrate 21 are etched with the patternedmask 32 serving as a mask so that a plurality of trenches are formed. - Subsequently, a process for forming a buried insulating
film 22 in thetrenches 33 or an STI structure forming step is carried out. This step is carried out in the same manner as the step of forming and heat-treating thesecond sample 13 as shown inFIG. 1 . More specifically, firstly, the SiO2 film 3 is deposited on thesubstrate 1 as shown inFIG. 9B . Successively, the Si-rich film 14 is deposited on the SiO2 film 3. The film forming conditions for the SiO2 film 3 and Si-rich film 14 are the same as described above. - A polysilazane coating liquid is applied to the Si-
rich film 14 by spin coating, thereby forming thepolysilazane coating film 4. Thereafter, thepolysilazane coating film 4 is oxidated by way of substitution or heat-treated to be formed into the SiO2 film. The heat-treating conditions are the same as described above. As a result, as shown inFIG. 9C , the buried insulatingfilm 22 comprising the SiO2 film is formed, whereby thetrenches 33 are filled. Subsequently, the aforesaid SiO2 film (buried insulating film) 22 is flattened by chemical mechanical polishing with themask 32 serving as a stopper. - Subsequently, the second floating
gate 24 b comprising, the surface of the SiO2 film 22 in eachtrench 33 is etched by the dry or wet etching so as to be slightly lower than the surface of themask 32. As a result, a step between the first floatinggate 24 a and the surface of the insulatingfilm 22 is reduced. Subsequently, themask 32 is removed. - Subsequently, as shown in
FIG. 10A , the second floatinggate 24 b comprising, for example, poly-silicon 8 is formed on the surface of the first floatinggate 24 a. Thereafter, the second floatinggate 24 b is patterned by the dry etching, and aslit 34 is formed in the upper surface of the buried insulatingfilm 22 as shown inFIG. 10B . For example, theONO film 25, the silicon gate (CG) 26 made from poly-silicon and themask 27 are formed sequentially as a composite insulating film including the second floating gate. - Thereafter, as well known in the art, the
mask 27 is patterned. Using the patternedmask 27, the poly-silicon composing thecontrol gate 26 and theONO film 25 are etched using the patternedmask 27. Themask 27,control gate 26 and first and second floatinggates silicon nitride film 28, whereupon the gate structure GS is formed, as shown inFIG. 8 . - Furthermore, the n-type diffusion layers 29 are formed in parts of the
substrate 21 located between the gate structures GS. The n-type diffusion layers 29 serve as source or drain regions. Each memory cell MC is composed of thediffusion layer 29 and the gate structure GS. The memory cells MC are covered with aninterlayer insulating film 30 made from, for example, BPSG.Wiring 31 made from tungsten and contact holes (not shown) are formed in theinterlayer insulating film 30, whereupon a NAND-type flash EEPROM is fabricated. - The invention should not be limited to the foregoing embodiment. The embodiment may be modified or expanded as follows. Firstly, although the thickness of the Si-
rich film 14 is 100 nm in the foregoing embodiment, the thickness of the Si-rich film may be set to a suitable value ranging from 10 nm to 500 nm according to a thickness of thepolysilazane coating film 4. - A film containing Si, for example, an Si film may be deposited, instead of the Si-
rich film 14. - An insulating film deposited under the Si-
rich film 14 or the SiO2 film has a thickness of 100 nm in the foregoing embodiment. However, the thickness of the SiO2 film may be set to a suitable value ranging from 10 nm to 300 nm according to a thickness of thepolysilazane coating film 4. - The SiO2 film 3 deposited under the Si-
rich film 14 is formed by the high density plasma (HDP) technique in the foregoing embodiment. However, for example, the plasma enhanced chemical vapor deposition (PECVD) technique or reflow burying technique may be employed, instead. Furthermore, the invention is applied to a burying technique for element isolation in the foregoing embodiment. However, for example, the invention may be applied to a burying technique for a space between the gate electrodes or for a space between metal wirings. - Furthermore, the coating liquid should not be limited to polysilazane. Any silica film forming liquid may be employed in which the oxide silicon whose characteristics are varied after the heat treatment is similar to the density of the oxide silica deposited by the high density plasma CVD.
- The foregoing description and drawings are merely illustrative of the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the invention as defined by the appended claims.
Claims (17)
1. A semiconductor device comprising:
a silicon substrate;
a first silicon oxide film deposited on the silicon substrate;
a silicon-rich film deposited on the first silicon oxide film; and
a second silicon film deposited on the silicon-rich film and formed by heat-treating a fluid applied for forming a silica coat.
2. A semiconductor device comprising:
a silicon substrate;
an element isolation trench formed on the substrate, the trench having an inner wall;
a first silicon oxide film deposited on the inner wall of the trench;
a silicon-rich film deposited on the first silicon oxide film; and
a second silicon film deposited on the silicon-rich film so as to bury the trench and formed by heat-treating a polysilazane film.
3. The semiconductor device according to claim 2 , wherein the silicon-rich film comprises a silicon film.
4. The semiconductor device according to claim 2 , wherein the silicon-rich film comprises a silicon-rich insulating film.
5. The semiconductor device according to claim 4 , wherein the silicon-rich insulating film comprises a silicon oxide film.
6. The semiconductor device according to claim 5 , wherein the silicon-rich insulating film has a refractive index ranging from 1.45 to 1.72.
7. The semiconductor device according to claim 2 , wherein the silicon-rich film has a film thickness ranging from 10 nm to 500 nm.
8. The semiconductor device according to claim 2 , further comprising an insulating film deposited under the silicon-rich film.
9. A method of fabricating a semiconductor device, comprising:
depositing a first silicon oxide film on a silicon substrate;
depositing a silicon-containing film on the first silicon oxide film;
applying a coating solution for silica film formation over the silicon-containing film; and
heat-treating the coating solution, thereby forming a second silicon oxide film.
10. The method according to claim 9 , wherein the second silicon oxide film depositing step includes forming an element isolation groove having an inner wall and depositing the first silicon oxide film on the inner wall of the element isolation groove, and the coating solution comprises a polysilazane solution.
11. The method according to claim 10 , wherein the silicon-containing film comprises a silicon film.
12. The method according to claim 10 , wherein the silicon-containing film comprises a stoichiometrically silicon-rich film.
13. The method according to claim 12 , wherein the stoichiometrically silicon-rich film comprises a silicon-rich insulating film.
14. The method according to claim 12 , wherein the silicon-rich film comprises a silicon oxide film.
15. The method according to claim 13 , wherein the silicon-rich insulating film has a refractive index ranging from 1.45 to 1.72.
16. The method according to claim 10 , wherein the silicon-containing film has a film thickness ranging from 10 nm to 500 nm.
17. The method according to claim 10 , wherein an insulating film is deposited under the silicon-rich film.
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US20060281336A1 (en) * | 2005-06-07 | 2006-12-14 | Osamu Arisumi | Semiconductor device and method of manufacturing the same |
US20080087981A1 (en) * | 2006-10-02 | 2008-04-17 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20100055868A1 (en) * | 2008-09-02 | 2010-03-04 | Mi-Young Lee | Method of forming insulation layer of semiconductor device and method of forming semiconductor device using the insulation layer |
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US20130334650A1 (en) * | 2012-06-13 | 2013-12-19 | Chih-Chien Liu | Semiconductor structure and process thereof |
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US20180006132A1 (en) * | 2009-09-09 | 2018-01-04 | Cypress Semiconductor Corporation | Varied silicon richness silicon nitride formation |
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US20060281336A1 (en) * | 2005-06-07 | 2006-12-14 | Osamu Arisumi | Semiconductor device and method of manufacturing the same |
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US20090206409A1 (en) * | 2005-06-07 | 2009-08-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
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US20080087981A1 (en) * | 2006-10-02 | 2008-04-17 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
US20100055868A1 (en) * | 2008-09-02 | 2010-03-04 | Mi-Young Lee | Method of forming insulation layer of semiconductor device and method of forming semiconductor device using the insulation layer |
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US10644126B2 (en) * | 2009-09-09 | 2020-05-05 | Monterey Research, Llc | Varied silicon richness silicon nitride formation |
US20180006132A1 (en) * | 2009-09-09 | 2018-01-04 | Cypress Semiconductor Corporation | Varied silicon richness silicon nitride formation |
US9698370B2 (en) * | 2012-01-20 | 2017-07-04 | Lintec Corporation | Gas barrier film and gas barrier film production method |
US20150287954A1 (en) * | 2012-01-20 | 2015-10-08 | Lintec Corporation | Gas barrier film and gas barrier film production method |
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US20130334650A1 (en) * | 2012-06-13 | 2013-12-19 | Chih-Chien Liu | Semiconductor structure and process thereof |
US20150064929A1 (en) * | 2013-09-05 | 2015-03-05 | United Microelectronics Corp. | Method of gap filling |
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Also Published As
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US7776689B2 (en) | 2010-08-17 |
US20080311759A1 (en) | 2008-12-18 |
JP4594648B2 (en) | 2010-12-08 |
JP2005340446A (en) | 2005-12-08 |
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