JP2008288263A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which an SiO<SB>2</SB>film used as an embedded insulating film for STI can be highly densified and its film quality can be also improved. <P>SOLUTION: The semiconductor device is manufactured by the following steps: a semiconductor film is formed on a semiconductor substrate 1; STI grooves 7a and 7b are formed at least on the semiconductor film; a coating type SiO<SB>2</SB>is applied on the semiconductor film by spin coating to put the coating type SiO<SB>2</SB>into the STI grooves 7a and 7b; the substrate is prebaked to form such a volatile substance discharge prevention layer 9 on the formed coating type SiO<SB>2</SB>film 8 that prevents a volatile substance containing Si from passing through but allows at least H<SB>2</SB>O and O<SB>2</SB>to pass through; and the substrate is heated at higher temperature than that in prebaking the coating type SiO<SB>2</SB>film 8. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which, for example, shallow trench isolation (STI) in which an insulating film is embedded as element isolation is formed on a semiconductor substrate.

  In recent years, it has been demanded to increase the operation speed and power consumption of elements by increasing the integration density of LSIs and to reduce the manufacturing cost. For this reason, it is necessary in the future to further miniaturize LSIs and reduce the element area. In order to reduce the element area, miniaturization of the element isolation region is very effective.

  Conventionally, as a method for miniaturizing an element isolation region, an STI technique in which an insulating film is embedded in a fine groove processed by anisotropic etching such as reactive ion etching (RIE) has been adopted. ing.

  The fine groove width of this STI reaches 70 nm or less. In order not to reduce the insulation even if the element isolation region is miniaturized, it is necessary to keep the depth of the STI fine groove substantially constant.

  On the other hand, the fine groove width of the STI becomes narrower with the miniaturization. For this reason, the aspect ratio of the STI trench in which the insulating film should be embedded increases rapidly as the generation of miniaturization progresses. This aspect ratio is regarded as an index representing the difficulty of embedding the insulating film, and it is considered that the difficulty increases as the numerical value increases.

In the generation after half pitch (Half Pitch) 55 nm, the aspect ratio of embedding the STI groove is 3 or more. In this case, it is very difficult to form STI by embedding SiO ₂ formed by a conventional high density plasma CVD (High Density Plasma-Chemical Vapor Deposition: HDP-CVD) method.

Therefore, as a method for replacing HDP-CVD, a method of forming a SiO ₂ film by a coating method, for example, a spin-on-glass (SOG) method has been studied. The coating type SiO ₂ film formed by this coating method is very advantageous for embedding a high aspect STI.

However, the coating-type SiO ₂ film generally has a lower film density than the SiO ₂ film formed by HDP-CVD. Furthermore, this coating type SiO ₂ film has a problem that there are many impurities in the film, and it is inferior in processing resistance, in particular, a high wet etching rate.

As a countermeasure against these problems, a technique of improving the film quality of the coating-type SiO ₂ film by annealing in an atmosphere of water vapor, oxygen, or nitrogen is used.

However, the annealing process also has an adverse effect, and low molecular weight volatiles are released from the SiO ₂ film to form a sparse film, which reduces the mechanical strength of the film.

Further, when the low molecular weight volatiles are released from the coating type SiO ₂ film, coating-type SiO ₂ film is contracted, generates high stresses. For this reason, there are problems such as peeling off of the film, cracking of the film, and deformation of the element region.

The coating type SiO ₂ film has some problems as described above.

For this reason, a hybrid type structure is proposed in which the coating type SiO ₂ film is confined only in the lower part of the STI, and the denser HTO (High Temperature Oxide) film is embedded in the upper part of the STI, instead of the coating type SiO ₂ film alone ( For example, see Patent Document 1.) There has also been proposed a hybrid structure in which a coating type SiO ₂ film is confined in the lower part of the STI and the SiO ₂ film is buried in the upper part of the STI by HDP-CVD (see, for example, Patent Documents 2 and 3).

  However, the prior art requires two CMP (Chemical Mechanical Polishing) steps. That is, the number of processes can be greatly increased and complicated, and the process margin can be reduced.

On the other hand, a hybrid structure in which a dense SiO ₂ film formed by HDP-CVD is embedded in the lower part of the STI and a coating type SiO ₂ film is embedded in the upper part of the STI has also been proposed (see, for example, Patent Document 3).

However, since the coating-type SiO ₂ film is disposed on the STI, film peeling or local shape abnormality due to wet etching may occur.

There has also been proposed a hybrid structure in which a coating type SiO ₂ film is embedded in the lower part of the STI and a dense SiO ₂ film formed by the CVD method is embedded in the upper part of the STI (see, for example, Patent Document 4).

However, the annealing treatment releases low molecular weight volatiles from the SiO ₂ film, resulting in a sparse film, which can reduce the mechanical strength of the film.
JP 2000-114362 A JP 2002-203895 JP2003-31650 JP2004-311487A

It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of increasing the density of a SiO ₂ film used for a buried insulating film of STI and improving the film quality.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
Forming a semiconductor film on the semiconductor substrate, forming an STI trench in at least the semiconductor film,
A coating material containing silicon is applied on the semiconductor film by spin coating to embed the coating material containing silicon in the STI groove, and then prebaked to form a coating type SiO ₂ film,
On the coated SiO ₂ film thus formed, a volatile substance containing Si is prevented from passing therethrough, and at least H ₂ O and O ₂ form a volatile matter release preventing layer that can pass through,
The heat treatment is performed at a temperature higher than the temperature at the time of pre-baking the coating type SiO ₂ film.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, it is possible to increase the density of the SiO ₂ film used for the STI buried insulating film and improve the film quality.

In the semiconductor device manufacturing method according to the present embodiment, a coating type SiO ₂ material (a coating material containing silicon) is applied over the entire surface of the wafer as an STI buried insulating film of the semiconductor device, thereby completely forming the STI groove. Embed in. For example, a TEOS film is formed on the coated SiO ₂ film as a volatile emission preventing layer. Thereafter, heat treatment is performed to increase the density of the coating type SiO ₂ film and improve the film quality.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. In the following embodiment, for example, a case where the present invention is applied to a NAND flash memory will be described. Note that the present invention can be similarly applied to the STI structure of other semiconductor devices.

In this embodiment, a case where a SiO ₂ insulating film is embedded in an STI trench in a state where a gate insulating film and a gate electrode film to be a floating gate are formed on a semiconductor substrate in advance will be described.

  1, FIG. 2, FIG. 4 to FIG. 7 are cross-sectional views of the NAND flash memory in each step of the semiconductor device manufacturing method according to the first embodiment of the present invention.

  First, as shown in FIG. 1, an SiON film 2 serving as a gate insulating film is formed to 8 nm on a semiconductor substrate 1 such as a silicon substrate. Further, a phosphorus-doped polycrystalline silicon film 3 serving as a floating gate is formed on the SiON film 2 to a thickness of 80 nm.

  As described above, at least the gate insulating film of the NAND flash memory formed on the semiconductor substrate 1 and the semiconductor film including the floating gate formed on the gate insulating film are formed on the semiconductor substrate 1.

Further, a 70 nm SiN film 4 serving as a polishing stopper for chemical mechanical polishing (CMP) is formed on the phosphorus-doped polycrystalline silicon film 3. Further, a SiO ₂ film 5 serving as a reactive ion etching (RIE) mask is formed on the entire surface of the semiconductor substrate 1 by a CVD method. Further, a photoresist is applied on the SiO ₂ film 5 to form a photoresist film 6.

Next, the photoresist film 6 is patterned by a normal lithography technique. Then, using the patterned photoresist film 6 as a mask, the SiO ₂ film 5 is etched by RIE to form a hard mask. The photoresist is removed by ashing and etching of a mixed solution of sulfuric acid and hydrogen peroxide solution.

Thereafter, using the SiO ₂ film 5 as a hard mask, the SiN film 4, the phosphorus-doped polycrystalline silicon film 3, the SiON film 2, and the semiconductor substrate 1 are etched in this order by RIE. Then, the STI groove 7a in the cell portion and the STI groove 7b in the peripheral circuit portion are formed by etching the semiconductor substrate 1 from its upper surface to a depth of 220 nm (FIG. 2). The width of the STI groove 7a in the cell portion is 45 nm or more, and the width of the STI groove 7b in the peripheral circuit is 100 nm or more.

  In this manner, the STI grooves 7a and 7b are formed at least in the semiconductor film.

Next, after forming the STI grooves 7a and 7b, as an insulating film material for embedding the STI grooves 7a and 7b, a coating material containing silicon, for example, a coating type SiO ₂ such as SOG is used. Examples of the coating-type SiO ₂ film include a polysilazane [polyperhydrosilazane :-( SiH ₂ NH) n-] film and an HSQ [hydrogen silsesquioxane :-( HSiO 3/2) n-] film.

Hereinafter, in the present embodiment, for example, a case where a polysilazane film is selected as the coating type SiO ₂ film will be described.

  The polysilazane solution, which is a coating material containing silicon used for coating film formation, is formed by dissolving polysilazane having an average molecular weight of 2000 to 6000 in xylene, dibutyl ether or the like. This polysilazane solution is applied to the entire surface of the semiconductor substrate 1 by a coating method at 400 to 600 nm. As a result, the STI grooves 7a and 7b are filled without gaps with the coating material containing silicon composed of polysilazane.

Subsequently, pre-baking is performed on a hot plate at 150 ° C. for 3 minutes to dry the solvent. At this stage, the coating type SiO ₂ film 8 containing polysilazane is in a state close to a low-density SiN film containing a residual solvent.

As described above, a coating material containing silicon is applied onto the semiconductor film by spin coating, and the coating material containing silicon is embedded in the STI grooves 7a and 7b, and then pre-baked to form the coating type SiO ₂ film 8. Form.

Here, in order to remove the C and N remaining in the coating type SiO ₂ film 8 containing polysilazane to increase the density and to improve the quality of the SiO ₂ film, it is necessary to perform heat treatment.

  FIG. 3 is a thermal desorption spectrum (TDS) showing the relationship between the heat treatment temperature of polysilazane and the integrated volatile emission rate.

For example, it is assumed that the heat treatment at 300 to 1000 ° C. is performed in an atmosphere of H ₂ O, O ₂ , N ₂ or the like in a state where the coating type SiO ₂ film 8 is close to a low-density SiN film containing a residual solvent. In this case, as shown in FIG. 3, the amount of volatile matter released from the coating-type SiO ₂ film 8 containing polysilazane increases. That is, the low molecular weight volatiles containing Si is released from the coating-type SiO ₂ film 8, coating-type SiO ₂ film 8 becomes sparse film, the mechanical strength is lowered. Further, when the low molecular weight volatiles are released, the coating type SiO ₂ film 8 contracts and generates high stress. As a result, film peeling, film cracking, and element region deformation may occur.

Therefore, in this embodiment, as shown in FIG. 4, a hygroscopic volatile emission preventing layer 9 is formed on the coating type SiO ₂ film 8 containing polysilazane. The volatile matter release preventing layer 9 is selected so that H ₂ O and O ₂ which are oxidants penetrate, and a low molecular weight volatile matter containing Si hardly penetrates (passes). It is possible to prevent the coating-type SiO ₂ film 8 containing polysilazane from becoming a sparse film.

When forming the volatile matter emission preventing layer 9, it is preferable to treat at a low temperature. For example, a TEOS (TetraEthyOxySilane) [Si (C ₂ H ₅ O) ₄ ] film is deposited as a volatile matter emission preventing layer 9 on the coating-type SiO ₂ film 8 by, for example, low-temperature CVD at 400 ° C. or lower. . The thickness of the TEOS film may be selected, for example, in a range where the sum of the thickness of the coating type SiO ₂ film 8 and the thickness of the TEOS film is 600 nm or less.

Thus, on the formed coating-type SiO ₂ film 8, the passage of volatile substances containing Si is prevented, and a volatile matter emission preventing layer 9 through which at least H ₂ O and O ₂ can pass is formed.

After the volatile matter emission preventing layer 9 is formed, heat treatment at 300 to 1000 ° C. is performed in an atmosphere of H ₂ O, O ₂ , N ₂ or the like. Thereby, the coating type SiO ₂ film 8 containing polysilazane can be modified to a high-quality and high-quality SiO ₂ film without releasing low molecular weight volatiles from the coating type SiO ₂ film 8. The temperature of the heat treatment is selected according to the performance required for the element to be manufactured.

In this way, the heat treatment is performed at a temperature higher than the temperature at the time of pre-baking the coating type SiO ₂ film.

  Next, planarization is performed by CMP using the SiN film 4 as a stopper (FIG. 5).

From the planarized state shown in FIG. 5, the coated SiO ₂ film 8 in the STI grooves 7a and 7b is etched back by, for example, about 120 nm by RIE. Further, the SiN film 4 is removed by heated phosphoric acid at 150 ° C. to form STI films 8a and 8b (FIG. 6).

  Then, after forming the STI films 8a and 8b as buried insulating films, as shown in FIG. 7, for example, an ONO film 10 as an interelectrode insulating film (IPD), and a phosphorus-doped polycrystalline Si film 11 as a control gate electrode , WSi film 12 and SiN film 13 are formed sequentially. Further, the SiN film 13, the WSi film 12, the phosphorus-doped polycrystalline silicon film 11, the ONO film 10, and the phosphorus-doped polycrystalline silicon film 3 are sequentially etched using a known lithography technique and RIE technique.

  Thereby, a control gate and a floating gate of the NAND flash memory are formed.

  Thereafter, a NAND flash memory is completed through a process of forming an interlayer insulating film (PMD) and wiring.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the SiO ₂ film used for the STI buried insulating film can be densified and the film quality can be improved.

In the first embodiment, for example, a method for preventing low molecular weight volatiles containing Si from being released from the coating-type SiO ₂ film during heat treatment has been described.

In this embodiment, a method for forming an impurity diffusion preventing film for preventing the diffusion of impurities from the coating type SiO ₂ film will be described.

  The manufacturing method of the semiconductor device according to the second embodiment is the same as the steps from FIGS. 1 to 2 described in the first embodiment.

  8 to 12 are cross-sectional views of the NAND flash memory in each step of the semiconductor device manufacturing method according to the second embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  First, STI grooves 7a and 7b are formed by a process similar to the process shown in FIGS.

Next, after forming the STI grooves 7a and 7b, the entire surface of the substrate (that is, at least on the surfaces of the STI grooves 7a and 7b and on the surface of the semiconductor film) is formed by CVD using silane and N ₂ O as raw materials. ), An SiO ₂ film having a thickness of 15 nm is formed to form an impurity diffusion preventing film 14 (FIG. 8).

This impurity diffusion preventing film 14 has functions of preventing impurity diffusion from the coated SiO ₂ film to the element region, improving the adhesion of the coated SiO ₂ film, and enhancing the mechanical strength of the element region.

After forming the impurity diffusion preventing film 14, as in Example 1, the impurity diffusion preventing film 14 is formed by applying and pre-baking a coating material containing silicon (for example, containing polysilazane) by a coating method. The formed STI grooves 7a and 7b are filled with a coating type SiO ₂ film 208 containing polysilazane.

As described above, after forming the impurity diffusion preventing film 14 for preventing the diffusion of impurities from the coating type SiO ₂ film by heat treatment on at least the surfaces of the STI grooves 7a and 7b and the surface of the semiconductor film, the coating is performed. A type SiO ₂ film 208 is formed.

Next, as in Example 1, as shown in FIG. 9, a hygroscopic volatile emission preventing layer 9 is formed on the coating type SiO ₂ film 208 containing polysilazane.

That is, in the same manner as in Example 1, on the formed coating type SiO ₂ film 208, the passage of volatiles containing Si is prevented, and at least H ₂ O and O ₂ can pass through the volatile matter emission preventing layer. 9 is formed.

Then, in the same manner as in Example 1, after forming the volatiles emission preventing layer _9, H 2 _O, heat treatment of 300 to 1000 ° C. in an atmosphere such as O 2, _{N 2.} Thereby, the coating type SiO ₂ film 208 containing polysilazane can be modified into a high-quality and high-quality SiO ₂ film without releasing low molecular weight volatiles from the coating type SiO 2 film 8. The temperature of the heat treatment is selected according to the performance required for the element to be manufactured.

In this way, the heat treatment is performed at a temperature higher than the temperature at the time of pre-baking the coating type SiO ₂ film.

  Next, planarization is performed by CMP using the SiN film 4 as a stopper (FIG. 10).

From the planarized state shown in FIG. 10, the coated SiO ₂ film 208 and the impurity diffusion preventing film 14 in the STI grooves 7a and 7b are etched back by, for example, about 120 nm by RIE. Further, the SiN film 4 is removed by heated phosphoric acid at 150 ° C. to form STI films 208a and 208b (FIG. 11).

  Then, after forming STI films 208a and 208b as buried insulating films, as shown in FIG. 12, for example, an ONO film 10 serving as an interelectrode insulating film (IPD), and a phosphorus-doped polycrystalline Si film 11 serving as a control gate electrode , WSi film 12 and SiN film 13 are formed sequentially. Further, the SiN film 13, the WSi film 12, the phosphorus-doped polycrystalline silicon film 11, the ONO film 10, and the phosphorus-doped polycrystalline silicon film 3 are sequentially etched using a known lithography technique and RIE technique.

  Thereby, a control gate and a floating gate of the NAND flash memory are formed.

  Thereafter, a NAND flash memory is completed through a process of forming an interlayer insulating film (PMD) and wiring.

As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the SiO ₂ film used for the STI buried insulating film can be densified and the film quality can be improved.

It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is a temperature-programmed desorption spectrum (TDS) which shows the relationship between the temperature of the heat processing of polysilazane, and an integrated volatile matter discharge | release rate. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the NAND type flash memory in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 SiON film 3 Phosphorus doped polycrystalline silicon film 4 SiN film 5 SiO ₂ film 6 Photoresist film 7a, 7b STI groove 8, 208 Coating type SiO ₂ film 8a, 8b, 208a, 208b STI film 9 Prevention of volatile emission Layer 10 ONO film 11 Phosphorus-doped polycrystalline silicon film 12 WSi film 13 SiN film 14 Impurity diffusion prevention film

Claims (5)

Forming a semiconductor film on the semiconductor substrate, forming an STI trench in at least the semiconductor film,
A coating material containing silicon is applied on the semiconductor film by spin coating to embed the coating material containing silicon in the STI groove, and then prebaked to form a coating type SiO ₂ film,
On the coated SiO ₂ film thus formed, a volatile substance containing Si is prevented from passing therethrough, and at least H ₂ O and O ₂ form a volatile matter release preventing layer that can pass through,
A method of manufacturing a semiconductor device, wherein the heat treatment is performed at a temperature higher than the temperature at the time of pre-baking the coating type SiO ₂ film. The method of manufacturing a semiconductor device according to claim 1, wherein the coating type SiO ₂ contains polysilazane.   The method for manufacturing a semiconductor device according to claim 1, wherein the volatile matter emission preventing layer is a TEOS film. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor film includes a floating gate formed on a gate insulating film of a NAND flash memory on the semiconductor substrate. After forming an impurity diffusion prevention film for preventing diffusion of impurities from the coating type SiO ₂ film by the heat treatment at least on the surface of the STI groove and the surface of the semiconductor film, the coating type SiO ₂ A method of manufacturing a semiconductor device according to claim 1, wherein a film is formed.

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