US20050179128A1 - Semiconductor device with capacitor - Google Patents

Semiconductor device with capacitor Download PDF

Info

Publication number
US20050179128A1
US20050179128A1 US11/104,436 US10443605A US2005179128A1 US 20050179128 A1 US20050179128 A1 US 20050179128A1 US 10443605 A US10443605 A US 10443605A US 2005179128 A1 US2005179128 A1 US 2005179128A1
Authority
US
United States
Prior art keywords
capacitor
chip
semiconductor device
substrate
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/104,436
Inventor
Takeshi Shioga
John Baniecki
Kazuaki Kurihara
Yasuo Yamagishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to US11/104,436 priority Critical patent/US20050179128A1/en
Publication of US20050179128A1 publication Critical patent/US20050179128A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • the present invention relates to a semiconductor device which incorporates a semiconductor integrated circuit chip for use in electronic equipment, such as a computer. More specifically, the present invention relates to a semiconductor device in which a decoupling capacitor for power supply use is arranged in close proximity with a semiconductor integrated circuit chip in order to stabilize operation of the semiconductor integrated circuit chip at high frequencies.
  • a decoupling capacitor (or bypass capacitor) is commonly used with the semiconductor integrated circuit (IC) chip to reduce the noise in the power supplied to the IC chip.
  • Advances in IC technology have increased the switching speeds employed by the recent IC devices, so that many IC chips are capable of operation at high frequencies, or microwave frequencies. High switching speeds increase the problem of power supply noise, a component of which is generated as the device is switched on and off. In order for the IC chip to function properly, the power supplied must be free from noise.
  • the decoupling capacitor to alleviate the problem of power supply noise is well known. It is also well known that it is desirable to position the decoupling capacitor as close as possible to the IC chip for best effect.
  • the leads connecting the capacitor to the IC chip have an inherent inductance which becomes significant at high speed operation, to the point that if the capacitor is positioned too far from the IC chip, the lead inductance can cancel the usefulness of the capacitor for eliminating power supply noise.
  • decoupling capacitors are arranged near a semiconductor integrated circuit (IC) chip as preventive measures against malfunctioning of the IC chip due to power supply noise at high frequencies
  • IC semiconductor integrated circuit
  • FIG. 1 shows the structure of a semiconductor device in which multi-layered chip capacitors are mounted.
  • the semiconductor IC chip 2 is connected to the top of the package substrate 1 using BGA (ball grid array) connection, and the multi-layered chip capacitors 4 are connected to the bottom surface of the package substrate 1 via solder bumps.
  • the package substrate 1 is also connected to the top of the circuit wiring board (mother board) 3 via solder bumps.
  • the package substrate 1 is, for example, a multi-chip module (MCM) substrate.
  • the portion of the circuit wiring substrate 3 where the capacitors 4 are mounted in opposing relationship to the substrate 3 must be cut through.
  • the semiconductor device such as shown in FIG. 1 , requires the wiring leads within the package substrate 1 to connect the multi-layered chip capacitors 4 and the semiconductor IC chip 2 , and the wiring leads within the package substrate 1 have a significant inductance when the IC chip 2 operates at high frequencies. Even if the decoupling capacitors 4 are arranged therein, the effect of suppressing the fluctuation of the power-supply voltage to the IC chip 2 during high-speed operation and the effect of absorbing the high frequency ripple are fading.
  • What is needed for suppressing the variation of the power-supply voltage to the IC chip 2 is to reduce the equivalent in-series resistance (ESR) and the equivalent in-series inductance (ESL) of the capacitors 4 .
  • ESR equivalent in-series resistance
  • ESL equivalent in-series inductance
  • Japanese Laid-Open Patent Application No. 4-211191 discloses a substrate with a built-in capacitor which is formed with a thin-film dielectric layer and conductive layers on a ceramic wiring substrate.
  • the capacitor is devised to reduce the inductance, thereby realizing reduction of the power supply noise.
  • Japanese Laid-Open Patent Applications No. 7-176453, No. 2001-68583 and No. 2001-35990 disclose some thin-film decoupling capacitors.
  • the upper surface pads of the capacitor formed on the carrier substrate having the via holes are connected to the semiconductor IC chip, and the lower surface pads are connected to the circuit wiring substrate.
  • the capacitor configurations are provided to reduce the inductance.
  • FIG. 2A and FIG. 2B show the structure of each of conventional semiconductor devices in which the interposer with a built-in capacitor is mounted.
  • the semiconductor IC chip 2 is connected to the top of the package substrate 1 using BGA connection, and the interposer 5 with the built-in capacitor is connected to the bottom of the IC chip 2 using BGA connection.
  • the surface portion of the package substrate 1 where the interposer 5 is mounted is cut partially.
  • the semiconductor IC chip 2 is connected to the top of the interpose 5 with the built-in capacitor using BGA connection, and the interposer 5 is connected to the top of the package substrate 3 using BGA connection.
  • the semiconductor devices of FIG. 2A and FIG. 2B have a shorter connection distance of the IC chip and the capacitor.
  • the interposer configuration is used, the number of production processes needed to manufacture the semiconductor devices will increase, and also the technical difficulty of the production may arise. This makes the low-cost production of the semiconductor devices difficult.
  • the number of interconnections between the components of the semiconductor devices increases, and the problem of reliability may arise.
  • the through vias in the substrate must be formed.
  • An object of the present invention is to provide an improved semiconductor device in which the above-described problems are eliminated.
  • Another object of the present invention is to provide a semiconductor device which is configured to position the decoupling capacitor as close as possible to the semiconductor IC chip for best effect of the decoupling capacitor, without using the interposer type configuration and the multi-layered chip capacitor configuration as in the conventional semiconductor devices.
  • a semiconductor device comprising: a carrier substrate; an integrated circuit chip mounted on the carrier substrate through bumps; and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies, wherein the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.
  • the capacitor is formed on a substrate made of silicon or glass and having a flat and smooth surface, and the entire thickness of the capacitor is reduced by machining the back surface of the capacitor substrate.
  • the thin film capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate, and it is possible that the capacitor be mounted in the shortest distance near the IC chip.
  • a semiconductor device comprising: a carrier substrate; an integrated circuit chip mounted on the carrier substrate; a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies; and a lead frame provided on the carrier substrate and electrically connected to the integrated circuit chip through a wire, wherein the capacitor is electrically connected to pads on the integrated circuit chip, and the capacitor is provided to have a height on the integrated circuit chip that is smaller than a height of the wire on the integrated circuit chip.
  • the capacitor is formed on a substrate made of silicon or glass and having a flat and smooth surface, and the entire thickness of the capacitor is reduced by machining the back surface of the capacitor substrate.
  • the thin film capacitor is electrically connected to pads on the integrated circuit chip, and the capacitor is provided to have a height on the integrated circuit chip that is smaller than a height of the wire on the integrated circuit chip. It is possible that the capacitor be mounted in the shortest distance near the IC chip.
  • the decoupling capacitor can be mounted directly on the IC chip bottom in the shortest distance near the IC chip.
  • the resistance and the inductance of the decoupling capacitor in the semiconductor device can be lowered by such configuration. Therefore, it is possible for the semiconductor device of the present invention to stabilize high-frequency operation of the IC chip.
  • FIG. 1 is a diagram showing the structure of a semiconductor device in which multi-layered chip capacitors are mounted.
  • FIG. 2A and FIG. 2B are diagrams showing the structure of each of conventional semiconductor devices in which an interposer with a built-in capacitor is mounted.
  • FIG. 3A and FIG. 3B are diagrams showing the structure of a semiconductor device of the first preferred embodiment of the present invention.
  • FIG. 4 is a diagram showing the structure of a semiconductor device of the second preferred embodiment of the present invention.
  • FIG. 5 is a diagram for explaining a method of production of a thin film capacitor for use in the semiconductor device of the present invention.
  • FIG. 6A and FIG. 6B are diagrams showing the structure of the semiconductor device of the present invention in which the thin film capacitor of FIG. 5 is mounted.
  • FIG. 3A and FIG. 3B show the structure of a semiconductor device of the first preferred embodiment of the present invention.
  • FIG. 3A is a cross-sectional view of the semiconductor device of the present embodiment
  • FIG. 3B is an enlarged view of the semiconductor device of FIG. 3A .
  • the semiconductor device 10 includes a package substrate 1 as a carrier substrate, a semiconductor integrated circuit (IC) chip 2 mounted on the package substrate 1 , and-a thin film capacitor 20 configured as a decoupling capacitor which stabilizes high-speed operation of the IC chip 2 .
  • IC semiconductor integrated circuit
  • the thin film capacitor 20 is electrically connected to the electrode pads on the bottom of the IC chip 2 .
  • the thin film capacitor 20 including the capacitor substrate, is provided to have a height on the package substrate 1 that is smaller than or equal to the height H of the solder bumps of the IC chip 2 on the package substrate 1 .
  • the thin film capacitor 20 in the present embodiment is provided on a substrate made of silicon or glass and having a flat and smooth surface, and an upper electrode layer and a lower electrode layer, which interpose a dielectric layer therebetween, are formed on the substrate.
  • the entire thickness of the capacitor 20 including the pads and the substrate, is reduced to 50 micrometers or less by machining the back surface of the capacitor substrate.
  • the capacitor 20 is electrically connected to the IC chip 2 by using the Au—Au ultrasonic joining of the pads of the capacitor 20 and the pads of the IC chip 2 .
  • the solder bumps are used to mount the IC chip 2 on the package substrate 1 , and the height H of the solder bumps of the IC chip 2 on the package substrate 1 is about 70 micrometers.
  • the solder bump height H in this case is considered as containing the thickness of each electrode pad of the package substrate 1 and the IC chip 2 .
  • the thickness of each of the pads of the package substrate 1 and the pads of the IC chip 2 is about 10 micrometers. Therefore, it is possible to configure the semiconductor device 10 of the present embodiment so that the thin film capacitor 20 , including the capacitor substrate, is provided to have a height on the package substrate 1 that is smaller than or equal to the height H of the solder bumps of the IC chip 2 on the package substrate 1 .
  • the thin film capacitor 20 is provided with the substrate having the bottom surface that is in contact with the top surface of the package substrate 1 , as shown in FIG. 3B .
  • the solder bumps are formed into the cylindrical configuration rather than the spherical configuration.
  • Japanese Laid-Open Patent Application No. 57-118650 discloses that if the solder connections between the electrodes of the carrier substrate and the electrodes of the circuit component are formed into the cylindrical configuration instead of the spherical configuration when the solder is reflowed, the height of the soldered joints is increased in the same amount of the solder, and the stress by the temperature change will be distributed to the soldered joints uniformly. Therefore, according to the semiconductor device 10 of the present embodiment, the reliability of the solder connections of the circuit components can be improved.
  • FIG. 4 shows the structure of a semiconductor device of the second preferred embodiment of the present invention.
  • the semiconductor device 11 includes the package substrate 1 as a carrier substrate, the semiconductor IC chip 2 mounted on the package substrate 1 , and the thin film capacitor 20 configured as a decoupling capacitor which stabilizes high-speed operation of the IC chip 2 .
  • the semiconductor device 11 of the present embodiment further includes a lead frame 16 , wires 17 , and a resin mold 18 .
  • the IC chip 2 and the lead frame 16 are electrically connected together by the wire bonding. After the wire bonding is performed, and the capacitor 20 , the IC chip 2 , the package substrate 1 and the wires 17 are enclosed in the resin mold 18 .
  • the thin film capacitor 20 is electrically connected to the electrode pads on the top surface of the semiconductor IC chip 2 , and the capacitor 20 , including the substrate thereof, is provided to have a height H 1 on the IC chip 2 that is smaller than a height H 2 of the wires 17 on the IC chip 2 , as shown in FIG. 4 .
  • the capacitor 20 in the present embodiment is provided on a substrate made of silicon or glass and having a flat and smooth surface, and an upper electrode layer and a lower electrode layer, which interpose a dielectric layer therebetween, are formed on the substrate.
  • the entire thickness of the capacitor 20 including the pads and the substrate, is reduced to 50 micrometers or less by machining the back surface of the capacitor substrate.
  • the capacitor 20 is electrically connected to the IC chip 2 by using the Au—Au ultrasonic joining of the pads of the capacitor 20 and the pads of the IC chip 2 .
  • the thin film capacitor 20 is provided to have the height H 1 on the IC chip 2 that is smaller than the height H 2 of the wires 17 on the IC chip 2 .
  • the height of the wires 17 on the lead frame 16 is about 150 micrometers, and the semiconductor device 11 in which the capacitor 20 is mounted can be easily produced. Therefore, it is possible for the semiconductor device 11 of the present embodiment that the thin film capacitor 20 be mounted in the shortest distance near the IC chip 2 .
  • the thickness of the capacitor 20 is reduced to 50 micrometers or less by grinding or polishing the back surface of the silicon wafer as the capacitor substrate.
  • the capacitor 20 is electrically connected to the IC chip 2 by using the Au—Au ultrasonic joining of the pads of the capacitor 20 and the pads of the IC chip 2 .
  • the height of the wires 17 on the lead frame 17 is about 150 micrometers, and the interference of the thin film capacitor 20 when the capacitor 20 and the IC chip 2 are enclosed in the resin mold 18 can be easily avoided. Therefore, the semiconductor device 11 in which the thin film capacitor 20 is mounted can be easily produced.
  • FIG. 5 is a diagram for explaining a method of production of a thin film capacitor for use in the semiconductor device of the present invention.
  • FIG. 6A and FIG. 6B show the detailed structure of the semiconductor device of the present invention in which the thin film capacitor of FIG. 5 is mounted.
  • the silicon wafer 21 is used as a carrier substrate of the thin film capacitor.
  • Use of the silicon wafer for the capacitor substrate facilitates formation of a thin film device since the back surface of the substrate (silicon) can be easily polished.
  • the silicone substrate does not easily break even if it is polished to a thickness of about 30 micrometers.
  • the silicon wafer 21 is appropriate for the carrier substrate of the thin film capacitor 20 according to the present invention.
  • the coefficient of thermal expansion of the semiconductor IC chip 2 and the coefficient of thermal expansion of the thin film capacitor 20 can be kept at the almost same level. It is possible to relieve the mounting stress during production of the semiconductor device.
  • the respective thin films of the lower electrode layer 23 , the dielectric layer 24 , and the upper electrode layer 25 are formed one by one on the silicon wafer 21 .
  • the silicon wafer 21 on which a silicon dioxide (SiO 2 ) film with a thickness of 0.3 mm is formed is employed.
  • the thin film of TiO 2 (0.05 micrometers)/Pt (0.1 micrometers), which is used as a lower electrode material is formed on top of the silicon wafer 21 by the sputtering method.
  • the thin film of (Ba, Sr)TiO 3 (hereinafter, called BST) which is used as a highly dielectric material, is formed on top of the lower electrode layer 23 by the sputtering method within the same vacuum system.
  • the thin film of Pt (thickness: 0.1 micrometers), which is used as an upper electrode material, is formed on top of the dielectric layer 24 by the sputtering method.
  • a composite oxide containing at least one of the elements including strontium (Sr), barium (Ba), lead (Pb), tin (Zr), bismuth (Bi), tantalum (Ta), titanium (Ti), magnesium (Mg), niobium (Nb), etc. may be used as the source material suitable for the dielectric layer 24 of the thin film capacitor 20 according to the present invention.
  • suitable dielectric oxide materials for the dielectric layer 24 of the thin film capacitor 20 may include Pb(Zr, Ti)O 3 , Pb(Mg, Nb)O 3 , SrBi 2 Ta 2 O 9 , Ta 2 O 5 , etc.
  • At least one of the metallic elements or the metallic oxides including platinum (Pt), gold (Au), copper (Cu), lead (Pb), ruthenium (Ru), ruthenium oxide, iridium (Ir), iridium oxide, chromium (Cr), etc. may be used as the source material suitable for the upper electrode layer 25 and the lower electrode layer 23 , which interpose the dielectric layer 24 therebetween, in the thin film capacitor 20 according to the present invention.
  • the patterning of the opening of the upper electrode layer 25 and the dielectric layer 24 is carried out by using the photolithographic method. Furthermore, the dry etching of both the Pt layer and the BST layer is performed by using the argon (Ar) ion milling.
  • the polyimide insulating layer 26 is formed, and the 0.05 micrometer thick Cr film, the 1 micrometer thick Cu film and the 10 micrometer thick Au film are laminated one by one, so that the electrode pads 22 are formed in the polyimide insulating layer 26 .
  • the outermost surfaces (Au) of the pads 22 of the thin film capacitor 20 are formed with a diameter of about 40 micrometers and a thickness of about 10 micrometers, while the outermost surfaces (Au) of the pads 12 of the IC chip 2 are formed with a thickness of about 0.2 micrometers.
  • the electrode pads 12 of the semiconductor IC chip 2 are formed similarly by laminating the 3 micrometer thick Cu film, the 2 micrometer thick Ni film and the 0.2 micrometer thick Au film one by one.
  • the back surface 21 a of the silicon wafer 21 is ground or polished so that the thickness (except for the electrode pads 22 ) of the thin film capacitor 20 containing the substrate 21 is made to about 40 micrometers. This causes the height of the capacitor 20 on the package substrate 1 to be smaller than or equal to the mounting height (bump height) of the semiconductor IC chip 2 on the package substrate 1 .
  • the thickness of the capacitor 20 including the substrate 21 and the pads 22 , is set to 50 micrometers or less.
  • the Au—Au ultrasonic joining of the electrode pads 22 of the thin film capacitor 20 and the electrode pads 12 of the semiconductor IC chip 2 attains electric connection between the electrodes of the thin film capacitor 20 and the electrodes of the semiconductor IC chip 2 , and the semiconductor device 10 of the present invention is thus produced.
  • the thickness of the thin film capacitor 20 is made to be slightly smaller than the solder bump height H of the semiconductor IC chip 2 , and the back surface 21 a of the substrate of the thin film capacitor 20 does not touch the top surface of the package substrate 1 .
  • the semiconductor device 10 When the semiconductor device 10 is used as a finished product, it is desirable to configure the semiconductor device like the above-described embodiment such that the thin film capacitor 20 may not be affected directly by the stress fluctuation of the solder junctions (bumps) of the semiconductor IC chip 2 due to temperature change. According to the above-described embodiment, the solder fatigue life can be prolonged and the reliability of electrical connection of the solder junctions can be improved.
  • the production method of the thin film capacitor 20 for use in the semiconductor device 10 of the first preferred embodiment of FIG. 3A and FIG. 3B has been described in the foregoing.
  • the thin film capacitor 20 for use in the semiconductor device 11 of the second preferred embodiment of FIG. 4 can be also produced in a similar manner.
  • the thin film capacitor 20 shown in FIG. 6A is placed upside down.
  • the Au—Au ultrasonic joining of the electrode pads 22 of the thin film capacitor 20 and the electrode pads 12 of the semiconductor IC chip 2 is performed.
  • the electrodes of the thin film capacitor 20 and the electrodes of the semiconductor IC chip 2 are joined together by the Au—Au ultrasonic joining.
  • the semiconductor device 11 of FIG. 4 is produced through the wire bonding and the resin molding.
  • the decoupling capacitor can be mounted directly on the IC chip bottom in the shortest distance near the IC chip.
  • the resistance and the inductance of the capacitor in the semiconductor device can be lowered by such configuration. Therefore, it is possible for the semiconductor device of the present invention to stabilize high-speed operation of the IC chip in the high frequency range (GHz band).
  • the semiconductor device of the present invention serves as a semiconductor package in which the height of the capacitor components is adjusted suitably. Therefore, the solder fatigue life can be prolonged and the reliability of electrical connections of solder junctions can be improved according to the semiconductor device of the present invention.

Abstract

A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-210176, filed on Jul. 18, 2002, the entire contents of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device which incorporates a semiconductor integrated circuit chip for use in electronic equipment, such as a computer. More specifically, the present invention relates to a semiconductor device in which a decoupling capacitor for power supply use is arranged in close proximity with a semiconductor integrated circuit chip in order to stabilize operation of the semiconductor integrated circuit chip at high frequencies.
  • 2. Description of the Related Art
  • A decoupling capacitor (or bypass capacitor) is commonly used with the semiconductor integrated circuit (IC) chip to reduce the noise in the power supplied to the IC chip. Advances in IC technology have increased the switching speeds employed by the recent IC devices, so that many IC chips are capable of operation at high frequencies, or microwave frequencies. High switching speeds increase the problem of power supply noise, a component of which is generated as the device is switched on and off. In order for the IC chip to function properly, the power supplied must be free from noise.
  • Use of the decoupling capacitor to alleviate the problem of power supply noise is well known. It is also well known that it is desirable to position the decoupling capacitor as close as possible to the IC chip for best effect. The leads connecting the capacitor to the IC chip have an inherent inductance which becomes significant at high speed operation, to the point that if the capacitor is positioned too far from the IC chip, the lead inductance can cancel the usefulness of the capacitor for eliminating power supply noise.
  • In a semiconductor device in which decoupling capacitors are arranged near a semiconductor integrated circuit (IC) chip as preventive measures against malfunctioning of the IC chip due to power supply noise at high frequencies, multi-layered chip capacitors have often been used as the decoupling capacitors.
  • FIG. 1 shows the structure of a semiconductor device in which multi-layered chip capacitors are mounted.
  • In the semiconductor device of FIG. 1, the semiconductor IC chip 2 is connected to the top of the package substrate 1 using BGA (ball grid array) connection, and the multi-layered chip capacitors 4 are connected to the bottom surface of the package substrate 1 via solder bumps. The package substrate 1 is also connected to the top of the circuit wiring board (mother board) 3 via solder bumps. The package substrate 1 is, for example, a multi-chip module (MCM) substrate.
  • As for the semiconductor device of FIG. 1, in order to avoid the interference of the height of the multi-layered chip capacitors 4 with the circuit wiring board 3, the portion of the circuit wiring substrate 3 where the capacitors 4 are mounted in opposing relationship to the substrate 3 must be cut through.
  • In this case the inductance between the semiconductor IC chip 2 and the capacitors 4 poses the problem of power supply noise at high frequencies.
  • The semiconductor device, such as shown in FIG. 1, requires the wiring leads within the package substrate 1 to connect the multi-layered chip capacitors 4 and the semiconductor IC chip 2, and the wiring leads within the package substrate 1 have a significant inductance when the IC chip 2 operates at high frequencies. Even if the decoupling capacitors 4 are arranged therein, the effect of suppressing the fluctuation of the power-supply voltage to the IC chip 2 during high-speed operation and the effect of absorbing the high frequency ripple are fading.
  • What is needed for suppressing the variation of the power-supply voltage to the IC chip 2 is to reduce the equivalent in-series resistance (ESR) and the equivalent in-series inductance (ESL) of the capacitors 4. Especially there is a problem in that the increase in the inductance due to the wiring leads within the package substrate 1 deteriorates the high frequency characteristics of the decoupling capacitors 4.
  • In order to overcome the problem, reduction of the inductance is attained by positioning the capacitors as close as possible to the IC chip such that the length of the wiring leads from the power supply and the ground of the IC chip to the capacitors is made shortest.
  • Japanese Laid-Open Patent Application No. 4-211191 discloses a substrate with a built-in capacitor which is formed with a thin-film dielectric layer and conductive layers on a ceramic wiring substrate. The capacitor is devised to reduce the inductance, thereby realizing reduction of the power supply noise.
  • Moreover, Japanese Laid-Open Patent Applications No. 7-176453, No. 2001-68583 and No. 2001-35990 disclose some thin-film decoupling capacitors. In such capacitor configurations, the upper surface pads of the capacitor formed on the carrier substrate having the via holes are connected to the semiconductor IC chip, and the lower surface pads are connected to the circuit wiring substrate. The capacitor configurations are provided to reduce the inductance.
  • FIG. 2A and FIG. 2B show the structure of each of conventional semiconductor devices in which the interposer with a built-in capacitor is mounted.
  • In the configuration of FIG. 2A, the semiconductor IC chip 2 is connected to the top of the package substrate 1 using BGA connection, and the interposer 5 with the built-in capacitor is connected to the bottom of the IC chip 2 using BGA connection. In the configuration, to avoid the interference between the interposer 5 and the package substrate 1, the surface portion of the package substrate 1 where the interposer 5 is mounted is cut partially.
  • In the configuration of FIG. 2B, the semiconductor IC chip 2 is connected to the top of the interpose 5 with the built-in capacitor using BGA connection, and the interposer 5 is connected to the top of the package substrate 3 using BGA connection.
  • When compared with the semiconductor device of FIG. 1, the semiconductor devices of FIG. 2A and FIG. 2B have a shorter connection distance of the IC chip and the capacitor. However, if the interposer configuration is used, the number of production processes needed to manufacture the semiconductor devices will increase, and also the technical difficulty of the production may arise. This makes the low-cost production of the semiconductor devices difficult. Moreover, the number of interconnections between the components of the semiconductor devices increases, and the problem of reliability may arise.
  • Furthermore, in the case of the configuration of FIG. 2A, because of the thickness of the capacitor itself, it is necessary to perform machining to cut partially the portion of the package substrate before the IC chip is mounted on the package substrate.
  • Conventionally, in order to position the capacitor in close proximity to the IC chip, it has been necessary to use the interposer-type chip capacitor mounted between the carrier substrate and the IC chip as shown in FIG. 2A or FIG. 2B.
  • However, to prepare the interposer-type chip capacitor, the through vias in the substrate must be formed. In order to form the through vias, it is necessary to carry out the simultaneous baking process for the conductive material and the ceramic material, or carry out the forming of through holes in the substrate such as a silicon substrate, and the filling of the conductive material into the through holes of the substrate. Therefore, the technical difficulty of the production will arise, and it is difficult to attain the low-cost production of the semiconductor devices.
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide an improved semiconductor device in which the above-described problems are eliminated.
  • Another object of the present invention is to provide a semiconductor device which is configured to position the decoupling capacitor as close as possible to the semiconductor IC chip for best effect of the decoupling capacitor, without using the interposer type configuration and the multi-layered chip capacitor configuration as in the conventional semiconductor devices.
  • The above-mentioned objects of the present invention is achieved by a semiconductor device comprising: a carrier substrate; an integrated circuit chip mounted on the carrier substrate through bumps; and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies, wherein the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.
  • In the semiconductor device of the present invention, the capacitor is formed on a substrate made of silicon or glass and having a flat and smooth surface, and the entire thickness of the capacitor is reduced by machining the back surface of the capacitor substrate. The thin film capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate, and it is possible that the capacitor be mounted in the shortest distance near the IC chip.
  • The above-mentioned objects of the present invention is also achieved by a semiconductor device comprising: a carrier substrate; an integrated circuit chip mounted on the carrier substrate; a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies; and a lead frame provided on the carrier substrate and electrically connected to the integrated circuit chip through a wire, wherein the capacitor is electrically connected to pads on the integrated circuit chip, and the capacitor is provided to have a height on the integrated circuit chip that is smaller than a height of the wire on the integrated circuit chip.
  • In the semiconductor device of the present invention, the capacitor is formed on a substrate made of silicon or glass and having a flat and smooth surface, and the entire thickness of the capacitor is reduced by machining the back surface of the capacitor substrate. The thin film capacitor is electrically connected to pads on the integrated circuit chip, and the capacitor is provided to have a height on the integrated circuit chip that is smaller than a height of the wire on the integrated circuit chip. It is possible that the capacitor be mounted in the shortest distance near the IC chip.
  • According to the semiconductor device of the present invention, the decoupling capacitor can be mounted directly on the IC chip bottom in the shortest distance near the IC chip. The resistance and the inductance of the decoupling capacitor in the semiconductor device can be lowered by such configuration. Therefore, it is possible for the semiconductor device of the present invention to stabilize high-frequency operation of the IC chip.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.
  • FIG. 1 is a diagram showing the structure of a semiconductor device in which multi-layered chip capacitors are mounted.
  • FIG. 2A and FIG. 2B are diagrams showing the structure of each of conventional semiconductor devices in which an interposer with a built-in capacitor is mounted.
  • FIG. 3A and FIG. 3B are diagrams showing the structure of a semiconductor device of the first preferred embodiment of the present invention.
  • FIG. 4 is a diagram showing the structure of a semiconductor device of the second preferred embodiment of the present invention.
  • FIG. 5 is a diagram for explaining a method of production of a thin film capacitor for use in the semiconductor device of the present invention.
  • FIG. 6A and FIG. 6B are diagrams showing the structure of the semiconductor device of the present invention in which the thin film capacitor of FIG. 5 is mounted.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • A description will now be given of preferred embodiments of the present invention with reference to the accompanying drawings.
  • FIG. 3A and FIG. 3B show the structure of a semiconductor device of the first preferred embodiment of the present invention. FIG. 3A is a cross-sectional view of the semiconductor device of the present embodiment, and FIG. 3B is an enlarged view of the semiconductor device of FIG. 3A.
  • As shown in FIG. 3A and FIG. 3B, the semiconductor device 10 includes a package substrate 1 as a carrier substrate, a semiconductor integrated circuit (IC) chip 2 mounted on the package substrate 1, and-a thin film capacitor 20 configured as a decoupling capacitor which stabilizes high-speed operation of the IC chip 2.
  • The thin film capacitor 20 is electrically connected to the electrode pads on the bottom of the IC chip 2. The thin film capacitor 20, including the capacitor substrate, is provided to have a height on the package substrate 1 that is smaller than or equal to the height H of the solder bumps of the IC chip 2 on the package substrate 1.
  • The thin film capacitor 20 in the present embodiment is provided on a substrate made of silicon or glass and having a flat and smooth surface, and an upper electrode layer and a lower electrode layer, which interpose a dielectric layer therebetween, are formed on the substrate. The entire thickness of the capacitor 20, including the pads and the substrate, is reduced to 50 micrometers or less by machining the back surface of the capacitor substrate. The capacitor 20 is electrically connected to the IC chip 2 by using the Au—Au ultrasonic joining of the pads of the capacitor 20 and the pads of the IC chip 2.
  • As shown in FIG. 3B, the solder bumps are used to mount the IC chip 2 on the package substrate 1, and the height H of the solder bumps of the IC chip 2 on the package substrate 1 is about 70 micrometers. The solder bump height H in this case is considered as containing the thickness of each electrode pad of the package substrate 1 and the IC chip 2.
  • Moreover, the thickness of each of the pads of the package substrate 1 and the pads of the IC chip 2 is about 10 micrometers. Therefore, it is possible to configure the semiconductor device 10 of the present embodiment so that the thin film capacitor 20, including the capacitor substrate, is provided to have a height on the package substrate 1 that is smaller than or equal to the height H of the solder bumps of the IC chip 2 on the package substrate 1.
  • In the present embodiment, the thin film capacitor 20 is provided with the substrate having the bottom surface that is in contact with the top surface of the package substrate 1, as shown in FIG. 3B. By this configuration, when connecting the semiconductor IC chip 2 to the package substrate 1 via the solder bumps, the solder bump height will be restricted to be in consistency with the height of the capacitor 20.
  • Since the distance between the semiconductor IC chip 2 and the package substrate 1 is specified in this manner, the spreading of the solder when the solder is melted or reflowed will be limited by the electrode pads of the IC chip 2 and the package substrate 1. By the surface tension of the solder, the solder bumps are formed into the cylindrical configuration rather than the spherical configuration.
  • For this reason, it is possible to prevent the stress concentration from arising at the solder connections between the pads of the semiconductor IC chip 2 and the pads of the package substrate 1.
  • In addition, Japanese Laid-Open Patent Application No. 57-118650 discloses that if the solder connections between the electrodes of the carrier substrate and the electrodes of the circuit component are formed into the cylindrical configuration instead of the spherical configuration when the solder is reflowed, the height of the soldered joints is increased in the same amount of the solder, and the stress by the temperature change will be distributed to the soldered joints uniformly. Therefore, according to the semiconductor device 10 of the present embodiment, the reliability of the solder connections of the circuit components can be improved.
  • FIG. 4 shows the structure of a semiconductor device of the second preferred embodiment of the present invention.
  • In the embodiment of FIG. 4, the semiconductor device 11 includes the package substrate 1 as a carrier substrate, the semiconductor IC chip 2 mounted on the package substrate 1, and the thin film capacitor 20 configured as a decoupling capacitor which stabilizes high-speed operation of the IC chip 2. The semiconductor device 11 of the present embodiment further includes a lead frame 16, wires 17, and a resin mold 18.
  • In the structure of the semiconductor device 11, the IC chip 2 and the lead frame 16 are electrically connected together by the wire bonding. After the wire bonding is performed, and the capacitor 20, the IC chip 2, the package substrate 1 and the wires 17 are enclosed in the resin mold 18.
  • In the present embodiment, the thin film capacitor 20 is electrically connected to the electrode pads on the top surface of the semiconductor IC chip 2, and the capacitor 20, including the substrate thereof, is provided to have a height H1 on the IC chip 2 that is smaller than a height H2 of the wires 17 on the IC chip 2, as shown in FIG. 4.
  • Similar to the previous embodiment of FIG. 3A and FIG. 3B, the capacitor 20 in the present embodiment is provided on a substrate made of silicon or glass and having a flat and smooth surface, and an upper electrode layer and a lower electrode layer, which interpose a dielectric layer therebetween, are formed on the substrate. The entire thickness of the capacitor 20, including the pads and the substrate, is reduced to 50 micrometers or less by machining the back surface of the capacitor substrate. The capacitor 20 is electrically connected to the IC chip 2 by using the Au—Au ultrasonic joining of the pads of the capacitor 20 and the pads of the IC chip 2.
  • As for the semiconductor device 11 of the present embodiment, it should be noted that the thin film capacitor 20 is provided to have the height H1 on the IC chip 2 that is smaller than the height H2 of the wires 17 on the IC chip 2. As shown in FIG. 4, the height of the wires 17 on the lead frame 16 is about 150 micrometers, and the semiconductor device 11 in which the capacitor 20 is mounted can be easily produced. Therefore, it is possible for the semiconductor device 11 of the present embodiment that the thin film capacitor 20 be mounted in the shortest distance near the IC chip 2.
  • Moreover, like the previous embodiment of FIG. 3A and FIG. 3B, in the semiconductor device 11 of FIG. 4, the thickness of the capacitor 20, including the substrate, is reduced to 50 micrometers or less by grinding or polishing the back surface of the silicon wafer as the capacitor substrate. In addition, the capacitor 20 is electrically connected to the IC chip 2 by using the Au—Au ultrasonic joining of the pads of the capacitor 20 and the pads of the IC chip 2. As mentioned above, the height of the wires 17 on the lead frame 17 is about 150 micrometers, and the interference of the thin film capacitor 20 when the capacitor 20 and the IC chip 2 are enclosed in the resin mold 18 can be easily avoided. Therefore, the semiconductor device 11 in which the thin film capacitor 20 is mounted can be easily produced.
  • Next, FIG. 5 is a diagram for explaining a method of production of a thin film capacitor for use in the semiconductor device of the present invention. FIG. 6A and FIG. 6B show the detailed structure of the semiconductor device of the present invention in which the thin film capacitor of FIG. 5 is mounted.
  • A description will now be given of the method of production of the thin film capacitor.
  • As shown in (a) of FIG. 5, the silicon wafer 21 is used as a carrier substrate of the thin film capacitor. Use of the silicon wafer for the capacitor substrate facilitates formation of a thin film device since the back surface of the substrate (silicon) can be easily polished. The silicone substrate does not easily break even if it is polished to a thickness of about 30 micrometers. Hence, the silicon wafer 21 is appropriate for the carrier substrate of the thin film capacitor 20 according to the present invention.
  • Moreover, if the silicon wafer 21 is used as the capacitor substrate, the coefficient of thermal expansion of the semiconductor IC chip 2 and the coefficient of thermal expansion of the thin film capacitor 20 can be kept at the almost same level. It is possible to relieve the mounting stress during production of the semiconductor device.
  • As shown in (b), (c) and (d) of FIG. 5, the respective thin films of the lower electrode layer 23, the dielectric layer 24, and the upper electrode layer 25 are formed one by one on the silicon wafer 21.
  • In the present embodiment, the silicon wafer 21 on which a silicon dioxide (SiO2) film with a thickness of 0.3 mm is formed is employed. First, the thin film of TiO2 (0.05 micrometers)/Pt (0.1 micrometers), which is used as a lower electrode material, is formed on top of the silicon wafer 21 by the sputtering method. Second, the thin film of (Ba, Sr)TiO3 (hereinafter, called BST), which is used as a highly dielectric material, is formed on top of the lower electrode layer 23 by the sputtering method within the same vacuum system. Third, the thin film of Pt (thickness: 0.1 micrometers), which is used as an upper electrode material, is formed on top of the dielectric layer 24 by the sputtering method.
  • A composite oxide containing at least one of the elements including strontium (Sr), barium (Ba), lead (Pb), tin (Zr), bismuth (Bi), tantalum (Ta), titanium (Ti), magnesium (Mg), niobium (Nb), etc. may be used as the source material suitable for the dielectric layer 24 of the thin film capacitor 20 according to the present invention. Besides (Ba, Sr)TiO3 in the above-described embodiment, suitable dielectric oxide materials for the dielectric layer 24 of the thin film capacitor 20 may include Pb(Zr, Ti)O3, Pb(Mg, Nb)O3, SrBi2Ta2O9, Ta2O5, etc.
  • Moreover, at least one of the metallic elements or the metallic oxides including platinum (Pt), gold (Au), copper (Cu), lead (Pb), ruthenium (Ru), ruthenium oxide, iridium (Ir), iridium oxide, chromium (Cr), etc. may be used as the source material suitable for the upper electrode layer 25 and the lower electrode layer 23, which interpose the dielectric layer 24 therebetween, in the thin film capacitor 20 according to the present invention.
  • Next, as indicated in (e) of FIG. 5, the patterning of the opening of the upper electrode layer 25 and the dielectric layer 24 is carried out by using the photolithographic method. Furthermore, the dry etching of both the Pt layer and the BST layer is performed by using the argon (Ar) ion milling.
  • As shown in (f) and (g) of FIG. 5, the polyimide insulating layer 26 is formed, and the 0.05 micrometer thick Cr film, the 1 micrometer thick Cu film and the 10 micrometer thick Au film are laminated one by one, so that the electrode pads 22 are formed in the polyimide insulating layer 26.
  • In order to perform the Au—Au ultrasonic joining of the electrode pads 12 of the semiconductor IC chip 2 and the electrode pads 22 as shown in FIG. 6B, the outermost surfaces (Au) of the pads 22 of the thin film capacitor 20 are formed with a diameter of about 40 micrometers and a thickness of about 10 micrometers, while the outermost surfaces (Au) of the pads 12 of the IC chip 2 are formed with a thickness of about 0.2 micrometers. The electrode pads 12 of the semiconductor IC chip 2 are formed similarly by laminating the 3 micrometer thick Cu film, the 2 micrometer thick Ni film and the 0.2 micrometer thick Au film one by one.
  • As shown in (h) of FIG. 5 and FIG. 6A, the back surface 21 a of the silicon wafer 21 is ground or polished so that the thickness (except for the electrode pads 22) of the thin film capacitor 20 containing the substrate 21 is made to about 40 micrometers. This causes the height of the capacitor 20 on the package substrate 1 to be smaller than or equal to the mounting height (bump height) of the semiconductor IC chip 2 on the package substrate 1. In the present embodiment, as shown in FIG. 6A, the thickness of the capacitor 20, including the substrate 21 and the pads 22, is set to 50 micrometers or less.
  • By applying the thus formed capacitor 20, it is possible to obtain the semiconductor device of the present embodiment in which the thin-film decoupling capacitor is mounted.
  • As shown in FIG. 6B, the Au—Au ultrasonic joining of the electrode pads 22 of the thin film capacitor 20 and the electrode pads 12 of the semiconductor IC chip 2 attains electric connection between the electrodes of the thin film capacitor 20 and the electrodes of the semiconductor IC chip 2, and the semiconductor device 10 of the present invention is thus produced.
  • In the semiconductor device 10 of the present embodiment, the thickness of the thin film capacitor 20 is made to be slightly smaller than the solder bump height H of the semiconductor IC chip 2, and the back surface 21 a of the substrate of the thin film capacitor 20 does not touch the top surface of the package substrate 1.
  • When the semiconductor device 10 is used as a finished product, it is desirable to configure the semiconductor device like the above-described embodiment such that the thin film capacitor 20 may not be affected directly by the stress fluctuation of the solder junctions (bumps) of the semiconductor IC chip 2 due to temperature change. According to the above-described embodiment, the solder fatigue life can be prolonged and the reliability of electrical connection of the solder junctions can be improved.
  • The production method of the thin film capacitor 20 for use in the semiconductor device 10 of the first preferred embodiment of FIG. 3A and FIG. 3B has been described in the foregoing. The thin film capacitor 20 for use in the semiconductor device 11 of the second preferred embodiment of FIG. 4 can be also produced in a similar manner.
  • Briefly, in a method of production of the thin film capacitor 20 for the second preferred embodiment of FIG. 4, the thin film capacitor 20 shown in FIG. 6A is placed upside down. In the inverted state of the thin film capacitor 20, the Au—Au ultrasonic joining of the electrode pads 22 of the thin film capacitor 20 and the electrode pads 12 of the semiconductor IC chip 2 is performed. The electrodes of the thin film capacitor 20 and the electrodes of the semiconductor IC chip 2 are joined together by the Au—Au ultrasonic joining. After the ultrasonic joining, the semiconductor device 11 of FIG. 4 is produced through the wire bonding and the resin molding.
  • As described in the foregoing, according to the semiconductor device of the present invention, the decoupling capacitor can be mounted directly on the IC chip bottom in the shortest distance near the IC chip. The resistance and the inductance of the capacitor in the semiconductor device can be lowered by such configuration. Therefore, it is possible for the semiconductor device of the present invention to stabilize high-speed operation of the IC chip in the high frequency range (GHz band).
  • Furthermore, the semiconductor device of the present invention serves as a semiconductor package in which the height of the capacitor components is adjusted suitably. Therefore, the solder fatigue life can be prolonged and the reliability of electrical connections of solder junctions can be improved according to the semiconductor device of the present invention.
  • The present invention is not limited to the above-described embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Claims (4)

1-2. (canceled)
3. A semiconductor device comprising:
a carrier substrate;
an integrated circuit chip mounted on the carrier substrate;
a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies; and
a lead frame provided on the carrier substrate and electrically connected to the integrated circuit chip through a wire,
wherein the capacitor is electrically connected to pads on the integrated circuit chip, and the capacitor is provided to have a height on the integrated circuit chip that is smaller than a height of the wire on the integrated circuit chip.
4-9. (canceled)
10. The semiconductor device of claim 3 further comprising a resin mold, the capacitor being enclosed in the resin mold.
US11/104,436 2002-07-18 2005-04-13 Semiconductor device with capacitor Abandoned US20050179128A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/104,436 US20050179128A1 (en) 2002-07-18 2005-04-13 Semiconductor device with capacitor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2002210176A JP4077261B2 (en) 2002-07-18 2002-07-18 Semiconductor device
JP2002-210176 2002-07-18
US10/619,483 US6894396B2 (en) 2002-07-18 2003-07-16 Semiconductor device with capacitor
US11/104,436 US20050179128A1 (en) 2002-07-18 2005-04-13 Semiconductor device with capacitor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/619,483 Division US6894396B2 (en) 2002-07-18 2003-07-16 Semiconductor device with capacitor

Publications (1)

Publication Number Publication Date
US20050179128A1 true US20050179128A1 (en) 2005-08-18

Family

ID=30437562

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/619,483 Expired - Lifetime US6894396B2 (en) 2002-07-18 2003-07-16 Semiconductor device with capacitor
US11/104,436 Abandoned US20050179128A1 (en) 2002-07-18 2005-04-13 Semiconductor device with capacitor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/619,483 Expired - Lifetime US6894396B2 (en) 2002-07-18 2003-07-16 Semiconductor device with capacitor

Country Status (2)

Country Link
US (2) US6894396B2 (en)
JP (1) JP4077261B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233061B1 (en) 2003-10-31 2007-06-19 Xilinx, Inc Interposer for impedance matching
US20080048290A1 (en) * 2006-08-23 2008-02-28 Jae-Won Han Semiconductor device and fabricating method
US20080280463A1 (en) * 2007-05-09 2008-11-13 Mercury Computer Systems, Inc. Rugged Chip Packaging
US7564130B1 (en) * 2007-07-06 2009-07-21 National Semiconductor Corporation Power micro surface-mount device package
US7566960B1 (en) * 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
US20110215460A1 (en) * 2008-07-15 2011-09-08 Infineon Technologies Ag Stacked semiconductor chips
US20110226957A1 (en) * 2010-03-16 2011-09-22 Kabushiki Kaisha Toshiba Radioactive ray detecting apparatus, method of manufacturing the same, and imaging system
US8084297B1 (en) * 2006-01-27 2011-12-27 Xilinx, Inc. Method of implementing a capacitor in an integrated circuit
US11404365B2 (en) * 2019-05-07 2022-08-02 International Business Machines Corporation Direct attachment of capacitors to flip chip dies

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005277355A (en) * 2004-03-26 2005-10-06 Sanyo Electric Co Ltd Circuit device
US7183644B2 (en) * 2004-04-26 2007-02-27 Intel Corporation Integrated circuit package with improved power signal connection
JP3961537B2 (en) * 2004-07-07 2007-08-22 日本電気株式会社 Manufacturing method of semiconductor mounting wiring board and manufacturing method of semiconductor package
US7916263B2 (en) * 2004-12-02 2011-03-29 Semiconductor Energy Laboratory Co., Ltd. Display device
US7064043B1 (en) * 2004-12-09 2006-06-20 Texas Instruments Incorporated Wafer bonded MOS decoupling capacitor
TW200735443A (en) * 2006-03-03 2007-09-16 Apogee Power Inc Compound battery set
JP3918851B2 (en) 2005-06-03 2007-05-23 株式会社村田製作所 Multilayer electronic component and method of manufacturing multilayer electronic component
JP4486553B2 (en) * 2005-06-23 2010-06-23 富士通株式会社 Electronic device having double-sided mounting circuit board with built-in capacitor
WO2007029445A1 (en) 2005-09-06 2007-03-15 Matsushita Electric Industrial Co., Ltd. Capacitor-equipped semiconductor device
JP5103724B2 (en) * 2005-09-30 2012-12-19 富士通株式会社 Manufacturing method of interposer
JP4969934B2 (en) * 2006-07-19 2012-07-04 株式会社東芝 Semiconductor device
KR100909322B1 (en) * 2007-07-02 2009-07-24 주식회사 네패스 Ultra-thin semiconductor package and manufacturing method thereof
KR100869832B1 (en) * 2007-09-18 2008-11-21 삼성전기주식회사 Package of semiconductor chip and pcb embedding it
KR100925665B1 (en) * 2007-12-10 2009-11-06 주식회사 네패스 System in package and fabrication method thereof
JP5099063B2 (en) * 2009-03-31 2012-12-12 Ｔｄｋ株式会社 Electronic component module
DE102011109338B3 (en) * 2011-08-03 2013-01-31 Dietrich Reichwein Device for storing electromagnetic energy
JP5994958B2 (en) * 2014-09-30 2016-09-21 株式会社村田製作所 Semiconductor package and its mounting structure
US9660017B2 (en) * 2015-01-20 2017-05-23 Mediatek Inc. Microelectronic package with surface mounted passive element
US9748227B2 (en) 2015-07-15 2017-08-29 Apple Inc. Dual-sided silicon integrated passive devices
US9553079B1 (en) * 2015-12-15 2017-01-24 International Business Machines Corporation Flip chip assembly with connected component
US10403560B2 (en) * 2018-09-28 2019-09-03 Intel Corporation Thermal cooling system
JP7279538B2 (en) * 2019-06-19 2023-05-23 富士フイルムビジネスイノベーション株式会社 light emitting device
US11342316B2 (en) 2020-01-16 2022-05-24 Mediatek Inc. Semiconductor package

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5442229A (en) * 1992-09-10 1995-08-15 Hitachi, Ltd. Metal lead-film carrier assembly having a plurality of film carriers, and film carrier-semiconductor chip assembly and semiconductor device containing such metal lead-film carrier assembly
US5548474A (en) * 1994-03-01 1996-08-20 Avx Corporation Electrical components such as capacitors having electrodes with an insulating edge
US6133637A (en) * 1997-01-24 2000-10-17 Rohm Co., Ltd. Semiconductor device having a plurality of semiconductor chips
US6184567B1 (en) * 1996-11-08 2001-02-06 Shinko Electric Industries Co., Ltd. Film capacitor and semiconductor package or device carrying same
US6222260B1 (en) * 1998-05-07 2001-04-24 Vlsi Technology, Inc. Integrated circuit device with integral decoupling capacitor
US6396154B1 (en) * 1999-01-29 2002-05-28 Rohm Co., Ltd Semiconductor device
US6404615B1 (en) * 2000-02-16 2002-06-11 Intarsia Corporation Thin film capacitors
US6570249B1 (en) * 2001-12-24 2003-05-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US6781247B2 (en) * 2001-10-23 2004-08-24 Rohm Co., Ltd. Semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3191529B2 (en) 1993-10-14 2001-07-23 株式会社村田製作所 Semiconductor device with ceramic capacitor and ceramic capacitor mounted
JPH09199374A (en) * 1995-11-13 1997-07-31 Shinko Electric Ind Co Ltd Thin film capacitor, package for semiconductor device mounted the capacitor, and the semiconductor device
JP3414333B2 (en) 1999-10-01 2003-06-09 日本電気株式会社 Capacitor mounting structure and method

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
US5442229A (en) * 1992-09-10 1995-08-15 Hitachi, Ltd. Metal lead-film carrier assembly having a plurality of film carriers, and film carrier-semiconductor chip assembly and semiconductor device containing such metal lead-film carrier assembly
US5548474A (en) * 1994-03-01 1996-08-20 Avx Corporation Electrical components such as capacitors having electrodes with an insulating edge
US6184567B1 (en) * 1996-11-08 2001-02-06 Shinko Electric Industries Co., Ltd. Film capacitor and semiconductor package or device carrying same
US6133637A (en) * 1997-01-24 2000-10-17 Rohm Co., Ltd. Semiconductor device having a plurality of semiconductor chips
US6222260B1 (en) * 1998-05-07 2001-04-24 Vlsi Technology, Inc. Integrated circuit device with integral decoupling capacitor
US6396154B1 (en) * 1999-01-29 2002-05-28 Rohm Co., Ltd Semiconductor device
US6404615B1 (en) * 2000-02-16 2002-06-11 Intarsia Corporation Thin film capacitors
US6781247B2 (en) * 2001-10-23 2004-08-24 Rohm Co., Ltd. Semiconductor device
US6570249B1 (en) * 2001-12-24 2003-05-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US6689636B2 (en) * 2001-12-24 2004-02-10 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method of the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233061B1 (en) 2003-10-31 2007-06-19 Xilinx, Inc Interposer for impedance matching
US7566960B1 (en) * 2003-10-31 2009-07-28 Xilinx, Inc. Interposing structure
US8062968B1 (en) 2003-10-31 2011-11-22 Xilinx, Inc. Interposer for redistributing signals
US8084297B1 (en) * 2006-01-27 2011-12-27 Xilinx, Inc. Method of implementing a capacitor in an integrated circuit
US20080048290A1 (en) * 2006-08-23 2008-02-28 Jae-Won Han Semiconductor device and fabricating method
US20080280463A1 (en) * 2007-05-09 2008-11-13 Mercury Computer Systems, Inc. Rugged Chip Packaging
US7564130B1 (en) * 2007-07-06 2009-07-21 National Semiconductor Corporation Power micro surface-mount device package
US20110215460A1 (en) * 2008-07-15 2011-09-08 Infineon Technologies Ag Stacked semiconductor chips
US8334586B2 (en) * 2008-07-15 2012-12-18 Infineon Technologies Ag Stacked semiconductor chips with separate encapsulations
US20110226957A1 (en) * 2010-03-16 2011-09-22 Kabushiki Kaisha Toshiba Radioactive ray detecting apparatus, method of manufacturing the same, and imaging system
US8912499B2 (en) * 2010-03-16 2014-12-16 Kabushiki Kaisha Toshiba Radioactive ray detecting apparatus, method of manufacturing the same, and imaging system
US11404365B2 (en) * 2019-05-07 2022-08-02 International Business Machines Corporation Direct attachment of capacitors to flip chip dies

Also Published As

Publication number Publication date
US6894396B2 (en) 2005-05-17
US20040012085A1 (en) 2004-01-22
JP2004055769A (en) 2004-02-19
JP4077261B2 (en) 2008-04-16

Similar Documents

Publication Publication Date Title
US6894396B2 (en) Semiconductor device with capacitor
JP4474431B2 (en) Semiconductor package and manufacturing method thereof
US6624501B2 (en) Capacitor and semiconductor device
US7046501B2 (en) Capacitor-embedded substrate
JP4606849B2 (en) Semiconductor chip package having decoupling capacitor and manufacturing method thereof
US8810007B2 (en) Wiring board, semiconductor device, and method for manufacturing wiring board
US8097954B2 (en) Adhesive layer forming a capacitor dielectric between semiconductor chips
US8179689B2 (en) Printed circuit board, method of fabricating printed circuit board, and semiconductor device
US20080099888A1 (en) Semiconductor device, method of manufacturing the same
JP2004128219A (en) Semiconductor device with additional function and its manufacturing method
JP2004079701A (en) Semiconductor device and its manufacturing method
WO2004047167A1 (en) Semiconductor device, wiring substrate, and method for manufacturing wiring substrate
JP2001326305A (en) Interposer for semiconductor device, its manufacturing method, and semiconductor device
US8669643B2 (en) Wiring board, semiconductor device, and method for manufacturing wiring board
JP4330367B2 (en) INTERPOSER, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE
US20060258048A1 (en) Integrated capacitor for wafer level packaging applications
JP3691995B2 (en) Semiconductor package, manufacturing method thereof, and semiconductor device
TWI447871B (en) Apparatus for connecting integrated circuit chip to power and ground circuits
US6683781B2 (en) Packaging structure with low switching noises
JP4538473B2 (en) Semiconductor device
JP4738228B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP4084255B2 (en) Probe card
JP2005302873A (en) Semiconductor device, method for manufacturing the same and electronic apparatus
JP2003332515A (en) Semiconductor integrated circuit device and its manufacturing method
JP3735986B2 (en) Multichip module and manufacturing method thereof

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION