US20050164609A1 - Reducing wafer defects from chemical mechanical polishing - Google Patents

Reducing wafer defects from chemical mechanical polishing Download PDF

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Publication number
US20050164609A1
US20050164609A1 US10/762,849 US76284904A US2005164609A1 US 20050164609 A1 US20050164609 A1 US 20050164609A1 US 76284904 A US76284904 A US 76284904A US 2005164609 A1 US2005164609 A1 US 2005164609A1
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setting
integrated circuit
margin
voltage level
signal lines
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US10/762,849
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Matthew Prince
Shaestagir Chowdhury
Brian Weselak
Jim Xu
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Intel Corp
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Intel Corp
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Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOWDHURY, SHAESTAGIR, PRINCE, MATTHEW, WESELAK, BRIAN, XU, JIM
Publication of US20050164609A1 publication Critical patent/US20050164609A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Definitions

  • This invention relates generally to processes for manufacturing semiconductor integrated circuits.
  • a copper metal line may be defined within a trench.
  • a trench is first formed in an interlayer dielectric.
  • a layer of a barrier material, such as tantalum, is then deposited.
  • a copper seed layer is deposited over the barrier layer and the copper may be electroplated thereafter onto the seed layer.
  • the entire structure may then be chemical mechanical polished (CMP) down to the dielectric material, thereby defining a copper line within the trench.
  • CMP chemical mechanical polished
  • tantalum barrier layer polishing involves the use of slurries including silica.
  • the silica preferentially removes tantalum while reducing any damage to dielectric and copper surfaces.
  • the silica abrasive, used for tantalum barrier layer polishing includes silica particles on the order of a couple hundred nanometers suspended in a basic pH solution.
  • FIG. 1 is an enlarged cross-sectional view of one embodiment of the present invention
  • FIG. 2 is an enlarged cross-sectional view at a subsequent stage
  • FIG. 3 is a graph of normalized clustered defects versus tantalum slurry by age.
  • a structure 10 may include a semiconductor wafer 12 covered by a first layer of dielectric 14 .
  • the dielectric layer 16 may be a low dielectric constant dielectric material and may have a trench 22 defined therein.
  • the dielectric 16 may be covered by a barrier layer 18 , including tantalum or tantalum containing compounds.
  • the barrier layer 18 may be covered by a copper seed layer, in turn covered by an electroplated copper layer 20 .
  • Chemical mechanical polishing is utilized to polish the structure shown in FIG. 1 from the top down, through the upper horizontal layer of barrier layer 18 .
  • the polishing produces the structure shown in FIG. 2 , having a planarized surface 24 and defining the copper line 20 encased in the barrier layer 18 .
  • the slurry involves a fluid mixture including silica and basic pH solution in one embodiment.
  • the inventors of the present invention noticed that the number of defects that were detected after chemical mechanical polishing of tantalum barrier layers were variable.
  • the inventors were able to discover that a determinant of the number of defects was the age of the silica slurry used in polishing. In other words, the younger or less old the silica slurry, the higher the number of defects.
  • slurry age it is intended to refer to the age defined as manufacture date of the slurry minus date of use. It was determined that silica slurries with ages of greater than fifty days resulted in less defects when used to chemical mechanical polish tantalum containing barrier layers.
  • the sufficiently aged slurries have softened silica particle agglomerations in a basic solution. This softening reduces the impact of large particle count defects.
  • the slurry may be more shear sensitive when the age is under fifty days. When the slurry is shear sensitive, large particle count defects can form during polish or slurry delivery due to shear effects. It is also possible that the particle size distribution also decreases with age.
  • aged chemical mechanical polishing slurries for other applications should likewise benefit from aging.
  • alumina and ceria slurries may benefit from aging, as do the silica slurries.
  • polishing metals other than tantalum and in polishing other materials, including oxides a benefit may be obtained from the use of aged slurries.

Abstract

Tantalum barrier layer chemical mechanical polishing may be improved by using suitably aged slurries. Slurries that are older than fifty days from their manufacture date result in significantly lower occurrences of defects.

Description

    BACKGROUND
  • This invention relates generally to processes for manufacturing semiconductor integrated circuits.
  • In the damascene process, a copper metal line may be defined within a trench. A trench is first formed in an interlayer dielectric. A layer of a barrier material, such as tantalum, is then deposited. A copper seed layer is deposited over the barrier layer and the copper may be electroplated thereafter onto the seed layer. The entire structure may then be chemical mechanical polished (CMP) down to the dielectric material, thereby defining a copper line within the trench.
  • Generally, tantalum barrier layer polishing involves the use of slurries including silica. The silica preferentially removes tantalum while reducing any damage to dielectric and copper surfaces. Generally the silica abrasive, used for tantalum barrier layer polishing, includes silica particles on the order of a couple hundred nanometers suspended in a basic pH solution.
  • Thus, there is a need for better ways to perform barrier layer chemical mechanical polishing to reduce the number of defects.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an enlarged cross-sectional view of one embodiment of the present invention;
  • FIG. 2 is an enlarged cross-sectional view at a subsequent stage; and
  • FIG. 3 is a graph of normalized clustered defects versus tantalum slurry by age.
    • DETAILED DESCRIPTION
  • Referring to FIG. 1, in the damascene process, a structure 10 may include a semiconductor wafer 12 covered by a first layer of dielectric 14. The dielectric layer 16 may be a low dielectric constant dielectric material and may have a trench 22 defined therein. The dielectric 16 may be covered by a barrier layer 18, including tantalum or tantalum containing compounds. The barrier layer 18 may be covered by a copper seed layer, in turn covered by an electroplated copper layer 20.
  • Chemical mechanical polishing is utilized to polish the structure shown in FIG. 1 from the top down, through the upper horizontal layer of barrier layer 18. The polishing produces the structure shown in FIG. 2, having a planarized surface 24 and defining the copper line 20 encased in the barrier layer 18. The slurry involves a fluid mixture including silica and basic pH solution in one embodiment.
  • The inventors of the present invention noticed that the number of defects that were detected after chemical mechanical polishing of tantalum barrier layers were variable. The inventors were able to discover that a determinant of the number of defects was the age of the silica slurry used in polishing. In other words, the younger or less old the silica slurry, the higher the number of defects. By slurry age, it is intended to refer to the age defined as manufacture date of the slurry minus date of use. It was determined that silica slurries with ages of greater than fifty days resulted in less defects when used to chemical mechanical polish tantalum containing barrier layers.
  • Without limitation, it is believed that the sufficiently aged slurries have softened silica particle agglomerations in a basic solution. This softening reduces the impact of large particle count defects. In addition, the slurry may be more shear sensitive when the age is under fifty days. When the slurry is shear sensitive, large particle count defects can form during polish or slurry delivery due to shear effects. It is also possible that the particle size distribution also decreases with age.
  • Generally the types of defects observed in young slurries include gouges in the copper and in dielectric films between copper lines. These defects adversely affect the next layer topography and generate metal shorts at the next layer. In addition, these detects create an electromigration concern.
  • Referring to FIG. 3, it is seen that after the slurry has been aged by fifty days, the number of normalized defects during chemical mechanical polishing of tantalum containing barrier layers using silica slurries decreases significantly.
  • For the same reasons, aged chemical mechanical polishing slurries for other applications should likewise benefit from aging. For example, alumina and ceria slurries may benefit from aging, as do the silica slurries. Similarly, in polishing metals other than tantalum and in polishing other materials, including oxides, a benefit may be obtained from the use of aged slurries.
  • While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (31)

1. (canceled)
2. An integrated circuit device, comprising:
a transmitter circuit including an output driver to synchronously output data with respect to a clock signal onto one or more external signal lines coupled to the transmitter circuit; and
a first register to store a first value representative of a transmit signal setting of the output driver, wherein the first value is determined in accordance with a configuration of one or more memory devices coupled to the one or more external signal lines and the transmit signal setting adjusts a transmit margin of the data.
3. The integrated circuit device of claim 2, wherein the transmit signal setting is selected from the group consisting of a high voltage level, a low voltage level, a reference voltage between the high voltage level and the low voltage level, a voltage asymmetry, a voltage swing, a current swing, a slew rate, an equalization setting to compensate for a residual signal on the one or more external signal lines, an equalization setting to compensate for a cross-coupled signal on the one or more external signal lines and a timing offset.
4. The integrated circuit device of claim 2, wherein the configuration is determined by accessing a supplemental memory device.
5. The integrated circuit memory device of claim 4, wherein the supplemental memory device comprises a serial presence detect memory device.
6. The integrated circuit memory device of claim 5, wherein the serial presence detect memory device is associated with a memory module coupled to the one or more external signal lines, wherein the memory module includes one or more memory devices.
7. The integrated circuit memory device of claim 2, wherein the integrated circuit device is configured to use a serial chain technique to determine the configuration of the one or more memory devices coupled to the one or more external signal lines, wherein positions of the one or memory devices on the one or more external signal lines are determined in order of closest to furthest from the integrated circuit device.
8. The integrated circuit device of claim 2, wherein the transmit margin comprises a voltage margin.
9. The integrated circuit device of claim 2, wherein the transmit margin comprises a timing margin.
10. The integrated circuit device of claim 2, wherein the configuration includes positions of one or more memory modules along the one or more external signal lines, the one or more memory modules including one or more memory devices.
11. The integrated circuit device of claim 2, wherein the configuration of the one or more memory devices includes positions of the one or more memory devices along the one or more external signal lines.
12. The integrated circuit device of claim 2, further comprising:
an input receiver coupled to the one or more external signal lines, wherein the input receiver samples data at a sample time with respect to the clock signal; and
a second register to store a second value representative of a receive signal setting of the input receiver, wherein the second value is determined in accordance with the configuration of the one or more memory devices coupled to the one or more external signal lines and the receive signal setting adjusts a receive margin of the data.
13. The integrated circuit device of claim 12, wherein the receive signal setting is selected from the group consisting of a high voltage level, a low voltage level, a reference voltage between the high voltage level and the low voltage level, a voltage asymmetry, a voltage swing, a threshold voltage, a current swing, a slew rate, an equalization setting to compensate for a residual signal on the one or more external signal lines, an equalization setting to compensate for a cross-coupled signal on the one or more external signal lines and a timing offset.
14. The integrated circuit device of claim 12, wherein the receive margin comprises a voltage margin.
15. The integrated circuit device of claim 12, wherein the receive margin comprises a timing margin.
16. A system comprising:
an integrated circuit device, the integrated circuit device including:
a first transmitter circuit including a first output driver to synchronously output data with respect to a first clock signal onto one or more external signal lines coupled to the first transmitter circuit; and
a first register to store a first value representative of a transmit signal setting of the first output driver, wherein the first value is determined in accordance with a configuration of one or more memory devices coupled to the one or more external signal lines and the transmit signal setting of the first output driver adjusts a transmit margin of the data; and
a memory device coupled to the one or more external signal lines, the memory device including:
a first input receiver, wherein the first input receiver samples data at a sample time with respect to a second clock signal; and
a second register to store a second value representative of a receive signal setting of the first input receiver, wherein the second value is determined in accordance with a configuration of the memory device and the integrated circuit device, and the receive signal setting of the first input receiver adjusts a receive margin of the data.
17. The system of claim 16, wherein the transmit signal setting of the first output driver is selected from the group consisting of a high voltage level, a low voltage level, a reference voltage between the high voltage level and the low voltage level, a voltage asymmetry, a voltage swing, a current swing, a slew rate, an equalization setting to compensate for a residual signal on the one or more external signal lines, an equalization setting to compensate for a cross-coupled signal on the one or more external signal lines and a timing offset.
18. The system of claim 16, wherein the configuration of the memory device is determined by accessing a supplemental memory device.
19. The system of claim 18, wherein the supplemental memory device comprises a serial presence detect memory device in the memory device.
20. The system of claim 16, wherein the transmit margin comprises a voltage margin.
21. The system of claim 16, wherein the transmit margin comprises a timing margin.
22. The system of claim 16, wherein the first value in the first register and the second value in the second register are complementary to one another such that increased margin associated with the transmit signal setting of the first output driver and the receive signal setting of the first input receiver do not substantially duplicate one another.
23. The system of claim 16, wherein the receive signal setting of the first input receiver is selected from the group consisting of a high voltage level, a low voltage level, a reference voltage between the high voltage level and the low voltage level, a voltage asymmetry, a voltage swing, a threshold voltage, a current swing, a slew rate, an equalization setting to compensate for a residual signal on the one or more external signal lines, an equalization setting to compensate for a cross-coupled signal on the one or more external signal lines and a timing offset.
24. The system of claim 16, wherein the receive margin comprises a voltage margin.
25. The system of claim 16, wherein the receive margin comprises a timing margin.
26. The system of claim 16, wherein the configuration comprises a position of the memory device along the one or more external signal lines.
27. The system of claim 16, the memory device further including:
a second transmitter circuit including a second output driver to synchronously output data with respect to the second clock signal onto the one or more external signal lines coupled to the second transmitter circuit; and
a third register to store a third value representative of a transmit signal setting of the second output driver, wherein the third value is determined in accordance with the configuration of the memory devices and the integrated circuit device, and the transmit signal setting of the second output driver adjusts the transmit margin of the data.
28. The system of claim 27, wherein the transmit signal setting of the second output driver is selected from the group consisting of a high voltage level, a low voltage level, a reference voltage between the high voltage level and the low voltage level, a voltage asymmetry, a voltage swing, a current swing, a slew rate, an equalization setting to compensate for a residual signal on the one or more external signal lines, an equalization setting to compensate for a cross-coupled signal on the one or more external signal lines and a timing offset.
29. The system of claim 27, the integrated circuit device further including:
a second input receiver, wherein the second input receiver samples data at a sample time with respect to the first clock signal; and
a fourth register to store a fourth value representative of a receive signal setting of the second input receiver, wherein the fourth value is determined in accordance with a configuration of the memory device and the integrated circuit device, and the receive signal setting of the second input receiver adjusts the receive margin of the data.
30. The system of claim 29, wherein the receive signal setting of the second input receiver is selected from the group consisting of a high voltage level, a low voltage level, a reference voltage between the high voltage level and the low voltage level, a voltage asymmetry, a voltage swing, a threshold voltage, a current swing, a slew rate, an equalization setting to compensate for a residual signal on the one or more external signal lines, an equalization setting to compensate for a cross-coupled signal on the one or more external signal lines and a timing offset.
31. The system of claim 29, wherein the third value in the third register and the fourth value in the fourth register are complementary to one another such that increased margin associated with the transmit signal setting of the second output driver and the receive signal setting of the second input receiver do not substantially duplicate one another.
US10/762,849 2004-01-22 2004-01-22 Reducing wafer defects from chemical mechanical polishing Abandoned US20050164609A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040185049A1 (en) * 2003-01-31 2004-09-23 Christopher Hunter Methods for modulating an inflammatory response

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3053646A (en) * 1960-07-15 1962-09-11 Dow Chemical Co Grinding and polishing compositions and method of making same
US3715842A (en) * 1970-07-02 1973-02-13 Tizon Chem Corp Silica polishing compositions having a reduced tendency to scratch silicon and germanium surfaces
US5916855A (en) * 1997-03-26 1999-06-29 Advanced Micro Devices, Inc. Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films
US20020028632A1 (en) * 2000-07-19 2002-03-07 Hajime Shimamoto Polishing composition and manufacturing and polishing methods
US20040020134A1 (en) * 2000-10-12 2004-02-05 Sang-Yong Kim Cmp slurry composition and a method for planarizing semiconductor device using the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3053646A (en) * 1960-07-15 1962-09-11 Dow Chemical Co Grinding and polishing compositions and method of making same
US3715842A (en) * 1970-07-02 1973-02-13 Tizon Chem Corp Silica polishing compositions having a reduced tendency to scratch silicon and germanium surfaces
US5916855A (en) * 1997-03-26 1999-06-29 Advanced Micro Devices, Inc. Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films
US20020028632A1 (en) * 2000-07-19 2002-03-07 Hajime Shimamoto Polishing composition and manufacturing and polishing methods
US20040020134A1 (en) * 2000-10-12 2004-02-05 Sang-Yong Kim Cmp slurry composition and a method for planarizing semiconductor device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040185049A1 (en) * 2003-01-31 2004-09-23 Christopher Hunter Methods for modulating an inflammatory response

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Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PRINCE, MATTHEW;CHOWDHURY, SHAESTAGIR;WESELAK, BRIAN;AND OTHERS;REEL/FRAME:014923/0581

Effective date: 20031217

STCB Information on status: application discontinuation

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