KR20020081663A - Fabrication method of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To reduce microscratches due to chemical-mechanical polishing. CONSTITUTION: Polishing slurry S right before supplied to the space between a polishing pad 102 and the polished surface of a wafer 1 is diluted with pure water. The polishing slurry S is thus diluted with the pure water and increased in amount to decrease the density of cohering particles in the polishing slurry S. The mixing rate of the polishing slurry S and pure water is about 1 (polishing slurry):(1 to 1.2) (pure water), and the silica density of the polishing slurry S diluted is adjusted to 3 to 9 wt.%, preferably 4 to 8 wt.%, and more preferably about 8 wt.%.

Description

Manufacturing method of semiconductor integrated circuit device {FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device including a step of polishing a thin film formed on a surface of a semiconductor wafer by using chemical mechanical polishing (CMP). A technique effective for application in the manufacture of

One of the fine processing techniques for high integration and high performance of semiconductor integrated circuits (LSI) is chemical mechanical polishing, for example, the formation of device isolation grooves called SGI (Shallow Groove Isolation), and the formation of interlayer insulating films in a multilayer wiring process. It is used for planarization, formation of buried metal wiring, and the like. This chemical mechanical polishing technique is described in, for example, US Patent No.4944836.

The chemical mechanical polishing method is a method of polishing a surface of a wafer while supplying a polishing slurry onto a surface to which a polishing pad containing a hard resin is bonded. As the polishing slurry, silica (silicon oxide) or the like is generally used. The abrasive fine particles of the present invention are dispersed in pure water, and an alkali for adjusting pH is added thereto.

However, when the wafer is polished with a polishing slurry containing silica, coarse aggregated silica particles in the slurry cause micro scratches on the surface of the wafer, resulting in a decrease in the production yield and reliability of the LSI. Is being pointed out.

Japanese Patent Laid-Open No. 10-321588 discloses one method for preventing micro scratches from occurring on a surface of a wafer due to agglomerated particles. According to this publication, generally, in a chemical mechanical polishing process, pure water is supplied to a polishing pad to maintain a wet state continuously. During the polishing step, the wafer is polished while the polishing slurry is supplied to the polishing pad moistened with pure water. By the way, the pH of the polishing slurry containing silica is about 10-11, and the pH of pure water is 7. Therefore, when the polishing slurry is supplied to the polishing pad moistened with pure water, coarse aggregated silica particles are generated in the polishing slurry due to a large pH difference between the polishing slurry and pure water, which causes micro scratches on the surface of the wafer.

Therefore, the above publication proposes a method of soaking the polishing pad with a pure liquid mixture pH adjusted to have the same pH as the polishing slurry in advance, and then supplying the polishing slurry to the polishing pad. Moreover, the method of manufacturing the mixture which mixed the pH adjusted pure liquid mixture and polishing slurry in predetermined ratio, and supplying this to a polishing pad is also proposed. When an alkaline substance is used as the polishing slurry, an alkaline reagent is used as the pH adjusting reagent, and when an acidic substance is used as the polishing slurry, an acidic reagent is used as the pH adjusting reagent. When using an alkaline polishing slurry containing silica, KOH or NH ₄ OH is preferred as a reagent for pH adjustment.

In recent years, in order to promote the miniaturization of devices and the multilayering of wirings, the LSI performs chemical mechanical polishing in various processes of the wafer process. For example, in the step of forming an element isolation groove in the main surface of the wafer, firstly, the main surface of the wafer is dry-etched using an oxidizing resistant insulating film as a mask to form a groove in the element isolation region, and then the inside of the groove is formed. After depositing a silicon oxide film having a film thickness thicker than the depth of the groove on the main surface of the wafer, the silicon oxide film is chemically mechanically polished using the oxidizing insulating film as a polishing stopper, and the silicon oxide film is formed inside the groove. Selective leaving in to form device isolation grooves.

In the chemical mechanical polishing process as described above, a polishing slurry in which silica particles are dispersed in water is generally used. Since silica has hydrophilic silanol groups (Si-OH) on its surface, when the silica particles are dispersed in water, the silica particles (1) may be formed by hydrogen bonding between the particles of the silanol groups or by van der Waals forces. Agglomeration of primary particles) occurs, and aggregated particles (secondary particles) having a larger particle size (diameter of particles) than single particles are formed. Therefore, in the abrasive slurry which disperse | distributed silica particle (dispersion substance) with water (dispersion medium), this aggregated particle comprises the abrasive grain component.

The agglomerated particles have no problem when their particle diameters are relatively small. By the way, in the actual polishing slurry, there are coarse agglomerated particles having a particle size of 1 μm or more (in the present invention, agglomerated particles having a particle size of 1 μm or more are particularly referred to as “coarse agglomerated particles”). It causes minor damage, called "degradation", which leads to a decrease in yield and reliability. For example, when the silicon oxide film is chemically mechanically polished by using the oxidizing insulating film as a polishing stopper in the above-described step of forming the element isolation groove, if a small scratch occurs on the surface of the oxidizing insulating film, a part of the underlying silicon substrate To reach, giving damage to its surface.

As a method of removing coarse aggregated particles in the polishing slurry, the method of filtering the polishing slurry is also effective to some extent. However, since the agglomeration starts again when the polishing slurry from which the aggregated particles have been removed is left, it is not a fundamental countermeasure.

Therefore, the present inventors have already proposed a method for preventing micro scratches from occurring on the surface of a wafer by aggregated particles (Japanese Patent Application No. 2000-145379). In such a method, agglomerated silica particles having a particle size of 1 μm or more contained in the polishing slurry are left in the polishing slurry by leaving the polishing slurry in a stopped state for a period of time prior to the step of supplying the polishing slurry to the target surface of the wafer to perform a chemical mechanical polishing process. The concentration of is 200,000 / 0.5cc, preferably 50,000 / 0.5cc, or less, and more preferably 20,000 / 0.5cc or less.

The above method proposed by the present inventors can very effectively reduce the concentration of coarse agglomerated silica particles contained in the polishing slurry. However, since the stop standing period is not necessarily constant due to variations in the production lot of the polishing slurry, the concentration of coarse aggregated silica particles may not be sufficiently reduced by this method alone.

An object of the present invention is to provide a technique capable of reducing the density of agglomerated particles in a polishing slurry used in a chemical mechanical polishing process.

Another object of the present invention is to provide a chemical mechanical polishing technique capable of reducing microscratches.

Another object of the present invention is to provide a technique capable of suppressing a decrease in yield and reliability of an integrated circuit device resulting from microscratches in a chemical mechanical polishing process.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of an essential part of a silicon substrate, showing a method for manufacturing a semiconductor integrated circuit device as one embodiment of the present invention.

Fig. 2 is a cross sectional view of an essential part of a silicon substrate, showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

3 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

4 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

Fig. 5 is a sectional view of principal parts of a silicon substrate, illustrating a method for manufacturing a semiconductor integrated circuit device as one embodiment of the present invention.

Fig. 6 is a cross sectional view of principal parts of a silicon substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

7 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

8 is a schematic view showing a processing unit of a chemical mechanical polishing apparatus used for chemical mechanical polishing of a silicon oxide film.

FIG. 9 is a schematic view showing a slurry supply pipe of the chemical mechanical polishing apparatus shown in FIG. 8. FIG.

Fig. 10 is a sectional view of principal parts of a silicon substrate, illustrating a method for manufacturing a semiconductor integrated circuit device as one embodiment of the present invention.

11 is a graph showing the results of evaluating the relationship between scratch defect density and polishing slurry concentration.

12A and 12B are graphs showing the results of evaluating the relationship between scratch defect density and polishing slurry concentration.

13 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

14 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

Fig. 15 is a sectional view of principal parts of a silicon substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

Fig. 16 is a cross sectional view of a main portion of a silicon substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

17 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

18 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

Fig. 19 is a sectional view of principal parts of a silicon substrate, showing a method for manufacturing a semiconductor integrated circuit device as one embodiment of the present invention.

20 is an essential part cross sectional view of a silicon substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

21 is an essential part cross sectional view of a silicon substrate showing a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention;

Fig. 22 is a sectional view of principal parts of a silicon substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

1: silicon substrate (wafer)

2. 6, 7, 10, 17, 21, 24, 28: silicon oxide film

3, 13, 15, 27: silicon nitride film

4: photoresist film

5: Device isolation groove

5a, 29: home

8: photoresist film

9: p-type well

11: gate oxide film

12: gate electrode

14: n-type semiconductor region (source, drain)

16: spin on glass film

18, 19: contact hole

20, 23, 26: plug

22, 25: through hole

30: lower electrode

31: capacitive insulating film

32: upper electrode

100: chemical mechanical polishing device

101: surface plate

102: Polishing Pad

103: wafer carrier

104: Retaining Ring

105: slurry feed pipe

105a, 105b: piping

106: membrane

107: Dresser

BL: Bit line

C: capacitive element for information storage

Qs: MISFET for memory cell selection

S: Polishing Slurry

WL: word line

Among the inventions disclosed herein, a typical but brief description is as follows.

The manufacturing method of the semiconductor integrated circuit device which is one invention of this application is a process of (a) preparing the polishing slurry which has a stable dispersion state, (b) the process of diluting the said polishing slurry with the aqueous solution which uses pure water as a main component, (c) The process of carrying out a chemical mechanical polishing process is supplied to the to-be-processed surface of the wafer which flows a mass-production process, immediately after diluting with the said aqueous solution, and performing a chemical mechanical polishing process.

In addition, in the present application, chemical mechanical polishing (CMP) generally refers to the surface to be moved relatively while feeding the polishing slurry while the surface to be polished is brought into contact with a polishing pad including a sheet material such as a relatively soft cloth. To perform polishing.

The polishing slurry generally refers to a liquid colloidal suspension (suspension) in which abrasive fine particles (dispersant) are blended with water and a chemical etching agent (dispersion medium). In addition, abrasive fine particles generally refer to fine particles such as silica, cerium oxide, zirconia and alumina.

The polishing planarization insulating film isolation groove refers to an element isolation groove formed by selectively leaving an insulating film whose surface is flattened by a chemical mechanical polishing process inside the groove. Therefore, the element isolation groove formed by simply depositing an insulating film inside the groove does not correspond to the polishing planarization insulating film isolation groove described herein. For example, an element isolation groove generally called SGI (Shallow Groove Isolation), STI (Shallow Trench Isolation), or the like corresponds to the polishing planarization insulating film isolation groove.

Deionized water is intended to include an aqueous solution, a chemical liquid, etc., in which pure water is a main component, in addition to water used as "pure water" in a semiconductor manufacturing process.

In the present application, the mass production process in a wafer line means a case where the throughput per day of a specific chemical mechanical polishing apparatus used in the wafer line is at least 25 sheets or more than 50 sheets, more generally 100 sheets or more in terms of 8 inch wafers. I say it. Moreover, of course, this limit wafer number is inversely proportional to the area of a wafer.

In addition, in the following embodiment, when it is necessary for the convenience, it divides and explains in several sections or embodiment, However, Except as specifically indicated, these are not mutually independent and one side is part or all of the other. It relates to modifications, details, supplementary explanations, and the like.

In addition, in the following examples, when referring to the number of elements (including number, numerical value, amount, range, etc.), except when specifically stated and in principle, except when explicitly limited to a specific number, It is not limited to the specific number, It may be more than a specific number or may be the following. In addition, in the following embodiment, the component (including an element step etc.) is not necessarily essential except the case where it specifically states and when it thinks that it is indispensable in principle.

Similarly, in the following embodiments, when referring to the shape, positional relationship, or the like of a component, substantially similar to or similar to the shape, etc., except in the case where it is specifically stated and when it is not obviously considered in principle. It shall be included. This also applies to the above numerical values and ranges.

In addition, in the present application, a semiconductor integrated circuit device is not only made on a single crystal silicon substrate but also a silicon on insulator (SOI) substrate or a thin film transistor (TFT) except when the purpose is not specifically stated. It shall include what is made on other board | substrates, such as the board | substrate for liquid crystal manufacture. In addition, a wafer means the single crystal silicon substrate (generally disk type), SOI substrate, glass substrate, other insulation, semi-insulation, a semiconductor substrate, etc. which were used for manufacture of a semiconductor integrated circuit device, or these combined.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the whole figure for demonstrating an Example, the same code | symbol is attached | subjected to the same member and the repeated description is abbreviate | omitted.

<First Embodiment>

A method of manufacturing a DRAM (Dynamic Random Access Memory), which is an embodiment of the present invention, will be described in the process order with reference to FIGS. 1 to 22.

First, as shown in FIG. 1, a substrate (wafer: 1) made of p-type single crystal silicon having a resistivity of about 1 to 10 OMEGA cm, for example, is thermally oxidized at about 850 DEG C, and has a film thickness of 10 nm on its surface. After forming a thin silicon oxide film 2 of a degree, a silicon nitride film (oxidized oxide film 3) having a thickness of about 120 nm is deposited on the silicon oxide film 2 by CVD.

The silicon nitride film 3 is used as a mask when etching the substrate 1 in the element isolation region to form grooves. In addition, since the silicon nitride film 3 has a property of being hard to be oxidized, it is used as a mask for preventing the surface of the lower substrate 1 from being oxidized. The silicon oxide film 2 in the lower portion of the silicon nitride film 3 relieves the stress generated at the interface between the substrate 1 and the silicon nitride film 3, and due to this stress is applied to the surface of the substrate 1. It is formed to prevent the occurrence of defects such as dislocations.

Next, as shown in FIG. 2, after selectively removing the silicon nitride film 3 and the silicon oxide film 2 in the lower portion of the device isolation region by dry etching using the photoresist film 4 as a mask, As shown in FIG. 3, the groove | channel 5a about 350 nm in depth is formed in the board | substrate 1 of an element isolation area | region by the dry etching which used the silicon nitride film 3 as a mask.

Next, after removing the photoresist film 4, as shown in FIG. 4, the substrate 1 is thermally oxidized at about 800 to 1000 ° C., whereby the inner wall of the groove 5a is about 10 nm thick. A thin silicon oxide film 6 is formed. The silicon oxide film 6 recovers the damage of the dry etching on the inner wall of the groove 5a, and the silicon oxide film 7 and the substrate 1 that are embedded in the groove 5a in a later step. It is formed to relieve stress generated at the interface with the.

Next, as shown in FIG. 5, the silicon oxide film 7 is deposited by the CVD method on the substrate 1 including the inside of the groove 5a. The silicon oxide film 7 is deposited to a film thickness (for example, about 500 to 600 nm) thicker than the depth of the groove 5a, and the inside of the groove 5a is buried without gaps in the silicon oxide film 7. Do it. The silicon oxide film 7 is, for example, the same as the silicon oxide film (hereinafter referred to as p-TEOS film) formed by plasma CVD using oxygen and tetraethoxysilane ((C ₂ H ₅ ) ₄ Si). The film has a good step coverage (step coverage).

Next, by thermally oxidizing the substrate 1 at about 1000 ° C., a densification (sintering) treatment for improving the film quality of the silicon oxide film 7 embedded in the grooves 5a is performed, as shown in FIG. 6. Similarly, the silicon oxide film 7 on the silicon nitride film 3 is dry-etched using the photoresist film 8 formed on the groove 5a as a mask. This dry etching is performed in order to make the height of the surface of the silicon oxide film 7 almost the same on the upper part of the groove 5a and the upper part of the silicon nitride film 3.

Next, as shown in FIG. 7, after removing the photoresist film 8 on the silicon oxide film 7, the silicon oxide film 7 is subjected to chemical mechanical polishing in the following manner.

8 is a schematic view showing a processing unit of the chemical mechanical polishing apparatus 100 used for polishing the silicon oxide film 7. As shown in the drawing, the processing unit of the chemical mechanical polishing apparatus 100 is provided with a surface plate 101 for polishing a wafer (substrate 1) in a single sheet method.

The surface plate 101 is driven to rotate in a horizontal plane by a drive mechanism (not shown). Further, the polishing pad 102 made of a synthetic resin such as polyurethane having a large number of pores is adhered to the upper surface of the surface plate 101.

Above the surface plate 101 is provided a wafer carrier 103 which is vertically moved by a driving mechanism (not shown) and rotates in a horizontal plane. The wafer 1 is held downward with its main surface (finished surface) by a retainer ring 104 and a membrane 106 provided at the lower end of the wafer carrier 103. The polishing pad 102 is pressed by the load of. Between the surface of the polishing pad 102 and the surface to be polished of the wafer 1, the polishing slurry S is supplied through the slurry supply pipe 105, and the surface to be polished of the wafer 1 is chemically and mechanically polished.

Moreover, above the surface plate 101, the dresser 107 which moves up and down and rotates in the horizontal plane by the drive mechanism which is not shown in figure is provided. A backing material electrodeposited with diamond particles is attached to the lower end of the dresser 107, and the surface of the polishing pad 102 is covered with this substrate in order to prevent clogging caused by abrasive grains. Are cut regularly.

Polishing slurry S As used herein, by dispersing the fumed silica (Fumed Silica) the abrasive grains component in water, to adjust the pH by the addition of ammonium hydroxide (NH ₄ OH). This polishing slurry S is supplied between the surface of the polishing pad 102 and the surface to be polished of the wafer 1 after the components are adjusted in the following manner.

First, the polishing slurry S which adjusted the silica concentration is prepared so that the silica dispersed in water may maintain the most stable state. Specifically, 11 to 15% by weight, preferably 11 to 13% by weight, more preferably 12% by weight of silica, the pH is adjusted to around 11 (10.5 to 10.5) by the addition of ammonium hydroxide (NH ₄ OH) Prepare the polishing slurry S adjusted in 11.5).

Since commercially available polishing slurry S has adjusted silica concentration to the said range, it is good to use it. In the commercial polishing slurry S, however, coarse aggregated particles or foreign matters having a particle size of 1 µm or more, which cause microscratches that are problematic in the present invention, are contained. Therefore, when supplying the commercial polishing slurry S to the chemical mechanical polishing apparatus 100, a filter is provided in the piping system which connects the tank which stores the polishing slurry S purchased from the slurry maker, and the chemical mechanical polishing apparatus 100, and grind | polishs. It is preferable to sufficiently remove coarse aggregated particles and foreign matter in slurry S.

In addition, the polishing slurry S supplied to the chemical mechanical polishing apparatus 100 is left to stand in the tank for at least 30 days or more, preferably 40 days or more, more preferably 45 days or more, and the polishing slurry S 0.5cc The occurrence of fine scratches can be effectively suppressed by using after confirming that the number of coarse agglomerated particles containing sugars having a particle diameter of 1 µm or more is 200,000 or less, preferably 50,000 or less, and more preferably 20,000 or less. . In addition, when the polishing slurry S left unattended for the above-mentioned period is extracted from the tank and transported to the chemical mechanical polishing apparatus 100, the bottom of the tank is avoided in order to avoid mixing of foreign matter and coarse agglomerated particles deposited at the bottom of the tank. A supernatant portion of at least 5 cm, preferably at least 10 cm is extracted from the portion.

Stopping and leaving the polishing slurry S refers to leaving the polishing slurry S in a stationary state without filling the tank with an operation such as vibration, stirring, and heating (which involves material transport by convection). In addition, the storage method of the grinding | polishing slurry S demonstrated here is described in detail in patent application 2000-145379 by this inventor.

Next, in the present embodiment, the polishing slurry S is diluted with pure water. The mixing ratio of the polishing slurry S and the pure water is about 1 (polishing slurry): 1 to 1.2 (pure), and the concentration of silica contained in the polishing slurry S after dilution is 3 to 9% by weight, preferably 4 to 8% by weight. More preferably, it adjusts to about 8 weight%. In addition, some commercially available polishing slurries contain silica at a high concentration (for example, 25% by weight). When using the polishing slurry S containing such a high concentration of silica, the silica concentration contained in the polishing slurry S after dilution is adjusted to the said range by increasing the mixing ratio of pure water. Moreover, in the case of pure water, although it contains the aqueous solution or chemical liquid etc. which make pure water a main component, it calls it "pure water" generically here.

Thus, by diluting the polishing slurry S with pure water and increasing its volume, the concentration of the aggregated particles contained in the polishing slurry S decreases. In addition, when the dilution rate of the polishing slurry S is increased, the concentration of the aggregated particles is further lowered. However, when the abrasive component concentration of the polishing slurry S is lowered, the polishing rate is also lowered. Therefore, the silica concentration contained in the polishing slurry S after dilution is It is preferable to set it as at least 3 weight% or more.

When the polishing slurry S is diluted with pure water, the concentration of the aggregated particles decreases temporarily. However, when the polishing slurry S is left, the aggregation of the silica particles starts again. Therefore, the polishing slurry S diluted with pure water should be provided for polishing as soon as possible. That is, the dilution operation of the polishing slurry S is performed immediately before the polishing slurry S is supplied between the polishing pad 102 and the to-be-polished surface of the wafer 1.

The time from dilution of the polishing slurry S with pure water to the polishing is up to about 2 hours, and when this time is exceeded, the concentration of the aggregated particles returns to the level before dilution, so that there is no effect of dilution. In addition, since the reagglomeration of the silica particles in the polishing slurry S proceeds with time, the time from diluting the polishing slurry S to providing polishing is preferably shorter, and is usually within 10 minutes after dilution. Preferably, you may be within 10 to 15 seconds.

As an example, as shown in FIG. 9, the grinding | polishing slurry supply pipe | tube 105a and the pure water supply piping 105b are provided in the slurry supply pipe 105, and are grind | polished at the front-end | tip part of the slurry supply pipe 105. FIG. By mixing the slurry S with pure water, the polishing slurry S diluted with pure water can be instantaneously provided for polishing.

Further, a pure water supply pipe is provided separately from the slurry supply pipe 105 on the polishing pad 102 so that the pure water supplied from the pure water supply pipe and the polishing slurry S supplied from the slurry supply pipe 105 are removed from the surface of the polishing pad 102. You may mix. In addition, after supplying the polishing slurry S to the surface of the polishing pad 102, you may mix them by supplying pure water to the surface of the polishing pad 102. FIG. However, when the polishing slurry S and pure water are mixed on the surface of the polishing pad 102, the ratio of both is locally nonuniform, and as a result, the polishing amount in the wafer surface may be nonuniform. Requires attention.

The substrate (wafer: 1) flowing through the mass production process is brought into the processing unit of the chemical mechanical polishing apparatus 100 one by one, fixed to the lower end of the wafer carrier 103, and then deposited on the surface of the silicon oxide film ( 7) is polished by diluted polishing slurry S. As an example, grinding | polishing conditions are load = 250g / cm <2>, wafer carrier rotation speed = 30rpm, surface rotation speed = 25rpm, slurry flow volume = 200cc / min.

FIG. 10: shows the cross section of the board | substrate (wafer 1) immediately after the chemical mechanical polishing process is completed. Polishing of the silicon oxide film 7 is performed by using the silicon nitride film 3 as a stopper, and the end point is a time when the film thickness of the silicon nitride film 3 becomes 60 nm. As a result, an element isolation groove 5 in which the silicon oxide film 7 is embedded is formed in the element isolation region of the main surface of the substrate (wafer: 1).

After the polishing process is completed, the substrate (wafer: 1) is removed (removed) from the wafer carrier 103 and then conveyed one by one to a cleaning apparatus (not shown) connected to the rear end of the chemical mechanical polishing apparatus 100. The silica abrasive grains and the alkali metal ions contained in the polishing slurry S are removed by a method such as pure scrub washing, pure ultrasonic cleaning, pure running water washing or pure spin washing. And after drying-processed by spin drying or IPA (isopropyl alcohol) steam drying, etc., it returns to the next process. On the other hand, in the chemical mechanical polishing apparatus 100, a new substrate (wafer: 1) in which the process shown in FIG. 7 is completed is brought in one by one, and the above-described chemical mechanical polishing process is repeated.

11 shows the case where the polishing slurry (silica concentration = 6% by weight) obtained by diluting the number of scratch defect densities generated on the surface of the wafer 1 in the formation process of the element isolation groove 5 described above with pure water, It is a graph compared with the case where the undiluted polishing slurry (silica concentration = 12 weight%) was used. The vertical axis represents scratch defect density measured using an automatic wafer appearance inspection device (WI-800) manufactured by Hitachi Tokyo Electronics, and the horizontal axis represents an inspection date. As shown, the scratch defect density was remarkably reduced after the day of using the polishing slurry diluted with pure water.

FIG. 12 shows a silicon oxide film deposited on the main surface of a mirrored wafer by plasma CVD, followed by polishing using a polishing slurry (silica concentration = 6% by weight) diluted with pure water (FIG. 12A). It is a graph which shows the result of comparing the number of microscratches when grinding | polishing is performed using a slurry (silica concentration = 12 weight%) (FIG. 12B). As the number of microscratches, an external appearance inspection device (LS-6510) manufactured by Hitachi DECO Corporation was used. As shown in the figure, the number of fine scratches was significantly reduced in the wafer polished using the pure slurry diluted with pure water, compared with the wafer polished using the undiluted polishing slurry.

Next, the process after formation of the element isolation groove 5 will be briefly described. First, as shown in FIG. 13, the silicon nitride film 3 on the substrate 1 is removed using thermal phosphoric acid, and then the silicon oxide film 2 under the silicon nitride film 3 is replaced with hydrofluoric acid. After removal, the substrate 1 is thermally oxidized at about 800 to 1000 캜 to form a thin silicon oxide film 10 having a thickness of about 10 nm on the surface of the active region.

Next, as shown in FIG. 14, the p-type well 9 is formed by ion implanting boron (B) into the substrate 1 through the silicon oxide film 10, and subsequently, the silicon oxide film 10. Is removed with hydrofluoric acid, and then the substrate 1 is thermally oxidized at about 800 to 850 캜 to form a clean gate oxide film 11 having a thickness of about 6 nm to 8 nm on the surface of the active region.

Next, as shown in FIG. 15, a gate electrode 12 (word line WL) is formed over the gate oxide film 11. For example, the gate electrode 12 (word line WL) deposits a polycrystalline silicon film having a thickness of about 50 nm on the gate oxide film 11 doped with phosphorus (P) by CVD, and then sputtered thereon. A WSi ₂ (tungsten silicide) film having a thickness of about 120 nm by a method; and a silicon nitride film 13 having a thickness of about 160 nm by a CVD method thereon, and a photoresist film (not shown). It forms by patterning these films by dry etching which used as a mask.

Next, after the surface of the gate oxide film 11 is cleaned with hydrofluoric acid to remove the etching residue, phosphorus (P) or arsenic (As) is ion-implanted into the p-type well 9 as shown in FIG. As a result, the n-type semiconductor region 14 (source, drain) is formed. By the processes thus far, DRAM's MISFETQs for memory cell selection are completed.

Next, as shown in FIG. 17, the silicon nitride film 15 is deposited on the substrate 1 by the CVD method, and the spin-on glass film 16 is then spin-coated on the silicon nitride film 15. After that, a silicon oxide film 17 is deposited on the spin-on glass film 16 by CVD.

Next, as shown in FIG. 18, the silicon oxide film 17 is polished by chemical mechanical polishing to planarize its surface. In the polishing step, when a small scratch occurs in the silicon oxide film 17 and a part of it reaches the lower spin-on glass film 16, the hydro-fluoric acid washing in the next step causes the spin-on glass film 16 to be removed. Since the scratches are enlarged, when the plugs 20 are embedded in the contact holes 18 and 19 formed in the spin-on glass film 16 in a later step, the plugs 20 may be short-circuited with each other through scratches. Therefore, in this chemical mechanical polishing step, polishing is performed using a polishing slurry diluted with pure water as described above.

Next, as shown in FIG. 19, the silicon oxide film 17, the spin-on glass film 16, and the silicon nitride film 15 are dry-etched using the photoresist film (not shown) as a mask, and n Contact holes 18 and 19 are formed in the upper portion of the type semiconductor region 14 (source and drain).

Next, after cleaning the inside of the contact holes 18 and 19 with hydrofluoric acid, the plug 20 is formed in the inside of the contact holes 18 and 19. In order to form the plug 20, for example, a low-resistance polycrystalline silicon film doped with phosphorus (P) in the contact holes 18 and 19 and on the silicon oxide film 17 is deposited by CVD, followed by oxidation. The unnecessary polycrystalline silicon film on the silicon film 17 is removed by dry etching (or chemical mechanical polishing).

Next, as shown in FIG. 20, the silicon oxide film 21 is deposited on the silicon oxide film 17 by CVD, and then the silicon oxide film 21 on the contact hole 18 is etched. After the through hole 22 is formed, the plug 23 is formed in the through hole 22. The plug 23 deposits a TiN (titanium nitride) film and a W (tungsten) film on top of the silicon oxide film 21, for example, and then removes the unnecessary W film and TiN film on the silicon oxide film 21 from the chemical machine. It forms by removing by a grinding | polishing method. Subsequently, by patterning the W film deposited by the sputtering method on the silicon oxide film 21, a bit line BL is formed on the plug 23.

Next, the silicon oxide film 24 is deposited on the bit line BL by CVD, and the silicon oxide film 24 on the contact hole 19 is subsequently etched to form the through holes 25. The plug 26 is formed in the through hole 25. In order to form the plug 26, a low-resistance polycrystalline silicon film doped with phosphorus (P), for example, inside the through hole 25 and above the silicon oxide film 24 is deposited by CVD, followed by a silicon oxide film. (24) The unnecessary polycrystalline silicon film on the top is removed by dry etching (or chemical mechanical polishing).

Next, as shown in Fig. 21, a silicon nitride film 27 is deposited on the silicon oxide film 24 by CVD, and then a silicon oxide film on the silicon nitride film 27 by CVD. After 28 is deposited, the silicon oxide film 28 and the underlying silicon nitride film 27 are dry-etched using a photoresist film (not shown) as a mask, thereby forming a groove in the upper portion of the through hole 25. (29) is formed. Since the lower electrode 30 of the information storage capacitor C, which will be described later, is formed along the inner wall of the groove 29, the silicon oxide film 28 is used to increase the amount of charge by increasing the surface area of the lower electrode 30. ), It is necessary to deposit a thick film thickness.

Next, as shown in FIG. 22, an information storage capacitor C including the lower electrode 30, the capacitor insulating film 31, and the upper electrode 32 is formed in the groove 29. The lower electrode 30 is made of, for example, a low resistance polycrystalline silicon film doped with phosphorus (P), and the capacitor insulating film 31 is made of, for example, a tantalum oxide (Ta ₂ O ₅ ) film. The upper electrode 32 is formed of a TiN film. By the steps up to this point, the memory cell composed of the memory cell selection MISFETQs and the information storage capacitor C connected in series thereto is completed.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example of this invention, this invention is not limited to the said Example, Of course, it can change variously in the range which does not deviate from the summary.

Among the inventions disclosed herein, the effects obtained by the representative ones are briefly described as follows.

Immediately before polishing the surface of the wafer using the chemical mechanical polishing method, fine scratches can be reduced by diluting the polishing slurry with pure water to lower the concentration of aggregated particles, thereby improving the yield and reliability of the semiconductor integrated circuit device. You can.

Claims (35)

In the method of manufacturing a semiconductor integrated circuit device, (a) preparing a polishing slurry having a stable dispersed state, (b) diluting the polishing slurry with an aqueous solution whose main component is pure water; (c) Process of supplying the polishing slurry immediately after dilution with the said aqueous solution to the to-be-processed surface of the wafer which progresses along a mass-production process, and performing a chemical mechanical polishing process. Method of manufacturing a semiconductor integrated circuit device comprising a. The method of claim 1, The polishing slurry having a stable dispersed state comprises 11 to 15% by weight of silica. The method of claim 2, The polishing slurry having a stable dispersed state comprises 11 to 13% by weight of silica. The method of claim 2, The polishing slurry having a stable dispersed state comprises 12% by weight of silica. The method of claim 1, The mixing ratio of the polishing slurry and the aqueous solution is 1 (polishing slurry): 1 to 1.2 (aqueous solution). The method of claim 1, And diluting the polishing slurry with the aqueous solution, and then supplying the polishing slurry to the to-be-processed surface of the wafer within 2 hours. The method of claim 6, And diluting the polishing slurry with the aqueous solution, and then supplying the polishing slurry to the target surface of the wafer within 10 minutes. The method of claim 7, wherein And diluting the polishing slurry with the aqueous solution, and then supplying the polishing slurry to the to-be-processed surface of the wafer within 10 to 15 seconds. The method of claim 2, The pH of the polishing slurry having a stable dispersed state is 10.5 to 11.5, characterized in that the semiconductor integrated circuit device manufacturing method. The method of claim 1, The polishing slurry having a stable dispersed state is used in which it is left to stand until the concentration of aggregated particles having a particle size of 1 μm or more contained therein is 200,000 pieces / 0.5 cc or less. . The method of claim 10, The polishing slurry having a stable dispersed state is used in which it is left to stand until the concentration of agglomerated particles with a particle size of 1 μm or more contained therein becomes 50,000 / 0.5 cc or less. . The method of claim 11, The polishing slurry having a stable dispersed state is used in which it is left to stand until the concentration of aggregated particles having a particle size of 1 μm or more included therein is 20,000 / 0.5 cc or less. . The method of claim 1, The polishing slurry having a stable dispersed state is a stationary stand for at least 30 days. The method of claim 13, The polishing slurry having the stable dispersed state is a stationary stand for at least 40 days. The method of claim 14, The polishing slurry having the stable dispersed state is a stationary stand for 45 days or longer. In the method of manufacturing a semiconductor integrated circuit device, (a) preparing a polishing slurry containing 11 to 15 wt% silica; (b) diluting the polishing slurry with an aqueous solution or chemical liquid whose main component is pure water; (c) a step of forming a polishing planarization insulating film isolation groove in the main surface of the wafer by supplying the polishing slurry immediately after dilution with the aqueous solution or the chemical solution to the main surface of the wafer proceeding along the mass production process. Method of manufacturing a semiconductor integrated circuit device comprising a. The method of claim 16, The mixing ratio of the polishing slurry and the aqueous solution or the chemical liquid is 1 (polishing slurry): 1 to 1.2 (aqueous solution or chemical liquid). The method of claim 16, And diluting the polishing slurry with the aqueous or chemical solution, and then supplying the polishing slurry to the main surface of the wafer within 2 hours. The method of claim 18, And diluting the polishing slurry with the aqueous or chemical solution, and then supplying the polishing slurry to the main surface of the wafer within 10 minutes. The method of claim 19, And diluting the polishing slurry with the aqueous or chemical solution, and then supplying the polishing slurry to the main surface of the wafer within 10 to 15 seconds. The method of claim 16, The concentration of the agglomerated silica particles having a particle diameter of 1 μm or more contained in the polishing slurry of the step (a) is 200,000 pieces / 0.5 cc or less, wherein the method for manufacturing a semiconductor integrated circuit device. The method of claim 16, The polishing slurry of the step (a) is left to stand for 30 days or more in advance. The method of claim 16, The polishing slurry of the step (a) comprises 11 to 13% by weight of silica, the method for producing a semiconductor integrated circuit device. The method of claim 23, wherein The polishing slurry of the step (a) comprises 12% by weight of silica, the method for producing a semiconductor integrated circuit device. In the method of manufacturing a semiconductor integrated circuit device, (a) forming a groove in the element isolation region of the main surface of the wafer by etching the element isolation region of the main surface of the wafer using an oxidizing insulating film formed on the main surface of the wafer as a mask; (b) forming a silicon oxide insulating film on a main surface of the wafer including the inside of the groove; (c) diluting the polishing slurry containing 11 to 15% by weight of silica with pure water; (d) Supplying a polishing slurry immediately after dilution with pure water on the main surface of the wafer where step (b) is completed, and chemically polishing the silicon oxide insulating film using the oxidizing resistant insulating film as a polishing stopper. Thereby selectively leaving the silicon oxide insulating film inside the groove to form a polishing planarization insulating film isolation groove in the device isolation region. Method of manufacturing a semiconductor integrated circuit device comprising a. The method of claim 25, And diluting the polishing slurry with the pure water, and then supplying the polishing slurry to the main surface of the wafer within 2 hours. The method of claim 26, And diluting the polishing slurry with the pure water, and then supplying the polishing slurry to the main surface of the wafer within 10 minutes. The method of claim 27, And diluting the polishing slurry with the pure water, and then supplying the polishing slurry to the main surface of the wafer within 10 to 15 seconds. In the method of manufacturing a semiconductor integrated circuit device, (a) preparing a polishing slurry containing 11 to 15 wt% silica; (b) A step of performing a chemical mechanical polishing process while supplying an aqueous solution containing the polishing slurry and pure water as main components to the main surface of the wafer that proceeds along the mass production process. Method of manufacturing a semiconductor integrated circuit device comprising a. The method of claim 29, The supply ratio of the polishing slurry and the aqueous solution is 1 (polishing slurry): 1 to 1.2 (aqueous solution). The method of claim 29, The concentration of the agglomerated silica particles having a particle size of 1 μm or more contained in the polishing slurry is 200,000 pieces / 0.5 cc or less. The method of claim 29, A method for manufacturing a semiconductor integrated circuit device, wherein the polishing slurry is left to stand for 30 days or more in advance. The method of claim 29, And (b) the step of forming a polishing planarization insulating film isolation groove in the main surface of the wafer. The method of claim 29, The polishing slurry of the step (a) comprises 11 to 13% by weight of silica, the method for producing a semiconductor integrated circuit device. The method of claim 34, wherein The polishing slurry of the step (a) comprises 12% by weight of silica, the method for producing a semiconductor integrated circuit device.