JP2006303520A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress occurrence of micro scratch by reducing flocculate grain density in polishing slurry used in a chemical mechanical polishing process. <P>SOLUTION: When performing the chemical mechanical polishing process by supplying the polishing slurry to a processed surface of each wafer flowing in a mass production process, the polishing slurry is left to stand in the vessel for longer than 30 days, preferably than 40 days, and more preferably than 50 days. Accordingly, a density of flocculate grain of the polish slurry profiled in a particle size of 1 μm or more by 200 thousand pieces/0.5 cc or less, preferably 50 thousand pieces/0.5 cc or less, and more preferably 20 thousand pieces or less/0.5 cc, is used. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a step of polishing a thin film formed on the surface of a semiconductor wafer using a chemical mechanical polishing (CMP) method. It relates to a technology that is effective when applied to manufacturing.

  In the manufacturing process of a semiconductor integrated circuit device, an insulating film or a conductive film deposited on a silicon wafer is polished by a chemical mechanical polishing method to form an element isolation groove, an interlayer insulating film is flattened, a plug In some cases, a buried wiring is formed.

  The chemical mechanical polishing method is a method in which the surface of a wafer is polished while supplying a polishing slurry onto a surface plate on which a pad made of a hard resin is attached. Generally, polishing slurry such as silica (silicon oxide) is used as the polishing slurry. The agent fine particles dispersed in pure water and added with an alkali for pH adjustment are used.

As silica in the polishing slurry, colloidal silica obtained using sodium silicate as a raw material, or fumed silica (fumed silica) obtained by burning silicon tetrachloride (SiCl ₄ ) with an oxyhydrogen flame is used. There is a problem that the former polishing slurry using colloidal silica contains sodium (Na) as an impurity. Further, although colloidal silica in which this point is improved and the sodium content is reduced is provided, there is a drawback that the production cost is higher than that of the latter fumed silica.

  On the other hand, fumed silica is inferior in dispersion stability in an aqueous dispersion medium compared to colloidal silica. When a wafer is polished with a polishing slurry using this silica, the surface of the wafer is caused by coarse aggregated silica particles in the slurry. The problem that minute scratches (micro scratches) occur is pointed out, and various techniques for improving the dispersion stability have been proposed.

  The production methods and physical properties of colloidal silica and fumed silica are described, for example, in “CMP Science” pages 128 to 142 (Non-patent Document 1) published on July 19, 1999 by Science Forum Inc.

  JP-A-8-257898 (Patent Document 1) gives a positive charge by charge determining ions to the surface of abrasive particles such as diamond, silicon carbide, alumina, silica, zirconia, cerium oxide, iron oxide, chromium oxide, By attaching a surfactant to this to make the abrasive particles hydrophobic and agglomerated, the abrasive particles are prevented from settling over time, and dispersion stability and redispersibility are improved over a long period of time. Disclosed is a water-based loose abrasive slurry that can be maintained and a method for producing the same.

  Japanese Patent Application Laid-Open No. 11-246852 (Patent Document 2) discloses a polishing slurry having good dispersibility of polishing abrasive grains and a method for preparing the same. This polishing slurry is a mixture of abrasive grains, an etching aqueous solution that is an alkaline aqueous solution or an acidic aqueous solution that chemically etches the material to be polished, and a polymer substance having a hydrophilic group. The polymer substance having a group is dispersed or dissolved in the state of fine particles in an aqueous etching solution.

  As the abrasive grains, silicon, aluminum, titanium, manganese, cerium, alkaline earth metal or alkali metal oxide, sulfate or carbonate is used. Examples of the polymer substance having a hydrophilic group include polyamides, polyimides, polyethylenes, polystyrenes, polyethers, polyurethanes, polycarbonates, polyvinyl alcohols, polyvinyl chlorides or polyvinyl chlorides having carboxyl groups, hydroxyl groups, nitro groups or amino groups. Vinylidene is used.

  In the above polishing slurry, a polymer substance having a hydrophilic group is adsorbed on the abrasive grains in the slurry, and the slurry is provided with thixotropic properties and an anti-settling function for abrasive particles. The grains maintain a weak aggregated state. And, as a result of the individual abrasive particles being maintained in a well dispersed state by the network structure due to the uniform secondary bonds between the polymer substances, the abrasive particles will not settle during storage of the slurry, so after long-term storage However, it is said that the slurry can be used for polishing as it is without performing an operation of stirring the slurry again to restore the dispersibility.

Japanese Patent Laid-Open No. 10-193255 (Patent Document 3) discloses that cerium oxide, alumina, manganese oxide, and the like have poor dispersibility in a liquid, so that the particles agglomerate over time when left standing, and the polishing rate or the polishing rate A method of storing a polishing slurry containing polishing abrasives that change polishing characteristics such as selectivity over time has been proposed. In this storage method, after applying ultrasonic vibration to the polishing slurry, the average particle size of the abrasive grains or the oxidation-reduction potential of the slurry is measured, and the polishing rate is controlled by monitoring the average particle size or the oxidation-reduction potential. Is. According to this method, the degree of aging of the polishing rate of the polishing slurry can be known, so the polishing rate of the slurry being stored can be easily and reliably managed, and high-throughput and precise polishing can be performed. It can be done.
JP-A-8-257898 JP 11-246852 A JP-A-10-193255 July 19, 1999, published by Science Forum Inc., "CMP Science" pages 128-142

  In recent LSIs, chemical mechanical polishing is performed in a plurality of steps of a wafer process in order to promote element miniaturization and multilayer wiring. For example, in the step of forming the element isolation groove on the main surface of the wafer, the main surface of the wafer is first dry-etched using the oxidation resistant insulating film as a mask to form a groove in the element isolation region, and then the groove is formed. After depositing a silicon oxide film having a thickness greater than the depth of the groove on the main surface of the wafer including the inside, the silicon oxide film is chemically mechanically polished using the oxidation-resistant insulating film as a polishing stopper, An element isolation trench is formed by selectively leaving the silicon oxide film inside the trench.

  In the chemical mechanical polishing process as described above, a polishing slurry in which silica particles are dispersed in water is generally used. Since silica has hydrophilic silanol groups (Si-OH) on its surface, when silica particles are dispersed in water, the particles (by the hydrogen bonds between the silanol groups and van der Waals force) Aggregation between primary particles) occurs, and aggregated particles (secondary particles) having a larger particle size (particle diameter) than single particles are formed. Therefore, in a polishing slurry in which silica particles (dispersoid) are dispersed in water (dispersion medium), the aggregated particles constitute an abrasive component.

  The aggregated particles have no problem when the particle size is relatively small. However, in an actual polishing slurry, there are coarse aggregated particles having a particle diameter of 1 μm or more (in this application, aggregated particles having a particle diameter of 1 μm or more are particularly referred to as “coarse aggregated particles”). Micro scratches called micro scratches are given to the surface of the wafer, resulting in a decrease in yield and reliability. For example, when the silicon oxide film is chemically mechanically polished using the oxidation-resistant insulating film as a polishing stopper in the element isolation groove forming process described above, a part of the micro-scratch occurs on the surface of the oxidation-resistant insulating film. Reaches the underlying silicon substrate and damages its surface.

  As a method for removing coarse agglomerated particles in the polishing slurry, a method of filtering the abrasive slurry is also effective to some extent. However, if the polishing slurry from which the agglomerated particles are removed is left as it is, agglomeration starts again, which is not a fundamental measure.

  It is also effective to add a surfactant to the polishing slurry as a measure for improving the dispersibility of the silica particles. However, in the case of using a surfactant, it is necessary to provide equipment capable of complying with BOD and COD regulations, and to take measures against contamination by metal ions in the surfactant. On the other hand, the method of stirring the polishing slurry before use cannot be an effective micro-scratch countermeasure because there is a possibility that foreign matters and coarse particles precipitated at the bottom of the slurry may be mixed.

  One object of the present invention is to provide a technique capable of reducing the density of agglomerated particles in a polishing slurry used in a chemical mechanical polishing process.

  One object of the present invention is to provide a flattening technique capable of reducing micro scratches.

  One object of the present invention is to provide a planarization technique capable of forming a highly reliable integrated circuit.

  One object of the present invention is to provide a planarization technique capable of improving the mass production yield of the planarization process of ULSI.

  One object of the present invention is to provide a planarization polishing slurry management technique suitable for mass production of integrated circuit devices having fine patterns.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A manufacturing method of a semiconductor integrated circuit device of the present invention includes:
(A) A groove is formed in the element isolation region of the main surface of the wafer by etching the element isolation region of the main surface of the wafer using an oxidation resistant insulating film formed on the main surface of the wafer as a mask. And a process of
(B) forming a silicon oxide insulating film on the main surface of the wafer including the inside of the groove;
(C) The silicon oxide insulating film is chemically mechanically polished using the oxidation-resistant insulating film as a polishing stopper, and the silicon oxide insulating film is selectively left in the trench, whereby the wafer Forming a polishing planarization insulating film isolation groove in the element isolation region of the main surface,
When the silicon oxide insulating film is subjected to chemical mechanical polishing, a polishing slurry is used which is allowed to stand still until the concentration of aggregated particles having a particle diameter of 1 μm or more becomes 200,000 particles / 0.5 cc or less.
(2) A method for manufacturing a semiconductor integrated circuit device of the present invention includes:
(A) A groove is formed in the element isolation region of the main surface of the wafer by etching the element isolation region of the main surface of the wafer using an oxidation resistant insulating film formed on the main surface of the wafer as a mask. And a process of
(B) forming a silicon oxide insulating film on the main surface of the wafer including the inside of the groove;
(C) The silicon oxide insulating film is chemically mechanically polished using the oxidation-resistant insulating film as a polishing stopper, and the silicon oxide insulating film is selectively left in the trench, whereby the wafer Forming a polishing planarization insulating film isolation groove in the element isolation region of the main surface,
When chemical mechanical polishing is performed on the silicon oxide insulating film, a polishing slurry that has been allowed to stand for 30 days or more in advance is used.
(3) A method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps.
(A) a step of allowing the concentration of aggregated particles having a particle diameter of 1 μm or more contained in the polishing slurry to be 200,000 particles / 0.5 cc or less by leaving the polishing slurry used for the chemical mechanical polishing treatment stationary;
(B) The polishing planarization insulating film is separated from the main surface of each wafer by supplying the polishing slurry subjected to the step (a) to the processing surface of each wafer flowing through the mass production process and performing chemical mechanical polishing. Forming grooves.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the invention of one embodiment of the present application, since the generation of micro scratches can be suppressed by reducing the aggregate particle density in the polishing slurry used in the chemical mechanical polishing step, a semiconductor having a chemical mechanical polishing step The manufacturing yield and reliability of the integrated circuit device can be improved.

  In this application, chemical mechanical polishing (CMP) is generally relative to the surface direction while supplying a polishing slurry in a state where the surface to be polished is in contact with a polishing pad made of a relatively soft cloth-like sheet material or the like. It means moving and polishing.

  The polishing slurry generally refers to a liquid colloidal suspension (suspension) in which abrasive fine particles (dispersoid) are blended with water and a chemical etching agent (dispersion medium). The abrasive fine particles generally mean fine particles such as silica, ceria, zirconia, and alumina.

  The standing of the polishing slurry means that the container is filled with the polishing slurry and left in a stationary state without any operation such as vibration, stirring, and heating. Specifically, for example, in a warehouse maintained at a relatively uniform temperature, fumed silica, pure water, and alkaline chemical liquid are mixed, and the polishing slurry after removing foreign matters with a filter is about 1 m square. For example, it can be stored in a cubic container. Therefore, the action of filling the container with the polishing slurry and carrying it does not correspond to the stationary standing here. For example, it is here that the polishing slurry is put in a container (tank) and transported by the ship via the open ocean without special vibration prevention measures, or transported via a general road by truck or other vehicle. It corresponds to the transportation.

  The polishing planarization insulating film isolation groove refers to an element isolation groove formed by selectively leaving an insulating film whose surface is flattened by a chemical mechanical polishing process inside the groove. Therefore, the element isolation trench formed simply by depositing an insulating film inside the trench does not correspond to the polishing planarization insulating film isolation trench here. For example, an element isolation trench generally called SGI (Shallow Groove Isolation) or STI (Shallow Trench Isolation) corresponds to the polishing planarization insulating film isolation trench here.

  In the present application, the mass production process in a wafer line means that the throughput per day of a specific chemical mechanical polishing apparatus used in the wafer line is at least 25 or 50 or more in terms of an 8-inch wafer, more generally The case of 100 sheets or more shall be said. Needless to say, the limit number of wafers is inversely proportional to the area of the wafer.

  Further, in the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified and clearly limited to a specific number in principle. It is not limited to the specific number, and may be a specific number or more. Furthermore, in the following embodiments, the constituent elements (including element steps) are not necessarily essential unless explicitly stated or apparently essential in principle. Not too long.

  Similarly, in the following embodiments, when referring to the shapes and positional relationships of components and the like, the shapes and the like of the components are substantially the same unless explicitly stated or otherwise apparent in principle. Including those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In addition, the term “semiconductor integrated circuit device” in the present application is not limited to a device manufactured on a single-crystal silicon substrate, but unless otherwise specified, it is particularly an SOI (Silicon On Insulator) substrate or a TFT (Thin Film). Transistors) including those made on other substrates such as liquid crystal manufacturing substrates. A wafer refers to a single crystal silicon substrate (generally substantially disk-shaped), an SOI substrate, a glass substrate, other insulating, semi-insulating, or semiconductor substrates used in the manufacture of a semiconductor integrated circuit device or a composite substrate thereof.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that in all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof is omitted.

(Embodiment 1)
In the present embodiment, the results of experiments conducted by the present inventors on the relationship between the period during which the polishing slurry is stored in a stationary state and the scratch level generated in the wafer process will be described.

-Polishing slurry-
FIG. 1 is a flowchart showing a series of operations of a polishing slurry from the start of production to the supply to a chemical mechanical polishing apparatus of a semiconductor mass production line.

  Generally, manufacturers of polishing slurries disperse single silica particles (primary particles) having an average particle diameter of about 20 nm to 40 nm, that is, fumed silica, in pure water, and an alkaline chemical such as ammonium hydroxide. Is added to prepare a polishing slurry having a pH adjusted to around 10-11. Subsequently, after removing foreign particles, coarse primary particles, and the like in the polishing slurry generated or mixed in the manufacturing process with a filter, the container is filled and allowed to stand, and then shipped to a semiconductor manufacturer. The stationary standing period in this application is generally the period from the start of standing still after filling the container to the inspection of the aggregated particle density for shipment, or the period from the start of moving to a transportation means such as a truck for shipping. Say.

  On the other hand, the semiconductor manufacturer purchases the polishing slurry filled in the container from the manufacturer, and supplies the required amount to the chemical mechanical polishing apparatus on the wafer line each time to perform the chemical mechanical polishing process. That is, the polishing slurry conveyed in the stationary container is left in the slurry receiving tank of FIG. 1 (a tank having substantially the same shape and size as the stationary tank, for example, a 1m square cubic container). Further, the sediment is pumped out from about 10 cm from the bottom of the conveyance-use container so as not to be rolled up and transferred to the receiving tank. Then, as shown in FIG. 1, a filter is passed to remove relatively large foreign matters (for example, foreign matters having a diameter of 50 micrometers or more) generated from the piping system, for example, about 10 to 20 (more than this) It is possible to supply the chemical mechanical polishing equipment through a piping system. Further, it is possible to install a receiving tank for each chemical mechanical polishing apparatus instead of such a concentrated system. However, according to the collective supply system, continuous supply for several hours to several days can be performed to a plurality of apparatuses with one operation, and there is an advantage that stable slurry supply can be performed.

In this embodiment, a polishing slurry containing about 13% by weight of fumed silica, which is a polishing abrasive grain component, and having a pH adjusted to around 11 by the addition of ammonium hydroxide (NH ₄ OH) was used (other added alkalis). As the chemical solution, sodium hydroxide, potassium hydroxide or the like can be used, but ammonium hydroxide has a merit that there is very little alkali metal). Since there is a hydrophilic silanol group (Si-OH) on the surface of fumed silica contained in this polishing slurry, when silica particles are added to a dispersion medium such as water, silanol group inter-particle hydrogen bonding Also, the particles are aggregated by the van der Waals force, and aggregated particles (secondary particles) having a particle size larger than the primary particles are formed. Therefore, the abrasive component in the polishing slurry used in the actual wafer polishing process is aggregated particles (secondary particles). Further, the particles that are a problem in the present invention are aggregated particles (coarse aggregated particles) having a particle diameter of 1 μm or more that cause micro scratches among the aggregated particles.

  The concentration of coarse agglomerated particles in the polishing slurry was measured using a particle size distribution analyzer for agglomerated particles, “AccuSizer Model 780” manufactured by Particle Sizing System. This measuring device obtains the number of particles by measuring the number of pulses generated from the particles passing through the measurement sensor based on the principle of the light blocking method and the light scattering method.

-Chemical mechanical polishing equipment-
The chemical mechanical polishing apparatus used was a system in which a surface to be processed of a wafer was placed downward on a polishing pad to which a polishing slurry was dropped and polishing was performed by pressurizing air. Further, the polishing pad surface damaged by polishing was sharpened and regenerated by a diamond dresser. As the polishing pad, a foamed urethane / urethane foam double-layer pad “IC1400KGr” manufactured by RODEL NITTA was used.

-Scratch-
Scratches are roughly classified into macro scratches and micro scratches. Macro scratches are characterized by flaws traversing the wafer, mainly due to the falling of diamond abrasive grains from the dresser. The micro scratch that is a problem in the present invention is a scratch having a depth of about several tens of nanometers. The micro scratch that can be observed by etching with dilute hydrofluoric acid (HF: H ₂ O = 1: 99) to widen the scratches. It is a serious wound. As described above, this micro scratch is mainly caused by coarse aggregated particles having a particle diameter of 1 μm or more contained in the polishing slurry.

  Micro scratches were evaluated by polishing a silicon wafer (20 cm in diameter) without a pattern using the chemical mechanical polishing apparatus for about 1 minute, and then etching the diluted hydrofluoric acid for several minutes to increase the size of the scratch. The laser irradiation type defect inspection device “LS6510” manufactured by Hitachi Electronics Engineering was used to separate the scratches.

  FIG. 2 shows the relationship between the aggregated particle density in the polishing slurry obtained in the above experiment and the micro scratch. The vertical axis represents the number of micro scratches per wafer, and the horizontal axis represents the number of agglomerated particles having a particle size of 1 μm or more contained in 0.5 cc of slurry in logarithm. As shown in the figure, it was confirmed that the lower the aggregate particle density in the polishing slurry, the smaller the number of micro scratches generated during the chemical mechanical polishing process.

  Next, a mechanism for generating aggregated particles in the polishing slurry and a method for reducing the aggregated particles in the polishing slurry will be described.

  FIG. 3 shows the sedimentation rate of agglomerated particles having a particle size of 1 μm or more in a polishing slurry stationary in a 1 m high container. The vertical axis represents the stationary standing time, and the horizontal axis represents the sedimentation distance. . As shown in the figure, it is estimated that it takes at least 30 days, usually 40 days or more for the aggregated particles to settle down to a height of 1 m.

On the other hand, FIG. 4 shows the dependence of the agglomerated particles in the polishing slurry on the static standing time. The vertical axis represents the number of agglomerated particles having a particle size of 1 μm or more in 1 cm ³ of the polishing slurry, and the horizontal axis represents the polishing slurry. It represents the stationary time. Here, the measurement was performed for the cases where the height of the container used for standing the polishing slurry was 0.5 m, 1 m, and 2 m. As shown in the figure, during the period from the start of standing still until about 30 days have passed, the number of agglomerated particles decreased only slightly, but thereafter decreased rapidly. In other words, if only the sedimentation phenomenon of particles occurs during standing still, it should decrease monotonously, but this was not the case. The following model can be considered as the reason.

  As shown in FIG. 5, in the polishing slurry immediately after production, the concentration distribution of the agglomerated particles is non-uniform, and therefore there are regions where the interparticle distance is short and regions which are long. Aggregated particles having an average particle size of about 13 nm, which occupy most of the particles in the polishing slurry, have Brownian motion at a diffusion rate of about 2.67 μm / second, and if the distance between particles is shorter than the particle size, Since the collision between them is constantly repeated, an increase in aggregated particles due to the collision and a decrease due to settling occur simultaneously. However, when the distance between the particles becomes longer than the particle size, the number of particle collisions decreases because the particles in Brownian motion slip through other particles, and the probability that the particles are aggregated decreases.

  When the distance between particles having the above particle diameter is calculated in a polishing slurry having an aggregated particle concentration of 13%, 0.133 μm is required to disperse at a uniform distance. Therefore, if the interparticle distance of all the particles becomes this distance, the aggregation is converged. The actual measurement result of FIG. 4 seems to be because it took a certain amount of time for the inter-particle distance to become constant, and when the aggregation settled, it seemed that the decrease in the number of particles due to sedimentation seemed to have started.

  From the above experimental results, there is a clear correlation between the period in which the polishing slurry is allowed to stand still and the occurrence of microscratches. To suppress the generation of microscratches, the polishing slurry is reduced until the aggregate particle concentration decreases. It was found that it was effective to leave it stationary.

  In addition, whether or not a stationary polishing slurry can be used is determined by measuring the concentration of coarse agglomerated particles using the aforementioned measuring instrument (AccuSizer Model 780), etc. Confirm by confirming. Specifically, from the results shown in FIG. 2 and FIG. 3, at least 30 days or more, preferably 40 days or more, taking the case of a columnar stationary container having a height of 1 m after manufacturing a polishing slurry as an example, More preferably, it is allowed to stand still for 50 days or more, and the number of aggregated particles having a particle size of 1 μm or more contained in 0.5 cc of the polishing slurry is 200,000 or less, preferably 50,000 or less, more preferably 20,000 or less. By using after confirming this, the generation of micro scratches can be suppressed to a level that does not cause a problem.

  “Standing the polishing slurry stationary” means filling the container with the polishing slurry and leaving it in a stationary state without any operation such as vibration, stirring, and heating (which involves mass transport with convection). Therefore, the act of filling the container with the polishing slurry and transporting it does not correspond to standing still. The polishing slurry is allowed to stand still within a temperature range of 5 ° C. to 35 ° C., preferably at a temperature around 20 ° C.

  When removing the polishing slurry that has been allowed to stand for the above period from the container and transporting it to the chemical mechanical polishing apparatus, in order to avoid contamination of foreign substances and coarse aggregated particles that have settled on the bottom of the container, it is at least 5 cm, preferably 10 cm from the bottom of the container. Remove the supernatant. It is also effective to supply the polishing slurry extracted from the container to the chemical mechanical polishing apparatus after filtering it with a filter.

  The concentration of the aggregated particles in the polishing slurry decreases while repeating aggregation and sedimentation, so that the concentration varies depending on the size and height of the container even if the stationary standing is the same. Therefore, by changing the extraction position in accordance with the stationary standing period, it is possible to supply a polishing slurry in which the density of the aggregated particles is further reduced to the chemical mechanical polishing apparatus. Therefore, if the height of the container for stationary standing is halved, it is considered that the necessary stationary standing period is proportionally halved.

  In addition, once the particles are allowed to stand for a long time (for example, 30 days) and the aggregated particles are fixed as a precipitated layer on the bottom of the tank, there is generally no problem even if a slight stirring such as transportation is performed. This also applies to transportation by ship or the like.

  In addition, when the polishing slurry is allowed to stand still, it is desirable to specify the date of manufacture and the time when the polishing slurry can be used in a polishing slurry container or an instruction manual.

  In addition, it goes without saying that a polishing slurry that has not been subjected to the above-mentioned stationary standing period or that has not been standing still for a long time may be used after being left standing still (for example, 30 days) after the semiconductor manufacturer purchases it. Absent. In this case, for example, when the polishing slurry manufacturer is left standing for 15 days and then transported to the semiconductor manufacturer, the semiconductor manufacturer needs to stand still for 30 days again. In this embodiment, an example in which the polishing slurry maker is allowed to stand still for a long time has been described. However, in the polishing slurry maker, the purchased semiconductor integrated circuit can be left without being left still for a long time (for example, 30 days or more). Circuit or semiconductor device manufacturers may be allowed to stand still for a long time. However, in such a case, for example, if one semiconductor square container is consumed for one square meter per day, a space for placing 30 stationary containers is required, which is a great disadvantage for semiconductor manufacturers. On the other hand, however, the polishing slurry manufacturer has an advantage that a large stationary space can be distributed to the semiconductor manufacturer.

(Embodiment 2)
Next, an embodiment applied to a DRAM (Dynamic Random Access Memory) manufacturing process will be described with reference to FIGS. Since the polishing slurry used in the present embodiment is basically the same as that described in the first embodiment, the same description will not be repeated unless necessary.

  First, as shown in FIG. 6, a substrate (wafer) 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is thermally oxidized at about 850 ° C., and the surface thereof is thin with a thickness of about 10 nm. After the silicon oxide film 2 is formed, a silicon nitride film 3 having a thickness of about 140 nm is deposited on the silicon oxide film 2 by a CVD method. The silicon nitride film 3 is used as a mask when the substrate 1 in the element isolation region is etched to form a groove. Further, since the silicon nitride film 3 has the property of being hardly oxidized, it is also used as a mask for preventing the surface of the underlying substrate 1 from being oxidized. The silicon oxide film 2 below the silicon nitride film 3 relieves stress generated at the interface between the substrate 1 and the silicon nitride film 3 and causes defects such as dislocations on the surface of the substrate 1 due to this stress. Form to prevent.

  Next, as shown in FIG. 7, the silicon nitride film 3 in the element isolation region and the silicon oxide film 2 under the element isolation region are selectively removed by dry etching using the photoresist film 4 as a mask, and then shown in FIG. As described above, the trench 5a having a depth of about 350 to 400 nm is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 3 as a mask.

  Next, as shown in FIG. 9, the substrate 1 is thermally oxidized at about 800 to 1000 ° C. to form a thin silicon oxide film 6 having a thickness of about 10 nm on the inner wall of the groove 5a. The silicon oxide film 6 recovers from dry etching damage generated on the inner wall of the groove 5a and relieves stress generated at the interface between the silicon oxide film 7 embedded in the groove 5a and the substrate 1 in a later step. Form for.

Next, as shown in FIG. 10, a silicon oxide film 7 is deposited on the substrate 1 including the inside of the groove 5a by the CVD method. The silicon oxide film 7 is deposited with a film thickness (for example, about 500 to 600 nm) thicker than the depth of the groove 5a, and the silicon oxide film 7 is embedded in the groove 5a without any gap. The silicon oxide film 7 is formed by a film forming method with good step coverage, such as a silicon oxide film formed using, for example, oxygen and tetraethoxysilane ((C ₂ H ₅ ) ₄ Si).

  Next, after the substrate 1 is thermally oxidized at about 1000 ° C. and subjected to a densification (baking) process for improving the film quality of the silicon oxide film 7 embedded in the groove 5a, as shown in FIG. The silicon oxide film 7 above the silicon nitride film 3 is dry-etched using the photoresist film 8 formed thereon as a mask to reduce the film thickness. This dry etching is performed so that the height of the surface of the silicon oxide film 7 is substantially the same between the upper part of the groove 5 a and the upper part of the silicon nitride film 3.

  Next, as shown in FIG. 12, after removing the photoresist film 8 on the silicon oxide film 7, the silicon oxide film 7 is subjected to chemical mechanical polishing.

  FIG. 13 is a schematic view showing a processing unit of the chemical mechanical polishing apparatus 100 used for polishing the silicon oxide film 7. As shown in the figure, a surface plate 101 for polishing a wafer (substrate) 1 is installed in the processing unit of the chemical mechanical polishing apparatus 100. The surface plate 101 is rotationally driven in a horizontal plane by a drive mechanism (not shown). A polishing pad 102 made of a synthetic resin such as polyurethane having a large number of pores is attached to the upper surface of the surface plate 101.

  Above the surface plate 101, a wafer carrier 103 that is vertically moved and rotated in a horizontal plane by a driving mechanism (not shown) is installed. The wafer 1 is held by a retainer ring 104 and a membrane 106 provided at the lower end of the wafer carrier 103 with its main surface (surface to be polished) facing downward, and is pressed against the polishing pad 102 with a predetermined load. A polishing slurry S is supplied between the surface of the polishing pad 102 and the surface to be polished of the wafer 1 through a slurry supply pipe 105, and the surface to be polished of the wafer 1 is chemically and mechanically polished.

  Further, a dresser 107 is installed above the surface plate 101 to move up and down and rotate in a horizontal plane by a drive mechanism (not shown). A base material electrodeposited with diamond particles is attached to the lower end of the dresser 107, and the surface of the polishing pad 102 is periodically cut by this base material in order to prevent clogging by the abrasive grains.

In the present embodiment, the silicon oxide film 7 is polished by using a polishing slurry (S) that is allowed to stand still until the number of aggregated particles having a particle diameter of 1 μm or more reaches 20,000 or less / 0.5 cc. For example, the polishing conditions were as follows: load = 250 g / cm ² , wafer carrier rotation speed = 30 rpm, surface plate rotation speed = 25 rpm, and slurry flow rate = 200 cc / min. This polishing was performed using the silicon nitride film 3 as a stopper, and the end point was when the film thickness of the silicon nitride film 3 reached 50 nm.

  As shown in FIG. 14, the element isolation trench 5 is formed in the element isolation region of the main surface of the substrate (wafer) 1 through the steps so far.

  FIG. 15 shows the relationship between the density of the micro scratches generated in the polishing step and the stationary time of the polishing slurry (S). As shown in the figure, the microscratch density could be reduced by allowing the polishing slurry (S) to stand still for at least 30 days, preferably 40 days or more, more preferably 50 days or more.

  Next, after removing the silicon nitride film 3 using an etching solution such as hot phosphoric acid, boron (B) ions are implanted into the substrate 1 to form a p-type well 9 as shown in FIG. . Subsequently, after removing the silicon oxide film 2 on the surface of the substrate 1 by wet etching using hydrofluoric acid, the substrate 1 is thermally oxidized at about 800 to 850 ° C. as shown in FIG. A clean gate oxide film 10 is formed.

  Next, as shown in FIG. 18, a gate electrode 11 (word line WL) is formed on the gate oxide film 10. For the gate electrode 11 (word line WL), for example, a polycrystalline silicon film doped with phosphorus is deposited on the gate oxide film 10 by a CVD method, and then a WN film and a W film are deposited thereon by a sputtering method. A silicon nitride film 12 is deposited thereon by CVD, and then formed by patterning these films by etching using a photoresist film (not shown) as a mask.

  Next, as shown in FIG. 19, n-type semiconductor regions 13 (source and drain) are formed by ion implantation of phosphorus (P) or arsenic (As) into the p-type well 9. The DRAM memory cell selection MISFET Qs is substantially completed by the steps so far.

  Next, as shown in FIG. 20, a silicon nitride film 14 is deposited on the substrate 1 by the CVD method, and then a spin-on-glass film 15 is spin-coated on the silicon nitride film 14, and then on the spin-on-glass film 15. A silicon oxide film 16 is deposited by CVD.

  Next, as shown in FIG. 21, the silicon oxide film 16 is polished by a chemical mechanical polishing method to flatten the surface. In this polishing process, micro scratches are generated in the silicon oxide film 16, and when a part thereof reaches the lower spin-on glass film 15, the scratches of the spin-on glass film 15 are expanded by the hydrofluoric acid cleaning performed in the next process. When the plug 19 is embedded in the contact holes 17 and 18 formed in the spin-on-glass film 15 in a later process, the plugs 19 may be short-circuited through the scratch.

  Therefore, in this polishing step, the silicon oxide film 14 is polished by using the polishing slurry (S) that is allowed to stand still until the number of aggregated particles having a particle size of 1 μm or more reaches 20,000 or less / 0.5 cc, and the silicon oxide film 16 is prevented from generating micro scratches.

  Next, as shown in FIG. 22, the silicon oxide film 16, the spin-on-glass film 15 and the silicon nitride film 14 are dry-etched using a photoresist film (not shown) as a mask to form an n-type semiconductor region 13 (source, drain). The contact holes 17 and 18 are formed on the upper part of the structure. Next, after cleaning the inside of the contact holes 17 and 18 with hydrofluoric acid, a plug 19 is formed inside the contact holes 17 and 18. In order to form the plug 19, for example, a low resistance polycrystalline silicon film doped with phosphorus (P) is deposited by CVD in the contact holes 17 and 18 and on the silicon oxide film 16, and then on the silicon oxide film 16. The unnecessary polycrystalline silicon film is removed by dry etching (or chemical mechanical polishing).

  Next, as shown in FIG. 23, after the silicon oxide film 20 is deposited on the upper portion of the silicon oxide film 16 by the CVD method, and then the through-hole 21 is formed by etching the silicon oxide film 20 on the upper portion of the contact hole 19. The plug 22 is formed inside the through hole 21. For example, the plug 22 is formed by depositing a TiN (titanium nitride) film and a W (tungsten) film on the silicon oxide film 20 and then removing unnecessary W film and TiN film on the silicon oxide film 20 by a chemical mechanical polishing method. To form. Subsequently, the bit line BL is formed on the plug 22 by patterning a W film deposited on the silicon oxide film 20 by sputtering.

  Next, a silicon oxide film 23 is deposited on the upper portion of the bit line BL by a CVD method. Subsequently, the silicon oxide film 23 on the upper portion of the contact hole 18 is etched to form a through hole 24, and then inside the through hole 24. A plug 25 is formed. In order to form the plug 25, for example, a low-resistance polycrystalline silicon film doped with phosphorus (P) is deposited by CVD in the through hole 24 and on the silicon oxide film 23, and then the upper portion of the silicon oxide film 23 is unnecessary. The polycrystalline silicon film is removed by dry etching (or chemical mechanical polishing).

  Next, as shown in FIG. 24, a silicon nitride film 26 is deposited on the silicon oxide film 23 by the CVD method, and then a silicon oxide film 27 is deposited on the silicon nitride film 26 by the CVD method. Using the resist film (not shown) as a mask, the silicon oxide film 27 and the silicon nitride film 26 below the silicon oxide film 27 are dry-etched to form a groove 28 on the through hole 25. Since the lower electrode 29 of the information storage capacitive element C, which will be described later, is formed along the inner wall of the groove 28, in order to increase the surface area of the lower electrode 29 and increase the amount of stored charge, the silicon oxide film 27 is used. It is necessary to deposit a thick film.

Next, as shown in FIG. 25, an information storage capacitive element C composed of the lower electrode 29, the capacitive insulating film 30 and the upper electrode 31 is formed inside the trench 28. The lower electrode 29 is made of, for example, a phosphorus (P) -doped low-resistance polycrystalline silicon film, and the capacitor insulating film 30 is made of, for example, a tantalum oxide (Ta ₂ O ₅ ) film. The upper electrode 31 is composed of a TiN film. Through the steps up to here, a memory cell composed of the memory cell selection MISFET Qs and the information storage capacitive element C connected in series is completed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the case where the present invention is applied to a polishing slurry to which fumed silica is added has been described. However, the present invention is also applicable to the case where chemical mechanical polishing is performed using a polishing slurry to which colloidal silica is added. be able to.

  In the above embodiment, the case where the present invention is applied to the flattening process of the insulating film has been described. However, the chemicals for flattening the conductive film on the insulating film in which the wiring groove and the through hole are formed to form the embedded wiring and the plug It can also be applied to a mechanical polishing process.

  That is, when applied to planarization of element isolation such as SGI, scratches reaching the element formation region, that is, the silicon surface of the active region can be reduced. This is particularly effective for reliability. In addition, when used for planarization of a general interlayer insulating film, the electrical or electrochemical stability of the interlayer region is improved by reducing scratches or fine scratches that extend between adjacent conductive regions. be able to. Moreover, the point which contributes to the improvement of the reliability of a general element is the same as that of the said case.

  The present invention can be applied to the manufacture of a semiconductor integrated circuit device having a step of polishing a thin film formed on the surface of a semiconductor wafer using a chemical mechanical polishing method.

It is a flowchart which shows a series of operation | movement of the polishing slurry from the manufacture start to supply to the chemical mechanical polishing apparatus of a semiconductor mass production line. It is a graph which shows the relationship between the aggregated particle density in a polishing slurry, and a micro scratch. It is a graph which shows the relationship between the sedimentation speed | velocity | rate of agglomerated particle | grains with a particle size of 1 micrometer or more in grinding | polishing slurry, and stationary standing time. 4 is a graph showing the relationship between the number of aggregated particles having a particle size of 1 μm or more in a polishing slurry and the standing time. It is a figure which shows typically the dispersion state of the aggregated particle in a polishing slurry. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is the schematic which shows the process part of a chemical mechanical polishing apparatus. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a graph which shows the relationship between the static standing time of a polishing slurry, and a micro scratch density. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the silicon substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention.

Explanation of symbols

1 Silicon substrate (wafer)
2 Silicon oxide film 3 Silicon nitride film 4 Photoresist film 5 Element isolation trench 5a Groove 6 Silicon oxide film 7 Silicon oxide film 8 Photoresist film 9 P-type well 10 Gate oxide film 11 Gate electrode 12 Silicon nitride film 13 N-type semiconductor region (Source, drain)
14 Silicon nitride film 15 Spin-on-glass film 16 Silicon oxide films 17 and 18 Contact hole 19 Plug 20 Silicon oxide film 21 Through hole 22 Plug 23 Silicon oxide film 24 Through hole 25 Plug 26 Silicon nitride film 27 Silicon oxide film 28 Groove 29 Lower electrode 30 Capacitance insulating film 31 Upper electrode 100 Chemical mechanical polishing apparatus 101 Surface plate 102 Polishing pad 103 Wafer carrier 104 Retaining ring 105 Slurry supply pipe 106 Membrane 107 Dresser BL Bit line C Information storage capacitor Qs Memory cell selection MISFET
S Polishing slurry WL Word line

Claims (16)

(A) A groove is formed in the element isolation region of the main surface of the wafer by etching the element isolation region of the main surface of the wafer using an oxidation resistant insulating film formed on the main surface of the wafer as a mask. The process of
(B) forming a silicon oxide insulating film on the main surface of the wafer including the inside of the groove;
(C) The silicon oxide insulating film is chemically mechanically polished using the oxidation-resistant insulating film as a polishing stopper, and the silicon oxide insulating film is selectively left in the trench, whereby the wafer Forming a polishing planarization insulating film isolation groove in the element isolation region of the main surface,
A semiconductor integrated circuit characterized by using a polishing slurry which is left stationary until the concentration of aggregated particles having a particle size of 1 μm or more is 200,000 particles / 0.5 cc or less when the silicon oxide insulating film is subjected to chemical mechanical polishing. Device manufacturing method.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a polishing slurry is used which is allowed to stand still until the concentration of aggregated particles having a particle size of 1 [mu] m or more becomes 50,000 / 0.5 cc or less. A method for manufacturing an integrated circuit device.   2. The semiconductor integrated circuit device manufacturing method according to claim 1, wherein a polishing slurry is used which is allowed to stand still until the concentration of aggregated particles having a particle diameter of 1 [mu] m or more is 20,000 / 0.5 cc or less. A method for manufacturing an integrated circuit device.   2. The semiconductor integrated circuit device manufacturing method according to claim 1, wherein the concentration of the aggregated particles having a particle diameter of 1 [mu] m or more is determined by measuring the diameter of the aggregated particles contained in the polishing slurry. A method of manufacturing an integrated circuit device.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the aggregated particles contain silica as a main component. (A) A groove is formed in the element isolation region of the main surface of the wafer by etching the element isolation region of the main surface of the wafer using an oxidation resistant insulating film formed on the main surface of the wafer as a mask. The process of
(B) forming a silicon oxide insulating film on the main surface of the wafer including the inside of the groove;
(C) The silicon oxide insulating film is chemically mechanically polished using the oxidation-resistant insulating film as a polishing stopper, and the silicon oxide insulating film is selectively left in the trench, whereby the wafer Forming a polishing planarization insulating film isolation groove in the element isolation region of the main surface,
A method of manufacturing a semiconductor integrated circuit device, wherein a polishing slurry that has been allowed to stand for 30 days or more in advance is used when the silicon oxide insulating film is chemically mechanically polished.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein a polishing slurry that is left stationary for 40 days or more is used.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein a polishing slurry that is left stationary for 45 days or more is used.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the agglomerated particles contained in the polishing slurry are mainly composed of silica. A method of manufacturing a semiconductor integrated circuit device having the following steps;
(A) a step of allowing the concentration of aggregated particles having a particle diameter of 1 μm or more contained in the polishing slurry to be 200,000 particles / 0.5 cc or less by leaving the polishing slurry used for the chemical mechanical polishing treatment stationary;
(B) The polishing planarization insulating film is separated from the main surface of each wafer by supplying the polishing slurry subjected to the step (a) to the processing surface of each wafer flowing through the mass production process and performing chemical mechanical polishing. Forming grooves.   11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the concentration of aggregated particles having a particle size of 1 μm or more contained in the polishing slurry is set to 50,000 / 0.5 cc or less. Manufacturing method.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the concentration of aggregated particles having a particle size of 1 [mu] m or more contained in the polishing slurry is 20,000 particles / 0.5 cc or less. Manufacturing method.   11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the polishing slurry is left still for 30 days or more.   14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the polishing slurry is left still for 40 days or more.   15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein the polishing slurry is left still for 45 days or more.   11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the aggregated particles contain silica as a main component.

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