US20050110080A1 - LDMOS transistor device, integrated circuit, and fabrication method thereof - Google Patents
LDMOS transistor device, integrated circuit, and fabrication method thereof Download PDFInfo
- Publication number
- US20050110080A1 US20050110080A1 US10/968,633 US96863304A US2005110080A1 US 20050110080 A1 US20050110080 A1 US 20050110080A1 US 96863304 A US96863304 A US 96863304A US 2005110080 A1 US2005110080 A1 US 2005110080A1
- Authority
- US
- United States
- Prior art keywords
- gate
- regions
- region
- ldmos
- insulation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009413 insulation Methods 0.000 claims abstract description 53
- 125000006850 spacer group Chemical group 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000000969 carrier Substances 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- -1 silicide metals Chemical class 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Definitions
- the present invention generally relates to the field of integrated circuit technology, and more specifically the invention relates to an LDMOS (lateral double diffused MOS) transistor device, to an integrated circuit including the LDMOS transistor device, and to a fabrication method of the integrated circuit with the LDMOS transistor device, respectively.
- LDMOS lateral double diffused MOS
- the speed of an LDMOS transistor is determined by the transconductance g m and the input capacitance C in , and more specifically, the speed is proportional to g m /C in .
- an object of the present invention to provide an LDMOS transistor device in an integrated circuit, particularly an integrated circuit for radio frequency applications, which LDMOS transistor device overcomes the problems associated with the prior art described above.
- an object of the invention to provide a method in the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, including an LDMOS transistor, which accomplishes the above object.
- an LDMOS transistor device in an integrated circuit, particularly an integrated circuit for radio frequency applications, comprising a semiconductor substrate, an LDMOS gate region on top of the substrate, LDMOS source and drain regions, and a channel region arranged in the substrate beneath the LDMOS gate region, the channel region interconnecting the LDMOS source and drain regions, wherein the LDMOS gate region comprises first and second gate insulation layer regions, a centrally located insulation layer region provided between the first and second gate insulation layer regions, and first and second gate conducting layer regions, each of which being provided on top of a respective one of the first and second gate insulation layer regions, each being an etched outside spacer region at the centrally located insulation layer region, and each having a length which is smaller than a length of the centrally located insulation layer region.
- the first and second gate conducting layer regions can be provided with individual contacts for electric connection.
- the channel region can be located at least partly directly beneath one of the first and second gate conducting layer regions, and a drain drift region can be located at least partly directly beneath another one of the first and second gate conducting layer regions.
- One of the first and second gate conducting layer regions can be connected to a control voltage, and the another one of the first and second gate conducting layer regions can be connected to a bias voltage, preferably high bias voltage, to invert channel carriers in the drain drift region.
- the first and second gate conducting layer regions can each be made of doped polycrystalline silicon.
- the first and second gate conducting layer regions can be silicided, particularly nickel silicided.
- the LDMOS transistor device can be a radio frequency power transistor.
- a monolithically integrated circuit may comprise the LDMOS transistor device.
- the object can also be achieved by a method in the fabrication of a monolithically integrated circuit including an LDMOS transistor device comprising the steps of providing a semiconductor substrate, forming an LDMOS gate region on top of the substrate, forming LDMOS source and drain regions, and forming a channel region arranged in the substrate beneath the LDMOS gate region, the channel region interconnecting the LDMOS source and drain regions, wherein the step of forming an LDMOS gate region on top of the substrate comprises the steps of forming a centrally located insulation layer region, forming first and second gate insulation layer regions on opposite sides of the centrally located insulation layer region, depositing conformally a layer of a conducting material on top of the centrally located insulation layer region and the first and second gate insulation layer regions, and etching anisotropically the conformally deposited layer of a conducting material to form first and second gate conducting layer regions in the shape of outside spacer regions on top of the first and second gate insulation layer regions and on opposite sides of the centrally located insulation layer region.
- the centrally located insulation layer region can be formed with a first length, and each of the first and second gate conducting layer regions can be formed with a second length, the first length being larger than the second length.
- the centrally located insulation layer region can be formed by depositing a layer of an insulating material, and etching the layer of an insulating material.
- the conducting material can be a doped, preferably heavily doped, semiconducting material, particularly polycrystalline silicon. Layouts of the outside spacer regions can be set by masking and isotropic etching of the layer of the conducting material.
- the outside spacer regions can be silicided, particularly nickel silicided.
- the LDMOS source and drain regions can be silicided simultaneously with the silicidation of the outside spacer regions.
- First and second contact regions can be formed, each of which being connected to a respective one of the outside spacer regions.
- the monolithically integrated circuit can be metallized, and each of the first and second contact regions can be connected individually during the metallization.
- an LDMOS transistor device in an integrated circuit, particularly an integrated circuit for radio frequency applications, comprising a novel split gate structure the gate length is considerably decreased, thereby reducing the input capacitance and increasing the speed of the LDMOS transistor device.
- the novel split gate structure comprises first and second gate insulation layer regions, a centrally located insulation layer region provided between the first and second gate insulation layer regions, and first and second gate conducting layer regions provided on top of the first and second gate insulation layer regions.
- the first and second gate conducting layers are etched outside spacer regions at opposite sides of the centrally located insulation layer region, and each has a length which is smaller, preferably much smaller, than a length of the centrally located insulation layer region.
- the length of the centrally located insulation layer region is set by a mask, whereas the gate lengths are shorter than the smallest mask dimensions that typical process lithography of today permits.
- the first and second gate conducting layer regions of the LDMOS transistor device are provided with individual contacts for electric connection.
- one of the first and second gate conducting layer regions can be connected to a control voltage
- the another one of the first and second gate conducting layer regions can be connected to a bias voltage, preferably high bias voltage, to invert channel carriers in the drain drift region of the LDMOS transistor device.
- a method of producing the inventive LDMOS transistor comprises the steps of forming a centrally located insulation layer region on top of a semiconductor substrate, preferably by means of masking and etching, forming first and second gate insulation layer regions on opposite sides of the centrally located insulation layer region, depositing conformally a layer of a conducting material on top of the centrally located insulation layer region and the first and second gate insulation layer regions, and etching anisotropically the conformally deposited layer of a conducting material to form first and second gate conducting layer regions in the shape of outside spacer regions on top of the first and second gate insulation layer regions and on opposite sides of the centrally located insulation layer region.
- a small feature size device having a gate length is produced using process steps that are typically already included in state-of-the-art BiCMOS and CMOS processes.
- FIGS. 1-10 are given by way of illustration only, and thus are not limitative of the present invention.
- FIG. 1 is a highly enlarged cross-sectional view of a monolithically integrated LDMOS transistor according to a preferred embodiment of the present invention.
- FIG. 2 illustrates typical doping concentrations in the substrate below the gate structure of an inventive LDMOS transistor, such as the one illustrated in FIG. 1 .
- FIGS. 3-6 are diagrams illustrating various simulated transistor characteristics of an inventive LDMOS transistor, such as the one illustrated in FIG. 1 , as compared to a conventional LDMOS transistor.
- FIGS. 7-10 are highly enlarged cross-sectional views of a portion of a semiconductor structure during processing according to a further preferred embodiment of the present invention.
- FIG. 1 A silicon LDMOS transistor according to a first preferred embodiment of the present invention is shown in FIG. 1 in an enlarged cross-sectional view.
- the LDMOS transistor which is particularly adapted for high power radio frequency applications, comprises a semiconductor substrate 11 , in which n 31 -type doped drain drift 12 , p-type doped channel pocket 13 , n + -type doped source 14 , and n + -type doped drain 15 regions are formed.
- the doped regions 12 - 15 in the substrate 11 are laterally surrounded by field oxide 16 or other kind of insulation areas, such as e.g. shallow trench isolation (STI) regions.
- STI shallow trench isolation
- the gate structure 17 includes a centrally located split gate-dividing separator 19 of an electrically insulating material and a first 18 a and a second 18 b gate insulation layer region on a respective side of the split gate-dividing separator 19 .
- the split gate-dividing separator 19 has a length L gd and a height h g , which are of comparable size, typically in the interval 0.5-1 micron.
- a first 20 a and second 20 b gate conducting layer region are arranged on top of the first 18 a and second 18 b gate insulation layer regions, where each of the gate conducting layer regions 20 a - b is an etched outside spacer region adjacent to the centrally located split gate-dividing separator 19 .
- each of the gate conducting layer regions 20 a - b has a length L g which is smaller to much smaller than the length L gd of the centrally located split gate-dividing separator 19 .
- the gate length L gd may preferably be less than 0.5 microns, more preferably less than 0.2 microns, and most preferably less than 0.1 microns such as e.g. about 50-70 nm.
- the gate length can be made much shorter than in conventional LDMOS transistors with lithographically defined gates.
- the channel pocket region 13 is located at least partly directly beneath one 20 a of the gate conducting layer regions, and the drain drift region 12 is located at least partly directly beneath the other one 20 b of the gate conducting layer regions.
- the first and second gate conducting layer regions 20 a - b and the source 14 and drain 15 regions are silicided.
- each of the first and second gate outside spacer regions 20 a - b consists of a silicon region 21 a - b , and a silicide region 22 a - b thereupon.
- the source and drain silicide regions are denoted 23 and 24 .
- the gate conducting layer regions 20 a - b are provided with individual contacts for electric connection.
- the gate conducting layer region 20 a closest to the source 14 is connected to a control voltage for the ordinary gate function
- the gate conducting layer region 20 b closest to the drain 15 is connected to a bias voltage, preferably high bias voltage, to invert channel carriers as much as possible below and beside itself in the drain drift region 12 .
- the drain drift region 12 should preferably be heavier doped than a drain drift region of a corresponding single gate transistor to ensure, together with the bias voltage of the gate conducting layer region 20 b closest to the drain 15 , that the channel carriers are inverted at control voltages above threshold.
- An adequate spacing between the gate conducting layer regions 20 a - b should advantageously be ensured to essentially avoid capacitive coupling between the gate conducting layer regions 20 a - b .
- the separation is preferably larger than the thickness of the gate insulation layer regions 18 a - b.
- FIG. 2 A typical doping concentration distribution of the various regions in the substrate of the inventive double spacer gate LDMOS transistor is illustrated in FIG. 2 . Also, typical feature dimensions of the transistor are indicated. The dashed lines indicate the source-channel and channel-drain pn-junctions.
- FIG. 3 The horizontal channel doping concentration distributions of the inventive double spacer gate LDMOS transistor and of a conventional prior art LDMOS transistor are illustrated in FIG. 3 . Ignoring the different locations of sources of the two LDMOS transistors it can be seen that the part of the doping concentration distribution determining the threshold voltage has the same peak value giving same threshold voltage V T in both cases.
- Drain current and transconductance, respectively, versus gate voltage at a drain bias voltage V DS 10 V for the inventive double spacer gate LDMOS transistor and for the conventional prior art LDMOS transistor are illustrated in FIG. 4 . It can here be seen that the transistors have the same threshold voltage V T .
- FIGS. 5-6 The input capacitance and the unity gain frequency f T , respectively, versus drain current for the inventive double spacer gate LDMOS transistor and for a conventional prior art LDMOS transistor are illustrated in FIGS. 5-6 . From FIG. 5 it can be seen that the input capacitance is about a factor two lower for the inventive double spacer gate LDMOS transistor. The combination of an unchanged transconductance and a reduced capacitance gives an improved gain and a corresponding increased unity gain transition frequency f T . From FIG. 6 it can be seen that the unity gain transition frequency f T is about a factor two higher for the inventive double spacer gate LDMOS transistor.
- the present invention is primarily intended for radio frequency power silicon LDMOS devices, it may as well be useful for smaller devices in silicon-based integrated radio frequency circuits.
- the double spacer gate LDMOS transistors of the present invention may be realized in other materials such as e.g. SiC, GaAs, etc.
- FIGS. 7-10 a preferred embodiment for manufacturing an integrated LDMOS transistor of the present invention is described with reference to FIGS. 7-10 .
- the fabrication may be performed in a BiCMOS process or in a pure CMOS process.
- Many of the steps in the process e.g. including ion implanting steps for forming wells and source and drain regions, are well known to the person skilled in the art and these steps will therefore not be described at all here, or will only be schematically indicated.
- the main focus is put on how the gate structure of the LDMOS transistor is formed.
- Field oxide regions 16 are formed in the surface of a semiconductor substrate 11 having an upper portion doped to n ⁇ type.
- the field oxide regions 16 are formed to surround, in a horizontal dimension, the LDMOS transistor.
- a rather thick layer of silicon oxide is deposited on top of the substrate 11 , and is then patterned and etched to form a centrally located split gate-dividing separator 19 .
- a thin gate oxide layer 71 is then deposited on the structure, and this is followed by a deposition of a conformal polycrystalline silicon layer 72 for the inventive double spacer gate structure of the LDMOS transistor.
- the conformal polycrystalline silicon layer 72 is preferably heavily doped to ensure adequate conductivity in the resulting gate structure.
- a cross-section of the resulting structure is illustrated in FIG. 7 .
- the height of the split gate-dividing structure is equal to the sum of the thickness of the thick layer of silicon oxide to form the split gate-dividing separator 19 and the thickness of the thin gate oxide layer 71
- the length of split gate-dividing structure is equal to the sum of the length of the thick layer of silicon oxide to form the split gate-dividing separator 19 and two times the thickness of the thin gate oxide layer 71 .
- the deposited thickness and etching of the thick layer of silicon oxide to form the split gate-dividing separator 19 are selected accordingly.
- the conformally deposited polycrystalline silicon layer 72 is subsequently etched anisotropically to form first and second gate conducting layer regions in the shape of outside spacer regions 21 a - b on top of the thin gate oxide layer 71 and on opposite sides of the centrally located split gate-dividing separator 19 .
- the etching is selective with respect to the underlying gate oxide layer 71 .
- a cross-section of the resulting structure is illustrated in FIG. 8 .
- the anisotropic etch is performed through a mask (not illustrated) to thereby form polycrystalline silicon contact regions 91 a - b on top of extensions of the outside spacer regions 21 a - b at an area outside the substrate area for the LDMOS transistor, where field oxide 16 has been created.
- a cross-section of such a structure is illustrated in FIG. 9 .
- the polycrystalline silicon contact regions 91 a - b may later, during metallization of the structure, be connected individually to metallic layers (not illustrated) of the structure.
- the masking and etching for formation of the polycrystalline silicon contact regions 91 a - b are used to define the layout of the outside spacer regions 21 a - b and to secure that they will be electrically insulated from each other.
- the thin gate oxide layer 71 is then etched, using the outside spacer regions 21 a - b as a mask, to form first 18 a and second 18 b gate oxide layer regions.
- the substrate dopings which have not been performed earlier in the process, are performed by ion implantation to form a channel pocket 13 , source 14 , and drain 15 regions. A cross-section of the resulting structure is illustrated in FIG. 10 .
- the process continues with silicidation of the outside spacer gate regions 21 a - b and of the source 14 and drain 15 regions to obtain a structure like the one illustrated in FIG. 1 .
- the polycrystalline silicon contact regions 91 a - b but not the extensions of the outside spacer regions 21 a - b below the polycrystalline silicon contact regions 91 a - b are nickel silicided concurrently.
- nickel, platinum, or palladium is used for silicidation. Since these atoms move essentially into the silicon during silicidation, there is no risk for bridging between the source 14 or drain 15 region and the outside spacer gate regions 21 a - b . Note that this is in contrast to some other common silicide metals, such as titanium and cobalt, where the silicon atoms move into the metal during the silicidation. In this case, the silicide might creep up and across the oxide, thereby causing short circuit between the source 14 or drain 15 region and the outside spacer gate regions 21 a - b . However, in applications where there is no risk of such short-circuiting, titanium or cobalt may equally well be used for the silicidation.
- the source 14 and drain 15 regions and the polycrystalline silicon contact regions 91 a - b can be contacted during the metallization of the device.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
- This application claims priority to Swedish application No. 0303106-9 filed Nov. 21, 2003.
- The present invention generally relates to the field of integrated circuit technology, and more specifically the invention relates to an LDMOS (lateral double diffused MOS) transistor device, to an integrated circuit including the LDMOS transistor device, and to a fabrication method of the integrated circuit with the LDMOS transistor device, respectively.
- The speed of an LDMOS transistor is determined by the transconductance gm and the input capacitance Cin, and more specifically, the speed is proportional to gm/Cin. By reducing the capacitance without changing the transconductance, the speed is increased with no additional drawbacks assuming that the process lithography is maintained unaffected.
- An improved performance using a scaled down device with a channel length shorter than the smallest mask dimensions that process lithography of today permits, has been obtained in several manners. One common method is to use a diffusion step that defines a critical length such as the channel length or the length of the gate, see e.g. the published U.S. patent application Ser. No. 20020055220 A1.
- Some prior art solutions do not take the full improvement potential into account. For instance, some of the prior art LDMOS transistors of the above-mentioned kind have still an unnecessary high input capacitance and thereby an unnecessary low speed.
- Still some prior art solutions for LDMOS transistors, such as the one depicted in the U.S. patent application, need additional process steps for fabrication of devices with sub-lithographic feature sizes.
- Accordingly, it is an object of the present invention to provide an LDMOS transistor device in an integrated circuit, particularly an integrated circuit for radio frequency applications, which LDMOS transistor device overcomes the problems associated with the prior art described above.
- Further, it is an object of the invention to provide an integrated circuit comprising such an LDMOS transistor device.
- Still further, it is an object of the invention to provide a method in the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, including an LDMOS transistor, which accomplishes the above object.
- These objects can, according to the present invention, be attained by an LDMOS transistor device in an integrated circuit, particularly an integrated circuit for radio frequency applications, comprising a semiconductor substrate, an LDMOS gate region on top of the substrate, LDMOS source and drain regions, and a channel region arranged in the substrate beneath the LDMOS gate region, the channel region interconnecting the LDMOS source and drain regions, wherein the LDMOS gate region comprises first and second gate insulation layer regions, a centrally located insulation layer region provided between the first and second gate insulation layer regions, and first and second gate conducting layer regions, each of which being provided on top of a respective one of the first and second gate insulation layer regions, each being an etched outside spacer region at the centrally located insulation layer region, and each having a length which is smaller than a length of the centrally located insulation layer region.
- The first and second gate conducting layer regions can be provided with individual contacts for electric connection. The channel region can be located at least partly directly beneath one of the first and second gate conducting layer regions, and a drain drift region can be located at least partly directly beneath another one of the first and second gate conducting layer regions. One of the first and second gate conducting layer regions can be connected to a control voltage, and the another one of the first and second gate conducting layer regions can be connected to a bias voltage, preferably high bias voltage, to invert channel carriers in the drain drift region. The first and second gate conducting layer regions can each be made of doped polycrystalline silicon. The first and second gate conducting layer regions can be silicided, particularly nickel silicided. The LDMOS transistor device can be a radio frequency power transistor. A monolithically integrated circuit may comprise the LDMOS transistor device.
- The object can also be achieved by a method in the fabrication of a monolithically integrated circuit including an LDMOS transistor device comprising the steps of providing a semiconductor substrate, forming an LDMOS gate region on top of the substrate, forming LDMOS source and drain regions, and forming a channel region arranged in the substrate beneath the LDMOS gate region, the channel region interconnecting the LDMOS source and drain regions, wherein the step of forming an LDMOS gate region on top of the substrate comprises the steps of forming a centrally located insulation layer region, forming first and second gate insulation layer regions on opposite sides of the centrally located insulation layer region, depositing conformally a layer of a conducting material on top of the centrally located insulation layer region and the first and second gate insulation layer regions, and etching anisotropically the conformally deposited layer of a conducting material to form first and second gate conducting layer regions in the shape of outside spacer regions on top of the first and second gate insulation layer regions and on opposite sides of the centrally located insulation layer region.
- The centrally located insulation layer region can be formed with a first length, and each of the first and second gate conducting layer regions can be formed with a second length, the first length being larger than the second length. The centrally located insulation layer region can be formed by depositing a layer of an insulating material, and etching the layer of an insulating material. The conducting material can be a doped, preferably heavily doped, semiconducting material, particularly polycrystalline silicon. Layouts of the outside spacer regions can be set by masking and isotropic etching of the layer of the conducting material. The outside spacer regions can be silicided, particularly nickel silicided. The LDMOS source and drain regions can be silicided simultaneously with the silicidation of the outside spacer regions. First and second contact regions, particularly made of doped, preferably heavily doped, semiconducting material, particularly polycrystalline silicon, can be formed, each of which being connected to a respective one of the outside spacer regions. The monolithically integrated circuit can be metallized, and each of the first and second contact regions can be connected individually during the metallization.
- By providing an LDMOS transistor device in an integrated circuit, particularly an integrated circuit for radio frequency applications, comprising a novel split gate structure the gate length is considerably decreased, thereby reducing the input capacitance and increasing the speed of the LDMOS transistor device.
- The novel split gate structure comprises first and second gate insulation layer regions, a centrally located insulation layer region provided between the first and second gate insulation layer regions, and first and second gate conducting layer regions provided on top of the first and second gate insulation layer regions. The first and second gate conducting layers are etched outside spacer regions at opposite sides of the centrally located insulation layer region, and each has a length which is smaller, preferably much smaller, than a length of the centrally located insulation layer region. Preferably, the length of the centrally located insulation layer region is set by a mask, whereas the gate lengths are shorter than the smallest mask dimensions that typical process lithography of today permits.
- Still preferably, the first and second gate conducting layer regions of the LDMOS transistor device are provided with individual contacts for electric connection. In this way one of the first and second gate conducting layer regions can be connected to a control voltage, and the another one of the first and second gate conducting layer regions can be connected to a bias voltage, preferably high bias voltage, to invert channel carriers in the drain drift region of the LDMOS transistor device.
- Further, a method of producing the inventive LDMOS transistor comprises the steps of forming a centrally located insulation layer region on top of a semiconductor substrate, preferably by means of masking and etching, forming first and second gate insulation layer regions on opposite sides of the centrally located insulation layer region, depositing conformally a layer of a conducting material on top of the centrally located insulation layer region and the first and second gate insulation layer regions, and etching anisotropically the conformally deposited layer of a conducting material to form first and second gate conducting layer regions in the shape of outside spacer regions on top of the first and second gate insulation layer regions and on opposite sides of the centrally located insulation layer region.
- By the fabrication method of the present invention a small feature size device having a gate length is produced using process steps that are typically already included in state-of-the-art BiCMOS and CMOS processes.
- Further characteristics of the invention and advantages thereof will be evident from the detailed description of preferred embodiments of the present invention given hereinafter and the accompanying
FIGS. 1-10 , which are given by way of illustration only, and thus are not limitative of the present invention. -
FIG. 1 is a highly enlarged cross-sectional view of a monolithically integrated LDMOS transistor according to a preferred embodiment of the present invention. -
FIG. 2 illustrates typical doping concentrations in the substrate below the gate structure of an inventive LDMOS transistor, such as the one illustrated inFIG. 1 . -
FIGS. 3-6 are diagrams illustrating various simulated transistor characteristics of an inventive LDMOS transistor, such as the one illustrated inFIG. 1 , as compared to a conventional LDMOS transistor. -
FIGS. 7-10 are highly enlarged cross-sectional views of a portion of a semiconductor structure during processing according to a further preferred embodiment of the present invention. - Identical reference numerals are used throughout the Figures to denote identical or similar components, portions, details and the like of the various embodiments.
- A silicon LDMOS transistor according to a first preferred embodiment of the present invention is shown in
FIG. 1 in an enlarged cross-sectional view. The LDMOS transistor, which is particularly adapted for high power radio frequency applications, comprises asemiconductor substrate 11, in which n31-type dopeddrain drift 12, p-type dopedchannel pocket 13, n+-type dopedsource 14, and n+-type dopeddrain 15 regions are formed. The doped regions 12-15 in thesubstrate 11 are laterally surrounded byfield oxide 16 or other kind of insulation areas, such as e.g. shallow trench isolation (STI) regions. - An inventive
LDMOS gate structure 17 is arranged on top of thesubstrate 11. Thegate structure 17 includes a centrally located split gate-dividingseparator 19 of an electrically insulating material and a first 18 a and a second 18 b gate insulation layer region on a respective side of the split gate-dividingseparator 19. The split gate-dividingseparator 19 has a length Lgd and a height hg, which are of comparable size, typically in the interval 0.5-1 micron. - A first 20 a and second 20 b gate conducting layer region, preferably of doped polycrystalline silicon, are arranged on top of the first 18 a and second 18 b gate insulation layer regions, where each of the gate conducting
layer regions 20 a-b is an etched outside spacer region adjacent to the centrally located split gate-dividingseparator 19. Further, each of the gate conductinglayer regions 20 a-b has a length Lg which is smaller to much smaller than the length Lgd of the centrally located split gate-dividingseparator 19. The gate length Lgd may preferably be less than 0.5 microns, more preferably less than 0.2 microns, and most preferably less than 0.1 microns such as e.g. about 50-70 nm. Thus, the gate length can be made much shorter than in conventional LDMOS transistors with lithographically defined gates. - The
channel pocket region 13 is located at least partly directly beneath one 20 a of the gate conducting layer regions, and thedrain drift region 12 is located at least partly directly beneath the other one 20 b of the gate conducting layer regions. - Preferably, the first and second gate conducting
layer regions 20 a-b and thesource 14 anddrain 15 regions are silicided. Thus, each of the first and second gate outsidespacer regions 20 a-b consists of asilicon region 21 a-b, and asilicide region 22 a-b thereupon. The source and drain silicide regions are denoted 23 and 24. - The gate conducting
layer regions 20 a-b are provided with individual contacts for electric connection. Preferably, the gate conductinglayer region 20 a closest to thesource 14 is connected to a control voltage for the ordinary gate function, and the gate conductinglayer region 20 b closest to thedrain 15 is connected to a bias voltage, preferably high bias voltage, to invert channel carriers as much as possible below and beside itself in thedrain drift region 12. Further, thedrain drift region 12 should preferably be heavier doped than a drain drift region of a corresponding single gate transistor to ensure, together with the bias voltage of the gateconducting layer region 20 b closest to thedrain 15, that the channel carriers are inverted at control voltages above threshold. - An adequate spacing between the gate conducting
layer regions 20 a-b should advantageously be ensured to essentially avoid capacitive coupling between the gate conductinglayer regions 20 a-b. Thus, the separation is preferably larger than the thickness of the gateinsulation layer regions 18 a-b. - A typical doping concentration distribution of the various regions in the substrate of the inventive double spacer gate LDMOS transistor is illustrated in
FIG. 2 . Also, typical feature dimensions of the transistor are indicated. The dashed lines indicate the source-channel and channel-drain pn-junctions. - The horizontal channel doping concentration distributions of the inventive double spacer gate LDMOS transistor and of a conventional prior art LDMOS transistor are illustrated in
FIG. 3 . Ignoring the different locations of sources of the two LDMOS transistors it can be seen that the part of the doping concentration distribution determining the threshold voltage has the same peak value giving same threshold voltage VT in both cases. - Drain current and transconductance, respectively, versus gate voltage at a drain bias voltage VDS=10 V for the inventive double spacer gate LDMOS transistor and for the conventional prior art LDMOS transistor are illustrated in
FIG. 4 . It can here be seen that the transistors have the same threshold voltage VT. - The input capacitance and the unity gain frequency fT, respectively, versus drain current for the inventive double spacer gate LDMOS transistor and for a conventional prior art LDMOS transistor are illustrated in
FIGS. 5-6 . FromFIG. 5 it can be seen that the input capacitance is about a factor two lower for the inventive double spacer gate LDMOS transistor. The combination of an unchanged transconductance and a reduced capacitance gives an improved gain and a corresponding increased unity gain transition frequency fT. FromFIG. 6 it can be seen that the unity gain transition frequency fT is about a factor two higher for the inventive double spacer gate LDMOS transistor. - It shall further be appreciated that while the illustrated preferred embodiments of the LDMOS transistor are n-channel devices, the present invention is not limited in this respect. The invention is equally applicable to p-channel devices.
- It shall yet further be appreciated that while the present invention is primarily intended for radio frequency power silicon LDMOS devices, it may as well be useful for smaller devices in silicon-based integrated radio frequency circuits. Further, the double spacer gate LDMOS transistors of the present invention may be realized in other materials such as e.g. SiC, GaAs, etc.
- Below, a preferred embodiment for manufacturing an integrated LDMOS transistor of the present invention is described with reference to
FIGS. 7-10 . The fabrication may be performed in a BiCMOS process or in a pure CMOS process. Many of the steps in the process, e.g. including ion implanting steps for forming wells and source and drain regions, are well known to the person skilled in the art and these steps will therefore not be described at all here, or will only be schematically indicated. The main focus is put on how the gate structure of the LDMOS transistor is formed. -
Field oxide regions 16 are formed in the surface of asemiconductor substrate 11 having an upper portion doped to n−type. Thefield oxide regions 16 are formed to surround, in a horizontal dimension, the LDMOS transistor. A rather thick layer of silicon oxide is deposited on top of thesubstrate 11, and is then patterned and etched to form a centrally located split gate-dividingseparator 19. A thingate oxide layer 71 is then deposited on the structure, and this is followed by a deposition of a conformalpolycrystalline silicon layer 72 for the inventive double spacer gate structure of the LDMOS transistor. The conformalpolycrystalline silicon layer 72 is preferably heavily doped to ensure adequate conductivity in the resulting gate structure. A cross-section of the resulting structure is illustrated inFIG. 7 . - Note that the height of the split gate-dividing structure is equal to the sum of the thickness of the thick layer of silicon oxide to form the split gate-dividing
separator 19 and the thickness of the thingate oxide layer 71, and that the length of split gate-dividing structure is equal to the sum of the length of the thick layer of silicon oxide to form the split gate-dividingseparator 19 and two times the thickness of the thingate oxide layer 71. The deposited thickness and etching of the thick layer of silicon oxide to form the split gate-dividingseparator 19 are selected accordingly. - The conformally deposited
polycrystalline silicon layer 72 is subsequently etched anisotropically to form first and second gate conducting layer regions in the shape ofoutside spacer regions 21 a-b on top of the thingate oxide layer 71 and on opposite sides of the centrally located split gate-dividingseparator 19. The etching is selective with respect to the underlyinggate oxide layer 71. A cross-section of the resulting structure is illustrated inFIG. 8 . - In order to create contacts for the
outside spacer regions 21 a-b the anisotropic etch is performed through a mask (not illustrated) to thereby form polycrystalline silicon contact regions 91 a-b on top of extensions of theoutside spacer regions 21 a-b at an area outside the substrate area for the LDMOS transistor, wherefield oxide 16 has been created. A cross-section of such a structure is illustrated inFIG. 9 . The polycrystalline silicon contact regions 91 a-b may later, during metallization of the structure, be connected individually to metallic layers (not illustrated) of the structure. The masking and etching for formation of the polycrystalline silicon contact regions 91 a-b, or other masking and etching, are used to define the layout of theoutside spacer regions 21 a-b and to secure that they will be electrically insulated from each other. - The thin
gate oxide layer 71 is then etched, using theoutside spacer regions 21 a-b as a mask, to form first 18 a and second 18 b gate oxide layer regions. The substrate dopings, which have not been performed earlier in the process, are performed by ion implantation to form achannel pocket 13,source 14, and drain 15 regions. A cross-section of the resulting structure is illustrated inFIG. 10 . - The process continues with silicidation of the outside
spacer gate regions 21 a-b and of thesource 14 and drain 15 regions to obtain a structure like the one illustrated inFIG. 1 . Note that the polycrystalline silicon contact regions 91 a-b, but not the extensions of theoutside spacer regions 21 a-b below the polycrystalline silicon contact regions 91 a-b are nickel silicided concurrently. - Preferably, nickel, platinum, or palladium is used for silicidation. Since these atoms move essentially into the silicon during silicidation, there is no risk for bridging between the
source 14 or drain 15 region and the outsidespacer gate regions 21 a-b. Note that this is in contrast to some other common silicide metals, such as titanium and cobalt, where the silicon atoms move into the metal during the silicidation. In this case, the silicide might creep up and across the oxide, thereby causing short circuit between thesource 14 or drain 15 region and the outsidespacer gate regions 21 a-b. However, in applications where there is no risk of such short-circuiting, titanium or cobalt may equally well be used for the silicidation. - After the formation of the silicide, the
source 14 and drain 15 regions and the polycrystalline silicon contact regions 91 a-b can be contacted during the metallization of the device.
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0303106-9 | 2003-11-21 | ||
SE0303106A SE0303106D0 (en) | 2003-11-21 | 2003-11-21 | Ldmos transistor device, integrated circuit, and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050110080A1 true US20050110080A1 (en) | 2005-05-26 |
US7391080B2 US7391080B2 (en) | 2008-06-24 |
Family
ID=29729128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/968,633 Expired - Fee Related US7391080B2 (en) | 2003-11-21 | 2004-10-19 | LDMOS transistor device employing spacer structure gates |
Country Status (4)
Country | Link |
---|---|
US (1) | US7391080B2 (en) |
JP (1) | JP4851080B2 (en) |
DE (1) | DE102004055640B4 (en) |
SE (1) | SE0303106D0 (en) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070045727A1 (en) * | 2005-08-25 | 2007-03-01 | Masaki Shiraishi | DMOSFET and planar type MOSFET |
US20100044789A1 (en) * | 2004-01-29 | 2010-02-25 | Enpirion, Incorporated | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052049A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated, A Delaware Corporation | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052050A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052051A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated, A Delaware Corporation | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052052A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US7868378B1 (en) * | 2005-07-18 | 2011-01-11 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
US9299691B2 (en) | 2012-11-30 | 2016-03-29 | Enpirion, Inc. | Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips |
US9536938B1 (en) | 2013-11-27 | 2017-01-03 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US9673192B1 (en) | 2013-11-27 | 2017-06-06 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US9680008B2 (en) | 2004-01-29 | 2017-06-13 | Empirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
US10020739B2 (en) | 2014-03-27 | 2018-07-10 | Altera Corporation | Integrated current replicator and method of operating the same |
US10103627B2 (en) | 2015-02-26 | 2018-10-16 | Altera Corporation | Packaged integrated circuit including a switch-mode regulator and method of forming the same |
CN111509029A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
CN111554579A (en) * | 2020-05-13 | 2020-08-18 | 上海华虹宏力半导体制造有限公司 | Switch LDMOS device and manufacturing method thereof |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8253197B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8124468B2 (en) | 2009-06-30 | 2012-02-28 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a well region |
US8222695B2 (en) | 2009-06-30 | 2012-07-17 | Semiconductor Components Industries, Llc | Process of forming an electronic device including an integrated circuit with transistors coupled to each other |
US8299560B2 (en) * | 2010-02-08 | 2012-10-30 | Semiconductor Components Industries, Llc | Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same |
US8298886B2 (en) * | 2010-02-08 | 2012-10-30 | Semiconductor Components Industries, Llc | Electronic device including doped regions between channel and drain regions and a process of forming the same |
US8389369B2 (en) * | 2010-02-08 | 2013-03-05 | Semiconductor Components Industries, Llc | Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same |
JP5732790B2 (en) | 2010-09-14 | 2015-06-10 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
US8822295B2 (en) * | 2012-04-03 | 2014-09-02 | International Business Machines Corporation | Low extension dose implants in SRAM fabrication |
US9059276B2 (en) * | 2013-05-24 | 2015-06-16 | International Business Machines Corporation | High voltage laterally diffused metal oxide semiconductor |
KR102171025B1 (en) | 2014-04-30 | 2020-10-29 | 삼성전자주식회사 | Non-volatile memory device |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574208A (en) * | 1982-06-21 | 1986-03-04 | Eaton Corporation | Raised split gate EFET and circuitry |
US5041895A (en) * | 1989-06-14 | 1991-08-20 | Sgs-Thomson Microelectronics S.R.L. | Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage |
US5548133A (en) * | 1994-09-19 | 1996-08-20 | International Rectifier Corporation | IGBT with increased ruggedness |
US5969383A (en) * | 1997-06-16 | 1999-10-19 | Motorola, Inc. | Split-gate memory device and method for accessing the same |
US6025237A (en) * | 1997-03-24 | 2000-02-15 | Fairchild Korea Semiconductor, Ltd. | Methods of forming field effect transistors having graded drain region doping profiles therein |
US6248633B1 (en) * | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
US6329687B1 (en) * | 2000-01-27 | 2001-12-11 | Advanced Micro Devices, Inc. | Two bit flash cell with two floating gate regions |
US20020055220A1 (en) * | 2000-11-03 | 2002-05-09 | Anders Soderbarg | Integration of high voltage self-aligned MOS components |
US20020140022A1 (en) * | 2001-03-29 | 2002-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical split gate field effect transistor (fet) device |
US20020149021A1 (en) * | 2001-01-03 | 2002-10-17 | Casady Jeffrey B. | Silicon carbide and related wide-bandgap transistors on semi-insulating epitaxy for high-speed, high-power applications |
US6506648B1 (en) * | 1998-09-02 | 2003-01-14 | Cree Microwave, Inc. | Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure |
US20040201078A1 (en) * | 2003-04-11 | 2004-10-14 | Liping Ren | Field plate structure for high voltage devices |
US20050106825A1 (en) * | 2003-11-13 | 2005-05-19 | Budong You | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH077824B2 (en) | 1984-01-06 | 1995-01-30 | セイコー電子工業株式会社 | Low voltage writing method for nonvolatile semiconductor memory |
JPS63213369A (en) * | 1987-03-02 | 1988-09-06 | Toshiba Corp | Mos type semiconductor device |
JPH0697439A (en) * | 1992-09-10 | 1994-04-08 | Toshiba Corp | High breakdown strength semiconductor element |
JP3166148B2 (en) * | 1995-07-11 | 2001-05-14 | 横河電機株式会社 | Semiconductor device |
JPH09121053A (en) | 1995-08-21 | 1997-05-06 | Matsushita Electric Ind Co Ltd | Vertical field-effect transistor and fabrication thereof |
JPH11266018A (en) * | 1998-03-16 | 1999-09-28 | Toshiba Corp | Semiconductor device |
US5569937A (en) * | 1995-08-28 | 1996-10-29 | Motorola | High breakdown voltage silicon carbide transistor |
JP4527814B2 (en) * | 1997-06-11 | 2010-08-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
EP1170803A3 (en) * | 2000-06-08 | 2002-10-09 | Siliconix Incorporated | Trench gate MOSFET and method of making the same |
US6468847B1 (en) * | 2000-11-27 | 2002-10-22 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
US6639276B2 (en) * | 2001-07-05 | 2003-10-28 | International Rectifier Corporation | Power MOSFET with ultra-deep base and reduced on resistance |
-
2003
- 2003-11-21 SE SE0303106A patent/SE0303106D0/en unknown
-
2004
- 2004-10-19 US US10/968,633 patent/US7391080B2/en not_active Expired - Fee Related
- 2004-11-18 DE DE102004055640A patent/DE102004055640B4/en not_active Expired - Fee Related
- 2004-11-19 JP JP2004335343A patent/JP4851080B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574208A (en) * | 1982-06-21 | 1986-03-04 | Eaton Corporation | Raised split gate EFET and circuitry |
US5041895A (en) * | 1989-06-14 | 1991-08-20 | Sgs-Thomson Microelectronics S.R.L. | Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage |
US5548133A (en) * | 1994-09-19 | 1996-08-20 | International Rectifier Corporation | IGBT with increased ruggedness |
US6025237A (en) * | 1997-03-24 | 2000-02-15 | Fairchild Korea Semiconductor, Ltd. | Methods of forming field effect transistors having graded drain region doping profiles therein |
US5969383A (en) * | 1997-06-16 | 1999-10-19 | Motorola, Inc. | Split-gate memory device and method for accessing the same |
US6506648B1 (en) * | 1998-09-02 | 2003-01-14 | Cree Microwave, Inc. | Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure |
US6248633B1 (en) * | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
US6329687B1 (en) * | 2000-01-27 | 2001-12-11 | Advanced Micro Devices, Inc. | Two bit flash cell with two floating gate regions |
US20020055220A1 (en) * | 2000-11-03 | 2002-05-09 | Anders Soderbarg | Integration of high voltage self-aligned MOS components |
US20020149021A1 (en) * | 2001-01-03 | 2002-10-17 | Casady Jeffrey B. | Silicon carbide and related wide-bandgap transistors on semi-insulating epitaxy for high-speed, high-power applications |
US20020140022A1 (en) * | 2001-03-29 | 2002-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical split gate field effect transistor (fet) device |
US20040201078A1 (en) * | 2003-04-11 | 2004-10-14 | Liping Ren | Field plate structure for high voltage devices |
US20050106825A1 (en) * | 2003-11-13 | 2005-05-19 | Budong You | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8987815B2 (en) | 2004-01-29 | 2015-03-24 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US20100044789A1 (en) * | 2004-01-29 | 2010-02-25 | Enpirion, Incorporated | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052049A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated, A Delaware Corporation | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052050A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052051A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated, A Delaware Corporation | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US20100052052A1 (en) * | 2004-01-29 | 2010-03-04 | Enpirion, Incorporated | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same |
US9680008B2 (en) | 2004-01-29 | 2017-06-13 | Empirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
US8212315B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212316B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8212317B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253196B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8253195B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US8431450B1 (en) * | 2005-07-18 | 2013-04-30 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
US7868378B1 (en) * | 2005-07-18 | 2011-01-11 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
US20070045727A1 (en) * | 2005-08-25 | 2007-03-01 | Masaki Shiraishi | DMOSFET and planar type MOSFET |
US9299691B2 (en) | 2012-11-30 | 2016-03-29 | Enpirion, Inc. | Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips |
US9443839B2 (en) | 2012-11-30 | 2016-09-13 | Enpirion, Inc. | Semiconductor device including gate drivers around a periphery thereof |
US9553081B2 (en) | 2012-11-30 | 2017-01-24 | Enpirion, Inc. | Semiconductor device including a redistribution layer and metallic pillars coupled thereto |
US9536938B1 (en) | 2013-11-27 | 2017-01-03 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US9673192B1 (en) | 2013-11-27 | 2017-06-06 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
US10020739B2 (en) | 2014-03-27 | 2018-07-10 | Altera Corporation | Integrated current replicator and method of operating the same |
US10103627B2 (en) | 2015-02-26 | 2018-10-16 | Altera Corporation | Packaged integrated circuit including a switch-mode regulator and method of forming the same |
CN111509029A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
CN111554579A (en) * | 2020-05-13 | 2020-08-18 | 上海华虹宏力半导体制造有限公司 | Switch LDMOS device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP4851080B2 (en) | 2012-01-11 |
JP2005159352A (en) | 2005-06-16 |
US7391080B2 (en) | 2008-06-24 |
DE102004055640A1 (en) | 2005-08-25 |
DE102004055640B4 (en) | 2009-03-19 |
SE0303106D0 (en) | 2003-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7391080B2 (en) | LDMOS transistor device employing spacer structure gates | |
US6518138B2 (en) | Method of forming Self-aligned lateral DMOS with spacer drift region | |
US7220646B2 (en) | Integrated circuit structure with improved LDMOS design | |
JP4723698B2 (en) | Power switching trench MOSFET having matched source region and method of manufacturing the same | |
KR101293927B1 (en) | Semiconductor device having screening electrode and method | |
JP5378635B2 (en) | Metal oxide semiconductor device formed in silicon-on-insulator | |
US20050056892A1 (en) | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | |
US20070218635A1 (en) | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | |
KR20010092309A (en) | Decoupling capacitors and methods for forming the same | |
US6509609B1 (en) | Grooved channel schottky MOSFET | |
KR100723076B1 (en) | Semiconductor device with transparent link area for silicide applications and fabrication thereof | |
US7517759B2 (en) | Method of fabricating metal oxide semiconductor device | |
KR100966033B1 (en) | Method of making a vertical gate semiconductor device | |
JPH08125180A (en) | Semiconductor device and fabrication thereof | |
US6100144A (en) | Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors | |
KR950011020B1 (en) | Semiconductor device and its making method | |
JP2000012851A (en) | Field-effect transistor and manufacture thereof | |
US9754839B2 (en) | MOS transistor structure and method | |
US6429056B1 (en) | Dynamic threshold voltage devices with low gate to substrate resistance | |
JPH07335837A (en) | Semiconductor device and logic circuit | |
US7060572B2 (en) | MOSFET with short channel structure and formation method thereof | |
JPH05198804A (en) | Semiconductor device and manufacturing method thereof | |
JP2001250950A (en) | Semiconductor device | |
JPH11214527A (en) | Semiconductor device and manufacture thereof | |
CN118016712A (en) | Transistor with metal field plate contact |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ARNBORG, TORKEL;SMITH, ULF;REEL/FRAME:015933/0736;SIGNING DATES FROM 20040910 TO 20040916 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20200624 |