US20050110045A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US20050110045A1 US20050110045A1 US10/994,261 US99426104A US2005110045A1 US 20050110045 A1 US20050110045 A1 US 20050110045A1 US 99426104 A US99426104 A US 99426104A US 2005110045 A1 US2005110045 A1 US 2005110045A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 4
- 239000010410 layer Substances 0.000 description 162
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 15
- 238000009413 insulation Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 2
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- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
Definitions
- the present invention relates to a semiconductor device such as heterojunction bipolar transistor (HBT) and a method of manufacturing the same.
- HBT heterojunction bipolar transistor
- the present invention relates to a semiconductor device which ensures electrical isolation between device elements such as HBT and easily achieves high current gain, high reliability, and planarization while reducing collector resistance to enhance the efficiency of an amplifier, and a method of manufacturing the same.
- a typical example of HBT is fabricated on a semi-insulating gallium arsenide (GaAs) substrate.
- GaAs gallium arsenide
- a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer are epitaxially grown on the semi-insulating GaAs substrate.
- an emitter electrode, a base electrode, and a collector electrode are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer.
- FIGS. 1A and 1B show examples of conventional semiconductor devices.
- a base electrode 108 formed of Pt/Ti/Pt/Au is placed on the base layer 103 .
- a collector electrode 109 formed of Ni/AuGe/Au is placed on the collector layer 101 .
- the semiconductor device of FIG. 1A has an element insulating region 110 created by ion implantation, and the semiconductor device of FIG. 1B has an element insulating region 111 , which is a recess, formed by removing the sub-collector layer 101 by etching.
- FIGS. 2A to 2 D show the configurations in the course of the process to form the device of FIG. 1 .
- an epitaxial wafer in which the sub-collector layer 101 , collector layer 102 , base layer 103 , emitter layer 104 , emitter cap layer 105 , and emitter cap layer 106 are sequentially laminated on the substrate 100 is formed.
- WSi which serves as the emitter electrode 107
- the emitter electrode 107 is then formed by dry etching, using a patterned photoresist mask. Using the emitter electrode 107 as a mask, etching is performed with sulfuric etchant to expose the surface of the emitter layer 104 .
- the emitter cap layers 105 , 106 , and emitter electrode 107 are thereby shaped as shown in FIG. 2B .
- Pt/Ti/Pt/Au is deposited on the emitter layer 104 by evaporation and lift-off process.
- the Pt/Ti/Pt/Au is sintered by alloy process to contact with the base layer 103 , thereby forming the base electrode 108 .
- etching is performed using a patterned photoresist as a mask to expose the sub-collector layer 101 .
- the configuration of FIG. 2C is thereby created.
- the collector electrode 109 is formed on the sub-collector 101 by the evaporation and lift-off process.
- the configuration of FIG. 2D is thereby created.
- the element insulating region 110 shown in FIG. 1A is created by ion implantation with boron and so on, using a photoresist as a mask. It allows insulation of the sub-collector layer 101 between elements.
- the recess-shaped element insulating region 111 shown in FIG. 1B may be formed by etching the sub-collector layer 101 . It also allows insulation of the sub-collector layer 101 between elements.
- the access resistance constituting part of the collector resistance is determined by sheet resistance of the sub-collector layer.
- the sheet resistance can be reduced by increasing the thickness of the sub-collector layer or by increasing the impurity concentration of the sub-collector layer.
- a normal thickness of the sub-collector layer is in the range of 100 to 700 nm, and a normal doping concentration is in the range of 1*10 18 /cm 3 to 6*10 18 /cm 3 .
- the thickness of the sub-collector layer exceeds the above range, it is difficult to completely insulate the sub-collector layer between elements by ion implantation with boron and so on. Though the ion implantation with proton, helium and the like allows deep implantation, it degrades reliability.
- the doping concentration of the sub-collector layer exceeds the above range, it causes problems such as decrease in current gain and degradation in reliability.
- Tanomura, et al. describes a heterojunction semiconductor device which overcomes problems of instable collector resistance in high-temperature testing and so on while the collector resistance is reduced as low as possible and eliminates the dislocation into a base layer to increase current gain or enhance reliability while minimizing the collector resistance.
- Tanomura teaches to form the delta-doped sheet region of a given concentration between the collector layer and the collector electrode on the surface of the sub-collector layer.
- Tanomura does not mention the insulation between device elements.
- the present invention has recognized that conventional heterojunction semiconductor devices have a problem that increasing the thickness of the sub-collector layer for higher amplifier efficiency sacrifices the insulation of the sub-collector between device elements.
- the present invention forms a sub-collector layer with two laminated layers. Further, the invention implants ion into a first sub-collector layer adjacent to the substrate, and forms a recess in a second sub-collector layer where a collector electrode is placed, thus creating an element insulating region in each layer.
- the present invention places an etching stop layer between the first and second sub-collector layers, and creates an element insulating region by ion implantation or recess formation using the etching stop layer.
- the sub-collector layer is made up of two laminated layers.
- the collector resistance can be reduced in the semiconductor device area.
- ion is implanted into the first layer adjacent to the substrate, and a recess is formed in the second layer where the collector electrode is placed. Since each of the first and second sub-collector layers has half the thickness required for resistance reduction, the ion implantation is ensured, and the planarization is easily achieved because of the low recess height.
- FIGS. 1A and 1B are cross sectional views showing the partial structures of conventional semiconductor devices
- FIGS. 2A to 2 D are cross sectional views showing the partial structures in the course of manufacturing the semiconductor device of FIGS. 1A or 1 B,
- FIG. 3 is a cross sectional view showing a example of the partial structure of a semiconductor device according to a first embodiment of the invention
- FIGS. 4A to 4 E are cross sectional views showing the partial structures in the course of manufacturing the semiconductor device of FIG. 3 .
- FIG. 5 is a cross sectional view showing a example of the partial structure of a semiconductor device according to a second embodiment of the invention.
- FIG. 6 is a cross sectional view showing a example of the partial structure of a semiconductor device according to a third embodiment of the invention.
- the present invention ensures electrical isolation of elements in spite of increase in the thickness of the sub-collector layer as a means of reducing the collector resistance of the sub-collector layer adjacent to the collector electrode in order to enhance the efficiency of an amplifier in HBT and so on.
- the present invention forms the sub-collector layer with two laminated layers, in which ion is implanted into the layer in the substrate side and a recess is formed in the layer in the surface side.
- the two sub-collector layers may be made of the same material, with an etching stop layer placed therebetween.
- a first embodiment of the present invention is explained hereinafter with reference to FIG. 3 .
- FIG. 3 is an explanatory view showing an example of the cross section of one device element of the semiconductor device according to the present invention.
- a first sub-collector layer 101 a On a semi-insulating GaAs substrate 100 , a first sub-collector layer 101 a , an etching stop layer 101 c , a second sub-collector layer 101 b , a collector layer 102 , a base layer 103 , an emitter layer 104 , an emitter cap layer 105 , and an emitter cap layer 106 , each having a given shape, are sequentially laminated.
- the sub-collector layer of this embodiment consists of three laminated layers: the first sub-collector layer 101 a at the bottom, the etching stop layer 101 c , and the second sub-collector layer 101 b at the top.
- the first sub-collector layer 101 a has an element insulating region 110 made by ion implantation.
- the second sub-collector layer 101 b has a recess-shaped element insulating region 111 penetrating into the etching stop layer 101 c.
- the first and second sub-collector layer 101 b and 101 a are formed of GaAs, and the etching stop layer 101 c is formed of AlGaAs, InGaP, or InGaAsP, for example.
- the first and second sub-collector layers 101 a and 101 b are formed of AlGaAs, and the etching stop layer 101 c is formed of InGaP or InGaAsP.
- the first and second sub-collector layers 101 a and 101 b are formed of InGaAs, and the etching stop layer 101 c is formed of InGaP or InGaAsP.
- the first and second sub-collector layers 101 a and 101 b preferably have the thickness of about 500 nm and the doping concentration of 1*10 18 /cm 3 or above.
- the etching stop layer 101 c normally has higher resistance than the sub-collector layers 101 a and 101 b , its thickness is as thin as 1 to 10 nm. If the etching stop layer 101 c is formed of InGaP having a crystal structure in which superlattice ordering partially occurs, it is possible to reduce the resistance between the sub-collector layers 101 a and 101 b since the InGaP does not induce a potential barrier with GaAs of the sub-collector layers 101 a and 101 b.
- the collector layer 102 may be formed of n-type or non-doped GaAs
- the base layer 103 may be formed of p-type GaAs
- the emitter layer 104 may be formed of n-type InGaP or AlGaAs lattice-matched to GaAs
- the emitter cap layer 105 may be formed of n-type GaAs
- the emitter cap layer 106 may be formed of InGaAs.
- the emitter electrode 107 formed of WSi is placed on the emitter cap layer 106 .
- the base electrode 108 formed of Pt/Ti/Pt/Au is placed on the base layer 103 .
- the collector electrode 109 formed of Ni/AuGe/Au is placed on the collector layer 101 .
- the HBT device is thereby composed.
- FIGS. 4A to 4 E show the configurations in the course of the process to form the device of FIG. 3 .
- an epitaxial wafer in which the sub-collector layer 101 a , etching stop layer 101 c , sub-collector layer 101 b , collector layer 102 , base layer 103 , emitter layer 104 , emitter cap layer 105 , and emitter cap layer 106 are sequentially laminated on the substrate 100 is formed.
- WSi which serves as the emitter electrode 107 , is deposited by sputtering on one surface of the epitaxial wafer, and it is patterned with photoresist. Using the patterned photoresist as a mask, dry etching is performed to form the emitter electrode 107 .
- etching is performed with sulfuric etchant to expose the surface of the emitter layer 104 .
- the emitter cap layers 105 , 106 , and emitter electrode 107 are thereby shaped as shown in FIG. 4B .
- Pt/Ti/Pt/Au is deposited on the emitter layer 104 by evaporation and lift-off process.
- the Pt/Ti/Pt/Au is sintered by alloy process so as to contact with the base layer 103 , thereby forming the base electrode 108 .
- etching is performed using a patterned photoresist as a mask to expose the sub-collector layer 101 .
- the configuration of FIG. 4C is thereby obtained.
- the collector electrode 109 is formed on the sub-collector 101 by the evaporation and lift-off process.
- the configuration of FIG. 4D is thereby obtained.
- a photoresist 112 is then deposited as shown in FIG. 4E . Using the photoresist 112 as a mask, selective etching is performed above the element insulating region 111 .
- the second sub-collector layer 101 b is selectively etched away, using the etching stop layer 101 c as a stopper. Further, the etching stop layer 101 c is selectively etched away to expose the first sub-collector layer 101 a .
- the recess-shaped element insulating region 111 is thereby formed.
- ion is implanted into the first sub-collector layer 101 a between adjacent device elements, thereby forming the element insulating region 110 .
- the dopant ion is boron and so on. The configuration of FIG. 3 is thus formed, allowing insulation of the first sub-collector layer 101 a from adjacent device elements.
- the sub-collector layer 101 in the ion implantation area consists of a single layer of the first sub-collector layer 101 a , the ion implantation can be performed easily.
- the sub-collector layer in the device element area consists of two layers of the first and second sub-collector layers 101 a and 101 b sandwiching the etching stop layer 101 c , the sub-collector layer of this area is thick enough to allow reduction of the sheet resistance in the device element area, thus reducing the access resistance to achieve low collector resistance.
- a second embodiment of the present invention is explained hereinafter with reference to FIG. 5 .
- FIG. 5 is an explanatory view showing an example of the cross section of a semiconductor device different from the above-described device.
- the same elements as in FIG. 3 are denoted by the same reference symbols and redundant description is omitted.
- the second sub-collector layer 101 b only is selectively etched away using the etching stop layer 101 c as a stopper, thereby creating the recess-shaped element insulating region 111 .
- the etching stop layer 101 c is not etched away. Then, ion implantation with boron and so on is performed both on the exposed etching stop layer 101 c and the first sub-collector layer 101 a , thereby creating the element insulating region 110 to insulate adjacent device elements from each other.
- a third embodiment of the present invention is explained hereinafter with reference to FIG. 6 .
- FIG. 6 is an explanatory view showing an example of the cross section of a semiconductor device different from the above-described devices.
- the same elements as in FIG. 3 are denoted by the same reference symbols and redundant description is omitted.
- This embodiment is different from the above embodiment in that it eliminates the etching stop layer.
- the first sub-collector layer 101 a is made of the material which has etching selectivity against the second sub-collector layer 101 b.
- the first sub-collector layer 101 a is formed of GaAs
- the second sub-collector layer 101 b is formed of AlGaAs, InGaP, or InGaAsP.
- the first sub-collector layer 101 a is formed of AlGaAs
- the second sub-collector layer 101 b is formed of InGaP or InGaAsP.
- the first sub-collector layer 101 a is formed of InGaAs
- the second sub-collector layer 101 b is formed of InGaP or InGaAsP.
- the second sub-collector layer 101 b is selectively etched away using the first sub-collector layer 101 a as a stopper, thereby creating the recess-shaped element insulating region 111 . Then, ion implantation with boron and so on is performed on the exposed first sub-collector layer 101 a , thereby creating the element insulating region 110 in the sub-collector layer 101 a . This allows insulation of adjacent device elements.
- This invention allows easy formation of an element insulating region for device element insulation by using two laminated sub-collector layers.
- This configuration is suitable for applications that require low collector resistance, easy planarization, and high reliability with secure element insulation. For example, it is applicable to the semiconductor device having the configuration taught by Tanomura.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device such as heterojunction bipolar transistor (HBT) and a method of manufacturing the same. Particularly, the present invention relates to a semiconductor device which ensures electrical isolation between device elements such as HBT and easily achieves high current gain, high reliability, and planarization while reducing collector resistance to enhance the efficiency of an amplifier, and a method of manufacturing the same.
- 2. Description of Related Art
- A typical example of HBT is fabricated on a semi-insulating gallium arsenide (GaAs) substrate. A sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer are epitaxially grown on the semi-insulating GaAs substrate. Further, an emitter electrode, a base electrode, and a collector electrode are respectively formed on the emitter cap layer, the base layer, and the sub-collector layer. In a high-power amplifier using the HBT, it is necessary to reduce collector resistance to as low as possible in order to enhance the efficiency, which is one of the important factors for a high-performance amplifier.
- In the HBT, a current path is created from the collector layer to the collector electrode through the conductive sub-collector layer. The resistance against the current flowing through the sub-collector layer, which is referred to hereinafter as “access resistance”, constitutes part of the collector resistance. On the other hand, in order to electrically isolate device elements such as transistors from each other, it is necessary to insulate the sub-collector layer between the elements.
-
FIGS. 1A and 1B show examples of conventional semiconductor devices. On asemi-insulating GaAs substrate 100, asub-collector layer 101 formed of n-type GaAs, acollector layer 102 formed of n-type or non-doped GaAs, abase layer 103 formed of p-type GaAs, anemitter layer 104 formed of n-type InGaP or AlGaAs lattice-matched to GaAs, anemitter cap layer 105 formed of n-type GaAs, and anemitter cap layer 106 formed of InGaAs are laminated sequentially. Further, anemitter electrode 107 formed of WSi is placed on theemitter cap layer 106. Abase electrode 108 formed of Pt/Ti/Pt/Au is placed on thebase layer 103. Acollector electrode 109 formed of Ni/AuGe/Au is placed on thecollector layer 101. These components constitute a HBT device. - In order to insulate the
sub-collector layer 101 between device elements, the semiconductor device ofFIG. 1A has anelement insulating region 110 created by ion implantation, and the semiconductor device ofFIG. 1B has an elementinsulating region 111, which is a recess, formed by removing thesub-collector layer 101 by etching. - A method of manufacturing the semiconductor device is explained hereinafter with reference to
FIGS. 2A to 2D, which show the configurations in the course of the process to form the device ofFIG. 1 . - First, as shown in
FIG. 2A , an epitaxial wafer in which thesub-collector layer 101,collector layer 102,base layer 103,emitter layer 104,emitter cap layer 105, andemitter cap layer 106 are sequentially laminated on thesubstrate 100 is formed. Next, WSi, which serves as theemitter electrode 107, is deposited by sputtering on one surface of the epitaxial wafer. Theemitter electrode 107 is then formed by dry etching, using a patterned photoresist mask. Using theemitter electrode 107 as a mask, etching is performed with sulfuric etchant to expose the surface of theemitter layer 104. Theemitter cap layers emitter electrode 107 are thereby shaped as shown inFIG. 2B . - Then, Pt/Ti/Pt/Au is deposited on the
emitter layer 104 by evaporation and lift-off process. The Pt/Ti/Pt/Au is sintered by alloy process to contact with thebase layer 103, thereby forming thebase electrode 108. Then, etching is performed using a patterned photoresist as a mask to expose thesub-collector layer 101. The configuration ofFIG. 2C is thereby created. - Then, the
collector electrode 109 is formed on thesub-collector 101 by the evaporation and lift-off process. The configuration ofFIG. 2D is thereby created. - After that, the element
insulating region 110 shown inFIG. 1A is created by ion implantation with boron and so on, using a photoresist as a mask. It allows insulation of thesub-collector layer 101 between elements. Alternatively, the recess-shapedelement insulating region 111 shown inFIG. 1B may be formed by etching thesub-collector layer 101. It also allows insulation of thesub-collector layer 101 between elements. - As described above, reduction of the collector resistance is critical to increase the amplifier efficiency of the semiconductor device. The access resistance constituting part of the collector resistance is determined by sheet resistance of the sub-collector layer. The sheet resistance can be reduced by increasing the thickness of the sub-collector layer or by increasing the impurity concentration of the sub-collector layer. Currently, a normal thickness of the sub-collector layer is in the range of 100 to 700 nm, and a normal doping concentration is in the range of 1*1018/cm3 to 6*1018/cm3.
- If the thickness of the sub-collector layer exceeds the above range, it is difficult to completely insulate the sub-collector layer between elements by ion implantation with boron and so on. Though the ion implantation with proton, helium and the like allows deep implantation, it degrades reliability.
- In the case of insulating the sub-collector layer between elements by a recess, it is necessary to form a recess whose depth equals the thickness of the sub-collector layer. Thus, if the sub-collector layer is thick, a step height on the sub-collector layer is large. This poses a problem for the subsequent manufacturing process such as planarization.
- If, on the other hand, the doping concentration of the sub-collector layer exceeds the above range, it causes problems such as decrease in current gain and degradation in reliability.
- Japanese Unexamined Patent Application Publication No. 2002-299603 (Tanomura, et al.) describes a heterojunction semiconductor device which overcomes problems of instable collector resistance in high-temperature testing and so on while the collector resistance is reduced as low as possible and eliminates the dislocation into a base layer to increase current gain or enhance reliability while minimizing the collector resistance. Tanomura teaches to form the delta-doped sheet region of a given concentration between the collector layer and the collector electrode on the surface of the sub-collector layer.
- However, Tanomura does not mention the insulation between device elements.
- As described above, the present invention has recognized that conventional heterojunction semiconductor devices have a problem that increasing the thickness of the sub-collector layer for higher amplifier efficiency sacrifices the insulation of the sub-collector between device elements.
- In order to obtain high insulation reliability and allow easy planarization in spite of increase in the thickness of the sub-collector layer and to obtain high current gain and reliability in spite of increase in the impurity concentration of the sub-collector layer, the present invention forms a sub-collector layer with two laminated layers. Further, the invention implants ion into a first sub-collector layer adjacent to the substrate, and forms a recess in a second sub-collector layer where a collector electrode is placed, thus creating an element insulating region in each layer.
- Furthermore, the present invention places an etching stop layer between the first and second sub-collector layers, and creates an element insulating region by ion implantation or recess formation using the etching stop layer.
- In the semiconductor device and the method of manufacturing the same according to this invention, the sub-collector layer is made up of two laminated layers. Thus, the collector resistance can be reduced in the semiconductor device area. To create an element insulating region in the sub-collector layer, ion is implanted into the first layer adjacent to the substrate, and a recess is formed in the second layer where the collector electrode is placed. Since each of the first and second sub-collector layers has half the thickness required for resistance reduction, the ion implantation is ensured, and the planarization is easily achieved because of the low recess height.
- In the case of making up the sub-collector layer only with the first and second sub-collector layers, it is needed to use two different materials having etching selectivity against each other for the first and second layers in consideration of the etching for recess formation. This need can be avoided by inserting the etching stop layer between the first and second sub-collector layers. This expands the range of choices for materials.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1A and 1B are cross sectional views showing the partial structures of conventional semiconductor devices, -
FIGS. 2A to 2D are cross sectional views showing the partial structures in the course of manufacturing the semiconductor device ofFIGS. 1A or 1B, -
FIG. 3 is a cross sectional view showing a example of the partial structure of a semiconductor device according to a first embodiment of the invention, -
FIGS. 4A to 4E are cross sectional views showing the partial structures in the course of manufacturing the semiconductor device ofFIG. 3 , -
FIG. 5 is a cross sectional view showing a example of the partial structure of a semiconductor device according to a second embodiment of the invention, and -
FIG. 6 is a cross sectional view showing a example of the partial structure of a semiconductor device according to a third embodiment of the invention. - The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed.
- The present invention ensures electrical isolation of elements in spite of increase in the thickness of the sub-collector layer as a means of reducing the collector resistance of the sub-collector layer adjacent to the collector electrode in order to enhance the efficiency of an amplifier in HBT and so on. To achieve high current gain and high reliability while ensuring the ion implantation and facilitating the planarization process by reducing the recess height, the present invention forms the sub-collector layer with two laminated layers, in which ion is implanted into the layer in the substrate side and a recess is formed in the layer in the surface side. For easier ion implantation and recess formation, the two sub-collector layers may be made of the same material, with an etching stop layer placed therebetween.
- First Embodiment
- A first embodiment of the present invention is explained hereinafter with reference to
FIG. 3 . -
FIG. 3 is an explanatory view showing an example of the cross section of one device element of the semiconductor device according to the present invention. On asemi-insulating GaAs substrate 100, a firstsub-collector layer 101 a, anetching stop layer 101 c, a secondsub-collector layer 101 b, acollector layer 102, abase layer 103, anemitter layer 104, anemitter cap layer 105, and anemitter cap layer 106, each having a given shape, are sequentially laminated. - Unlike the conventional one, the sub-collector layer of this embodiment consists of three laminated layers: the first
sub-collector layer 101 a at the bottom, theetching stop layer 101 c, and the secondsub-collector layer 101 b at the top. The firstsub-collector layer 101 a has anelement insulating region 110 made by ion implantation. The secondsub-collector layer 101 b has a recess-shapedelement insulating region 111 penetrating into theetching stop layer 101 c. - Preferably, the first and second
sub-collector layer etching stop layer 101 c is formed of AlGaAs, InGaP, or InGaAsP, for example. For another example, the first and secondsub-collector layers etching stop layer 101 c is formed of InGaP or InGaAsP. For still another example, the first and secondsub-collector layers etching stop layer 101 c is formed of InGaP or InGaAsP. The first and secondsub-collector layers - Since the
etching stop layer 101 c normally has higher resistance than thesub-collector layers etching stop layer 101 c is formed of InGaP having a crystal structure in which superlattice ordering partially occurs, it is possible to reduce the resistance between thesub-collector layers sub-collector layers - Other components may be made of the same materials as conventional ones or other materials having the same function. For example, as is the conventional case, the
collector layer 102 may be formed of n-type or non-doped GaAs, thebase layer 103 may be formed of p-type GaAs, theemitter layer 104 may be formed of n-type InGaP or AlGaAs lattice-matched to GaAs, theemitter cap layer 105 may be formed of n-type GaAs, and theemitter cap layer 106 may be formed of InGaAs. - The
emitter electrode 107 formed of WSi is placed on theemitter cap layer 106. Thebase electrode 108 formed of Pt/Ti/Pt/Au is placed on thebase layer 103. Thecollector electrode 109 formed of Ni/AuGe/Au is placed on thecollector layer 101. The HBT device is thereby composed. - A method of manufacturing the semiconductor device is explained hereinafter with reference to
FIGS. 4A to 4E, which show the configurations in the course of the process to form the device ofFIG. 3 . - First, as shown in
FIG. 4A , an epitaxial wafer in which thesub-collector layer 101 a,etching stop layer 101 c,sub-collector layer 101 b,collector layer 102,base layer 103,emitter layer 104,emitter cap layer 105, andemitter cap layer 106 are sequentially laminated on thesubstrate 100 is formed. Next, WSi, which serves as theemitter electrode 107, is deposited by sputtering on one surface of the epitaxial wafer, and it is patterned with photoresist. Using the patterned photoresist as a mask, dry etching is performed to form theemitter electrode 107. Then, using theemitter electrode 107 as a mask, etching is performed with sulfuric etchant to expose the surface of theemitter layer 104. The emitter cap layers 105, 106, andemitter electrode 107 are thereby shaped as shown inFIG. 4B . - After that, Pt/Ti/Pt/Au is deposited on the
emitter layer 104 by evaporation and lift-off process. The Pt/Ti/Pt/Au is sintered by alloy process so as to contact with thebase layer 103, thereby forming thebase electrode 108. After that, etching is performed using a patterned photoresist as a mask to expose thesub-collector layer 101. The configuration ofFIG. 4C is thereby obtained. - Then, the
collector electrode 109 is formed on the sub-collector 101 by the evaporation and lift-off process. The configuration ofFIG. 4D is thereby obtained. - A
photoresist 112 is then deposited as shown inFIG. 4E . Using thephotoresist 112 as a mask, selective etching is performed above theelement insulating region 111. - In this selective etching, the second
sub-collector layer 101 b is selectively etched away, using theetching stop layer 101 c as a stopper. Further, theetching stop layer 101 c is selectively etched away to expose the firstsub-collector layer 101 a. The recess-shapedelement insulating region 111 is thereby formed. Then, ion is implanted into the firstsub-collector layer 101 a between adjacent device elements, thereby forming theelement insulating region 110. The dopant ion is boron and so on. The configuration ofFIG. 3 is thus formed, allowing insulation of the firstsub-collector layer 101 a from adjacent device elements. - Since the
sub-collector layer 101 in the ion implantation area consists of a single layer of the firstsub-collector layer 101 a, the ion implantation can be performed easily. On the other hand, since the sub-collector layer in the device element area consists of two layers of the first and secondsub-collector layers etching stop layer 101 c, the sub-collector layer of this area is thick enough to allow reduction of the sheet resistance in the device element area, thus reducing the access resistance to achieve low collector resistance. - Second Embodiment
- A second embodiment of the present invention is explained hereinafter with reference to
FIG. 5 . -
FIG. 5 is an explanatory view showing an example of the cross section of a semiconductor device different from the above-described device. The same elements as inFIG. 3 are denoted by the same reference symbols and redundant description is omitted. - In this embodiment, the second
sub-collector layer 101 b only is selectively etched away using theetching stop layer 101 c as a stopper, thereby creating the recess-shapedelement insulating region 111. Theetching stop layer 101 c is not etched away. Then, ion implantation with boron and so on is performed both on the exposedetching stop layer 101 c and the firstsub-collector layer 101 a, thereby creating theelement insulating region 110 to insulate adjacent device elements from each other. - This configuration offers substantially the same effect as the above embodiment.
- Third Embodiment
- A third embodiment of the present invention is explained hereinafter with reference to
FIG. 6 . -
FIG. 6 is an explanatory view showing an example of the cross section of a semiconductor device different from the above-described devices. The same elements as inFIG. 3 are denoted by the same reference symbols and redundant description is omitted. - This embodiment is different from the above embodiment in that it eliminates the etching stop layer.
- Thus, the first
sub-collector layer 101 a is made of the material which has etching selectivity against the secondsub-collector layer 101 b. - For example, the first
sub-collector layer 101 a is formed of GaAs, and the secondsub-collector layer 101 b is formed of AlGaAs, InGaP, or InGaAsP. For another example, the firstsub-collector layer 101 a is formed of AlGaAs, and the secondsub-collector layer 101 b is formed of InGaP or InGaAsP. For still another example, the firstsub-collector layer 101 a is formed of InGaAs, and the secondsub-collector layer 101 b is formed of InGaP or InGaAsP. - In this embodiment, firstly, the second
sub-collector layer 101 b is selectively etched away using the firstsub-collector layer 101 a as a stopper, thereby creating the recess-shapedelement insulating region 111. Then, ion implantation with boron and so on is performed on the exposed firstsub-collector layer 101 a, thereby creating theelement insulating region 110 in thesub-collector layer 101 a. This allows insulation of adjacent device elements. - This configuration offers substantially the same effect as the above embodiments.
- This invention allows easy formation of an element insulating region for device element insulation by using two laminated sub-collector layers. This configuration is suitable for applications that require low collector resistance, easy planarization, and high reliability with secure element insulation. For example, it is applicable to the semiconductor device having the configuration taught by Tanomura.
- It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.
Claims (9)
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CN104392923A (en) * | 2014-10-20 | 2015-03-04 | 中国电子科技集团公司第十三研究所 | Manufacturing method of heterojunction bipolar transistor |
US20190088768A1 (en) * | 2017-09-15 | 2019-03-21 | Murata Manufacturing Co., Ltd. | Bipolar transistor and radio-frequency power amplifier module |
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JP5564161B2 (en) * | 2007-05-08 | 2014-07-30 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
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US5340755A (en) * | 1989-09-08 | 1994-08-23 | Siemens Aktiegensellschaft | Method of making planar heterobipolar transistor having trenched isolation of the collector terminal |
US20040065897A1 (en) * | 2002-10-08 | 2004-04-08 | Eic Corporation | Heterojunction bipolar transistor having non-uniformly doped collector for improved safe-operating area |
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JPH0812910B2 (en) * | 1988-09-05 | 1996-02-07 | 日本電気株式会社 | Compound semiconductor device and manufacturing method thereof |
JPH10107042A (en) * | 1996-09-27 | 1998-04-24 | Sanyo Electric Co Ltd | Compound semiconductor device |
JP3235574B2 (en) * | 1998-11-09 | 2001-12-04 | 日本電気株式会社 | Method for manufacturing semiconductor device having hetero bipolar transistor |
JP3421631B2 (en) * | 2000-03-24 | 2003-06-30 | 富士通カンタムデバイス株式会社 | Semiconductor integrated circuit device and method of manufacturing the same |
JP2002299603A (en) | 2001-03-29 | 2002-10-11 | Nec Corp | Semiconductor device |
JP3573737B2 (en) * | 2002-01-18 | 2004-10-06 | Nec化合物デバイス株式会社 | Heterojunction bipolar transistor and semiconductor integrated circuit |
JP2003243527A (en) * | 2002-02-15 | 2003-08-29 | Hitachi Ltd | Manufacturing method of semiconductor device |
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US5340755A (en) * | 1989-09-08 | 1994-08-23 | Siemens Aktiegensellschaft | Method of making planar heterobipolar transistor having trenched isolation of the collector terminal |
US20040065897A1 (en) * | 2002-10-08 | 2004-04-08 | Eic Corporation | Heterojunction bipolar transistor having non-uniformly doped collector for improved safe-operating area |
Cited By (6)
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CN104392923A (en) * | 2014-10-20 | 2015-03-04 | 中国电子科技集团公司第十三研究所 | Manufacturing method of heterojunction bipolar transistor |
US20190088768A1 (en) * | 2017-09-15 | 2019-03-21 | Murata Manufacturing Co., Ltd. | Bipolar transistor and radio-frequency power amplifier module |
CN109616516A (en) * | 2017-09-15 | 2019-04-12 | 株式会社村田制作所 | Bipolar transistor and high-frequency power amplifier module |
US10665704B2 (en) * | 2017-09-15 | 2020-05-26 | Murata Manufacturing Co., Ltd. | Bipolar transistor and radio-frequency power amplifier module |
US11164963B2 (en) | 2017-09-15 | 2021-11-02 | Murata Manufacturing Co., Ltd. | Bipolar transistor and radio-frequency power amplifier module |
US11978786B2 (en) | 2017-09-15 | 2024-05-07 | Murata Manufacturing Co., Ltd. | Bipolar transistor and radio-frequency power amplifier module |
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US7038244B2 (en) | 2006-05-02 |
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