US20050090037A1 - Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding - Google Patents

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding Download PDF

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US20050090037A1
US20050090037A1 US10/978,198 US97819804A US2005090037A1 US 20050090037 A1 US20050090037 A1 US 20050090037A1 US 97819804 A US97819804 A US 97819804A US 2005090037 A1 US2005090037 A1 US 2005090037A1
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Prior art keywords
metal
conducting polymer
polymer plug
bump
substrate
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US10/978,198
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Yakub Aliyu
Simon Chooi
Mei Zhou
John Sudijono
Subhash Gupta
Sudipto Roy
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GlobalFoundries Singapore Pte Ltd
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Chartered Semiconductor Manufacturing Pte Ltd
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Priority to US10/978,198 priority Critical patent/US20050090037A1/en
Publication of US20050090037A1 publication Critical patent/US20050090037A1/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates generally to the packaging of semiconductor devices, and more specifically to copper interconnect processes between chips and substrates in packaging processes.
  • Recent integration of copper interconnect processes into IC (integrated circuit) manufacturing requires copper terminating chips to be bonded directly on the copper metal pad and circuit boards.
  • the present invention allows the use of conducting polymers to bond copper terminating chips directly on copper substrate or printed circuit boards.
  • U.S. Pat. No. 5,923,955 to Wong describes a process for creating a flip-chip bonded combination for a first and second integrated circuits using a Ni/Cu/TiN structure.
  • U.S. Pat. No. 5,891,756 to Erickson describes a method for forming a solder bump pad, and specifically to converting a wire bond pad of a surface-mount IC device to a flip-chip solder bump pad such that the IC device can be flip-chip mounted to a substrate.
  • the method uses a Ni layer over the pad.
  • U.S. Pat. No. 5,795,818 to Marrs describes a method of forming an interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate. The method uses coined ball bond bumps.
  • UBM under bump metallization
  • an object of the present invention is to provide a method of bonding a chip to a substrate without the need for a bump metal, wetting agents, and barrier materials.
  • Another object of the present invention is to provide a method of bonding a chip to a substrate avoiding the use of environmentally unfriendly solder and solder material.
  • An additional object of the present invention is to provide a method of bonding a chip to a substrate in smaller micron scale metal pitch sizes.
  • a semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided.
  • a conducting polymer plug is formed over the exposed metal terminating pad.
  • a conforming interface layer is formed over the conducting polymer plug.
  • the conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump.
  • the conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump.
  • the conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug of the semiconductor chip with the corresponding metal bump of the separate substrate.
  • FIGS. 1 to 6 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
  • semiconductor structure 200 includes an overlying final metal layer 212 connected to, for example, metal line 214 through metal via 216 .
  • Metal terminating pad 218 overlies final metal layer 212 at a predetermined position within first passivation layer 220 .
  • Semiconductor structure 200 is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface.
  • conductive layers and dielectric layers e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.
  • semiconductor structure 200 is meant to include a semiconductor chip.
  • Final metal layer 212 and metal terminating pad 218 are preferably comprised of copper as will be used for illustrative purposes hereafter.
  • Additional metal vias 216 , metal lines 214 , metal terminating pads 218 , etc., may be formed within and over semiconductor structure 200 although for purposes of illustration, only single such structures are shown in FIGS. 11 .
  • metal via 216 , metal line 214 , and final metal layer 212 are not explicitly illustrated in the following FIGS. 2-6 .
  • Final passivation layer 222 is formed over first passivation layer 220 and copper terminating pad 218 to a thickness of from about 1000 to 10,000 ⁇ , and more preferably from about 2000 to 5000 ⁇ .
  • Opening 224 is formed within second passivation layer 222 exposing copper terminating pad 218 .
  • planarized conducting polymer plug 250 is formed within opening 224 by flowing or using a spin-on-technique on copper surfaces such a bonding pads 218 or copper tracks on printed circuit boards.
  • Planarized conducting polymer plug 250 is preferably from about 1000 to 10,000 ⁇ thick, and more preferably from about 3000 to 6000 ⁇ thick.
  • Conducting polymer plug 250 includes, but is not restricted to doped polyacetylene, poly (para-phenylene vinylene) (PPV), or polyaniline manufactured by DuPont, Ciba Geigy, and Sieman's and others.
  • Conducting polymer plug 250 is used to achieve an effective copper/copper surface bonding in copper terminating IC chip pads 218 .
  • the conducting polymer has good conductive properties, is highly doped to degeneracy (see below), has good adhesive properties and very useful thermal insulation properties.
  • the main characteristics of the conducting polymer forming conducting polymer plug 250 is the presence of the so-called conjugated chain where the chemical bonding between the atoms in the mainly carbon “backbone” of the polymer chain alternates between single and double bonds.
  • omega-bond There are two types of bonds namely the omega-bond and the phi-bond. Electrons in the former (omega-bond) are strongly localized and form strong bonds, in contrast to the later (phi-bond) in which the electrons form weak bonds and are not localized.
  • the electrons in phi-bonds can be thought of a cloud that extends along the entire length of the conjugated chain in which electrons are free to move in a similar fashion to conducting electrons in a metal.
  • the conducting polymer is heavily doped to achieve a conduction which is comparable to a degenerate semiconductor and is sufficient enough not to perturb the device performance.
  • interface layer 260 is formed over second passivation layer 222 and conducting polymer plug 250 .
  • Interface layer 260 is preferably comprised of nickel carbonyl (Ni(CO) 4 ) as will be used for illustrative purposes hereafter.
  • the material for interface layer is selected to be subject to thermal decomposition be chemical combustible.
  • Ni(CO) 4 has a freezing point of ⁇ 19° C., between ⁇ 19° C. and 40° C. nickel carbonyl exists as a liquid and, at temperatures above 40° C., the following reaction takes place: Ni(CO) 4 ⁇ Ni+4CO Below 40° C., the reverse reaction takes place: Ni+4CO ⁇ Ni(CO) 4
  • Ni(CO) 4 interface layer 260 Two methods may be used to form Ni(CO) 4 interface layer 260 .
  • nickel is first deposited (through sputtering or electroplating) over second passivation layer 222 and conducting polymer plug 250 .
  • carbon monoxide (CO) is introduced into the reaction chamber and reacts with the deposited nickel layer to form Ni(CO) 4 interface layer 260 .
  • the CO may be pressurized as necessary.
  • the temperature of the chamber and/or the temperature of the wafer must be less than 40° C. to form the Ni(CO) 4 and then keep below ⁇ 19° C. to maintain the Ni(CO) 4 interface layer 260 as a solid.
  • liquid Ni(CO) 4 (at a temperature between ⁇ 19° C. and 40° C.) is flowed over second passivation layer 222 and conducting polymer plug 250 and then the temperature of the chamber and/or the temperature of the wafer is lowered to less than ⁇ 19° C. so as to convert the liquid Ni(CO) 4 into solid Ni(CO) 4 interface layer 260 .
  • the temperature of the chamber and/or the temperature of the wafer must be less than ⁇ 19° C. to maintain the Ni(CO) 4 interface layer 260 as a solid.
  • the excess of Ni(CO) 4 interface layer 260 not over conducting polymer plug 250 is removed to form conforming Ni(CO) 4 interface layer 260 ′ over conducting polymer plug 250 .
  • a partial chrome photomask (not shown) is formed over the wafer with the chrome portion of the photomask overlying that portion of the Ni(CO) 4 interface layer 260 overlying the conducting polymer plug 250 .
  • the partial chrome photomask is then subjected to a radiation source such that radiation penetrates the photomask to the Ni(CO) 4 interface layer 260 not over conducting polymer plug 250 and raising the temperature of that portion of the Ni(CO) 4 interface layer 260 above 40° C. so that the reaction Ni(CO) 4 ⁇ Ni+4CO takes place, removing the Ni(CO) 4 interface layer 260 not over conducting polymer plug 250 .
  • No radiation may penetrate the chrome portion of the photomask overlying the Ni(CO) 4 interface layer 260 over conducting polymer plug 250 so that portion of the Ni(CO) 4 interface layer 260 remains as Ni(CO) 4 .
  • Final passivation layer 222 is also then removed, exposing conducting polymer plug 250 with overlying conforming Ni(CO) 4 interface layer 260 ′.
  • pre-formed metal bump 300 (connected to metal track 310 within substrate 320 ) is aligned, mechanically pressed, and mated with, conducting polymer plug 250 with overlying conforming Ni(CO) 4 interface layer 260 ′.
  • Substrate 320 may be a bond pad or a printed circuit board, for example.
  • Metal bump 300 and metal track 310 are preferably comprised of copper as will be used for illustrative purposes hereafter.
  • Cu metal bump 300 is formed by electroless plating, at about 200° C.
  • conforming Ni(CO) 4 interface layer 260 ′ thermally decomposes allowing copper bump 300 to adhere directly with conducting polymer plug 250 at temperature above about 40° C.: Ni(CO) 4 ⁇ Ni+4CO With slight application of pressure, the thermal decomposition of Ni(CO) 4 interface layer 260 ′ facilitates Ni bonding of copper bump 300 to conducting poly plug 250 .
  • the present invention may find wide application in flip-chip, chip-on-board, and micron metal bonding and provides for micron scale bonding.
  • the present invention permits semiconductor chips with copper interconnect termination to be directly bonded by a flip-chip, chip-on-board, and micron metal bonding processes onto a copper substrate or printed circuit board, eliminating the need for a bump metal, wetting agent metals and barrier materials with the attendant costly process steps and materials involved. It further avoids the use of environmentally unfriendly solder and solder materials, and allows for use in smaller micron scale metal pitch sizes unlike most of the current bonding techniques.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Description

  • This application is a Continuation-in-Part of application Ser. No. 09/612,576 filed on Jul. 7, 2000 and assigned to a common assignee.
    • FIELD OF THE INVENTION
  • The present invention relates generally to the packaging of semiconductor devices, and more specifically to copper interconnect processes between chips and substrates in packaging processes.
    • BACKGROUND OF THE INVENTION
  • Recent integration of copper interconnect processes into IC (integrated circuit) manufacturing requires copper terminating chips to be bonded directly on the copper metal pad and circuit boards. The present invention allows the use of conducting polymers to bond copper terminating chips directly on copper substrate or printed circuit boards.
  • U.S. Pat. No. 5,923,955 to Wong describes a process for creating a flip-chip bonded combination for a first and second integrated circuits using a Ni/Cu/TiN structure.
  • U.S. Pat. No. 5,891,756 to Erickson describes a method for forming a solder bump pad, and specifically to converting a wire bond pad of a surface-mount IC device to a flip-chip solder bump pad such that the IC device can be flip-chip mounted to a substrate. The method uses a Ni layer over the pad.
  • U.S. Pat. No. 5,795,818 to Marrs describes a method of forming an interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate. The method uses coined ball bond bumps.
  • U.S. Pat. No. 5,904,859 to Degani describes a method for applying under bump metallization (UBM) for solder bump interconnections on interconnection substrates. The UBM comprises a Cu, Cu/Cr, Cr multilayer structure.
  • U.S. Pat. No. 5,767,009 to Yoshida et al. describes a method of reducing cross talk noise between stacked semiconductor chips by the use of a chip on chip mounting structure.
  • U.S. Pat. No. 5,804,876 to Lake et al. describes a low contact resistance electrical bonding interconnect having a metal bond pad portion and conductive epoxy portion.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the present invention is to provide a method of bonding a chip to a substrate without the need for a bump metal, wetting agents, and barrier materials.
  • Another object of the present invention is to provide a method of bonding a chip to a substrate avoiding the use of environmentally unfriendly solder and solder material.
  • An additional object of the present invention is to provide a method of bonding a chip to a substrate in smaller micron scale metal pitch sizes.
  • Other objects will appear hereinafter.
  • It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug of the semiconductor chip with the corresponding metal bump of the separate substrate. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
  • FIGS. 1 to 6 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Unless otherwise specified, all structures, layers, etc. may be formed or accomplished by conventional methods known in the prior art.
  • Accordingly, as shown in FIG. 1, semiconductor structure 200 includes an overlying final metal layer 212 connected to, for example, metal line 214 through metal via 216. Metal terminating pad 218 overlies final metal layer 212 at a predetermined position within first passivation layer 220.
  • Semiconductor structure 200 is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure 200” is meant to include a semiconductor chip.
  • Final metal layer 212 and metal terminating pad 218 are preferably comprised of copper as will be used for illustrative purposes hereafter.
  • Additional metal vias 216, metal lines 214, metal terminating pads 218, etc., may be formed within and over semiconductor structure 200 although for purposes of illustration, only single such structures are shown in FIGS. 11. For purposes of simplicity, metal via 216, metal line 214, and final metal layer 212 are not explicitly illustrated in the following FIGS. 2-6.
  • Final passivation layer 222 is formed over first passivation layer 220 and copper terminating pad 218 to a thickness of from about 1000 to 10,000 Å, and more preferably from about 2000 to 5000 Å.
  • Opening 224 is formed within second passivation layer 222 exposing copper terminating pad 218.
  • As shown in FIG. 2, planarized conducting polymer plug 250 is formed within opening 224 by flowing or using a spin-on-technique on copper surfaces such a bonding pads 218 or copper tracks on printed circuit boards. Planarized conducting polymer plug 250 is preferably from about 1000 to 10,000 Å thick, and more preferably from about 3000 to 6000 Å thick.
  • Conducting polymer plug 250 includes, but is not restricted to doped polyacetylene, poly (para-phenylene vinylene) (PPV), or polyaniline manufactured by DuPont, Ciba Geigy, and Sieman's and others.
  • Conducting polymer plug 250 is used to achieve an effective copper/copper surface bonding in copper terminating IC chip pads 218. The conducting polymer has good conductive properties, is highly doped to degeneracy (see below), has good adhesive properties and very useful thermal insulation properties.
  • The main characteristics of the conducting polymer forming conducting polymer plug 250 is the presence of the so-called conjugated chain where the chemical bonding between the atoms in the mainly carbon “backbone” of the polymer chain alternates between single and double bonds.
  • There are two types of bonds namely the omega-bond and the phi-bond. Electrons in the former (omega-bond) are strongly localized and form strong bonds, in contrast to the later (phi-bond) in which the electrons form weak bonds and are not localized.
  • The electrons in phi-bonds can be thought of a cloud that extends along the entire length of the conjugated chain in which electrons are free to move in a similar fashion to conducting electrons in a metal. The conducting polymer is heavily doped to achieve a conduction which is comparable to a degenerate semiconductor and is sufficient enough not to perturb the device performance.
  • As shown in FIG. 3, interface layer 260 is formed over second passivation layer 222 and conducting polymer plug 250. Interface layer 260 is preferably comprised of nickel carbonyl (Ni(CO)4) as will be used for illustrative purposes hereafter. The material for interface layer is selected to be subject to thermal decomposition be chemical combustible.
  • Ni(CO)4 has a freezing point of −19° C., between −19° C. and 40° C. nickel carbonyl exists as a liquid and, at temperatures above 40° C., the following reaction takes place:
    Ni(CO)4→Ni+4CO
    Below 40° C., the reverse reaction takes place:
    Ni+4CO→Ni(CO)4
  • Two methods may be used to form Ni(CO)4 interface layer 260. In the first method, nickel is first deposited (through sputtering or electroplating) over second passivation layer 222 and conducting polymer plug 250. Then, carbon monoxide (CO) is introduced into the reaction chamber and reacts with the deposited nickel layer to form Ni(CO)4 interface layer 260. The CO may be pressurized as necessary. The temperature of the chamber and/or the temperature of the wafer must be less than 40° C. to form the Ni(CO)4 and then keep below −19° C. to maintain the Ni(CO)4 interface layer 260 as a solid.
  • In the second method, liquid Ni(CO)4 (at a temperature between −19° C. and 40° C.) is flowed over second passivation layer 222 and conducting polymer plug 250 and then the temperature of the chamber and/or the temperature of the wafer is lowered to less than −19° C. so as to convert the liquid Ni(CO)4 into solid Ni(CO)4 interface layer 260.
  • Regardless of which method is used, the temperature of the chamber and/or the temperature of the wafer must be less than −19° C. to maintain the Ni(CO)4 interface layer 260 as a solid.
  • As shown in FIG. 4, the excess of Ni(CO)4 interface layer 260 not over conducting polymer plug 250 is removed to form conforming Ni(CO)4 interface layer 260′ over conducting polymer plug 250. To remove the excess of Ni(CO)4 interface layer 260 not over conducting polymer plug 250, a partial chrome photomask (not shown) is formed over the wafer with the chrome portion of the photomask overlying that portion of the Ni(CO)4 interface layer 260 overlying the conducting polymer plug 250. The partial chrome photomask is then subjected to a radiation source such that radiation penetrates the photomask to the Ni(CO)4 interface layer 260 not over conducting polymer plug 250 and raising the temperature of that portion of the Ni(CO)4 interface layer 260 above 40° C. so that the reaction
    Ni(CO)4→Ni+4CO
    takes place, removing the Ni(CO)4 interface layer 260 not over conducting polymer plug 250. No radiation may penetrate the chrome portion of the photomask overlying the Ni(CO)4 interface layer 260 over conducting polymer plug 250 so that portion of the Ni(CO)4 interface layer 260 remains as Ni(CO)4.
  • Final passivation layer 222 is also then removed, exposing conducting polymer plug 250 with overlying conforming Ni(CO)4 interface layer 260′. As shown in FIG. 5, pre-formed metal bump 300 (connected to metal track 310 within substrate 320) is aligned, mechanically pressed, and mated with, conducting polymer plug 250 with overlying conforming Ni(CO)4 interface layer 260′. Substrate 320 may be a bond pad or a printed circuit board, for example.
  • Metal bump 300 and metal track 310 are preferably comprised of copper as will be used for illustrative purposes hereafter. Cu metal bump 300 is formed by electroless plating, at about 200° C.
  • As shown in FIG. 6, conforming Ni(CO)4 interface layer 260′ thermally decomposes allowing copper bump 300 to adhere directly with conducting polymer plug 250 at temperature above about 40° C.:
    Ni(CO)4→Ni+4CO
    With slight application of pressure, the thermal decomposition of Ni(CO)4 interface layer 260′ facilitates Ni bonding of copper bump 300 to conducting poly plug 250.
  • The present invention may find wide application in flip-chip, chip-on-board, and micron metal bonding and provides for micron scale bonding.
  • Thus, the present invention permits semiconductor chips with copper interconnect termination to be directly bonded by a flip-chip, chip-on-board, and micron metal bonding processes onto a copper substrate or printed circuit board, eliminating the need for a bump metal, wetting agent metals and barrier materials with the attendant costly process steps and materials involved. It further avoids the use of environmentally unfriendly solder and solder materials, and allows for use in smaller micron scale metal pitch sizes unlike most of the current bonding techniques.
  • While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.

Claims (21)

1. A method of bonding a chip to a substrate, comprising the steps of:
providing a semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover;
forming a conducting polymer plug over said exposed metal terminating pad;
forming a conforming interface layer over said conducting polymer plug;
aligning said conducting polymer plug of said semiconductor chip with said corresponding metal bump;
mating said conforming interface layer over said conducting polymer plug with said corresponding metal bump; and
thermally decomposing said conforming interface layer, adhering and permanently attaching said conducting polymer plug of said semiconductor chip with said corresponding metal bump of said separate substrate.
2-30. (canceled)
31. A chip/substrate structure, comprising:
a chip;
a substrate; and
a conforming interface Ni(CO)4 layer between the chip and the substrate.
32. The structure of claim 31, further comprising:
a metal terminating pad on the chip; and
a metal bump on the substrate;
wherein the conforming interface Ni(CO)4 layer is between the metal terminating pad and the metal bump.
33. The structure of claim 31, further comprising:
a metal terminating pad on the chip;
a conducting polymer plug over the metal terminating pad;
a metal track on the substrate; and
a metal bump over at least a portion of the metal track;
wherein the conforming interface Ni(CO)4 layer is between the conducting polymer plug and the metal bump.
34. The structure of claim 31, further comprising:
a copper terminating pad on the chip;
a conducting polymer plug over the copper terminating pad;
a metal track on the substrate; and
a copper bump over at least a portion of the metal track;
wherein the conforming interface Ni(CO)4 layer is between the conducting polymer plug and the copper bump.
35. The structure of claim 31, further comprising:
a copper terminating pad on the chip;
a conducting polymer plug over the copper terminating pad; the conducting polymer plug being comprised of doped polyacetylene, poly (para-phenylene vinylene) (PPV) or polyaniline;
a metal track on the substrate; and
a copper bump over at least a portion of the metal track;
wherein the conforming interface Ni(CO)4 layer is between the conducting polymer plug and the copper bump.
36. The structure of claim 31, further comprising:
a metal terminating pad on the chip;
a conducting polymer plug over the metal terminating pad;
a metal track on the substrate; and
a metal bump over at least a portion of the metal track;
wherein the conforming interface Ni(CO)4 layer contacts the conducting polymer plug and the metal bump.
37. A chip/substrate structure, comprising:
a chip having a metal terminating pad thereover;
a substrate having a metal bump thereover; and
a conforming interface Ni(CO)4 layer between the metal terminating pad and the metal bump.
38. The structure of claim 37, further comprising:
a conducting polymer plug over the metal terminating pad; and
a metal track on the substrate and under the metal bump;
wherein the conforming interface Ni(CO)4 layer is between the conducting polymer plug and the metal bump.
39. The structure of claim 37, further comprising:
a conducting polymer plug over the metal terminating pad; the conducting polymer plug having a thickness of from about 1000 to 10,000 Å and being comprised of doped polyacetylene, poly (para-phenylene vinylene) (PPV) or polyaniline;
a metal track on the substrate and under the metal bump;
wherein the conforming interface Ni(CO)4 layer is between the conducting polymer plug and the metal bump.
40. The structure of claim 37, further comprising:
a conducting polymer plug over the metal terminating pad; and
a metal track on the substrate and under the metal bump;
wherein the conforming interface Ni(CO)4 layer contacts the conducting polymer plug and the metal bump.
41 The structure of claim 37, wherein the metal terminating pad and the metal bump are each comprised of copper.
42. The structure of claim 37, wherein the conducting polymer plug is from about 3000 to 6000 Å thick.
43. A chip/substrate structure, comprising:
a chip having a metal terminating pad thereover;
a conducting polymer plug over the metal terminating pad;
a substrate having a metal track thereover;
a metal bump over the metal track; and
a conforming interface Ni(CO)4 layer between the conducting polymer plug and the metal bump.
44. The structure of claim 43, wherein the conforming interface Ni(CO)4 layer contacts the conducting polymer plug and the metal bump.
45. The structure of claim 43, wherein:
the conducting polymer plug having a thickness of from about 1000 to 10,000 Å.
46. The structure of claim 43, wherein:
the conducting polymer plug having a thickness of from about 3000 to 6000 Å.
47. The structure of claim 43, wherein:
the conducting polymer plug is comprised of doped polyacetylene, poly (para-phenylene vinylene) (PPV) or polyaniline.
48. The structure of claim 43, wherein the metal terminating pad and the metal bump are each comprised of copper.
49. The method of claim 43, wherein the conducting polymer plug is a material doped to degeneracy.
US10/978,198 2000-07-07 2004-10-29 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding Abandoned US20050090037A1 (en)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2879347A1 (en) * 2004-12-14 2006-06-16 Commissariat Energie Atomique ELECTRONIC DEVICE COMPRISING TWO COMPONENTS AND METHOD FOR MANUFACTURING SUCH A DEVICE
US20070074741A1 (en) * 2005-09-30 2007-04-05 Tokyo Electron Limited Method for dry cleaning nickel deposits from a processing system
US7344959B1 (en) * 2006-07-25 2008-03-18 International Business Machines Corporation Metal filled through via structure for providing vertical wafer-to-wafer interconnection
KR100829385B1 (en) * 2006-11-27 2008-05-13 동부일렉트로닉스 주식회사 Semiconductor device and method of manufacturing the same
US8062861B2 (en) * 2008-02-21 2011-11-22 George Mason Intellectual Properties, Inc. Tissue sample preprocessing methods and devices
US20110270067A1 (en) * 2010-04-30 2011-11-03 Boozarjomehr Faraji Biocompatible Bonding Method
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271851A (en) * 1963-01-14 1966-09-13 Motorola Inc Method of making semiconductor devices
US4363076A (en) * 1980-12-29 1982-12-07 Honeywell Information Systems Inc. Integrated circuit package
US4519939A (en) * 1981-04-02 1985-05-28 Bayer Aktiengesellschaft Particulate doped polyacetylene
US4685030A (en) * 1985-04-29 1987-08-04 Energy Conversion Devices, Inc. Surface mounted circuits including hybrid circuits, having CVD interconnects, and method of preparing the circuits
US5171826A (en) * 1989-03-23 1992-12-15 Hitachi Chemical Company, Ltd. Heat resistant adhesive composition and bonding method using the same
US5441569A (en) * 1993-11-29 1995-08-15 The United States Of America As Represented By The United States Department Of Energy Apparatus and method for laser deposition of durable coatings
US5459098A (en) * 1992-10-19 1995-10-17 Marietta Energy Systems, Inc. Maskless laser writing of microscopic metallic interconnects
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
US5753523A (en) * 1994-11-21 1998-05-19 Brewer Science, Inc. Method for making airbridge from ion-implanted conductive polymers
US5767009A (en) * 1995-04-24 1998-06-16 Matsushita Electric Industrial Co., Ltd. Structure of chip on chip mounting preventing from crosstalk noise
US5798188A (en) * 1997-06-25 1998-08-25 E. I. Dupont De Nemours And Company Polymer electrolyte membrane fuel cell with bipolar plate having molded polymer projections
US5804876A (en) * 1993-12-13 1998-09-08 Micron Communications Inc. Electronic circuit bonding interconnect component and flip chip interconnect bond
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
US5904859A (en) * 1997-04-02 1999-05-18 Lucent Technologies Inc. Flip chip metallization
US5923955A (en) * 1998-05-28 1999-07-13 Xerox Corporation Fine flip chip interconnection
US6177729B1 (en) * 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6410415B1 (en) * 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US6552555B1 (en) * 1998-11-19 2003-04-22 Custom One Design, Inc. Integrated circuit testing apparatus

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB399815A (en) 1932-04-11 1933-10-11 Automatic Electric Co Ltd Improvements in or relating to automatic switches for use in telephone or like systems
GB428610A (en) 1933-11-11 1935-05-13 Charles Frederick Reed Harriso Improvements in and relating to the purification of crude nickel carbonyl
GB813819A (en) 1955-12-02 1959-05-21 Montedison Spa Process for preparing nickel carbonyl
US4042006A (en) * 1973-01-05 1977-08-16 Siemens Aktiengesellschaft Pyrolytic process for producing a band-shaped metal layer on a substrate
US5021401A (en) 1989-04-03 1991-06-04 Westinghouse Electric Corp. Integrated production of superconductor insulation for chemical vapor deposition of nickel carbonyl
US5092967A (en) * 1991-06-17 1992-03-03 Romar Technologies Incorporated Process for forming printed circuits
US5795818A (en) 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
AU1015999A (en) * 1998-11-03 2000-05-22 Chemical Vapour Deposition Systems Inc. Nickel carbonyl vapour deposition apparatus and process
US6703169B2 (en) * 2001-07-23 2004-03-09 Applied Materials, Inc. Method of preparing optically imaged high performance photomasks
CA2461624C (en) 2003-03-27 2005-10-18 Chemical Vapour Metal Refining Inc. Process for producing nickel carbonyl, nickel powder and use thereof

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271851A (en) * 1963-01-14 1966-09-13 Motorola Inc Method of making semiconductor devices
US4363076A (en) * 1980-12-29 1982-12-07 Honeywell Information Systems Inc. Integrated circuit package
US4519939A (en) * 1981-04-02 1985-05-28 Bayer Aktiengesellschaft Particulate doped polyacetylene
US4685030A (en) * 1985-04-29 1987-08-04 Energy Conversion Devices, Inc. Surface mounted circuits including hybrid circuits, having CVD interconnects, and method of preparing the circuits
US5171826A (en) * 1989-03-23 1992-12-15 Hitachi Chemical Company, Ltd. Heat resistant adhesive composition and bonding method using the same
US5459098A (en) * 1992-10-19 1995-10-17 Marietta Energy Systems, Inc. Maskless laser writing of microscopic metallic interconnects
US5441569A (en) * 1993-11-29 1995-08-15 The United States Of America As Represented By The United States Department Of Energy Apparatus and method for laser deposition of durable coatings
US5804876A (en) * 1993-12-13 1998-09-08 Micron Communications Inc. Electronic circuit bonding interconnect component and flip chip interconnect bond
US5753523A (en) * 1994-11-21 1998-05-19 Brewer Science, Inc. Method for making airbridge from ion-implanted conductive polymers
US5767009A (en) * 1995-04-24 1998-06-16 Matsushita Electric Industrial Co., Ltd. Structure of chip on chip mounting preventing from crosstalk noise
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
US5904859A (en) * 1997-04-02 1999-05-18 Lucent Technologies Inc. Flip chip metallization
US5798188A (en) * 1997-06-25 1998-08-25 E. I. Dupont De Nemours And Company Polymer electrolyte membrane fuel cell with bipolar plate having molded polymer projections
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
US5923955A (en) * 1998-05-28 1999-07-13 Xerox Corporation Fine flip chip interconnection
US6552555B1 (en) * 1998-11-19 2003-04-22 Custom One Design, Inc. Integrated circuit testing apparatus
US6410415B1 (en) * 1999-03-23 2002-06-25 Polymer Flip Chip Corporation Flip chip mounting technique
US6177729B1 (en) * 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector

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US7452808B2 (en) 2008-11-18
US20030032275A1 (en) 2003-02-13
US20050112799A1 (en) 2005-05-26
US20050090039A1 (en) 2005-04-28
US6967162B2 (en) 2005-11-22
US20050090102A1 (en) 2005-04-28
US6821888B2 (en) 2004-11-23
US7060613B2 (en) 2006-06-13

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