CN103681595B

CN103681595B - Semiconductor device

Info

Publication number: CN103681595B
Application number: CN201310725962.9A
Authority: CN
Inventors: 鴫原宏美; 塚本博; 矢岛明
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2008-12-03
Filing date: 2009-12-02
Publication date: 2018-02-09
Anticipated expiration: 2029-12-02

Abstract

The present invention provides a kind of semiconductor device.It is using golden wire etc. that the aluminum pad on semiconductor chip and external devices is coupled to each other generally by wire bonding etc. for ease of installation in the semiconductor device for vehicular applications etc..However, this semiconductor device causes connecting fault due to the interaction in the much time using under comparative high temperature (about 150 DEG C) between aluminium and gold.Present invention provides a kind of semiconductor device (semiconductor devices or electronic circuit), and it includes the semiconductor chip of the part as the device, sets the electrolyzing gold coating surface film on the bonding welding pad based on aluminium (the metal-plated overlay film based on gold) on a semiconductor die and the gold bond wires (bonding lead based on gold) for the interconnection between the coating surface film and the outside lead being arranged on wiring plate etc. (wiring board) via barrier metal film.

Description

Semiconductor device

Divisional application explanation

The application is on December 2nd, 2009 is submitting, Application No. 200910224397.1, entitled " semiconductor collection Into circuit devcie " Chinese invention patent application divisional application.

Technical field

The present invention relates to one kind for half in semiconductor device (semiconductor devices or electronic circuit) The interconnection technique between pad electrode and external devices on conductor chip can effectively applicable technology.

Background technology

PCT application No.2004-533711 Japanese disclosure (patent document 1) or United States Patent (USP) No.6,534,863 (patent document 2) discloses a kind of technology, in the semiconductor devices with thin copper film structure, from lower layer side by golden wire It is bonded to and is made up of TaN (bonded layer)/Ta (barrier layer)/Cu (Seed Layer)/Ni (the first electrodeposited coating)/Au (the second electrodeposited coating) etc. Pad on, rather than surface tended on oxidized aluminum pad.

(patent document 1)

PCT application No.2004-533711 Japanese disclosure

(patent document 2)

United States Patent (USP) No.6,534,863

The content of the invention

In the semiconductor circuit device for vehicular applications etc., for ease of installation, generally by wire bonding etc., use Golden wire etc. is coupled to each other by the aluminum pad on semiconductor chip and external devices.However, this semiconductor device Connecting fault is caused due to the interaction in (about 150 DEG C) much time using at a relatively high temperature between aluminium and gold Such as Kirkendall effect (Kirkendall Void).

Present invention is intended to solve foregoing problems.

It is an advantage of the invention to provide the semiconductor device with high reliability.

The above-mentioned and other purpose and novel feature of the present invention will become aobvious from this specification description referring to the drawings And it is clear to.

The summary of the representative embodiment of invention disclosed in the present application is described briefly below.

That is, in present invention, the surface metal-layer based on gold is arranged on semiconductor chip via barrier metal film On the bonding welding pad based on aluminium or copper on.The bonding welding pad is semiconductor device (semiconductor devices or electronics Circuit devcie) a part.Moreover, the coupling part of the bonding lead based on gold or copper or bond ball are arranged for outside Connection.

The effect obtained by the representative embodiment of invention disclosed in the present application will be summarized as follows.

That is, because the bonding lead based on gold or copper or bond ball are bonded to based on aluminium via the skin covering of the surface based on gold or layer Or the bonding welding pad of copper, so even if semiconductor device uses for a long time at a relatively high temperature, also will not It is caused by connecting fault caused by the interaction between gold and aluminium etc..

Brief description of the drawings

Fig. 1 be according to one embodiment of the application when completing bonding pad opening step in semiconductor device Longitudinal device junction composition (corresponding to the part surrounded by dotted line shown in Fig. 3) of semiconductor chip,

Fig. 2 be the manufacturing process for showing the semiconductor device in the embodiment of the present application during from bonding pad opening Step to the flow of wire bonding process process chart,

Fig. 3 be show the semiconductor device in the embodiment of the present application semiconductor chip (complete weld During dish opening step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 18),

Fig. 4 be show the semiconductor device in the embodiment of the present application semiconductor chip (in barrier film In forming step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 19),

Fig. 5 be show the semiconductor device in the embodiment of the present application semiconductor chip (in resist In film coating step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 20),

Fig. 6 be show the semiconductor device in the embodiment of the present application semiconductor chip (in resist In film opening procedure) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 21),

Fig. 7 be show the semiconductor device in the embodiment of the present application semiconductor chip (in golden plating In step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 22),

Fig. 8 be show the semiconductor device in the embodiment of the present application semiconductor chip (in resist In removal step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 23),

Fig. 9 be show the semiconductor device in the embodiment of the present application semiconductor chip (stop gold In category removal step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 24),

Figure 10 corresponds to the top of Fig. 9, semiconductor device in the embodiment of the present application semiconductor chip View,

Figure 11 is the top view of the semiconductor device in the embodiment of the present application,

Figure 12 is exemplary cross-sectional corresponding with the part by dotted line shown in Figure 11,

Figure 13 is the exemplary cross-sectional for being shown in which to change from the wire bonding in Figure 12 the example of wire bonding order Face figure,

Figure 14 is the example for being shown in which to be substituted wiring plate by the other electron component on wiring plate in fig. 12 Exemplary cross-sectional,

Figure 15 is that be shown in which to substitute by another electronic component on (back bonding) wiring plate in fig. 12 will The exemplary cross-sectional of the example of the target part of the semiconductor chip of tube core bonding is wanted,

Figure 16 is (two layers of polyimide film to be arranged into additional final blunt wherein according to another embodiment of the application Change film example in) semiconductor device semiconductor chip (when completing wafer processing step) device it is transversal Face figure (corresponds to the section taken along Figure 25 line X-X '),

Figure 17 corresponds to the top of Fig. 3, semiconductor device in the embodiment of the present application semiconductor chip View,

Figure 18 is the amplification vertical view (Fig. 3 shows its corresponding cross-sectional view) of the part by dotted line in Figure 17,

Figure 19 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 4 in Figure 17,

Figure 20 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 5 in Figure 17,

Figure 21 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 6 in Figure 17,

Figure 22 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 7 in Figure 17,

Figure 23 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 8 in Figure 17,

Figure 24 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 9 in Figure 17,

Figure 25 corresponds to the amplification vertical view of the step of Figure 16,

Figure 26 be for illustrating the illustrative cross section the non-electrolytic gold plating on nickel surface the problem of,

Figure 27 is that wafer probe is surveyed in the manufacturing process for show the semiconductor device in the embodiment of the present application The enlarged drawing of the wafer top surface (square pads in first example) of the state of trial work skill,

Wafer top surface when Figure 28 is the completion wire bonding process in the example corresponding to Figure 27 is (in first example Square pads) enlarged drawing,

Figure 29 is to show that wafer probe tests work in the manufacturing process of semiconductor device in the embodiment of the present application The enlarged drawing of another wafer top surface (rectangular pads of the general type in second example) of the state of skill,

Wafer top surface when Figure 30 is the completion wire bonding process in the example corresponding to Figure 29 is (in second example General rectangular pads) enlarged drawing,

Figure 31 is to show that wafer probe tests work in the manufacturing process of semiconductor device in the embodiment of the present application The enlarged drawing of the another wafer top surface (rectangular pads of the modification in third example) of the state of skill,

Wafer top surface when Figure 32 is the completion wire bonding process in the example corresponding to Figure 31 is (in third example The rectangular pads of modification) enlarged drawing,

Figure 33 is for illustrating Kirkendall effect, aluminum pad and bonding lead caused by bonding between aluminium and gold Local exemplary cross-sectional,

Figure 34 is the key for showing the bonding lead at the semiconductor device in the embodiment of the present application on pad The partial cross section view of one of various examples of conjunction state (general modfel),

Figure 35 is the key for showing the bonding lead at the semiconductor device in the embodiment of the present application on pad The partial cross section view of one of various examples of conjunction state (sliding laterally pattern 1),

Figure 36 is the key for showing the bonding lead at the semiconductor device in the embodiment of the present application on pad The partial cross section view of one of various examples of conjunction state (sliding laterally pattern 2),

Figure 37 is for illustrating the bonding lead at the semiconductor device in the embodiment of the present application on pad The partial cross section view of relation between the various sizes of bonding structure,

Figure 38 is semiconductor device (wire bonding type when packaging technology is completed in the embodiment of the present application BGA whole top view (to should be readily appreciated that the diagram omitted to resin seal part)),

Figure 39 is Figure 38 exemplary cross-sectional,

Figure 40 is semiconductor device (QFP when packaging technology is completed in the embodiment of the present application：The flat envelope in four sides Dress) whole top view (to should be readily appreciated that the diagram omitted to the top half of resin seal part),

Figure 41 is Figure 40 exemplary cross-sectional,

Figure 42 is semiconductor device (flip-chip variety when packaging technology is completed in the embodiment of the present application BGA whole top view),

Figure 43 is Figure 42 exemplary cross-sectional,

Figure 44 is the amplification cross-sectional view of the part surrounded in Figure 43 by dotted line,

Figure 45 is for illustrating under a type of projection in the semiconductor device of the embodiment of the present application The cross-sectional view of the pad periphery of metal (under bump metal) structure (two layers of structure),

Figure 46 is the cross-sectional view of the pad periphery in Figure 45 modification example, and

Figure 47 is for illustrating the another type of projection in the semiconductor device of the embodiment of the present application The cross-sectional view of the pad periphery of lower metal structure (sandwich construction of three layers or more layers).

Embodiment

(summary of preferred embodiment)

First, it will be outlined below the representative preferred embodiment of invention disclosed herein.

1. a kind of semiconductor device includes：(a) pad electrode based on aluminium or copper, is arranged on semiconductor chip Device surface on；(b) barrier metal film, it is arranged on pad electrode；(c) metal film on surface, it is arranged on barrier metal Main component is used as on film and including gold；And (d) bond ball or bonding lead, be bonded with metal film on surface and including Gold or copper are as main component.

2. in the semiconductor device according to item 1, the thickness of metal film on surface is more than the thickness of barrier metal film Degree.

3. in the semiconductor device according to item 1 or 2, metal film on surface is by electrolytic coating or sputtering and shape Into.

4. in the semiconductor device according to any one of item 1 to 3, metal film on surface by electrolytic coating and Formed.

5. in the semiconductor device according to any one of item 1 to 4, the area of metal film on surface is more than pad The area of the opening of dielectric film on electrode.

6. in the semiconductor device according to any one of item 1 to 5, the area of pad electrode is more than surface gold Belong to the area of layer.

7. in the semiconductor device according to any one of item 1 to 6, from plan view, pad electrode it On the opening of dielectric film be located in metal film on surface.

8. in the semiconductor device according to any one of item 1 to 7, from plan view, metal film on surface In pad electrode.

9. in the semiconductor device according to any one of item 1 to 4, metal film on surface is extended in the absence of weldering The region of disc electrode.

10. in the semiconductor device according to any one of item 1 to 9, bond ball is the bulb of bonding lead Point.

11. in the semiconductor device according to any one of item 1 to 10, bond ball is main by being used as including gold The part of composition is formed.

12. in the semiconductor device according to any one of item 1 to 10, bond ball is main by being used as including copper The part of composition is formed.

13. in the semiconductor device according to any one of item 1 to 12, pad electrode is based on aluminium or copper Pad electrode.

14. in the semiconductor device according to any one of item 1 to 13, barrier metal film includes titanium as master Want composition.

15. in the semiconductor device according to any one of item 1 to 13, barrier metal film include selected from titanium, A composition in chromium, titanium nitride and tungsten nitride is as main component.

16. in the semiconductor device according to any one of item 1 to 15, in addition to：(e) seed metal film, It is arranged between barrier metal film and metal film on surface.

17. in the semiconductor device according to item 16, seed metal film includes palladium as main component.

18. in the semiconductor device according to item 16, seed metal film include selected from copper, gold, nickel, platinum, rhodium, A composition in molybdenum, tungsten, chromium and tantalum is as main component.

19. in the semiconductor device according to any one of item 1 to 18, from plan view, pad electrode With substantially square.

20. in the semiconductor device according to any one of item 1 to 18, from plan view, pad electrode With generally rectangular.

Next, it will be outlined below other preferred embodiments of invention disclosed herein.

1. a kind of semiconductor device, including：(a) wiring plate；(b) the first semiconductor chip, fixed to wiring Plate or fixed to the first electronic component being arranged on wiring plate；(c) pad electrode based on aluminium or copper, is arranged on first On the device surface of semiconductor chip；(d) barrier metal film, it is arranged on pad electrode；(e) seed metal film, set On barrier metal film；(f) metal film on surface, it is arranged on seed metal film by electrolytic coating, and is made including gold For main component；(g) external metallization electrode, it is arranged on outside the first semiconductor chip；And (h) bonding lead, it is provided for Metal film on surface is coupled to external metallization electrode, and main component is used as including gold.

2. in the semiconductor device according to item 1, pad electrode is the pad electrode based on aluminium.

3. in the semiconductor device according to item 1 or 2, barrier metal film includes titanium as main component.

4. in the semiconductor device according to any one of item 1 to 3, seed metal film includes palladium as main Composition.

5. in the semiconductor device according to any one of item 1,2 and 4, barrier metal film includes titanium, chromium, nitrogen Change a composition in titanium and tungsten nitride.

6. in the semiconductor device according to any one of item 1 to 3 and 5, seed metal film include selected from copper, A composition in gold, nickel, platinum, rhodium, molybdenum, tungsten, chromium and tantalum is as main component.

7. in the semiconductor device according to any one of item 1 to 6, the first semiconductor chip is fixed to wiring Plate.

8. in the semiconductor device according to any one of item 1 to 6, the first semiconductor chip is fixed to wiring The first electronic component on plate.

9. in the semiconductor device according to any one of item 1 to 8, external metallization electrode be located at wiring plate it On.

10. in the semiconductor device according to any one of item 1 to 8, external metallization electrode, which is located at, to be connected up On the first electronic component on plate.

11. in the semiconductor device according to any one of item 1 to 10, bonding lead has positioned at surface gold Belong to the first bonding point on film side.

12. in the semiconductor device according to any one of item 1 to 10, bonding lead has positioned at surface gold Belong to the second bonding point on film side.

13. in the semiconductor device according to any one of item 1 to 12, at the surface of outside metal electrode It is provided with the metal film including gold, silver or palladium as main component.

14. provide a kind of method for manufacturing semiconductor device.The semiconductor device includes： (a) wiring plate；(b) the first semiconductor chip, fixed to wiring plate or fixed to the first electronics being arranged on wiring plate Element；(c) pad electrode based on aluminium or copper, is arranged on the device surface of the first semiconductor chip；(d) barrier metal Film, it is arranged on pad electrode；(e) seed metal film, it is arranged on barrier metal film；(f) metal film on surface, it is arranged on On seed metal film, and main component is used as including gold；(g) external metallization electrode, it is arranged on outside the first semiconductor chip Portion；And (h) bonding lead, be provided for metal film on surface and external metallization electrode is coupled to each other, and including golden conduct Main component.This method comprises the following steps：(I) seed metal is substantially formed on whole surface in semiconductor wafer Film；(II) resist film with opening is formed on seed metal film；And (III) by electrolytic coating in opening shape Into coating layer, metal film on surface is consequently formed.

In addition, it will be outlined below other preferred embodiments of invention disclosed herein.

1. a kind of semiconductor device includes：(a) pad electrode based on aluminium or copper, is arranged on semiconductor chip Device surface on；(b) barrier metal film, it is arranged on pad electrode；(c) metal film on surface, set by electrolytic coating Put on barrier metal film and be used as main component including gold；And (d) bond ball or bonding lead, it is arranged on surface gold Belong on film and including gold or copper as main component.

4. further comprised according to the semiconductor device of any one of item 1 to 3：(e) seed metal film, set Between barrier metal film and metal film on surface.

5. in the semiconductor device according to item 4, seed metal film includes palladium as main component.

6. in the semiconductor device according to any one of item 1,2,4 and 5, barrier metal film includes being selected from A composition in titanium, chromium, titanium nitride and tungsten nitride is as main component.

7. in the semiconductor device according to item 4 or 6, seed metal film include selected from copper, gold, nickel, platinum, A composition in rhodium, molybdenum, tungsten, chromium and tantalum is as main component.

(to the describing mode in the application, basic terms and the explanation used)

1. for convenience's sake, the description of the preferred embodiment below in the application if necessary can be divided into some, but These embodiments be not it is separated independently of one another, unless otherwise noted.One embodiment in these embodiments is on another One embodiment has certain relation, including each part of corresponding single example, another embodiment part it is specific All or part of modification example of description and another embodiment etc..It will omit in principle to being retouched with the repetition of a part State.In addition, each component of these embodiments is not required in that, unless otherwise noted, unless ought be limited to certain number in theory Purpose component, and unless when substantially being limited in addition by context.

In addition, term " semiconductor device " used herein means mainly to lead including being integrated in one and half The device of various transistors (active component) such as resistor or capacitor on body chip etc. (for example, monocrystalline substrate).Respectively The representative transistor of type can include such as conductor insulator semiconductor fet (MISFET), with metal oxygen Compound semiconductor field effect transistor (MOSFET) is Typical Representative.Now, typical integrated circuit structure can be included for example Complementary metal insulator semiconductor (CMIS) type integrated circuit, with the combination with N-channel type MISFET and P-channel type MISFET Complementary metal oxide semiconductor type integrated circuit be Typical Representative.

Modern semiconductors IC-components are that the wafer technique of large-scale integrated (LSI) can be generally broadly classified as Front end of line (FEOL) technique and back end of line (BEOL) technique.FEOL techniques include the conveying of the silicon wafer as raw material (delivery) (premetal) technique (is included between lower end and the gate electrode structure of M1 wiring layers before technique and metal Interlayer dielectric is formed, contact hole is formed, forms tungsten plug, embedding etc.).The formation process of BEOL techniques including M1 wiring layers and (it can also include wafer-class encapsulation to the formation process of the bonding pad opening in final passivating film on the pad electrode based on aluminium Technique).Gate electrode patterning technique and contact hole formation process among FEOL techniques are need unusual hand work micro- Manufacturing process.By contrast, in BEOL techniques, the local cloth of via and groove formation process particularly at relative lower layer Line (for example, the fine embedded wiring layer in the case of the embedded wiring structure with four-layer structure from M1 to M3, or having Have the fine embedded wiring layer from M1 to M5 in the case of ten layers of embedded wiring structure) the very fine work of needs such as formation Skill.It should be noted that " MN (generally, N scope is about from 1 to 15 (N=1 to 15)) " represent the n-th wiring layer counted from downside. Reference symbol M1 represents the first wiring layer, and reference symbol M3 represents the 3rd wiring layer.

2. same, in the description of embodiment etc., unless otherwise noted and unless context shows, otherwise on material " X " is not precluded from including the part of the element in addition to the A as main component to the wording of material, composition etc. made of A.Example Such as, for composition, above-mentioned wording means " X includes A as main component " etc..Such as term " silicon parts " etc. and unlimited obviously, In pure silicon, but there can be the part for including multicomponent alloy and other additives etc., the multicomponent alloy includes SiGe Alloy or other silicon materials are as main component.Equally, term " silicon oxide film ", " dielectric film based on silica " etc. include by It is relatively pure undoped with silica made of film.Obviously, above-mentioned term also includes：By fluorine silica glass (FSG), based on TEOS Silica, silicon oxide carbide (SiOC) or silica or oxygen silica glass (OSG), phosphorosilicate glass (PSG), boron phosphorus silicon based on carbon Heat oxide film or CVD oxidation films made of glass (BPSG) etc.；By systems such as spin-coating glass (SOG), nanometer cluster silicas (NSC) Into coating type silicon oxide film；Low k insulation film made of having porose above-mentioned same parts based on silica is (porous exhausted Velum)；And comprising above-mentioned material as composite membrane of main component and another dielectric film based on silicon etc..

In addition to the dielectric film based on silica, the usually used dielectric film based on silicon in field of semiconductor devices Also include the dielectric film based on silicon nitride.The material for belonging to this dielectric film is, for example, SiN, SiNH, SiCNH etc..Unless in addition Point out, otherwise term " silicon nitride " used herein refers to both SiN and SiNH.Equally, unless otherwise noted, otherwise make here Term " SiCN " refers to both SiCN and SiCNH.

Dielectric film has the property similar with the dielectric film made of SiN made of SiC, and is insulated made of SiON Film should generally be classified as the dielectric film based on silica.

It is used as etching stopping film, Er Qie in self-aligned contacts (SAC) technology of silicon nitride film not only in many cases It is used as stress in stress memory technique (SMT) and applies film.

Similarly, term " thin copper film ", " aluminium wiring ", " aluminum pad ", " golden projection (golden watch facial mask) " etc. are referred not only to by pure The part that material is formed, and refer to the part including aluminium or gold as main component, i.e., it is " wiring based on copper ", " base respectively In the wiring of aluminium ", " pad based on aluminium " and " based on gold projection (based on gold metal film on surface) ".These expression refer to The major part for stating part is made up of these materials as main component.Obviously, these expression are not necessarily referring to whole part All it is made up of these materials.

This is also applied for term " barrier metal ", " seed metal " etc..

3. also, it should be apparent that described in embodiment be schematic diagram, position, property etc. preferred example, and the present invention simultaneously This is not strictly limited to, unless is shown unless otherwise noted and from context in addition.

4. in addition, when being related to particular value or quantity, the present invention can have the value beyond the particular value, or can have There is the value less than the particular value, unless otherwise noted, except non-invention is not limited to the value in theory, and unless in addition from upper and lower Text shows.

(pay attention to, this is equally applicable to half formed with semiconductor device 5. term " chip " is often referred to side thereon Conductor device and electronic device) silicon single crystal wafer, but can include for dielectric substrate composite crystal, such as epitaxial wafer, SOI wafer or LCD glass substrates and semiconductor layer etc..

6. term " bonding welding pad " used herein means pad based on aluminium etc., multilayer gold has been primarily formed thereon Belong to structure or projection cube structure (including region scope from barrier metal film to metal film on surface).Appropriate material for bonding welding pad Material can include the material based on copper and the material based on aluminium.

7. in this application, the termination electrode electrode of coupled outside (be used for) by electrolytic coating on bonding welding pad etc. by The formation such as gold, and relatively thick (compared with barrier metal layer immediately below the electrode etc.).Termination electrode namely " surface Metal level ", it is not intended to direct-coupled intrinsic salient pole, it is contemplated that shape it is similar, for convenience, generally by end Electrode is referred to as " golden projection ", " salient pole " or " salient pole layer " etc..Intrinsic salient pole generally has about 15 μm of thickness, And surface metal-layer generally has about 1 μm to 5 μm of thickness.Formed relatively thickly under the layer gold as surface metal-layer Made of copper, nickel etc. in the example of electrolytic coating layer, including these layers as its part whole surface metal level some There is about 15 μm of thickness in situation.

Term " bond ball " in ball used herein bonding mean the spherical metal core formed at the first bonding point or It is deformed, and refers to the spherical metal core formed by bonding lead or its deformation, such as column-like projection block (stud bump).

8. in this application, term " wiring plate " used herein not only has including general made of glass epoxide thing etc. Machine wiring plate (individual layer and multilayer), and including flexible distributing board, ceramic wiring plate, glass wiring plate etc..Art used herein " electronic component " on language wiring plate includes semiconductor devices, semiconductor chip, the other chipsets of sealing in a package Part (resistor, capacitor etc.) etc..

(the further specific descriptions of preferred embodiment)

Preferred embodiment will be further described in detail below.In each accompanying drawing, by same or similar with reference to symbol Number or label refer to same or similar part, and descriptions thereof will not be repeated in principle.

1. bonding pad opening work is completed in the semiconductor device of the application one embodiment on the pad based on aluminium The explanation of device cross-section structure during skill (referring primarily to Fig. 1)

Fig. 1 is to show to manufacture by the manufacture method of the semiconductor device in the present application one embodiment 65nm technology nodes device cross-sectional structure an example when bonding pad opening technique (complete) device cross. Below by the overview of the device architecture of the semiconductor device described based on Fig. 1 in the embodiment of the present application.

As shown in figure 1, for example, P-channel MOSFET or N-channel are formed on the device surface of p type single crystal silicon substrate 1 MOSFET gate electrode 8, wherein p type single crystal silicon substrate 1 isolate the element separation field insulating membrane of (STI) type by shallow trench 2 isolation.On these components, silicon nitride liner film 4 (for example, thickness is about 30nm) is formed for use as etching stopping film. On film 4, with interlayer dielectric 5 before the thickness formation metal more much bigger than silicon nitride liner film 4.Dielectric film 5 includes passing through hot CVD Method is formed as the ozone TEOS silicon oxide films (for example, thickness is about 200nm) of lower floor and is formed as the plasma on upper strata TEOS silicon oxide films (for example, thickness is about 270nm).Dielectric film forms tungsten plug 3 before through the metal.Until this region put is Metal forefoot area PM.

The first wiring layer M1 thereon includes insulating made of SiCN films (for example, thickness is about 50nm) as lower floor Barrier film 14, the pecvd silicon oxide film 15 as dominant layer dielectric film (for example, thickness is about 150nm) and it is embedded in Thin copper film 13 in the wiring groove formed in insulating barrier films 14 and pecvd silicon oxide film 15 etc..

Second thereon has essentially identical configuration to the 6th wiring layer M2, M3, M4, M5 and M6 each other.Every layer includes As lower floor made of SiCO films (for example, thickness is about 30nm)/SiCN films (for example, thickness is about 30nm) compound inslation Barrier film (pad film) 24,34,44,54 or 64 and the dominant layer dielectric film 25 for occupying most of region as upper strata, 35, 45th, 55 or 65.It is SiOC films that dominant layer dielectric film 25,35,45,55 or 65, which is included as the carbon doped silicon oxide film of lower floor, (for example, about 350nm) and the plasma TEOS silicon oxide films (for example, thickness is about 80nm) as epiphragma.Through interlayer Dielectric film forms the copper embedded wiring 23,33,43,53 or 63 for including copper plug and thin copper film.

The the 7th and the 8th wiring layer M7 and M8 thereon has essentially identical configuration each other.Every layer is included as lower floor Insulating barrier films 74 or 84 and the dominant layer dielectric film 75 as upper strata made of SiCN films (for example, thickness is about 70nm) Or 85.Dominant layer dielectric film 75 or 85 includes the plasma TEOS silicon oxide films as lower floor (for example, thickness is about 250nm), fsg film (for example, thickness is about 300nm) and the usg film (for example, thickness is about 200nm) as epiphragma.Through this A little interlayer dielectrics, form the copper embedded wiring 73 or 83 for including copper plug and thin copper film.

The the 9th and the tenth wiring layer M9 and M10 thereon has essentially identical configuration each other.Every layer is divided into as under The interlayer portion of layer and the layer inside points as upper strata.Interlayer dielectric is included as lower floor by SiCN films (for example, about Insulating barrier films 94b or 104b and the dominant layer dielectric film as upper strata etc. made of 70nm) etc..Dominant layer dielectric film bag The usg film 96b or 106b of fsg film 95b or 105b (for example, thickness is about 800nm) and the epiphragma as upper strata are included (for example, thick Degree is about 100nm) etc..Layer interior insulation film include as lower floor made of SiCN films (for example, thickness is about 50nm) etc. it is exhausted Edge barrier film 94a or 104a and primary layer interior insulation film as upper strata etc..Primary layer interior insulation film includes the FSG as lower floor Film 95a or 105a (for example, thickness is about 1200nm) and as upper strata epiphragma usg film 96a or 106a (for example, thickness is about For 100nm).Through interlayer dielectric, layer interior insulation film etc., the copper embedded wiring 93 or 103 for including copper plug and thin copper film is formed.

Most upper wiring layer (pad layer) AP thereon is included as lower floor by the grade of SiCN films 114 (for example, thickness is about Insulating barrier films made of 100nm), as intermediate layer made of usg film 117 (for example, thickness is about 900nm) primary layer Between dielectric film and as outermost portion made of plasma SiN119 (for example, thickness is about 600nm) final passivating film Deng.Tungsten plug 113 is arranged through interlayer dielectric, and the bonding welding pad 118 (for example, thickness is about 1000nm) based on aluminium is set On usg film 117.(the example of titanium adhesive layer 151 as lower floor is provided between bonding welding pad 118 and tungsten plug 113 based on aluminium Such as, thickness is about 10nm) and titanium nitride barrier metal layer 152 (for example, thickness is about 30nm) as upper strata.In bonding welding pad Titanium nitride layer 153 (for example, thickness is about 70nm) is formed on 118, then forms key in layer 153 and plasma SiN film 119 Close bonding pad opening 163.

Instead of the bonding welding pad 118 based on aluminium, the bonding welding pad based on copper can be used.

2. form bond pad openings in the manufacture method of the semiconductor device in the application one embodiment The explanation of the technique performed afterwards (referring primarily to Fig. 2, Fig. 3 to Fig. 9, Figure 16, Figure 17 to Figure 24 and Figure 25)

Then, below by the semiconductor collection based on Fig. 3 to Fig. 9 and Figure 17 to Figure 24 descriptions according to the present application embodiment The work of metal-layer structure (surface metal-layer, golden projection etc.) is formed on bonding welding pad into the manufacture method of circuit devcie Skill.

Fig. 2 is from bonding pad opening in the manufacturing process for show semiconductor device in the embodiment of the present application Process chart of the step to the flow of wire bonding process.Fig. 3 is to show the integrated electricity of semiconductor in the embodiment of the present application (when completing bonding pad opening step) device section of the semiconductor chip of road device (corresponds to what is taken along Figure 18 line X-X ' Section) process chart.Fig. 4 is the semiconductor chip for showing the semiconductor device in the embodiment of the present application The process chart in (in barrier film forming step) device section (corresponding to the section taken along Figure 19 line X-X ').Fig. 5 Be show the semiconductor device in the embodiment of the present application semiconductor chip (in resist film coating step In) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 20).Fig. 6 is to show that the application is implemented (in resist film opening procedure) device section of the semiconductor chip of semiconductor device in example (corresponds to edge The section that Figure 21 line X-X ' is taken) process chart.Fig. 7 is to show the semiconductor integrated circuit in the embodiment of the present application (in golden plating steps) device section (corresponding to the section taken along Figure 22 line X-X ') of the semiconductor chip of device Process chart.Fig. 8 be show the semiconductor device in the embodiment of the present application semiconductor chip (against corrosion In agent removal step) process chart in device section (corresponding to the sections that are taken of line X-X ' along Figure 23).Fig. 9 is to show (in barrier metal removal step) device of the semiconductor chip of semiconductor device in the embodiment of the present application is cut The process chart in face (corresponding to the section taken along Figure 24 line X-X ').Figure 16 be according to another embodiment of the application ( Wherein two layers of polyimide film is arranged in the example of additional final passivating film) semiconductor device half (when completing wafer processing step) device cross (corresponding to the section taken along Figure 25 line X-X ') of conductor chip. Figure 17 corresponds to the top view of Fig. 3, semiconductor device in the embodiment of the present application semiconductor chip.Figure 18 It is the amplification vertical view of the part in Figure 17 by dotted line (Fig. 3 shows its corresponding cross-sectional view).Figure 19 is in Figure 17 By amplification vertical view of the part of dotted line in corresponding to the step of Fig. 4.Figure 20 is by the part of dotted line in Figure 17 Amplification vertical view in corresponding to the step of Fig. 5.Figure 21 be in Figure 17 by the part of dotted line corresponding to Fig. 6 the step of In amplification vertical view.Figure 22 is the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 7 in Figure 17.Figure 23 be the amplification vertical view by the part of dotted line in corresponding to the step of Fig. 8 in Figure 17.Figure 24 is by dotted line in Figure 17 Amplification vertical view of the part of encirclement in corresponding to the step of Fig. 9.Figure 25 corresponds to the amplification vertical view of the step of Figure 16.

First, as shown in Fig. 3, Figure 17 and Figure 18, formed on the main surface of chip 101 made of such as silicon nitride Final passivating film 119 (it is not limited to inoranic membrane, and can be organic film), the main surface of the chip 101 is including formed therein The multiple devices and cloth below pad (paying attention to, polyimide resin layer 120 is generally formed on pad, as shown in figure 16) Line (is made up) of silica or various metal levels.Bonding pad opening 163 (its opening for formation in final passivating film 119) is set With in 118 corresponding position of aluminum pad (in the bonding pad opening step S201 shown in Fig. 2).

Then, ise is performed in comprising argon gas as the atmosphere of main component, so as in the state shown in Fig. 3 Remove the natural oxide film (sputter etching craft at the step S202 shown in Fig. 2 on the surface of bonding welding pad 118 In).

Then, as shown in Fig. 4 and Figure 19, formed and stopped and seed metal layer (Underbump metallization film) by sputtering sedimentation 67.Barrier metal film 121 as lower floor for example can be that (its thickness can preferably exist for the titanium film of e.g., about 175 μm of thickness In the range of 150-220 μm) (in the Ti sputtering technologies at the step S203 shown in Fig. 2).Seed metal film as upper strata 122 for example can be the palladium film (its thickness can be preferably in the range of 150-220 μm) of e.g., about 175 μm of thickness (in Fig. 2 In Pd sputtering technologies at shown step S204).

Then, as shown in Fig. 5 and Figure 20, (its thickness can be preferably about 2 for e.g., about 4 μm of thickness of formation on film 122 Into 6 μm of scopes) eurymeric resist film 12 (or being negative resist film if necessary) (at the step S205 shown in Fig. 2 Resist coating processes in).

Then, as shown in Fig. 6 and Figure 21, (for example, being exposed to i rays) and development are exposed to resist (for example, logical Parlkaline developer solution), it is (aobvious at the exposure technology and step S207 at step S206 as shown in Figure 2 to form opening 66 In shadow technique).Then, oxygen ashing process (oxygen plasma body technology) (for example, performing at room temperature about 120 seconds) is performed, To remove (the O at the step S208 shown in Fig. 2 such as organic pollution at the bottom of opening 66₂In cineration technics).

Then, as shown in Fig. 7 and Figure 22, by electrolytic coating, embedding such as thickness is about 2 μm of (its thickness in opening 66 Spend preferably in the range of 1-5 μm) the layer gold 115 as surface metal-layer (salient pole) (in the step S209 shown in Fig. 2 In the electrolytic coating process at place).Condition for plating for example can be, on 300 φ chip, in 55 DEG C of solution temperature And 0.1-1A/dm²Current value under use gold sodium sulfide coating solution, Plating times are about 20 minutes.

Afterwards, as shown in Fig. 8 and Figure 23, removing resist film 12, (resist at the step S210 shown in Fig. 2 removes In technique).Then, (such as performing at room temperature about 120 seconds) perform oxygen ashing process (oxygen plasma body technology) so as to Remove (the O at the step S211 shown in Fig. 2 such as removal organic polluter₂In cineration technics).Finally, as shown in Fig. 9 and Figure 24, connect And use surface metal-layer (golden salient pole) 115 to be used as mask, by wet etching, optionally remove and stop and plant interest Belong to the unnecessary portion of layer 67 (UBM films) (in the Pd wet-etching technologies at the step S212 shown in Fig. 2 and step In Ti wet-etching technologies at S213).Etching solution for seed metal film 122 for example can be iodine etching solution, and And it is used for the etching solution of barrier film 121 such as the mixture that can be ammonia and hydrogen peroxide.Then, (for example, at room temperature Perform about 120 seconds) oxygen ashing process (oxygen plasma body technology) is performed to remove removal organic polluter etc. (shown in Fig. 2 Step S214 at O₂In cineration technics).

Now, surface metal-layer (salient pole) is completed.Surface metal-layer (golden salient pole) 115 is generally by relatively pure Golden material is formed.However, surface metal-layer can be made up of the alloy based on gold substantially, golden conduct should be included based on the alloy of gold Main component.Description is directed in Fig. 9 by following steps of part of dotted line etc. in third portion later.

Barrier metal film can be including a composition in titanium, chromium, titanium nitride and tungsten nitride as main component.Resistance Gear metal film needs the ability with sputtering sedimentation and enough barrier properties to gold.

In addition, seed metal film can include one in copper, gold, nickel, platinum, rhodium, molybdenum, tungsten, chromium and tantalum into being allocated as For main component.Seed metal film needs not react with barrier metal film, it is necessary to not by anti-to form fragility with gold reaction Layer is answered, and needs to turn into the low electrical resistant material for allowing growth plating layer gold.

Figure 16 is modification example corresponding with the structure of the description such as reference picture 3 to Fig. 9.Example shown in Figure 16 and Figure 25 In son, after plasma SiN film (the inorganic final passivating film on pad) 119 is graphical, it is formed on as having The polyimide film 120 of machine passivating film, then by its graphical (to form opening 123 in polyimide film).The example enters Row complicated technology, thus there is labyrinth, but there is the advantages of improving reliability.Instead of the structure, or except the structure it Outside, inorganic final passivating film 119 can include the inorganic insulating membrane as lower floor and the polyimide film as upper strata.

3. packaging technology and device junction in the manufacture method of the semiconductor device in the application one embodiment The explanation of structure (in addition to Fig. 2 and Fig. 9 etc., referring primarily to Figure 10 to Figure 12)

Below in this section in process after technique described in part 2 will be described, from the step shown in Fig. 2 S214 O₂Wire bonding process (in its use form column-like projection block) of the cineration technics to step S219.

Figure 10 corresponds to the top of Fig. 9, semiconductor device in the embodiment of the present application semiconductor chip View.Figure 11 is the top view of the semiconductor device in the embodiment of the present application.Figure 12 be with Figure 11 by dotted line bag Exemplary cross-sectional corresponding to the part enclosed.

As shown in Fig. 2 the O in the step S214 (referring to Fig. 2) described by reference picture 9 (Figure 16)₂After cineration technics, Probe test 215 (wafer inspection) is performed on wafer 101.Afterwards, by the grinding back surface of chip 101 into predetermined thickness, also It is that the grinding back surface in step S216 BG techniques is carried out to it.Then, scribing process is performed, being included in step S217 makes With laser, rotating knife or its both, chip 101 is divided into multiple chips 101.Divided chip 101 is illustrated below State.

Figure 10 corresponds to Fig. 9 (or Figure 16), semiconductor device in the embodiment of the present application semiconductor The whole top view of chip 101.In the figure, the substantially whole surface of semiconductor chip 101 is covered with final passivating film 119 (120), and metal film on surface 115 is arranged on each pad of film periphery.

Then, as shown in Figure 11 and Figure 12 (the amplification cross-sectional view of Figure 11 part by dotted line), by semiconductor Chip 101 exists via adhesive layer 130 (tube core adhesive film (die attach film), paste etc.) tube core bonding (die-bond) As the wiring plate 133 of organic multilayer wiring plate etc. (can be single layer cloth line plate), (it can be ceramic substrate, flexible distributing board Deng) on (in the tube core bonding technology of the step S218 shown in Fig. 2).

Then, as shown in figure 12, will using the bonding lead 132 and bonding capillary 171 including gold as main component Surface metal-layer 115 (metal surface) on bonding welding pad 118 on chip (tube core) 101 and the lead outside chip 101 Part 131 (in this case, on wiring plate 133) is coupled (under as shown in Figure 2 e.g., from about 150 DEG C of bonding temperature Step S219 at wire bonding process in).In this case, the side of surface metal-layer 115 is subjected to the ball together with ball 134 Bonding is (at main ball bonded portion 135), and the side of lead portion 131 is subjected to wedge bonding (at secondary bonded portion 136) (paying attention to, this two parts is considered as a collection merging and is referred to as " ball bonding ", " ball wedge bonding ", " ailhead bonding " etc.).From right For the requirement for reducing temperature, the type of bonding is preferably thermo-sonic bonding technique (using heating and the combination of ultrasonic energy).Will (wherein mode of the chip side as time bonded portion) is particularly referred to as in chip side using the bonding of ball 134 in this way " forward direction bonding ", to be different from " reverse bonding " shown in Figure 14 described in following part.

In this embodiment, via the intermediate metal layer being made up of barrier metal etc., using including gold as main component Surface metal-layer is formed on the bonding welding pad based on aluminium (or based on copper) in semiconductor chip side, and its performance is not Determine.Even if work as the bonding based on gold for including gold as main component (for example, it can include palladium and other additives) When wire is used for the interconnection with wiring plate etc., it can also avoid undesirable anti-caused by using for a long time at high temperature Answer process.

For the angle of reliability, it is desirable to the surface of lead portion 131 be so-called bond wire film (including gold, silver, The metal film of palladium or its alloy as main component).

4. packaging technology and device junction in the manufacture method of the semiconductor device in the application one embodiment The explanation of the modification example of structure (referring to Figure 13 to Figure 15)

The various modification example on the packaging technology described in third portion and package assembly are described below.

Figure 13 is the exemplary cross-sectional for being shown in which to change from the wire bonding in Figure 12 the example of wire bonding order Face figure.Figure 14 is the example for being shown in which to be substituted the example of wiring plate by the other electron component on wiring plate in fig. 12 Property cross-sectional view.Figure 15 is to be shown in which to substitute by another electronic component on (back bonding) wiring plate in fig. 12 Will tube core bonding semiconductor chip target part example exemplary cross-sectional.

(1) explanation of reverse bonding system (backward bonding) (referring to Figure 13)

As shown in figure 13, the order of the wire bonding shown in Figure 12 can be inverted.It is, back bond can be used Close.In this case, the side of surface metal-layer 115 is time bonded portion 136, and this has the advantages of reducing wire loop height. Generally there is the problem of producing impact to device to the Direct Bonding of aluminium bonding welding pad 118.However, in this example, it is relatively thick The presence of surface metal-layer 115 relatively reduce the influence of above mentioned problem.

Similar to third portion, for the angle of reliability, it is desirable to which the surface of lead portion 131 has so-called bonding Metal film (including metal film gold, silver, palladium or its alloy as main component).

(2) explanation of the wire bonding system between two chips (referring to Figure 14)

Different from Figure 12 and Figure 13, in this example as shown in figure 14, the not direct tube core of semiconductor chip 101 is bonded in On wiring plate 133, but another semiconductor chip 101b that tube core is bonded on wiring plate 133 (more generally, is device core Piece) on, it is, on lower layer chip (hereinafter referred to as underlying electronic component).Surface on semiconductor chip 101 wherein In the case of metal level 115 interconnects via the surface metal-layer 115 on bonding lead 132 and lower layer chip 101b, when second half Conductor chip 101b has with the identical of semiconductor chip 101 in the multi-layer metal structure on pad, the two bonded portions Structure with high reliability.

It is equally applicable reverse bonding.

(3) explanation of flip chip tube core Bonding Type (referring to Figure 15)

As shown in figure 15, can be on another semiconductor chip 101b, that is, on lower layer chip, perform semiconductor The tube core bonding of chip 101, another semiconductor chip 101b flip-chips are bonded to wiring plate 133 (by solder projection 137 Bonding pad (land) electrode 138 for the solder projection being bonded on wiring board 133).In this case, in semiconductor Surface metal-layer 115 on chip 101, electrode (lead portion) or cloth on the device chip in addition to lower layer chip 101b At lead portion 131 on line plate 133, the interconnection by bonding lead 132 is performed.

Similar to the description in third portion, for the angle of reliability, it is desirable to which the surface of lead portion 131 is institute The bond wire film (including metal film gold, silver, palladium or its alloy as main component) of meaning.

It is equally applicable reverse bonding.

5. the various packing forms of the semiconductor device in the application one embodiment explanation (referring primarily to Figure 38 to Figure 44)

Below by the various encapsulation of the semiconductor device in the application one embodiment described in this section Form (pays attention to, this is equally applicable to other embodiments).

Figure 38 is semiconductor device (wire bonding type when packaging technology is completed in the embodiment of the present application BGA whole top view) (to should be readily appreciated that the diagram omitted to resin seal part).Figure 39 is Figure 38 exemplary cross section Figure.Figure 40 is semiconductor device (QFP when packaging technology is completed in the embodiment of the present application：Four-armed olfactometer) Whole top view (to should be readily appreciated that the diagram omitted to the top half of resin seal part).Figure 41 is Figure 40 exemplary horizontal stroke Sectional view.Figure 42 is semiconductor device (flip-chip variety when packaging technology is completed in the embodiment of the present application BGA whole top view).Figure 43 is Figure 42 exemplary cross-sectional.Figure 44 is the part surrounded in Figure 43 by dotted line Amplify cross-sectional view.

First, wire of Figure 38 and Figure 39 descriptions using wiring plate 133 (for example, organic multilayer wiring plate) will be based on below The BGA of Bonding Type.As shown in Figure 38 and Figure 39, device chip 101 (semiconductor chip) is via adhesive layer 130 (for example, tube core Adhesive film or tube core bonding paste etc.) tube core is bonded on wiring plate 133.Set on the upper surface of device chip 101 Multiple surface metal-layers 115 (it is on bonding welding pad), the plurality of surface metal-layer 115 are coupled to via bonding lead 132 The multiple outer leads 131 set on the upper surface of wiring plate 133.In this example, bond ball 134 is produced on surface metal-layer 115 On side.The upper surface sealing resin 181 of wiring plate 133 seals.On the contrary, set in the lower face side of wiring plate 133 multiple Solder projection 137.

Figure 40 and Figure 41 will be then based on below describes wire bonding type QFP (resin-encapsulated for using lead frame). As shown in Figure 40 and Figure 41, device chip 101 (semiconductor chip) via adhesive layer 130 (for example, tube core adhesive film or tube core key Closing paste etc.) tube core is bonded on the pipe core welding disc 145 kept by four pipe core welding disc support bars 146.Multiple surface metals Layer 115 is arranged on (on bonding welding pad) on the upper surface of device chip 101, and is coupled to by bonding lead 132 and drawn Line part 131.In this example, bond ball 134 is produced on the side of surface metal-layer 115.The inner side of lead 131, pipe core welding disc branch Stay 146, pipe core welding disc 145, device chip 101 and bonding lead 132 are sealed with resin seal part 181 (sealing resin).

In addition, the BGA of flip-chip variety will be described based on Figure 42 to Figure 44 below (for example, by the column based on gold The flip-chip bonding of projection).As shown in Figure 42 to Figure 44, multiple bonding pad pads 155 are arranged on wiring plate 133.In device (it can be based on to the golden column-like projection block 157 under surface metal-layer 115 (bonding welding pad) on the lower surface of part chip 101 The projection of copper) via solder layer 156 (for example, by weight than the silver for 3.5% and residue (balance) structure comprising tin Into lead-free solder etc.) be coupled to bonding pad pad 155.The coupling by underfill (underfill) resin 148 (for example, Include the epoxy resin of Cab-O-sil etc.) reinforce.The solder projection of coupled outside is provided on the lower surface of wiring plate 133 137 (e.g., including weight than the silver for 3.5%, weight than the copper for 0.5% and the Pb-free coating of the residue comprising tin Material).

6. wafer probe inspection in the manufacture method of the semiconductor device in the application one embodiment etc. Illustrate (referring primarily to Figure 27 to Figure 32)

This part will be described with wire bonding work of the above based on Fig. 2 at step S219 described in third portion Skill and probe test 215.

Figure 27 is that wafer probe is surveyed in the manufacturing process for show the semiconductor device in the embodiment of the present application The enlarged drawing of the wafer top surface (square pads in first example) of the state of trial work skill.Figure 28 is corresponding to Figure 27 The enlarged drawing of wafer top surface (square pads in first example) in example during completion wire bonding process.Figure 29 is to show In the embodiment of the present application in the manufacturing process of semiconductor device the state of wafer probe test technology another chip The enlarged drawing of top surface (rectangular pads of the general type in second example).Figure 30 is completed in the example corresponding to Figure 29 The enlarged drawing of wafer top surface (the general rectangular pads in second example) during wire bonding process.Figure 31 is to show the application The another chip top table of the state of wafer probe test technology in embodiment in the manufacturing process of semiconductor device The enlarged drawing in face (rectangular pads of the modification in third example).Figure 32 is that wire bonding is completed in the example corresponding to Figure 31 The enlarged drawing of wafer top surface (rectangular pads of the modification in third example) during technique.Based on above description, below will say Bright relation in bonding lead, probe tip and surface metal-layer (also including orientation) between the shape of bonding welding pad etc..

First, Figure 27 descriptions will be based on below use the probe test work of square pads in step S215 (referring to Fig. 2) place Skill.As shown in figure 27, surface metal-layer 115 (is paid attention in this example, bonding welding pad 118 with bonding welding pad 118 with similar shape It is more slightly larger than metal level 115) concentric locating (sharing a center substantially).In addition to surface metal-layer 115 and bonding welding pad 118 Part nearly all covered with plasma SiN119 (the inorganic final passivating film on pad) etc..In probe test 215, Multiple probe tips 221 are in contact with corresponding surface metal-layer 115.By based on gold metal material (including high-purity gold or Including metal of the gold as main component) surface metal-layer 115 of composition has good contact.Because based on gold Metal material be nearly free from natural oxide film in its surface, this necessarily brings reduced contact to damage and (also brings phase To less contact load and amount of overdrive).The mechanical frangible low-k film of this inter wiring layer insulating film under as pad Deng use in it is especially effective.

Wire bonding process by using square pads, at step S219 will be described based on Figure 28 below.Such as Figure 28 It is shown, in this case, with probe test technique middle probe syringe needle 221 contacts at step S215 position identical position The middle bonding for performing bonding lead 132 (bond ball 134).The presence of surface metal-layer 115 has due to small contact damage (no Excessive contact vestige can be left) adverse effect without causing para-linkage performance the advantages of, this is different from wherein because Al is welded The stripping of disk and leave contact vestige situation.

Below by based on Figure 29 and Figure 30 description using general rectangular pads step S215 locate probe test technique with Wire bonding process at step S219 (referring to Fig. 2).As shown in Figure 29 and Figure 30, from plan view, surface metal-layer 115 With bonding welding pad 118 with similar shape (noticing that bonding welding pad 118 is more slightly larger than metal level 115 in this case) concentric locating (sharing a center substantially).However, in this embodiment, can because surface metal-layer 115 and bonding welding pad 118 are rectangle To perform wire bonding in the different position in the position contacted with probe tip 221.Thus, in various probe tests, example Such as, perform rechecking and (reexamine) technique etc..Even if when contact damage may become relatively large, can also avoid to wire The influence of bonding.

Then the probe test technique at the step S215 of the rectangular pads of modification will be used based on Figure 31 and Figure 32 descriptions With the wire bonding process at step S219 (referring to Fig. 2).As shown in Figure 31 and Figure 32, from plan view, surface metal-layer 115 have rectangular shape, and bonding welding pad 118 has substantially square shape.From orientation or the angle of position relationship, layer 115 It is partially overlapped by each other, but offsets one from another with pad 118.The part without bonding welding pad 118 of each surface metal-layer 115 via Underbump metallization layer (stop and seed metal layer) 67 is formed in plasma SiN (the inorganic final passivating film on pad) 119 On.Thus, it is possible to obtain the advantages of identical with above-mentioned general rectangular pads.Generally it is desirable that such as damping of bonding welding pad 118 Material (damping of shocks layer) is present under part to be detected.In some cases, it is made up of the metal material based on gold Surface metal-layer 115 may insure its hardness, and contact damage can be reduced into relatively small degree.Thus, even if When the part without bonding welding pad 118 of probe tip 221 as shown in figure 31 and layer 115, (i.e. no bonding welding pad 118 is in the portion / under) when being in contact, can also reduce to the plasma SiN film (the inorganic final passivating film on pad) 119 of lower section Damage.Wire bonding point can be arranged in the position for allowing to be bonded on surface metal-layer 115.As shown in figure 32, wire key Chalaza is located in the part with bonding welding pad 118, thus, it is possible to reduce the possibility being damaged.

7. under each type of surface metal-layer of the semiconductor device in the application one embodiment The explanation of metal-layer structure (or Underbump metallization structure) (referring primarily to Figure 45 to Figure 47)

Various types of metal-layer structures under surface metal-layer as described above will be described further in more details.

Figure 45 is a type of convex in the semiconductor device of the application one embodiment for illustrating The cross-sectional view of the pad periphery of metal structure (two layers of structure) under block.Figure 46 is outside the pad in Figure 45 modification example The cross-sectional view enclosed.Figure 47 is for illustrating another species in the semiconductor device of the application one embodiment The cross-sectional view of the pad periphery of the Underbump metallization structure (sandwich construction of three layers or more layers) of type.

First, below by the basic surface of the semiconductor device based on Figure 45 descriptions in the embodiment of the present application Metal-layer structure under metal level.In this case, as shown in figure 45, it is such as golden as the stop of main component including titanium Category film 121 is stacked on the bonding welding pad 118 based on aluminium (for example, by sputtering sedimentation, to be about 0.175 μm of thickness). It is stacked to include palladium as the seed metal film 122 of main component (for example, by sputtering sedimentation, with about in barrier metal film 0.175 μm of thickness).Then, on metal film 122, the stacked electrolyzing gold plating salient pole for including gold as main component 115 (metals on golden projection, surface metal-layer or pad) are (for example, in the range of about 1 to 3 μm, for example, to be about 2.8 μm Thickness).Titanium film 121 is the interior diffusion barrier film for preventing aluminium and gold.Palladium film 122 is to be used to form electrolyzing gold coating surface metal level 115 seed membrane.

The modification example of example shown in Figure 45 is described below with reference to Figure 46.As shown in figure 46, the structure is included between kind Electrolytic nickel coating layer 127 (e.g., about 2 μm of its thickness) between sub- metal film 122 and electrolyzing gold coating surface metal level 115. Nickel is harder than gold etc., and this is efficiently reduced due to damage caused by wire bonding.

Below by an example of the Underbump metallization structure based on sandwich construction of Figure 47 descriptions with three layers or more layers Son.In this case, as shown in figure 47, such as the barrier metal film 124 including chromium as main component is stacked in based on aluminium Bonding welding pad 118 on (for example, by sputtering sedimentation, to be about 0.075 μm of thickness).In barrier metal film, bag is stacked Include seed metal film 125 (for example, by sputtering sedimentation, to be about 0.25 μm of thickness) of the copper as main component.Then, exist It is stacked to include copper as the cathode copper coating layer 126 of main component (for example, if necessary at about 1 to 10 μm on metal film 125 In the range of, for example, to be about 2 μm of thickness).In addition, on coating layer 126, it is stacked to include electrolysis of the nickel as main component Nickel coating layer 127 (to be about 2 μm of thickness).On coating layer 127, the stacked electrolyzing gold plating for including gold as main component Salient pole 115 (metal film on golden projection, surface metal-layer or pad) (for example, in the range of about 1 to 3 μm, for example, with About 2.8 μm of thickness).Chromium film 124 is the interior diffusion barrier film for preventing aluminium and copper.Copper film 125 is to be used to form cathode copper plating The seed membrane of overlay film 126.

The structure has following feature：Relatively thick and harder nickel dam and layers of copper are formed in electrolyzing gold plating salient pole Under 115, thus it can efficiently reduce due to damage caused by wire bonding.Additionally, the structure may be used as by nickel dam The wiring route of the high reliability formed with layers of copper (there is low-resistance rewiring circuit).In addition, the structure can also have Effect ground reduces the resistance of outside terminal.

8. the consideration on various embodiments (referring primarily to Figure 26 and Figure 33 to Figure 37)

This part will be provided for each embodiment is common or the description of specific feature and technique effect etc. or other benefits Fill description.

Figure 26 is for illustrating the illustrative cross section the non-electrolytic gold plating on nickel surface the problem of.Figure 33 is to use The aluminum pad of caused Kirkendall effect and the local exemplary cross-sectional of bonding lead when explanation is bonded between aluminium and gold Face figure.Figure 34 is the bonding shape for showing the bonding lead at the semiconductor device in the embodiment of the present application on pad The partial cross section view of one of various examples of state (general modfel).Figure 35 is to show the semiconductor collection in the embodiment of the present application The partial cross sectional of one of various examples of the bond styles of the bonding lead at into circuit devcie on pad (sliding laterally pattern 1) Face figure.Figure 36 is the bonding shape for showing the bonding lead at the semiconductor device in the embodiment of the present application on pad The partial cross section view of one of various examples of state (sliding laterally pattern 2).Figure 37 is for illustrating in the embodiment of the present application The partial cross-section of relation between the various sizes of the bonding structure of bonding lead at semiconductor device on pad Figure.

First, Figure 26 will be based on, by using the feelings that non-electrolytic gold plating (replacing golden plating) is carried out on nickel surface 30 As an example, description uses non-electrolytic gold plating (this is not limited to gold, can be by copper or nickel replacement) rather than electrolyzing gold plating to condition The problem of.As shown in figure 26, non-electrolytic gold plating film is to lack the portion that metal is covered under nickel is used as by the way that golden part 302 is attached to Formed on points 303.Golden plating zones 302 are porous state in itself, because plating reaction stops while the surface is covered Only.Then, nickel element is prone to deposit from porous part, and the nickel element deposited is oxidized to form nickel oxide (NiO).Nickel oxide, which is present on golden plating zones 302, to be made it difficult to bonding lead being bonded, and even if wire is attached, So that wire is easily peeled off.It is generally difficult because golden plating zones 302 cover the stage upper plating reaction stopping on the surface wherein To ensure about 100nm (or about 0.1 μm) or more plated thickness.In addition, between nickel surface 301 and golden plating zones 302 The formed therein which hole in interface, thus appropriate bonding (bonding) performance can not be ensured, this easily causes the stripping (boundary of layer gold Peel off in face).

By contrast, in electrolytic coating process, plating reaction is carried out by the electric field from outer side, and can be with shape Into the plating film of densification, and formed plating film can be made to be thicker than the film for being subjected to non-electrolytic gold plating.Obviously, this is not limited to Wherein descend coating situation made of nickel.

Based on Figure 33, description below is bonded directly to based on aluminium in the bonding lead (or bond ball) of the material based on gold etc. Pad, and be not based on aluminum pad in such case of surface metal-layer 115 of material etc. of gold the problem of.When by based on Bonding lead is maintained under relatively lower temp (for example, about 150 DEG C) for a long time made of material of gold etc., while direct-coupling When on to the pad based on aluminium, as shown in figure 33, intermetallic nitride layer 140,141,142 and 143 based on Au-Al (for example, Au₄Al layers 140, Au₂Al layers 141, Au₅Al₂142 and AuAl of layer₂143) interface that layer is appeared between aluminum and golden material is attached Closely.In this state, hole 139 (Kirkendall effect) is produced in the side of bond ball 134, this may cause what is connected or couple Disconnect.Because gold element is diffused into the speed ratio aluminium in the intermetallic nitride layer 140,141,142 and 143 based on Au-Al Elements diffusion is faster to the speed in the intermetallic nitride layer 140,141,142 and 143 based on Au-Al.It is, gold ion To aluminum pad 118, this causes to produce a large amount of rooms that will be progressively condensed into hole high-speed mobile.

By contrast, the surface metal-layer 115 of the material based on gold etc. can on aluminum pad 118 via barrier layer intervention To ensure bonding performance, and also effectively prevent the appearance of hole.

Based on Figure 34 to Figure 36, bonding lead 132 or 115 (or bond ball of the description below based on golden (or based on copper) 134) to the various types of bonding patterns for the surface metal-layer 115 being made up of material based on gold etc..Figure 34 is shown typically Pattern.It is, bond ball 134 is contained in the upper surface of surface metal-layer 115.Example shown in Figure 35 is a kind of sliding die The main bonded portion (center of ball) of formula, wherein bond ball 134 is contained in the upper surface of surface metal-layer 115.From performance Angle for, the pattern has no problem.Example shown in Figure 36 is another sliding-modes, wherein bond ball 134 Main bonded portion (center of ball) is contained in the upper surface of surface metal-layer 115, and ball 134 deformation itself or ball 134 Change the shape of the end of surface metal-layer 115, so as to the lower end of ball 134 reach plasma SiN film (on pad it is inorganic most Whole passivating film) 119 surface.Moreover, in this case, due to the cushioning effect of surface metal-layer 115, in plasma Seldom occur being broken in SiN (the inorganic final passivating film on pad) 119 grades.The problem of seldom in properties of product be present. Therefore, above-mentioned principal character can apply to Figure 34 to any situation shown in Figure 36.In other words, in Figure 34 to Figure 36 institutes In the case of showing, the major part of wire bonding part can be located at the substantially directly over of bonding welding pad on the whole.

Below with reference to Figure 37 (Figure 28, Figure 30, Figure 32 and Figure 45 to Figure 47), describe in each embodiment of the application In semiconductor device on pad bonding lead bonding structure, it is, on pad metal structure various sizes Between relation.As shown in figure 37, in typically layout (general structure), the width LP of pad is maximum in all directions, weldering The width LW of dish opening is minimum in all directions, and the width LB of surface metal-layer is median in all directions.Cause And from plan view, surface metal-layer 115, which is located in bonding welding pad 118, (to be paid attention to, surface metal-layer 115 is less than on area The area of pad).Similarly, bond pad openings 163, which are located in surface metal-layer 115, (pays attention to, bond pad openings 163 exist It is less than the area of metal level on area).

Non- general structure shown in Figure 32 only meets this size relationship and inclusion relation in given crosswise direction, and Not exclusively meet these relations in longitudinal direction.

Similarly, as shown in figure 37, in general structure, the thickness TB (or its equivalent thickness) of surface metal-layer is more than resistance Keep off the thickness TU (generally, the thickness of barrier metal film 121) of metal level.The relatively thick original in this way of surface metal-layer 115 Because being, metal level 115 will ensure the performance or function of bonding welding pad substantially.However, it is assumed that by changing ambient parameters etc., The thickness TB of surface metal-layer becomes essentially identical with the thickness TU of barrier metal layer.The two thickness can have opposite pass System.Thus, when surface metal-layer is relatively thin or is partly formed, surface metal-layer is not limited to electrolytic coating, and can be by splashing Penetrate deposition or electroless plating is formed.Specifically, sputtering sedimentation is a kind of to be related to enter to forming film on whole chip The process of row photoengraving, in many cases due to the strong internal stress in the film with unnecessary (discarding) portion of generation Point and the shortcomings that chip warpage.But compared with plating film, this method has the advantages of can forming very clean film.

As shown in Figure 46 and Figure 47, when electrolytic metal layer formed barrier metal layer 121 (or stop and seed metal layer 67) when on, the whole thickness of these electrolytic metal layers is consistent with the thickness TB of surface metal-layer in theory.Work as seed metal When layer (such as being made of copper) and the electrolytic coating layer (such as being made of copper) of top have same nature, in fact, kind interest Category layer is preferably adapted to be formed a part for electrolytic coating layer in a thickness direction.

Reference picture 37, the width LB of surface metal-layer can be more than the width of pad on such as Figure 32 specific orientation or direction Spend LP.This structure can strengthen the flexibility of bonding point (position for being used for wire bonding).Similarly, the width of surface metal-layer The width LP of pad can be more than in all orientations or direction by spending LB.In addition, the width LB of surface metal-layer is in specific orientation Or (or in all orientations and direction) can be less than the width LW of bonding pad opening on direction.The structure, which can have, reduces gold Consumption and the various layouts of increase in flexibility the advantages of.

9. summarize

Although having been based on preferred embodiment specifically describes the present invention that the present inventor makes, of the invention and unlimited In this.It will be apparent to one skilled in the art that without departing from the present invention, presently disclosed embodiment can be entered The various modifications of row.

For example, although the embodiment specifically describe with Damascus interconnection such as copper Damascus interconnection (cupric, The embedded wiring as main wiring composition such as silver) semiconductor chip, but the invention is not restricted to this.Obviously, the present invention also may be used With the use applied to the semiconductor chip with the general wiring (non-embedded wiring) based on aluminium.

In the above-described embodiments, for bonding lead or the material of bond ball (including column-like projection block) mainly for example based on The wire of gold.Obviously, in the same way, bonding lead can apply to based on gold wire (high-purity gold or it is added Have the gold of various additives), wire based on copper (high-purity copper, oxygen-free copper are added with the copper of various additives to it), base In wire (containing metal material of the palladium as main component) of palladium etc..

Claims

1. a kind of semiconductor device, including：

(a) wiring part, there is chip mounting part and electrode terminal；

(b) semiconductor chip, on the chip mounting part of the wiring part and including：

(b1) pad electrode, it is arranged on the device surface of the semiconductor chip；

(b2) dielectric film, formed on the device surface and opening is formed in the dielectric film so that the pad A part for electrode exposes from the opening；

(b3) barrier metal film, it is arranged on the part exposed from the opening of the pad electrode；And

(b4) metal film on surface, it is arranged on the barrier metal film；

(c) bonding lead, it is electrically connected to the metal film on surface of the semiconductor chip and is electrically connected to the wiring portion The electrode terminal of part；And

(d) seal, the semiconductor chip and the bonding lead are sealed；

Wherein in plan view, the metal film on surface has rectangular shape, and the metal film on surface has two longer sides With two shorter sides；

Wherein in plan view, the metal film on surface is located in the circumference of the pad electrode, and

Wherein, in section view, every side of the opening in the dielectric film, along the device surface with the semiconductor chip The distance component of neighboring edge of the parallel direction from the outer ledge of the pad electrode to the metal film on surface is more than edge Neighboring edge of the direction parallel with the device surface from the neighboring edge of the metal film on surface to the opening Distance component.

2. semiconductor device according to claim 1,

Wherein in plan view, the semiconductor chip has tetragonal shape, and

Wherein in plan view, the metal film on surface is arranged such that two shorter sides of the metal film on surface are basic The direction of two longer sides extension of the first side and the metal film on surface parallel to the semiconductor chip and described half Intersect in the direction of first side extension of conductor chip.

3. semiconductor device according to claim 2,

Wherein in plan view, two of the first shorter side than the metal film on surface of two shorter sides of the metal film on surface Second shorter side of individual shorter side is closer to first side of the semiconductor chip；And

Wherein in plan view, the coupling part of the bonding lead and the metal film on surface is closer to the metal film on surface First shorter side, rather than second shorter side closer to the metal film on surface.

4. semiconductor device according to claim 3, wherein in plan view, the bonding lead and described Part between the coupling part of metal film on surface and second shorter side of the metal film on surface is can be with engaged test The part of probe.

5. semiconductor device according to claim 3, wherein in plan view, one of the bonding lead Divide and intersect with first shorter side of the metal film on surface.

6. semiconductor device according to claim 1, wherein in plan view, the pad electrode has square Shape shape, the pad electrode have two longer sides and two shorter sides.

7. semiconductor device according to claim 1, wherein in the sectional view of the pad electrode, it is described The part of barrier metal film contact the top surface of the dielectric film in the parameatal part.

8. semiconductor device according to claim 7, wherein in the sectional view of the pad electrode, it is described The width of barrier metal film is more than the width of the opening.

9. semiconductor device according to claim 8, wherein in the sectional view of the pad electrode, it is described The width of metal film on surface is identical with the width of the barrier metal film.

10. semiconductor device according to claim 9, wherein in the sectional view of the pad electrode, institute State narrow width of the width than the pad electrode of metal film on surface.

11. semiconductor device according to claim 1,

Wherein described pad electrode includes aluminium as main component；

Wherein described metal film on surface includes gold and is used as main component；And

Wherein described bonding lead includes copper as main component.

12. semiconductor device according to claim 1,

Wherein described bonding lead is electrically connected to the surface of the semiconductor chip via the ball portion of the bonding lead Metal film；And

Wherein in plan view, the ball portion is located in the circumference of the metal film on surface.

13. semiconductor device according to claim 1,

Wherein described electrode terminal is lead, and

A part for wherein described electrode terminal is protruded from seal.