US20050022091A1 - Method, system, and apparatus for adjacent-symbol error correction and detection code - Google Patents

Method, system, and apparatus for adjacent-symbol error correction and detection code Download PDF

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Publication number
US20050022091A1
US20050022091A1 US10/624,424 US62442403A US2005022091A1 US 20050022091 A1 US20050022091 A1 US 20050022091A1 US 62442403 A US62442403 A US 62442403A US 2005022091 A1 US2005022091 A1 US 2005022091A1
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United States
Prior art keywords
error
memory
syndrome
bits
codeword
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/624,424
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English (en)
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Thomas Holman
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Intel Corp
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Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/624,424 priority Critical patent/US20050022091A1/en
Application filed by Individual filed Critical Individual
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOLMAN, THOMAS J.
Priority to KR1020067001341A priority patent/KR100865195B1/ko
Priority to PCT/US2004/022353 priority patent/WO2005010754A2/en
Priority to CNB2004800212847A priority patent/CN100447750C/zh
Priority to EP04778060A priority patent/EP1646947A2/en
Priority to TW093121485A priority patent/TWI259357B/zh
Publication of US20050022091A1 publication Critical patent/US20050022091A1/en
Priority to US11/584,059 priority patent/US7496826B2/en
Priority to US11/585,411 priority patent/US20070061685A1/en
Priority to US11/968,148 priority patent/US8127213B2/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

Definitions

  • the present disclosure pertains to the field of memory and computer memory systems and more specifically to error detection and correction for memory errors.
  • ECC Error correcting codes
  • SEC single error correcting
  • DED double error detecting
  • SbEC single symbol error correcting
  • DbED double symbol error detecting
  • FIG. 1 illustrates a block diagram of a code word utilized in an embodiment.
  • FIG. 2 illustrates an apparatus utilized in an embodiment.
  • FIG. 3 illustrates a flowchart of a method utilized in an embodiment.
  • FIG. 4 illustrates an apparatus utilized in an embodiment described in connection with FIG. 2 .
  • FIG. 5 illustrates a system utilized in an embodiment.
  • typical ECC code utilizes 36 memory devices for chipfail detection and correction that results in increased cost and design of a computer system.
  • the present ECC codes do not scale.
  • the claimed subject matter facilitates a new ECC code, “adjacent-symbol” code that supports memory systems with 18 memory devices
  • the claimed subject matter facilitates the ability for decoding and correcting memory errors in systems that utilize 18 memory devices for a memory transaction (memory rank).
  • the claimed subject matter facilitates forming a code word of data with only two clock phases.
  • the adjacent-symbol ECC code corrects any error pattern within the data from one memory device and detects various errors (double device errors) from failures in 2 memory devices.
  • the adjacent-symbol ECC code is utilized for a memory system with two channels of Double Data Rate (DDR) memory, wherein each channel is 64 bits wide with eight optional bits for ECC.
  • the memory system may utilize x4 or x8 wide memory devices (x4 and x8 refers to the number of bits that can be output from the memory device).
  • x4 and x8 refers to the number of bits that can be output from the memory device.
  • the claimed subject matter supports various configurations of memory systems. For example, a memory system with x8 devices would utilize 18 memory devices per memory rank if ECC is supported, otherwise, 16 memory devices per memory rank if ECC is not supported. Alternatively, a memory system with x4 devices would utilize 36 memory devices-per memory rank if ECC is supported, otherwise, 32 memory devices per memory rank if ECC is not supported.
  • FIG. 1 illustrates a block diagram of a code word utilized in an embodiment.
  • the block diagram 100 comprises an adjacent symbol codeword 106 to be formed from two clock phases of data 102 and 104 from a memory device.
  • a memory access transaction comprises a transfer of 128 data bits plus an additional 16 ECC check bits per clock edge, for a total of 144 bits for each clock edge (288 bits for both clock edges).
  • a first nibble “n0” and a second nibble “n2” of data from a memory are transferred and mapped to a first nibble of each of two symbols of the codeword 106 .
  • a first nibble “n1” and a second nibble “n3” from a memory are transferred and mapped to a second nibble of each of two symbols of the codeword 106 .
  • the two symbols of the codeword 106 are adjacent and are on a 16 bit boundary of the code word, which are designated as “adjacent symbols”, thus, the codeword 106 is an adjacent symbol codeword.
  • the scheme illustrated in the block diagram facilitates error detection and improves fault coverage of common mode errors.
  • an x4 memory device there is a one to one mapping of nibbles from the x4 memory device to a symbol in the underlying code word.
  • a x8 memory device there is a one to one mapping of nibbles from half of the x8 memory device to a symbol in the underlying code word
  • the claimed subject matter facilitates isolating common mode errors across nibbles to the symbol level and results in increased fault coverage. Therefore, for the x8 memory device, the claimed subject matter precludes aliasing for a second device failure.
  • device errors in the x4 memory devices are isolated to a single symbol in the codeword 106 , thus, there is complete double device coverage for the x4 memory devices.
  • a simultaneous double device failure has no early sign warning because there is no indication of an error in a previous memory transaction.
  • the computer system reports an uncorrectable error in the absence of an aliasing.
  • the system might incorrectly report a correctable single device failure. This time the aliasing may be discovered in subsequent accesses because an error pattern might change as to preclude the alias.
  • a sequential double device failure is a more typical failure pattern than a simultaneous double device failure.
  • the first device error is detected as a correctable error.
  • the error is reported as uncorrectable, otherwise, the error is reported as a correctable error at a new location.
  • the analysis is complete. Otherwise, the system changes the error location from the first device failure to the second device's failure location. Therefore, the preceding method for detecting the alias is accurate because it is unlikely that the first device failure location resolves itself and even less likely that is does at the simultaneous instant that the second device failure has failed.
  • double device errors that are always detected (no aliasing) are double bit errors, double wire faults, wire faults in one memory device with a single bit error in a second memory device, and a fault that affects only one nibble of each memory device.
  • all 16 bits of the codeword may be affected (corrupted) because the failure results in an error for both nibbles and both clock phases of the memory device's data.
  • the claimed subject matter facilitates the correction of this device failure by first correcting the 16 bits that are in error.
  • the code detects the error pattern in two groups of 16 bits which are aligned on 16-bit boundaries in the code word 106 .
  • FIG. 2 illustrates an apparatus utilized in an embodiment. From a high-level perspective, the apparatus generates a code word by creating check bits to be appended to data that is forwarded to memory. Subsequently, the apparatus generates a syndrome based at least in part on decoding the code word received from memory and facilitates classifying errors and correcting the errors.
  • the code word from the memory device is an adjacent symbol codeword that was described in connection with FIG. 1 .
  • the apparatus comprises an encoder circuit 202 , at least one memory device 204 , a decoder circuit 206 , an error classification circuit 208 , and a correction circuit 210 .
  • the encoder circuit receives data that is to be forwarded to the memory device or memory devices 204 .
  • the encoder circuit generates a plurality of check bits based at least in part on the data.
  • a codeword is formed based at least in part on the plurality of check bits and the data and is forwarded to the memory device or memory devices 204 .
  • the check bits are generated from the binary form of a G-matrix, wherein the matrix has 32 rows and 256 columns to form 32 check bits.
  • the multiply operation becomes an AND function and the sum operation the 1-bit sum or XOR operation.
  • the resulting encoding circuit comprises 32 XOR, each tree computing one of the 32 check bits.
  • the memory device or memory devices 104 returns data and the check bits back to the decoder circuit 106 .
  • the decoder circuit generates a 32-bit syndrome based at least in part on a 288-bit code word (as earlier described in connection with FIG. 1 for the 288-bit code word).
  • the syndrome is generated from an H-matrix, wherein the matrix comprises 32 rows and 288 columns.
  • the generation of the syndrome bits is simplified to a XOR operation over the code word bits corresponding to the columns of the H-matrix that have a binary 1 value.
  • the decoding circuit comprises 32-XOR trees, each tree computing one of the 32 syndrome bits. Therefore, in one embodiment, a 32 bit syndrome is generated by an H matrix receiving a 288 bit codeword.
  • the claimed subject matter is not limited to this bit configuration.
  • One skilled in the art appreciates modifications to the size of the syndrome and codeword.
  • FIG. 3 depicts a flowchart for a method utilized in an embodiment.
  • the flowchart depicts a method for detecting whether there were errors in data in a transaction with a memory device or devices.
  • a first block 302 generates check bits to be appended to data for forwarding to a memory device or devices.
  • An adjacent symbol codeword is generated based at least in part on data received from the memory device or devices to be utilized for checking the integrity of the data, as depicted by a block 304 .
  • a decoder generates a syndrome based at least in part on the adjacent symbol codeword, as depicted by a block 306 . In the presence of an error as determined by the syndrome, an error classification and correction is performed, as depicted by a block 308 .
  • FIG. 4 illustrates an apparatus utilized in an embodiment described in connection with FIG. 2 . As previously described, FIG. 4 describes one embodiment of the error classification and error correction in connection with FIG. 2 .
  • a single device correctable error may be classified based at least in part on a weight of the error value.
  • an adjacent pair may generate error values e 0 and e 1 .
  • the error locator vector L is then used to gate the error values on a plurality of busses, 402 and 404 because the circuits allow for the error locator bits for one adjacent pair will be enabled for a given error pattern.
  • the claimed subject matter allows for test coverage of both single and double device errors.
  • FIG. 5 depicts a system in accordance with one embodiment.
  • the system in one embodiment is a processor 502 that is coupled to a chipset 504 that is coupled to a memory 506 .
  • the chipset performs and facilitates various operations, such as, memory transactions between the processor and memory and verifies the data integrity by utilizing the adjacent symbol codeword as described in connection with FIG. 1 .
  • the chipset is a server chipset to support a computer server system.
  • the chipset is a desktop chipset to support a computer desktop system.
  • the system comprises the previous embodiments depicted in FIGS. 1-4 of the specification to support the adjacent symbol codeword and error correction and detection methods and apparatus.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Probability & Statistics with Applications (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
US10/624,424 2003-07-21 2003-07-21 Method, system, and apparatus for adjacent-symbol error correction and detection code Abandoned US20050022091A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
US10/624,424 US20050022091A1 (en) 2003-07-21 2003-07-21 Method, system, and apparatus for adjacent-symbol error correction and detection code
KR1020067001341A KR100865195B1 (ko) 2003-07-21 2004-07-14 인접 기호 오류 수정을 위한 방법, 시스템, 장치와 검출코드
PCT/US2004/022353 WO2005010754A2 (en) 2003-07-21 2004-07-14 A method, system, and apparatus for adjacent-symbol error correction and detection code
CNB2004800212847A CN100447750C (zh) 2003-07-21 2004-07-14 用于相邻符号纠错检错码的方法、系统和装置
EP04778060A EP1646947A2 (en) 2003-07-21 2004-07-14 A method, system, and apparatus for adjacent-symbol error correction and detection code
TW093121485A TWI259357B (en) 2003-07-21 2004-07-19 A method, system, and apparatus for adjacent-symbol error correction and detection code
US11/584,059 US7496826B2 (en) 2003-07-21 2006-10-20 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/585,411 US20070061685A1 (en) 2003-07-21 2006-10-23 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/968,148 US8127213B2 (en) 2003-07-21 2007-12-31 Method, system, and apparatus for adjacent-symbol error correction and detection code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/624,424 US20050022091A1 (en) 2003-07-21 2003-07-21 Method, system, and apparatus for adjacent-symbol error correction and detection code

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US11/584,059 Division US7496826B2 (en) 2003-07-21 2006-10-20 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/585,411 Division US20070061685A1 (en) 2003-07-21 2006-10-23 Method, system, and apparatus for adjacent-symbol error correction and detection code

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US10/624,424 Abandoned US20050022091A1 (en) 2003-07-21 2003-07-21 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/584,059 Expired - Fee Related US7496826B2 (en) 2003-07-21 2006-10-20 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/585,411 Abandoned US20070061685A1 (en) 2003-07-21 2006-10-23 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/968,148 Expired - Fee Related US8127213B2 (en) 2003-07-21 2007-12-31 Method, system, and apparatus for adjacent-symbol error correction and detection code

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US11/584,059 Expired - Fee Related US7496826B2 (en) 2003-07-21 2006-10-20 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/585,411 Abandoned US20070061685A1 (en) 2003-07-21 2006-10-23 Method, system, and apparatus for adjacent-symbol error correction and detection code
US11/968,148 Expired - Fee Related US8127213B2 (en) 2003-07-21 2007-12-31 Method, system, and apparatus for adjacent-symbol error correction and detection code

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US (4) US20050022091A1 (ko)
EP (1) EP1646947A2 (ko)
KR (1) KR100865195B1 (ko)
CN (1) CN100447750C (ko)
TW (1) TWI259357B (ko)
WO (1) WO2005010754A2 (ko)

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CN104484310A (zh) * 2014-12-11 2015-04-01 北京国双科技有限公司 公式规范性校验方法及装置
US9058890B2 (en) 2007-02-27 2015-06-16 Samsung Electronics Co., Ltd. Over-sampling read operation for a flash memory device
US11392454B2 (en) 2020-05-12 2022-07-19 Samsung Electronics Co., Ltd. Memory controllers, memory systems and memory modules

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CN104486615B (zh) * 2014-12-09 2016-08-24 广东威创视讯科技股份有限公司 Ddr芯片的故障定位方法与装置
US9912355B2 (en) 2015-09-25 2018-03-06 Intel Corporation Distributed concatenated error correction
CN110209524B (zh) * 2019-06-18 2022-12-06 哈尔滨工业大学 一种抗单粒子瞬态效应的ecc译码器加固方法
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US11392454B2 (en) 2020-05-12 2022-07-19 Samsung Electronics Co., Ltd. Memory controllers, memory systems and memory modules

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CN1826588A (zh) 2006-08-30
EP1646947A2 (en) 2006-04-19
US20080104476A1 (en) 2008-05-01
KR100865195B1 (ko) 2008-10-23
WO2005010754A2 (en) 2005-02-03
US20070061675A1 (en) 2007-03-15
US7496826B2 (en) 2009-02-24
US8127213B2 (en) 2012-02-28
CN100447750C (zh) 2008-12-31
TW200508851A (en) 2005-03-01
TWI259357B (en) 2006-08-01
KR20060061335A (ko) 2006-06-07
WO2005010754A3 (en) 2005-04-14
US20070061685A1 (en) 2007-03-15

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