US20040159911A1 - Method for fabricating base-emitter self-aligned heterojunction bipolar transistors - Google Patents
Method for fabricating base-emitter self-aligned heterojunction bipolar transistors Download PDFInfo
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- US20040159911A1 US20040159911A1 US10/367,342 US36734203A US2004159911A1 US 20040159911 A1 US20040159911 A1 US 20040159911A1 US 36734203 A US36734203 A US 36734203A US 2004159911 A1 US2004159911 A1 US 2004159911A1
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 122
- 239000011241 protective layer Substances 0.000 claims abstract description 40
- 238000005304 joining Methods 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000002184 metal Substances 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000000463 material Substances 0.000 description 13
- 239000010953 base metal Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
Definitions
- the present invention relates to semiconductor fabrication methods, and more particularly to heterojunction bipolar transistors.
- a heterojunction bipolar transistor is constructed from a stack of semiconductor layers in which one of the layers is etched to form a mesa.
- the emitter that is constructed on the mesa, which overlies the base and collector layers in a vertical arrangement.
- the emitter ohmic contact is deposited on the top surface of this mesa.
- the base ohmic contacts are typically deposited adjacent to the mesa on the base layer. The performance of the device is critically dependent on the relative positioning of the emitter and base ohmic contacts.
- One prior art method for providing the required alignment utilizes a self-alignment scheme in which the metal layer in the emitter is used to align the metal layer of the base.
- the emitter metal layer is deposited on the surface of the emitter layer and the emitter layer is then etched using the emitter metal as a mask.
- the base metal is subsequently deposited using the emitter metal to align the base metal.
- These schemes frequently involve fabricating the emitter mesa with a wet-etchant that also undercuts the emitter metal and enables the base metal that is subsequently deposited to be self-aligned to the emitter.
- the undercut prevents the base metal from forming a bridge that shorts the base metal to the emitter.
- the present invention includes a transistor and method for making the same.
- the transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement.
- An emitter contact is patterned on the emitter layer, and the emitter layer is etched to form a mesa on an etched surface, the mesa having a top surface that includes a portion of the emitter layer and sides joining the top surface with the etched surface.
- a first protective layer is deposited over the emitter contact and the etched surface, and a second protective layer is deposited over the first protective layer. The first and second protective layers are removed over the portions thereof that overlie the etched surface, leaving a portion of the second protective layer on a portion of the sides of the mesa.
- the first protective layer is then etched with an etchant that removes the first protective layer faster than the second protective layer thereby undercutting a portion of the first protective layer on the sides of the mesa.
- a patterned metallic layer is then deposited on the etched surface at a position determined by the remaining portion of the second protective layer.
- the etched surface may be a portion of the base layer or a portion of the emitter layer depending on the desired transistor geometry.
- the protective layers are preferably dielectrics.
- FIGS. 1 - 4 are cross-sectional views of a prior art heterojunction transistor at various stages in the fabrication process.
- FIGS. 5 - 11 are cross-sectional views of a heterojunction transistor according to the present invention at various stages in the fabrication process.
- FIG. 12 is a cross-sectional view of a transistor 60 in which a thin emitter layer is also connected to the base metalization.
- FIGS. 1 - 4 are cross-sectional views of a prior art heterojunction transistor at various stages in the fabrication process.
- the emitter metal layer 14 is patterned on an n-type emitter layer 11 .
- the emitter metal layer is then used as a mask for a wet etch process that etches through emitter layer 11 to the top surface of a p-type base layer 12 which is deposited on a collector layer 13 as shown in FIG. 2.
- the base metal layer 16 is then deposited using the emitter metal layer 14 as a mask for the inner edge of the metal deposition as shown in FIG. 3.
- the emitter metal layer and most of the base metal layer are then covered with a photoresist mask 17 to protect these structures during the etching of the base layer as shown in FIG. 4.
- the outer edge of the base metal layer remains exposed and determines the location of the emitter-base mesa area thus assuring the correct alignment of the emitter-base mesa.
- the alignment of the emitter and base electrodes depends on the accuracy of the undercut.
- only air gap 19 shown in FIG. 3 prevents the base metal from shorting to the emitter electrode 14 during the deposition of base metal layer 16 .
- a metal bridge can be formed between emitter electrode 14 and base metal layer 16 thereby shorting the base to the emitter.
- the wet-etch undercut of the emitter metal layer is difficult to control. Errors in this etch step lead to poor emitter size control and emitter-base shorts. Such errors reduce the device yield, and hence, increase the cost of the transistors.
- FIGS. 5 - 11 are cross-sectional views of a heterojunction transistor according to the present invention at various stages in the fabrication process.
- the patterning steps begin with a substrate 21 that has a collector contact layer 22 , collector layer 23 , base layer 24 , and emitter layer 25 as shown in FIG. 5.
- the various layers may include a plurality of sub-layers.
- the emitter layer is constructed from three sub-layers.
- the uppermost layer an n-doped InGaAs layer that is doped with Si to a level of 1 ⁇ 10 19 atoms/cm 3 .
- This InGaAs layer is deposited on an n-doped InAlAs layer having a dopant concentration of 3 ⁇ 10 17 atoms/cm 3 .
- the InAlAs layer is deposited on a super lattice layer having alternating undoped InGaAs and AlInAs layers.
- the base layer has two sub-layers, a p-doped InGaAs layer having a dopant concentration of 3 ⁇ 10 19 C atoms/cm 3 , deposited on an undoped super lattice layer having alternating undoped InGaAs and AlInAs layers.
- the collector layer is constructed from a layer of n-doped InP having a dopant concentration of 5 ⁇ 10 16 Si atoms/cm 3 deposited on an n-doped InGaAs layer having a dopant concentration of 1 ⁇ 10 19 Si atoms/cm 3 .
- the sub-collector contact layer is a single n-doped InP layer having a dopant concentration of 6 ⁇ 10 18 Si atoms/cm 3 .
- the patterning process begins with the deposition of metallic emitter electrode 26 by conventional deposition techniques.
- the emitter electrode is then used as a mask for etching emitter layer 25 to provide the emitter 28 of the transistor as shown in FIG. 6.
- the etching operation is preferably accomplished via a chlorine-based reactive ion etch (RIE) or a high-density plasma etch.
- RIE reactive ion etch
- a 300 nm layer 29 of silicon nitride and a 100 nm layer 30 of silicon dioxide are deposited as shown in FIG. 7. These layers are preferably deposited by PECVD.
- the portions of the silicon dioxide on the horizontal surfaces are then removed as shown in FIG. 8.
- This etching operation is preferably performed using a low pressure, high-bias anisotropic CF4-based RIE.
- the etch is monitored by laser reflectometry or a fixed time based on the etch rate of silicon dioxide to produce a minimal over-etch into the silicon nitride layer.
- a thin layer 31 of silicon dioxide remains on the vertical surfaces of the silicon nitride.
- the portions of the silicon nitride layer that are not protected by silicon dioxide layer 31 are etched using a high pressure, low-bias isotropic SF6-based RIE. This etching operation removes silicon nitride at a rate that is greater than 8 times the rate at which silicon dioxide is removed. This operation undercuts the dielectric area as shown at 32 .
- the base electrodes are deposited with the aid of a photoresist mask 33 as shown in FIG. 10.
- the base contacts 37 are preferably deposited on base layer 24 through the openings 35 in photoresist mask 33 via electron-beam evaporation.
- photoresist mask 33 is removed leaving the transistor as shown in FIG. 11 at 40 .
- the portion of the base layer shown at 39 is removed by an etching operation that isolates the various devices constructed on the substrate. Since such isolation is known to the art, it will not be discussed in detail here.
- the alignment of the base electrode with respect to the emitter region is determined by the position of the dielectric layer 31 , not by a difficult to control undercut etching operation.
- the position of the dielectric layer depends on the precision with which layers 29 and 30 shown in FIG. 7 are deposited and on the precision of the etching of these layers.
- the thickness of the layers in question can be precisely controlled.
- the RIE used to etch these layers is much more controllable than the wet etch used in prior art devices.
- the method of the present invention can also be utilized to fabricate a modified transistor in which a thin layer of emitter material is also connected to the base metalization.
- FIG. 12 is a cross-sectional view of a transistor 60 in which a thin emitter layer is also connected to the base metalization.
- Transistor 60 includes a thin layer of emitter material shown at 61 that connects to the base electrodes 62 .
- Transistor 60 is constructed by a manner that is analogous to that described above with reference to transistor 40 .
- the fabrication process for transistor 60 differs in that the etching of the emitter layer 25 shown in FIG. 5 is halted before the emitter layer is completely removed in the regions that are not protected by electrode 26 . This leaves a thin layer of emitter material of approximately 300 Angstroms over the surface of base layer 24 .
- the fabrication of the transistor then continues as described above with respect to transistor 40 through the deposition of the photoresist mask 33 shown in FIG. 10. At this point, the photoresist mask is used to define an etch window on the thin layer of emitter material. The material in this window is then etched through the layer of emitter material and terminates on the surface of the underlying base layer. This etching operation is preferably performed using a Chlorine-based RIE .
- Metal electrode 62 is then deposited through the mask, and the mask and any excess metal are then removed leaving transistor 60 as shown in FIG. 12.
- Transistor 60 is a significant improvement over transistor 40 .
- the thin emitter layer left on top of the base layer acts as a self-passivation layer for the base and has been shown to improve the transistor performance (i.e., current gain) and reliability.
- transistor 40 the external (lateral) separation between the emitter mesa and the base ohmic contact is exposed to process-induced damage, which degrades the transistor performance.
- the above-described embodiments utilize silicon nitride and silicon dioxide to provide the self-alignment structures utilized in the present invention.
- other materials can also be utilized.
- the materials must have the property that the layer closest to the emitter material can be selectively etched without destroying the layer farthest from the emitter layer.
- a different etch system must be selected to provide the appropriate specificity for each possible pair of materials.
- titanium oxide and tungsten oxide can be used in place of silicon dioxide. Both of these materials can be deposited by sputtering and etched in a high density plasma etcher with a mixture of Chlorine and Argon.
- Tantalum nitride may be used in place of silicon nitride and etched with an SF6 based RIE.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
- The present invention relates to semiconductor fabrication methods, and more particularly to heterojunction bipolar transistors.
- Vertical structure heterojunction bipolar transistors are often used in high-frequency applications such as microwave communication systems. Typically, a heterojunction bipolar transistor is constructed from a stack of semiconductor layers in which one of the layers is etched to form a mesa. Typically, it is the emitter that is constructed on the mesa, which overlies the base and collector layers in a vertical arrangement. The emitter ohmic contact is deposited on the top surface of this mesa. The base ohmic contacts are typically deposited adjacent to the mesa on the base layer. The performance of the device is critically dependent on the relative positioning of the emitter and base ohmic contacts.
- One prior art method for providing the required alignment utilizes a self-alignment scheme in which the metal layer in the emitter is used to align the metal layer of the base. In these schemes, the emitter metal layer is deposited on the surface of the emitter layer and the emitter layer is then etched using the emitter metal as a mask. The base metal is subsequently deposited using the emitter metal to align the base metal. These schemes frequently involve fabricating the emitter mesa with a wet-etchant that also undercuts the emitter metal and enables the base metal that is subsequently deposited to be self-aligned to the emitter. In addition, the undercut prevents the base metal from forming a bridge that shorts the base metal to the emitter. Unfortunately, the degree of undercutting of the emitter metal in a wet-etchant process is difficult to control. Since this undercut is critical to the device, such fabrication methods have a low device performance and yield due to poor emitter size control and emitter-base shorts.
- The present invention includes a transistor and method for making the same. The transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement. An emitter contact is patterned on the emitter layer, and the emitter layer is etched to form a mesa on an etched surface, the mesa having a top surface that includes a portion of the emitter layer and sides joining the top surface with the etched surface. A first protective layer is deposited over the emitter contact and the etched surface, and a second protective layer is deposited over the first protective layer. The first and second protective layers are removed over the portions thereof that overlie the etched surface, leaving a portion of the second protective layer on a portion of the sides of the mesa. The first protective layer is then etched with an etchant that removes the first protective layer faster than the second protective layer thereby undercutting a portion of the first protective layer on the sides of the mesa. A patterned metallic layer is then deposited on the etched surface at a position determined by the remaining portion of the second protective layer. The etched surface may be a portion of the base layer or a portion of the emitter layer depending on the desired transistor geometry. The protective layers are preferably dielectrics.
- FIGS.1-4 are cross-sectional views of a prior art heterojunction transistor at various stages in the fabrication process.
- FIGS.5-11 are cross-sectional views of a heterojunction transistor according to the present invention at various stages in the fabrication process.
- FIG. 12 is a cross-sectional view of a
transistor 60 in which a thin emitter layer is also connected to the base metalization. - The manner in which the present invention provides its advantages can be more easily understood with reference to FIGS.1-4, which are cross-sectional views of a prior art heterojunction transistor at various stages in the fabrication process. Referring to FIG. 1, the
emitter metal layer 14 is patterned on an n-type emitter layer 11. The emitter metal layer is then used as a mask for a wet etch process that etches throughemitter layer 11 to the top surface of a p-type base layer 12 which is deposited on acollector layer 13 as shown in FIG. 2. Thebase metal layer 16 is then deposited using theemitter metal layer 14 as a mask for the inner edge of the metal deposition as shown in FIG. 3. The emitter metal layer and most of the base metal layer are then covered with aphotoresist mask 17 to protect these structures during the etching of the base layer as shown in FIG. 4. The outer edge of the base metal layer remains exposed and determines the location of the emitter-base mesa area thus assuring the correct alignment of the emitter-base mesa. - The alignment of the emitter and base electrodes depends on the accuracy of the undercut. In addition, only
air gap 19 shown in FIG. 3 prevents the base metal from shorting to theemitter electrode 14 during the deposition ofbase metal layer 16. If the undercut is insufficient, a metal bridge can be formed betweenemitter electrode 14 andbase metal layer 16 thereby shorting the base to the emitter. As noted above, the wet-etch undercut of the emitter metal layer is difficult to control. Errors in this etch step lead to poor emitter size control and emitter-base shorts. Such errors reduce the device yield, and hence, increase the cost of the transistors. - The present invention overcomes these problems by eliminating the need for undercutting the emitter-metal layer via a wet-etchant process. Refer now to FIGS.5-11, which are cross-sectional views of a heterojunction transistor according to the present invention at various stages in the fabrication process. The patterning steps begin with a
substrate 21 that has acollector contact layer 22,collector layer 23,base layer 24, andemitter layer 25 as shown in FIG. 5. - It should be understood that the various layers may include a plurality of sub-layers. For example, in one embodiment of the present invention, the emitter layer is constructed from three sub-layers. The uppermost layer an n-doped InGaAs layer that is doped with Si to a level of 1×1019 atoms/cm3. This InGaAs layer is deposited on an n-doped InAlAs layer having a dopant concentration of 3×1017 atoms/cm3. The InAlAs layer is deposited on a super lattice layer having alternating undoped InGaAs and AlInAs layers. In this example, the base layer has two sub-layers, a p-doped InGaAs layer having a dopant concentration of 3×1019 C atoms/cm3, deposited on an undoped super lattice layer having alternating undoped InGaAs and AlInAs layers. The collector layer is constructed from a layer of n-doped InP having a dopant concentration of 5×1016 Si atoms/cm3 deposited on an n-doped InGaAs layer having a dopant concentration of 1×1019 Si atoms/cm3. The sub-collector contact layer is a single n-doped InP layer having a dopant concentration of 6×1018 Si atoms/cm3.
- The patterning process begins with the deposition of
metallic emitter electrode 26 by conventional deposition techniques. The emitter electrode is then used as a mask foretching emitter layer 25 to provide theemitter 28 of the transistor as shown in FIG. 6. The etching operation is preferably accomplished via a chlorine-based reactive ion etch (RIE) or a high-density plasma etch. - Next, a 300
nm layer 29 of silicon nitride and a 100nm layer 30 of silicon dioxide are deposited as shown in FIG. 7. These layers are preferably deposited by PECVD. - The portions of the silicon dioxide on the horizontal surfaces are then removed as shown in FIG. 8. This etching operation is preferably performed using a low pressure, high-bias anisotropic CF4-based RIE. The etch is monitored by laser reflectometry or a fixed time based on the etch rate of silicon dioxide to produce a minimal over-etch into the silicon nitride layer. After this etching operation, a
thin layer 31 of silicon dioxide remains on the vertical surfaces of the silicon nitride. - Refer now to FIG. 9. Next, the portions of the silicon nitride layer that are not protected by
silicon dioxide layer 31 are etched using a high pressure, low-bias isotropic SF6-based RIE. This etching operation removes silicon nitride at a rate that is greater than 8 times the rate at which silicon dioxide is removed. This operation undercuts the dielectric area as shown at 32. - Next, the base electrodes are deposited with the aid of a
photoresist mask 33 as shown in FIG. 10. Thebase contacts 37 are preferably deposited onbase layer 24 through theopenings 35 inphotoresist mask 33 via electron-beam evaporation. After the deposition of thebase contacts 37,photoresist mask 33 is removed leaving the transistor as shown in FIG. 11 at 40. The portion of the base layer shown at 39 is removed by an etching operation that isolates the various devices constructed on the substrate. Since such isolation is known to the art, it will not be discussed in detail here. - It should be noted that the alignment of the base electrode with respect to the emitter region is determined by the position of the
dielectric layer 31, not by a difficult to control undercut etching operation. The position of the dielectric layer depends on the precision with which layers 29 and 30 shown in FIG. 7 are deposited and on the precision of the etching of these layers. The thickness of the layers in question can be precisely controlled. Furthermore, the RIE used to etch these layers is much more controllable than the wet etch used in prior art devices. - The method of the present invention can also be utilized to fabricate a modified transistor in which a thin layer of emitter material is also connected to the base metalization. Refer now to FIG. 12, which is a cross-sectional view of a
transistor 60 in which a thin emitter layer is also connected to the base metalization. To simplify the following discussion, those elements oftransistor 60 that are the same as the elements oftransistor 40 shown in FIG. 11 have been given the same numeric designations as used in FIG. 11.Transistor 60 includes a thin layer of emitter material shown at 61 that connects to thebase electrodes 62. -
Transistor 60 is constructed by a manner that is analogous to that described above with reference totransistor 40. The fabrication process fortransistor 60 differs in that the etching of theemitter layer 25 shown in FIG. 5 is halted before the emitter layer is completely removed in the regions that are not protected byelectrode 26. This leaves a thin layer of emitter material of approximately 300 Angstroms over the surface ofbase layer 24. The fabrication of the transistor then continues as described above with respect totransistor 40 through the deposition of thephotoresist mask 33 shown in FIG. 10. At this point, the photoresist mask is used to define an etch window on the thin layer of emitter material. The material in this window is then etched through the layer of emitter material and terminates on the surface of the underlying base layer. This etching operation is preferably performed using a Chlorine-based RIE .Metal electrode 62 is then deposited through the mask, and the mask and any excess metal are then removed leavingtransistor 60 as shown in FIG. 12. -
Transistor 60 is a significant improvement overtransistor 40. The thin emitter layer left on top of the base layer acts as a self-passivation layer for the base and has been shown to improve the transistor performance (i.e., current gain) and reliability. Intransistor 40, the external (lateral) separation between the emitter mesa and the base ohmic contact is exposed to process-induced damage, which degrades the transistor performance. - The above-described embodiments utilize silicon nitride and silicon dioxide to provide the self-alignment structures utilized in the present invention. However, other materials can also be utilized. In general, the materials must have the property that the layer closest to the emitter material can be selectively etched without destroying the layer farthest from the emitter layer. In general, a different etch system must be selected to provide the appropriate specificity for each possible pair of materials.
- The above-described embodiments of the present invention have utilized specific materials for the protective layers. However, other materials can be utilized without departing from the teachings of the present invention. For example, titanium oxide and tungsten oxide can be used in place of silicon dioxide. Both of these materials can be deposited by sputtering and etched in a high density plasma etcher with a mixture of Chlorine and Argon. In addition, Tantalum nitride may be used in place of silicon nitride and etched with an SF6 based RIE.
- Various modifications to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims.
Claims (15)
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US20050035391A1 (en) * | 2003-08-14 | 2005-02-17 | Lee Deok Hyung | Multi-structured Si-fin and method of manufacture |
US20070048947A1 (en) * | 2003-08-14 | 2007-03-01 | Lee Deok H | Multi-structured Si-fin and method of manufacture |
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US6940149B1 (en) * | 2004-03-11 | 2005-09-06 | International Business Machines Corporation | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base |
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US6541346B2 (en) * | 2001-03-20 | 2003-04-01 | Roger J. Malik | Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process |
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Cited By (4)
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US20050035391A1 (en) * | 2003-08-14 | 2005-02-17 | Lee Deok Hyung | Multi-structured Si-fin and method of manufacture |
US7141856B2 (en) * | 2003-08-14 | 2006-11-28 | Samsung Electronics Co., Ltd. | Multi-structured Si-fin |
US20070048947A1 (en) * | 2003-08-14 | 2007-03-01 | Lee Deok H | Multi-structured Si-fin and method of manufacture |
US7534686B2 (en) | 2003-08-14 | 2009-05-19 | Samsung Electronics Co., Ltd. | Multi-structured Si-fin and method of manufacture |
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