US20040121537A1 - [mask rom structure and manufacturing method thereof] - Google Patents
[mask rom structure and manufacturing method thereof] Download PDFInfo
- Publication number
- US20040121537A1 US20040121537A1 US10/707,737 US70773704A US2004121537A1 US 20040121537 A1 US20040121537 A1 US 20040121537A1 US 70773704 A US70773704 A US 70773704A US 2004121537 A1 US2004121537 A1 US 2004121537A1
- Authority
- US
- United States
- Prior art keywords
- layer
- substrate
- dielectric layer
- mask rom
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/36—Gate programmed, e.g. different gate material or no gate
- H10B20/367—Gate dielectric programmed, e.g. different thickness
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/383—Channel doping programmed
Definitions
- mask read-only-memory comprises a plurality of bit lines (BL) and a plurality of word lines (WL) running across and above the bit lines.
- the channel region of each memory cell is located underneath the word lines and between two neighboring bit lines.
- programming involves planting ions into some of the memory cell channels so that a data bit “1” or “0” is stored in the memory cell.
- the process of planting ions into specified channel regions is often called a coding implant.
- the coding implant for a mask ROM is carried out in a few steps. First, a photoresist layer is formed over a substrate and the photoresist layer is patterned using a photomask so that the channel regions where an ion implantation is desired are exposed. Thereafter, using the patterned photoresist layer as a mask, ions are implanted into the exposed channel regions.
- the photomask that serves as a coding mask in the code implant process for producing the mask ROM may contain both isolated pattern regions and dense pattern regions. While transferring the pattern in a photo-exposure operation, average intensity of the light falling on the photoresist in the isolated pattern regions is stronger than average intensity of light falling on the dense pattern regions.
- critical dimensions of the exposed pattern may deviate from the standard values due to optical proximity effect (OPE) between the isolated pattern regions and the dense pattern regions.
- OPE optical proximity effect
- the coding mask in the coding implant process is misaligned or if the critical dimensions have some deviation, the coding ions originally intended for the channel regions may diffuse into the buried bit lines. When this happens, ion concentration within the buried bit lines may change leading to a reduction of current flow in the buried bit lines.
- one object of the present invention is to provide a mask read-only-memory (mask ROM) structure and its method of manufacture capable of preventing the diffusion of coding ions into buried bit lines in the mask ROM and the subsequent reduction of current flow in the buried bit lines.
- mask ROM mask read-only-memory
- a second object of this invention is to provide a mask read-only-memory structure and its method of manufacture capable of preventing critical dimension deviations in isolated pattern regions and dense pattern regions when a conventional coding implant process for programming the memory cells inside the mask ROM is deployed.
- a third object of this invention is to provide a mask read-only-memory structure and its method of manufacture capable of programming the mask ROM while employing neither the optical proximity method nor the phase shifting mask technique, thereby reducing production cost.
- the invention provides a mask read-only-memory (mask ROM) structure.
- the mask ROM includes a substrate, a buried bit line, a patterned stack layer, a gate oxide layer and a word line.
- the buried bit line is embedded inside the substrate.
- the stack layer covers a portion of the upper surface of the substrate.
- the stack layer comprises a first dielectric layer, a stopping layer and a second dielectric layer.
- the first dielectric layer and the second dielectric layer are, for example, silicon oxide layer.
- the stopping layer is, for example, a silicon nitride layer or a silicon oxynitride layer.
- the gate oxide layer covers a portion of the upper surface of the substrate.
- the word line runs over and across the buried bit line to form a plurality of coding memory cells.
- the ones having a stack layer thereon are at a logic state “0” while the ones having a gate oxide layer thereon are at a logic state “1”.
- the first line/distance pattern comprises a plurality of trenches running perpendicular to the buried bit line.
- the second dielectric layer and the stopping layer outside the first photoresist layer are removed to expose the first dielectric layer. Thereafter, the first photoresist layer is removed and a second photoresist layer is formed over the substrate.
- the second photoresist layer has a second line/distance pattern.
- the second line/distance pattern extends in a direction different from the first line/distance pattern.
- the second line/distance pattern extends in a direction perpendicular to the first line/distance pattern.
- the second line/distance pattern comprises a plurality of trenches parallel to the buried bit line.
- the second photoresist layer and the stopping layer as an etching mask, a portion of the second dielectric layer and the first dielectric layer are removed to expose the substrate and the stopping layer.
- a gate oxide layer is formed over the exposed substrate.
- a word line is formed over the substrate in a direction perpendicular to the buried bit line, thereby forming a plurality of coding cells.
- the ones having a stack layer thereon are at a logic state “0” while the ones having a gate oxide layer thereon are at a logic state “1”.
- the mask ROM structure according to this invention is programmed not by a coding implant process. Hence, the problem of having coding ions diffusing into the buried bit line resulting in a reduction in the current-carrying capacity in the bit line is entirely eliminated.
- the memory cells inside the mask ROM structure are programmed through patterning the stack layer.
- the non-uniformity of critical dimensions in the isolated pattern regions and dense pattern regions resulting from using a conventional method to form a coding mask layer is prevented.
- FIGS. 1A to 1 F are sectional perspective views showing the progression of steps for producing a mask ROM according to one preferred embodiment of this invention.
- FIGS. 1A to 1 F are sectional perspective views showing the progression of steps for producing a mask ROM according to one preferred embodiment of this invention.
- a stack layer 107 comprising a first dielectric layer 102 , a stopping layer 104 and a second dielectric layer 106 is formed over a substrate 100 to form a stack layer 107 .
- the stack layer 107 is formed, for example, by sequentially depositing a first dielectric material, a stopping layer material and a second dielectric material over the substrate 100 and patterning the second dielectric layer, the stopping layer and the first dielectric layer in photolithographic and etching processes.
- the first dielectric layer 102 and the second dielectric layer 106 are silicon oxide layers and the stopping layer 104 is a silicon nitride layer or a silicon oxynitride layer, for example.
- the first dielectric layer 102 preferably has a thickness between about 200 ⁇ to 800 ⁇
- the stopping layer 104 preferably has a thickness between about 20 ⁇ to 80 ⁇
- the second dielectric layer 106 preferably has a thickness between about 200 ⁇ to 800 ⁇ .
- the exposed second dielectric layer 106 and the stopping layer 104 are etched using the photoresist layer 109 as an etching mask to form a patterned second dielectric layer 106 a and a stopping layer 104 a as well as an opening pattern 112 that exposes the first dielectric layer 102 .
- the etching operation is a two-stage etching process that etches the second dielectric layer 106 and the stopping layer 104 separately.
- etching will stop at the stopping layer 104 and the first dielectric layer 102 in each of the two-stage etching operations.
- the second line/distance pattern extends in a direction perpendicular to the first line/distance pattern.
- the second line/distance pattern comprises a plurality of trenches 116 running parallel to the buried bit line 108 .
- the trenches 116 expose a portion of the first dielectric layer 102 , a portion of the stopping layer 104 a and a portion of the second dielectric layer 106 a.
- the exposed second dielectric layer 106 a and the first dielectric layer 102 in the trenches 116 is removed to form a patterned second dielectric layer 106 b and a patterned first dielectric layer 102 a.
- a T-shaped opening 118 that exposes the substrate 100 is also formed (as shown in FIG. 1E).
- FIG. 2 is a cross-sectional view of the mask ROM cell according to one preferred embodiment of this invention.
- the photoresist layer 114 is removed.
- a gate oxide layer 120 is formed on the exposed surface of the substrate 100 .
- the gate oxide layer 120 is formed, for example, by thermal oxidation.
- a word line 122 is formed over the substrate 100 in a direction perpendicular to the buried bit line 108 , thereby forming a plurality of coding cells.
- the ones having a three-layered stack 107 a including a first dielectric layer 102 a, a stopping layer 104 a and a second dielectric layer 106 b are in a logic state “0”.
- the other coding cells having no stack layer 107 a thereon but a gate oxide layer 120 thereon are in a logic state “1”.
- the mask ROM includes a substrate 100 , a buried bit line 108 , a patterned stack layer 107 a, a gate oxide layer 120 and a word line 122 .
- the buried bit line 108 is embedded inside the substrate 100 .
- the stack layer 107 a covers a portion of the upper surface of the substrate 100 .
- the stack layer 107 a comprises a first dielectric layer 102 a, a stopping layer 104 a and a second dielectric layer 106 b.
- the first dielectric layer 102 a and the second dielectric layer 106 b are made from silicon oxide material and the stopping layer 104 a is made from silicon nitride or silicon oxynitride material, for example.
- the gate oxide layer 120 covers only the portion of the upper surface of the substrate 100 without any first dielectric layer 102 a, stopping layer 104 a and second dielectric layer 106 b thereon.
- the word line 122 runs over the buried bit line 108 and forms a plurality of coding cells. Among these coding cells, the ones having a stack layer 107 a thereon are at a logic state “0” while the ones having a gate oxide layer 120 thereon are at a logic state “1”.
- the mask ROM fabricated according to this invention has a three-layered structure including the second dielectric layer 106 b, the stopping layer 104 a and the first dielectric layer 102 a as well as a two-layered structure including the stopping layer 104 a and the first dielectric layer 102 a over the surface of the substrate 100 between two neighboring word lines 122 .
- the memory cells inside the mask ROM structure are programmed through patterning the stack layer instead of a conventional coding implant process.
- the non-uniformity of critical dimensions in the isolated pattern regions and dense pattern regions resulting from using a conventionally manufactured coding mask is prevented.
- the mask ROM structure according to this invention is not programmed by a conventional coding implant process, the problem of having coding ions diffusing into the buried bit line resulting in a reduction in the current-carrying capacity in the bit line is eliminated.
- a pair of masks each having a different line/distance pattern is used to pattern the stack layer so that openings having a dimension as small as 0.12 ⁇ m are easily formed in the stack layer.
- the mask ROM structure according to this invention is manufactured without using either the optical proximity correction method or the phase shift mask technique.
- the cost of producing the mask ROM is lowered considerably.
Landscapes
- Semiconductor Memories (AREA)
Abstract
A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion of the upper surface of the substrate. The stack layer includes a first dielectric layer, a stopping layer and a second dielectric layer. A gate oxide layer covers a portion of the upper surface of the substrate. A word line runs across the buried bit line to form a plurality of coding cells. The memory cells having a stack layer thereon are at a logic state “0” while the memory cells having a gate oxide layer thereon are at a logic state “1”.
Description
- This application is a divisional application of, and claims the priority benefit of, U.S. application Ser. No. 10/065,431 filed Oct. 17, 2002.
- 1. Field of Invention
- The present invention relates to a memory structure and a manufacturing method thereof. More particularly, the present invention relates to a mask read-only-memory (mask ROM) structure and its method of manufacture.
- 2. Description of Related Art
- Most mask read-only-memory (mask ROM) comprises a plurality of bit lines (BL) and a plurality of word lines (WL) running across and above the bit lines. The channel region of each memory cell is located underneath the word lines and between two neighboring bit lines. For some mask ROM, programming involves planting ions into some of the memory cell channels so that a data bit “1” or “0” is stored in the memory cell. The process of planting ions into specified channel regions is often called a coding implant.
- In general, the coding implant for a mask ROM is carried out in a few steps. First, a photoresist layer is formed over a substrate and the photoresist layer is patterned using a photomask so that the channel regions where an ion implantation is desired are exposed. Thereafter, using the patterned photoresist layer as a mask, ions are implanted into the exposed channel regions. However, the photomask that serves as a coding mask in the code implant process for producing the mask ROM may contain both isolated pattern regions and dense pattern regions. While transferring the pattern in a photo-exposure operation, average intensity of the light falling on the photoresist in the isolated pattern regions is stronger than average intensity of light falling on the dense pattern regions. Consequently, critical dimensions of the exposed pattern may deviate from the standard values due to optical proximity effect (OPE) between the isolated pattern regions and the dense pattern regions. Thus, when ions are implanted into the designated channel regions to program the mask ROM, misalignment of the implanted ions may occur leading to possible data error in some ROM cells. As a result, operating properties of each ROM cell may vary and overall reliability of the mask ROM may drop.
- To minimize the non-uniformity of critical dimensions after pattern exposure due to the presence of both dense pattern regions and isolated pattern regions in the coding mask, an optical proximity correction (OPC) method or a phase shift mask (PSM) technique is often deployed. In the optical proximity correction (OPC) method, a specially designed auxiliary pattern is introduced to eliminate critical dimension deviation caused by proximity effect. However, to implement the correction, a photomask with specially designed pattern must be produced. Since the photomask is expensive and difficult to make, overall production cost is increased. Moreover, debugging the defects in the pattern after fabrication is extremely difficult.
- Furthermore, if the coding mask in the coding implant process is misaligned or if the critical dimensions have some deviation, the coding ions originally intended for the channel regions may diffuse into the buried bit lines. When this happens, ion concentration within the buried bit lines may change leading to a reduction of current flow in the buried bit lines.
- Accordingly, one object of the present invention is to provide a mask read-only-memory (mask ROM) structure and its method of manufacture capable of preventing the diffusion of coding ions into buried bit lines in the mask ROM and the subsequent reduction of current flow in the buried bit lines.
- A second object of this invention is to provide a mask read-only-memory structure and its method of manufacture capable of preventing critical dimension deviations in isolated pattern regions and dense pattern regions when a conventional coding implant process for programming the memory cells inside the mask ROM is deployed.
- A third object of this invention is to provide a mask read-only-memory structure and its method of manufacture capable of programming the mask ROM while employing neither the optical proximity method nor the phase shifting mask technique, thereby reducing production cost.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a mask read-only-memory (mask ROM) structure. The mask ROM includes a substrate, a buried bit line, a patterned stack layer, a gate oxide layer and a word line. The buried bit line is embedded inside the substrate. The stack layer covers a portion of the upper surface of the substrate. The stack layer comprises a first dielectric layer, a stopping layer and a second dielectric layer. In this invention, the first dielectric layer and the second dielectric layer are, for example, silicon oxide layer. The stopping layer is, for example, a silicon nitride layer or a silicon oxynitride layer. The gate oxide layer covers a portion of the upper surface of the substrate. The word line runs over and across the buried bit line to form a plurality of coding memory cells. Among the coding cells, the ones having a stack layer thereon are at a logic state “0” while the ones having a gate oxide layer thereon are at a logic state “1”.
- This invention also provides a method of manufacturing a mask read-only-memory (mask ROM). A first dielectric layer, a stopping layer and a second dielectric layer are sequentially formed over a substrate to form a stack layer. The first dielectric layer and the second dielectric layer are silicon oxide layers and the stopping layer is a silicon nitride or a silicon oxynitride layer, for example. Using the stack layer as an implant mask, an ion implantation is carried out to form a buried bit line in the exposed substrate. A first photoresist layer is formed over the substrate. The first photoresist layer has a first line/distance pattern thereon. In this invention, the first line/distance pattern comprises a plurality of trenches running perpendicular to the buried bit line. The second dielectric layer and the stopping layer outside the first photoresist layer are removed to expose the first dielectric layer. Thereafter, the first photoresist layer is removed and a second photoresist layer is formed over the substrate. The second photoresist layer has a second line/distance pattern. The second line/distance pattern extends in a direction different from the first line/distance pattern. In this invention, the second line/distance pattern extends in a direction perpendicular to the first line/distance pattern. The second line/distance pattern comprises a plurality of trenches parallel to the buried bit line. Using the second photoresist layer and the stopping layer as an etching mask, a portion of the second dielectric layer and the first dielectric layer are removed to expose the substrate and the stopping layer. A gate oxide layer is formed over the exposed substrate. A word line is formed over the substrate in a direction perpendicular to the buried bit line, thereby forming a plurality of coding cells. Among the coding cells, the ones having a stack layer thereon are at a logic state “0” while the ones having a gate oxide layer thereon are at a logic state “1”.
- The mask ROM structure according to this invention is programmed not by a coding implant process. Hence, the problem of having coding ions diffusing into the buried bit line resulting in a reduction in the current-carrying capacity in the bit line is entirely eliminated.
- In this invention, the memory cells inside the mask ROM structure are programmed through patterning the stack layer. Thus, the non-uniformity of critical dimensions in the isolated pattern regions and dense pattern regions resulting from using a conventional method to form a coding mask layer is prevented.
- The mask ROM structure according to this invention is manufactured without using either the optical proximity correction method or the phase shift mask technique. Hence, cost of producing the mask ROM is lowered considerably.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
- FIGS. 1A to1F are sectional perspective views showing the progression of steps for producing a mask ROM according to one preferred embodiment of this invention.
- FIG. 2 is a cross-sectional view of a mask ROM cell according to one preferred embodiment of this invention.
- Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
- FIGS. 1A to1F are sectional perspective views showing the progression of steps for producing a mask ROM according to one preferred embodiment of this invention. As shown in FIG. 1A, a stack layer 107 comprising a first
dielectric layer 102, a stopping layer 104 and asecond dielectric layer 106 is formed over asubstrate 100 to form a stack layer 107. The stack layer 107 is formed, for example, by sequentially depositing a first dielectric material, a stopping layer material and a second dielectric material over thesubstrate 100 and patterning the second dielectric layer, the stopping layer and the first dielectric layer in photolithographic and etching processes. In this embodiment, thefirst dielectric layer 102 and thesecond dielectric layer 106 are silicon oxide layers and the stopping layer 104 is a silicon nitride layer or a silicon oxynitride layer, for example. Furthermore, thefirst dielectric layer 102 preferably has a thickness between about 200 Å to 800 Å, the stopping layer 104 preferably has a thickness between about 20 Å to 80 Å and thesecond dielectric layer 106 preferably has a thickness between about 200 Å to 800 Å. Thereafter, using the stack layer 107 as an implant mask, an ion implantation is carried out to form a buriedbit line 108 in the substrate 10 outside the stack layer 107. - As shown in FIG. 1B, a
photoresist layer 109 is formed over thesubstrate 100 covering the stack layer 107. Aphotomask 200 is placed over thephotoresist layer 109. Thephotomask 200 includes a first line/distance pattern. Here, the first line/distance pattern on thephotomask 200 comprises a plurality ofrectangular opening patterns 202. A photolithographic process is conducted to transfer the pattern on thephotomask 200 to thephotoresist layer 109, thereby forming a first line/distance pattern in thephotoresist layer 109. In this embodiment, the first line/distance pattern comprises a plurality oftrenches 110 running in a direction perpendicular to the buriedbit line 108 and thetrenches 110 expose a portion of the stack layer 107. - As shown in FIG. 1C, the exposed
second dielectric layer 106 and the stopping layer 104 are etched using thephotoresist layer 109 as an etching mask to form a patterned seconddielectric layer 106 a and a stoppinglayer 104 a as well as anopening pattern 112 that exposes thefirst dielectric layer 102. The etching operation is a two-stage etching process that etches thesecond dielectric layer 106 and the stopping layer 104 separately. Since the etching rate between the stopping layer 104 and thesecond dielectric layer 106 are different and the etching rate between thefirst dielectric layer 102 and the stopping layer 104 are also different, etching will stop at the stopping layer 104 and thefirst dielectric layer 102 in each of the two-stage etching operations. - As shown in FIG. 1D, the
photoresist layer 109 is removed. Anotherphotoresist layer 114 is formed over thesubstrate 100. Anotherphotomask 300 is placed over thephotoresist layer 114. Thephotomask 300 has a second line/distance pattern thereon comprising a plurality ofrectangular opening patterns 302. A photolithographic process is conducted to transfer the pattern on thephotomask 300 to thephotoresist layer 114, thereby forming a second line/distance pattern in thephotoresist layer 114. The second line/distance pattern extends in a direction that differs from the first line/distance pattern. In this embodiment, the second line/distance pattern extends in a direction perpendicular to the first line/distance pattern. The second line/distance pattern comprises a plurality oftrenches 116 running parallel to the buriedbit line 108. Thetrenches 116 expose a portion of thefirst dielectric layer 102, a portion of the stoppinglayer 104 a and a portion of thesecond dielectric layer 106 a. - Using the
photoresist layer 114 and the stoppinglayer 104 a as an etching mask, the exposedsecond dielectric layer 106 a and thefirst dielectric layer 102 in thetrenches 116 is removed to form a patterned seconddielectric layer 106 b and a patterned firstdielectric layer 102 a. A T-shapedopening 118 that exposes thesubstrate 100 is also formed (as shown in FIG. 1E). - Refer next to FIGS. 1F and 2. FIG. 2 is a cross-sectional view of the mask ROM cell according to one preferred embodiment of this invention. The
photoresist layer 114 is removed. Agate oxide layer 120 is formed on the exposed surface of thesubstrate 100. Thegate oxide layer 120 is formed, for example, by thermal oxidation. Thereafter, aword line 122 is formed over thesubstrate 100 in a direction perpendicular to the buriedbit line 108, thereby forming a plurality of coding cells. Among the coding cells, the ones having a three-layered stack 107 a including a firstdielectric layer 102 a, a stoppinglayer 104 a and asecond dielectric layer 106 b are in a logic state “0”. The other coding cells having no stack layer 107 a thereon but agate oxide layer 120 thereon are in a logic state “1”. - In this invention, the mask ROM includes a
substrate 100, a buriedbit line 108, a patterned stack layer 107 a, agate oxide layer 120 and aword line 122. The buriedbit line 108 is embedded inside thesubstrate 100. The stack layer 107 a covers a portion of the upper surface of thesubstrate 100. The stack layer 107 a comprises a firstdielectric layer 102 a, a stoppinglayer 104 a and asecond dielectric layer 106 b. In this embodiment, thefirst dielectric layer 102 a and thesecond dielectric layer 106 b are made from silicon oxide material and the stoppinglayer 104 a is made from silicon nitride or silicon oxynitride material, for example. In addition, thegate oxide layer 120 covers only the portion of the upper surface of thesubstrate 100 without any firstdielectric layer 102 a, stoppinglayer 104 a and seconddielectric layer 106 b thereon. Theword line 122 runs over the buriedbit line 108 and forms a plurality of coding cells. Among these coding cells, the ones having a stack layer 107 a thereon are at a logic state “0” while the ones having agate oxide layer 120 thereon are at a logic state “1”. - Note that the mask ROM fabricated according to this invention has a three-layered structure including the
second dielectric layer 106 b, the stoppinglayer 104 a and thefirst dielectric layer 102 a as well as a two-layered structure including the stoppinglayer 104 a and thefirst dielectric layer 102 a over the surface of thesubstrate 100 between two neighboring word lines 122. - In this invention, the memory cells inside the mask ROM structure are programmed through patterning the stack layer instead of a conventional coding implant process. Thus, the non-uniformity of critical dimensions in the isolated pattern regions and dense pattern regions resulting from using a conventionally manufactured coding mask is prevented.
- Since the mask ROM structure according to this invention is not programmed by a conventional coding implant process, the problem of having coding ions diffusing into the buried bit line resulting in a reduction in the current-carrying capacity in the bit line is eliminated.
- Moreover, a pair of masks each having a different line/distance pattern is used to pattern the stack layer so that openings having a dimension as small as 0.12 μm are easily formed in the stack layer.
- In addition, the mask ROM structure according to this invention is manufactured without using either the optical proximity correction method or the phase shift mask technique. Thus, the cost of producing the mask ROM is lowered considerably.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (6)
1. A mask read-only-memory (ROM) structure, comprising:
a substrate;
a buried bit line embedded inside the substrate;
a patterned stack layer covering a portion of the upper surface of the substrate, wherein the stack layer comprises a first dielectric layer, a stopping layer and a second dielectric layer;
a gate oxide layer covering a portion of the upper surface of the substrate; and
a word line crossing over the buried bit line to form a plurality of coding cells, wherein the coding cells having a stack layer thereon are at a first data state while the coding cells having a gate oxide layer thereon are at a second data state.
2. The mask ROM of claim 1 , wherein the stack layer includes a first silicon oxide layer, a silicon oxynitride layer and a second silicon oxide layer stacked on top of each other.
3. The mask ROM of claim 1 , wherein the stack layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked on top of each other.
4. The mask ROM of claim 1 , wherein the first dielectric layer has a thickness between about 200 Å to 800 Å.
5. The mask ROM of claim 1 , wherein the stopping layer has a thickness between about 20 Å to 80 Å.
6. The mask ROM of claim 1 , wherein the second dielectric layer has a thickness between about 200 Å to 800 Å.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/707,737 US20040121537A1 (en) | 2002-10-17 | 2004-01-08 | [mask rom structure and manufacturing method thereof] |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/065,431 US6720210B1 (en) | 2002-10-17 | 2002-10-17 | Mask ROM structure and manufacturing method thereof |
US10/707,737 US20040121537A1 (en) | 2002-10-17 | 2004-01-08 | [mask rom structure and manufacturing method thereof] |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/065,431 Division US6720210B1 (en) | 2002-10-17 | 2002-10-17 | Mask ROM structure and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040121537A1 true US20040121537A1 (en) | 2004-06-24 |
Family
ID=32041317
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/065,431 Expired - Lifetime US6720210B1 (en) | 2002-10-17 | 2002-10-17 | Mask ROM structure and manufacturing method thereof |
US10/707,737 Abandoned US20040121537A1 (en) | 2002-10-17 | 2004-01-08 | [mask rom structure and manufacturing method thereof] |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/065,431 Expired - Lifetime US6720210B1 (en) | 2002-10-17 | 2002-10-17 | Mask ROM structure and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
US (2) | US6720210B1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7084014B2 (en) * | 2003-10-07 | 2006-08-01 | Endicott Interconnect Technologies, Inc. | Method of making circuitized substrate |
JP5110247B2 (en) * | 2006-07-31 | 2012-12-26 | ミツミ電機株式会社 | Semiconductor integrated circuit device |
JP2008033724A (en) * | 2006-07-31 | 2008-02-14 | Mitsumi Electric Co Ltd | Manufacturing method of single-chip semiconductor integrated circuit device, program-debugging method, and manufacturing method of microcontroller |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5576573A (en) * | 1995-05-31 | 1996-11-19 | United Microelectronics Corporation | Stacked CVD oxide architecture multi-state memory cell for mask read-only memories |
US5824585A (en) * | 1997-01-10 | 1998-10-20 | United Microelectronics Corp | Semiconductor read-only memory device and method of fabricating the same |
US5895241A (en) * | 1997-03-28 | 1999-04-20 | Lu; Tao Cheng | Method for fabricating a cell structure for mask ROM |
US20010035589A1 (en) * | 1997-12-30 | 2001-11-01 | Jin Soo Kim | Mask rom cell and method of fabricating the same |
US6417548B1 (en) * | 1999-07-19 | 2002-07-09 | United Microelectronics Corp. | Variable work function transistor high density mask ROM |
US20030205770A1 (en) * | 2002-05-06 | 2003-11-06 | Yao-Wen Chang | Mask read only memory device and fabrication method thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5837426A (en) * | 1996-07-29 | 1998-11-17 | United Microelectronics Corp. | Photolithographic process for mask programming of read-only memory devices |
TW340966B (en) * | 1997-04-07 | 1998-09-21 | United Microelectronics Corp | The salicide process for mask ROM |
KR100297711B1 (en) * | 1998-07-20 | 2001-08-07 | 윤종용 | Method for fabricating mask ROM |
US6420237B1 (en) * | 2001-10-22 | 2002-07-16 | Macronix International Co. Ltd. | Method of manufacturing twin bit cell flash memory device |
-
2002
- 2002-10-17 US US10/065,431 patent/US6720210B1/en not_active Expired - Lifetime
-
2004
- 2004-01-08 US US10/707,737 patent/US20040121537A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5576573A (en) * | 1995-05-31 | 1996-11-19 | United Microelectronics Corporation | Stacked CVD oxide architecture multi-state memory cell for mask read-only memories |
US5824585A (en) * | 1997-01-10 | 1998-10-20 | United Microelectronics Corp | Semiconductor read-only memory device and method of fabricating the same |
US5895241A (en) * | 1997-03-28 | 1999-04-20 | Lu; Tao Cheng | Method for fabricating a cell structure for mask ROM |
US20010035589A1 (en) * | 1997-12-30 | 2001-11-01 | Jin Soo Kim | Mask rom cell and method of fabricating the same |
US6417548B1 (en) * | 1999-07-19 | 2002-07-09 | United Microelectronics Corp. | Variable work function transistor high density mask ROM |
US20030205770A1 (en) * | 2002-05-06 | 2003-11-06 | Yao-Wen Chang | Mask read only memory device and fabrication method thereof |
Also Published As
Publication number | Publication date |
---|---|
US6720210B1 (en) | 2004-04-13 |
US20040077131A1 (en) | 2004-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5946563A (en) | Semiconductor device and method of manufacturing the same | |
US7422937B2 (en) | Semiconductor device and manufacturing method thereof | |
US7214580B2 (en) | Semiconductor device and method of manufacturing the same | |
KR100247862B1 (en) | Semiconductor device and method for manufacturing the same | |
US6949801B2 (en) | Dual trench isolation using single critical lithographic patterning | |
KR100694973B1 (en) | method for fabricating flash memory device | |
US5966602A (en) | Nonvolatile semiconductor memory and fabricating method thereof | |
US6806535B2 (en) | Non-volatile memory and fabricating method thereof | |
US7075182B2 (en) | Semiconductor device | |
JP2006156657A (en) | Method of manufacturing semiconductor device and semiconductor memory device | |
US20050258498A1 (en) | Semiconductor device and method for fabricating the same | |
KR100564578B1 (en) | Forming method for self-aligned contact pads of non-vertical semiconductor memory device | |
US6022779A (en) | Method of forming mask ROM | |
US6150281A (en) | Method for manufacturing contact hole using an etching barrier layer pattern | |
US6720210B1 (en) | Mask ROM structure and manufacturing method thereof | |
CN100527353C (en) | Method for manufacturing semiconductor device | |
KR100341159B1 (en) | Method of manufacturing semiconductor memory device using two etching patterns | |
KR100438403B1 (en) | Method for manufacturing a flat cell memory device | |
US20030235789A1 (en) | Photolithography process for Mask ROM coding | |
US20040115887A1 (en) | Non-volatile memory structure and method of fabricating the same | |
US20030235790A1 (en) | Method for forming opening and application thereof | |
KR100524460B1 (en) | Manufacturing Method of Flash Memory Device_ | |
US6916713B2 (en) | Code implantation process | |
KR0167607B1 (en) | Method of making gate electrode of rom | |
US6713354B1 (en) | Coding method for mask ROM |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |