US20040072451A1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
- Publication number
- US20040072451A1 US20040072451A1 US10/310,867 US31086702A US2004072451A1 US 20040072451 A1 US20040072451 A1 US 20040072451A1 US 31086702 A US31086702 A US 31086702A US 2004072451 A1 US2004072451 A1 US 2004072451A1
- Authority
- US
- United States
- Prior art keywords
- oxide film
- pad
- film
- nitride film
- pad nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 30
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000006731 degradation reaction Methods 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000008878 coupling Effects 0.000 abstract description 2
- 238000010168 coupling process Methods 0.000 abstract description 2
- 238000005859 coupling reaction Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 210000002445 nipple Anatomy 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910007258 Si2H4 Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
Definitions
- the invention relates generally to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of manufacturing a semiconductor device capable of improving a characteristic of the device and reducing the manufacture cost, by preventing formation of a moat generating around the top comer of a trench having a STI (shallow trench isolation) structure.
- STI shallow trench isolation
- the semiconductor substrate is defined into an active region and a field region.
- a semiconductor device is formed in the active region and a device isolation film for isolation the devices is formed in the field region.
- a method for forming the device isolation film of the semiconductor device includes one by which a trench of a STI (shallow trench isolation) structure is formed and the device isolation film for isolating the devices is them.
- the method by which the trench of the STI structure is formed to isolate the devices will be described in short.
- a silicon substrate in the field region is etched by a depth of about 3500 ⁇ to form the trench.
- a high-density plasma (HDP) oxide film is then deposited.
- the oxide film is polished by a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- FIG. 1 is a TEM (transmission electron microscope) photography of the semiconductor device in which the device isolation film is formed according to a prior art.
- a moat (see portion ‘M’ in FIG. 1) is formed at a field oxide film where the active region and the field region meet by means of a pre-cleaning process for forming a gate oxide film, a subsequent cleaning process and an etch process for the oxide film. Due to this, a parasitic effect, degradation in gate oxide integrity (GOI), an inverse narrow effect and a sub-threshold hump phenomenon occur.
- GOI gate oxide integrity
- sub-threshold hump phenomenon occur.
- the gate oxide film at the top comer of the trench is made thin by the moat of the HDP oxide film. This may cause a breakdown when the voltage is applied to the device.
- the present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing generation of a moat, in such a way that a thickness of a pad oxide film is formed by minimum to an extent that stress between a semiconductor substrate and a pad nitride film is mitigated and before a HDP oxide film is deposited, a portion of the pad nitride film is etched to compensate for a portion recessed in a cleaning process.
- the method of manufacturing a semiconductor device is characterized in that it comprises the steps of sequentially forming a pad oxide film, a pad nitride film and a screen oxide film on a semiconductor substrate in which an active region and a field region are defined, removing the screen oxide film and the pad nitride film formed in the field region, performing a wet etch process to remove the pad nitride film exposed at the boundary of the active region and the field region, in a lateral direction by a given width, performing a dry etch process using the screen oxide film and an etch mask to remove portions of the pad oxide film and the semiconductor substrate formed in the field region, thus forming a trench, removing the screen oxide film and the pad nitride film in the lateral direction by a given width and simultaneously removing the exposed portion of the pad oxide film, performing an oxidization process to form a rounding oxide film in the exposed portion of the semiconductor substrate, depositing a field oxide film of
- FIG. 1 is a TEM (transmission electron microscope) photography of a semiconductor device in which a device isolation film is formed according to a prior art
- FIG. 2A through FIG. 2K are cross sectional views of semiconductor devices for explaining a method of the semiconductor device capable of preventing generation of a moat at the boundary of an active region and a field region according to a preferred embodiment of the present invention.
- FIG. 3 is a TEM photography of the semiconductor device in which the device isolation film is formed according to the present invention.
- FIG. 2A through FIG. 2K are cross sectional views of semiconductor devices for explaining a method of the semiconductor device capable of preventing generation of a moat at the boundary of an active region and a field region according to a preferred embodiment of the present invention.
- a pad oxide film 12 , a pad nitride film 14 and a screen oxide film 16 are sequentially formed on a semiconductor substrate 10 in which an active region ‘A’ and a field region ‘B’ are defined.
- the pad oxide film 12 is formed to have a thickness that can serve as a barrier for mitigating stress between the semiconductor substrate 10 and the pad nitride film 14 and for protecting the underlying semiconductor substrate 10 when the pad nitride film 14 is etched.
- the pad oxide film 12 may be thinly formed in thickness of 30 through 150 ⁇ , more preferably about 33 through 75 ⁇ . Thereby, it is possible to reduce, by maximum, time taken to perform a subsequent process for removing the pad oxide film 12 .
- the pad oxide film 12 may be formed using a PE-TEOS (plasma enhanced tetra ethyl ortho silicate) film, a TEOS (tetra ethyl ortho silicate) film, an USG (undoped silicate glass) film, a HDP (high density plasma) film, or the like.
- PE-TEOS plasma enhanced tetra ethyl ortho silicate
- TEOS tetra ethyl ortho silicate
- USG undoped silicate glass
- HDP high density plasma
- the pad nitride film 14 is formed in thickness of 500 through 1500 ⁇ so that it can serve as a stop layer in a subsequent CMP process. At this time, the pad nitride film 14 is deposited using any one of a SiH 4 +NH 3 gas, a Si 2 H 4 +NH 3 gas and a DCS (Dichlosilane; SiH 2 Cl 2 )+NH 3 gas by means of a LP-CVD (low-pressure chemical vapor deposition) method or a PE-CVD (plasma enhanced CVD) method. However, it should be noted that the present invention is not limited to the above description.
- the pad nitride film 14 may be formed using a nitride film having a high etch selective ratio with the pad oxide film 12 formed on its bottom and the screen oxide film 16 formed on its top.
- the screen oxide film 16 is formed in thickness of 100 through 500 ⁇ that can prevent etching of the underlying pad nitride film 14 when a trench is formed and can serve as a mask for forming the trench.
- the screen oxide film 16 may be formed using the PE-TEOS film, the TEOS film, the USG film, the HDP film, etc. However, it should be noted that the screen oxide film is not limited to the above films.
- the pad nitride film 14 formed below the screen oxide film 16 and the oxide film having a high etch selective ratio may be used as the screen oxide film 16 .
- a photoresist film is applied on the screen oxide film 16 .
- a photoresist pattern 18 through the field region ‘B’ is exposed is formed by means of a photolithography process using an exposure mask.
- the screen oxide film 16 and the pad nitride film 14 are sequentially removed by an etch process using the photoresist pattern 18 through which the field region ‘B’ is exposed as an etch mask.
- the photoresist pattern 18 used as the etch mask is then removed.
- ‘lateral direction’ to be described later indicates toward the active region ‘A’ direction at a boundary between the active region ‘A’ and the field region ‘B’.
- the lateral direction could be a positive X-direction or a negative X-direction along the active region ‘A’ and the field region ‘B’ defined in the semiconductor substrate 10 .
- a portion of the pad nitride film 14 which is exposed between the active region ‘A’ and the field region ‘B’ and located between the screen oxide film 16 on the active region ‘A’ and the pad oxide film 12 , is removed by a wet etch process. (see portion ‘K’ in FIG. 2D).
- the exposed portion of the pad nitride film 14 is removed in a lateral direction by the amount of the field oxide film (HDP oxide film) removed by an etch process for forming a subsequent gate oxide film.
- the exposed sidewalls of the pad nitride film 14 is etched toward the active region ‘A’ direction by performing the wet etch process having a high etch selective ratio with the oxide film.
- An etch condition of the wet etch process is as follows. Polymer that may be formed at the sidewalls of the pad nitride film 14 is removed in a solution in which the ratio of hydrofluoric acid (HF):H 2 O is 1:99. The pad nitride film 14 is removed by a thickness of about 200 through 500 ⁇ by performing the wet etch process using a phosphoric acid (H 3 PO 4 ) solution at a temperature of 110 through 130° C. for 300 through 750 second. At this time, the pad oxide film 12 having a high etch selective ratio with the pad nitride film 14 serves as an etch barrier to prevent damage of the underlying semiconductor substrate 10 .
- a recessed shape (see portion ‘K’ in FIG. 2D) is formed below the screen oxide film 16 .
- the pad oxide film 12 exposed by the field region ‘B’ defined by the photoresist pattern 18 is further exposed in the active region ‘A’ direction.
- the width of the pad oxide film 12 by the wet etch process is more exposed by about 400 through 1000 ⁇ being the width of the removed pad nitride film 14 .
- a field oxide film to be removed in a given thickness can be supplemented in the field region ‘B’ direction in a subsequent etch process of a gate oxide film.
- the total width ‘H2’ of the exposed pad oxide film 12 is about 1400 through 2000 ⁇ , which is same to the sum (H1+L1+L2) of the width ‘H1’ exposed by the photoresist pattern 18 and the width ‘L1’ and ‘L2’ exposed by etching of the pad nitride film 14 .
- portions of the pad oxide film 12 and the semiconductor substrate 10 are removed by a dry etch process using the screen oxide film 16 as an etch mask.
- the pad oxide film 12 in the field region ‘B’ exposed by the screen oxide film 16 is removed using the straightness of the dry etch process, and the portion of the semiconductor substrate 10 exposed by removing the pad oxide film 12 is removed to a trench 30 .
- the pad oxide film 12 on the active region ‘A’ which is exposed by removing the portion of the pad nitride film 14 below the screen oxide film 16 , is not removed but only the pad oxide film 12 on the field region ‘B’ is removed.
- the trench 30 is formed by etching the semiconductor substrate 10 by 3500 through 4000 ⁇ from the upper surface of the substrate 10 .
- the screen oxide film 16 used as the etch mask for forming the trench 30 is removed.
- the etch conditions are not limited to the mentioned conditions.
- the screen oxide film 16 on the pad nitride film 14 may be removed by means of various etch methods such as an etch method using plasma, a dry etch method, or the like. At this time, a portion of the semiconductor substrate 10 on the active region ‘A’ is also exposed by removing the exposed portion of the pad oxide film 12 below the pad nitride film 14 .
- a rounding oxide film 20 is formed on the semiconductor substrate 10 by means of an oxidization process.
- the rounding oxide film 20 having a thickness of 90 through 110 ⁇ is formed within the trench 30 , at the upper corner portion of the trench 30 and the exposed portion of the semiconductor substrate 10 on an upper portion of the active region ‘A’, by means of a dry oxidization process at a temperature of 950 through 1150° C.
- the upper corner portion of the trench 30 has a rounding shape (see portion ‘R’ in FIG. 2G).
- the oxidization conditions are not limited to the mentioned oxidization process. Instead, various oxidization methods may be used.
- the upper corner portion of the trench 30 has the round shape (see portion ‘R’ in FIG. 2G) through the oxidization process.
- a high-density plasma (HDP) oxide film 22 is deposited on the entire structure to bury the trench 30 .
- a high-temperature annealing process is then performed.
- the HDP oxide film 22 having a thickness of 4000 through 6000 ⁇ is buried to bury the trench 30 .
- the annealing process is performed at a temperature of 900 through 1000° C. for 25 through 35 minutes.
- the HDP oxide film 22 on the pad nitride film 14 and a portion of the pad nitride film 14 are moved by a CMP process. At this time, the HDP oxide film 22 is left in thickness of about 400 through 600 ⁇ from the surface of the semiconductor substrate 10 on the active region ‘A’. Also, the height of the HDP oxide film 22 is adjusted using the pad nitride film 14 as a stop layer of the CMP process.
- the pad nitride film 14 on an upper side of the active region ‘A’ is removed to expose the pad oxide film 12 .
- the HDP oxide film 22 on upper side of the trench 30 has a nipple shape that is protruded by about 200 through 500 ⁇ in the active region ‘A’ direction at both sides of the field region ‘B’ as well as the field region ‘B’ and protruded by about 400 through 600 ⁇ from the semiconductor substrate 10 .
- the critical dimension of the active region ‘A’ is reduced due to the above shape.
- a target critical dimension can be obtained by removing the HDP oxide film 22 on an upper side of the active region ‘A’ by the etch process for forming a subsequent gate oxide film.
- An ion implantation for forming a well (not shown) is performed to form the well.
- a passivation oxide film (not shown) for preventing damage of the underlying semiconductor substrate 10 due to ion implantation without removing the exposed pad oxide film 12 and protecting the semiconductor substrate 10 after the pad oxide film 12 is removed is deposited in order to prevent damage of the surface of the semiconductor substrate 10 when the ion implantation process for forming the well is performed.
- the pad oxide film 12 is removed to expose the semiconductor substrate 10 .
- the upper side and the sidewall of the HDP oxide film 22 of the nipple shape as well as the pad oxide film 12 are removed by an isotropic etch process using a HF solution.
- the etch process is performed under the above conditions, the HDP oxide film 22 at the lateral direction of the field region ‘B’ is not removed but the HDP oxide film 22 protruded on the upper side of the active region ‘A’ is removed.
- the HDP oxide film is protruded in the active region, formation of a moat formed since the HDP oxide film at the lateral direction of the field region was removed in the prior art can be reduced.
- FIG. 3 is a TEM photography of the semiconductor device in which the device isolation film is formed according to the present invention.
- a gate electrode consisting of a gate oxide film and a polysilicon layer is formed by the process of manufacturing the semiconductor device.
- An ion implantation process is then performed to form source and drain.
- a moat is not formed around the upper corner of the device isolation film where the active region ‘A’ and the field region ‘B’ meet and the upper comer portion of the device isolation film is rounded (see portion ‘N’ in FIG. 3).
- the present invention when a trench of a STI structure is formed, a portion of a pad nitride film on an active region is removed. Therefore, the present invention has an advantageous effect that it can prevent formation of a moat around an upper comer portion of the trench of the STI structure.
- the present invention has outstanding effects that it can prevent a parasitic effect, degradation in gate oxide integrity, an inverse narrow effect and a sub-threshold hump phenomenon.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
- 1. Field of the Invention
- The invention relates generally to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of manufacturing a semiconductor device capable of improving a characteristic of the device and reducing the manufacture cost, by preventing formation of a moat generating around the top comer of a trench having a STI (shallow trench isolation) structure.
- 2. Description of the Prior Art
- Generally, in order to isolate between-semiconductor devices, the semiconductor substrate is defined into an active region and a field region. Next, a semiconductor device is formed in the active region and a device isolation film for isolation the devices is formed in the field region.
- A method for forming the device isolation film of the semiconductor device includes one by which a trench of a STI (shallow trench isolation) structure is formed and the device isolation film for isolating the devices is them. The method by which the trench of the STI structure is formed to isolate the devices will be described in short. A silicon substrate in the field region is etched by a depth of about 3500 Å to form the trench. A high-density plasma (HDP) oxide film is then deposited. Next, the oxide film is polished by a chemical mechanical polishing (CMP) process.
- FIG. 1 is a TEM (transmission electron microscope) photography of the semiconductor device in which the device isolation film is formed according to a prior art.
- Referring now to FIG. 1, in the conventional technology of forming the device isolation film having the STI structure, a moat (see portion ‘M’ in FIG. 1) is formed at a field oxide film where the active region and the field region meet by means of a pre-cleaning process for forming a gate oxide film, a subsequent cleaning process and an etch process for the oxide film. Due to this, a parasitic effect, degradation in gate oxide integrity (GOI), an inverse narrow effect and a sub-threshold hump phenomenon occur.
- Further, there are many problems in proceeding subsequent processes. If the gate oxide film is deposited, the gate oxide film at the top comer of the trench is made thin by the moat of the HDP oxide film. This may cause a breakdown when the voltage is applied to the device.
- Also, after a polysilicon layer is deposited, the moat that is concaved is formed even at the polysilicon layer at the boundary of the active region and the field region. It makes it difficult to remove polysilicon at this portion. Thus, a gate bridge may be caused due to remaining polysilicon.
- In addition, if the CMP process is performed with polysilicon concaved, CMP could not be performed uniformly due to the step of polysilicon. Thus, it makes it difficult to form the gate electrodes of the same shape. In case of the flash device, there is difference in the coupling ratio between the gate electrodes. Due to this, there is a problem that the characteristic of the semiconductor device is degraded.
- The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing generation of a moat, in such a way that a thickness of a pad oxide film is formed by minimum to an extent that stress between a semiconductor substrate and a pad nitride film is mitigated and before a HDP oxide film is deposited, a portion of the pad nitride film is etched to compensate for a portion recessed in a cleaning process.
- In order to accomplish the above object, the method of manufacturing a semiconductor device according to the present invention, is characterized in that it comprises the steps of sequentially forming a pad oxide film, a pad nitride film and a screen oxide film on a semiconductor substrate in which an active region and a field region are defined, removing the screen oxide film and the pad nitride film formed in the field region, performing a wet etch process to remove the pad nitride film exposed at the boundary of the active region and the field region, in a lateral direction by a given width, performing a dry etch process using the screen oxide film and an etch mask to remove portions of the pad oxide film and the semiconductor substrate formed in the field region, thus forming a trench, removing the screen oxide film and the pad nitride film in the lateral direction by a given width and simultaneously removing the exposed portion of the pad oxide film, performing an oxidization process to form a rounding oxide film in the exposed portion of the semiconductor substrate, depositing a field oxide film of a thickness by which the trench is sufficiently buried and then polishing the field oxide film, and removing the pad nitride film and the pad oxide film in the active region.
- The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
- FIG. 1 is a TEM (transmission electron microscope) photography of a semiconductor device in which a device isolation film is formed according to a prior art;
- FIG. 2A through FIG. 2K are cross sectional views of semiconductor devices for explaining a method of the semiconductor device capable of preventing generation of a moat at the boundary of an active region and a field region according to a preferred embodiment of the present invention; and
- FIG. 3 is a TEM photography of the semiconductor device in which the device isolation film is formed according to the present invention.
- The present invention will be described in detail by way of a preferred embodiment with reference to accompanying drawings, in which like reference numerals are used to identify the same or similar parts.
- FIG. 2A through FIG. 2K are cross sectional views of semiconductor devices for explaining a method of the semiconductor device capable of preventing generation of a moat at the boundary of an active region and a field region according to a preferred embodiment of the present invention.
- Referring now to FIG. 2A, a
pad oxide film 12, apad nitride film 14 and ascreen oxide film 16 are sequentially formed on asemiconductor substrate 10 in which an active region ‘A’ and a field region ‘B’ are defined. - In more concrete, the
pad oxide film 12 is formed to have a thickness that can serve as a barrier for mitigating stress between thesemiconductor substrate 10 and thepad nitride film 14 and for protecting theunderlying semiconductor substrate 10 when thepad nitride film 14 is etched. For example, thepad oxide film 12 may be thinly formed in thickness of 30 through 150 Å, more preferably about 33 through 75 Å. Thereby, it is possible to reduce, by maximum, time taken to perform a subsequent process for removing thepad oxide film 12. Also, thepad oxide film 12 may be formed using a PE-TEOS (plasma enhanced tetra ethyl ortho silicate) film, a TEOS (tetra ethyl ortho silicate) film, an USG (undoped silicate glass) film, a HDP (high density plasma) film, or the like. However, it should be noted that the type of the film is not limited to them. At this time, thepad nitride film 14 formed on an upper side and an oxide film having a high etch selective ratio can be used as thepad oxide film 12. - The
pad nitride film 14 is formed in thickness of 500 through 1500 Å so that it can serve as a stop layer in a subsequent CMP process. At this time, thepad nitride film 14 is deposited using any one of a SiH4+NH3 gas, a Si2H4+NH3 gas and a DCS (Dichlosilane; SiH2Cl2)+NH3 gas by means of a LP-CVD (low-pressure chemical vapor deposition) method or a PE-CVD (plasma enhanced CVD) method. However, it should be noted that the present invention is not limited to the above description. Thepad nitride film 14 may be formed using a nitride film having a high etch selective ratio with thepad oxide film 12 formed on its bottom and thescreen oxide film 16 formed on its top. - The
screen oxide film 16 is formed in thickness of 100 through 500 Å that can prevent etching of the underlyingpad nitride film 14 when a trench is formed and can serve as a mask for forming the trench. Thescreen oxide film 16 may be formed using the PE-TEOS film, the TEOS film, the USG film, the HDP film, etc. However, it should be noted that the screen oxide film is not limited to the above films. Thepad nitride film 14 formed below thescreen oxide film 16 and the oxide film having a high etch selective ratio may be used as thescreen oxide film 16. - Referring to FIG. 2B, a photoresist film is applied on the
screen oxide film 16. Aphotoresist pattern 18 through the field region ‘B’ is exposed is formed by means of a photolithography process using an exposure mask. - By reference to FIG. 2C, the
screen oxide film 16 and thepad nitride film 14 are sequentially removed by an etch process using thephotoresist pattern 18 through which the field region ‘B’ is exposed as an etch mask. Thephotoresist pattern 18 used as the etch mask is then removed. - At this time, ‘lateral direction’ to be described later indicates toward the active region ‘A’ direction at a boundary between the active region ‘A’ and the field region ‘B’. The lateral direction could be a positive X-direction or a negative X-direction along the active region ‘A’ and the field region ‘B’ defined in the
semiconductor substrate 10. - Referring to FIG. 2D, a portion of the
pad nitride film 14, which is exposed between the active region ‘A’ and the field region ‘B’ and located between thescreen oxide film 16 on the active region ‘A’ and thepad oxide film 12, is removed by a wet etch process. (see portion ‘K’ in FIG. 2D). In concrete, the exposed portion of thepad nitride film 14 is removed in a lateral direction by the amount of the field oxide film (HDP oxide film) removed by an etch process for forming a subsequent gate oxide film. In other words, the exposed sidewalls of thepad nitride film 14 is etched toward the active region ‘A’ direction by performing the wet etch process having a high etch selective ratio with the oxide film. - An etch condition of the wet etch process is as follows. Polymer that may be formed at the sidewalls of the
pad nitride film 14 is removed in a solution in which the ratio of hydrofluoric acid (HF):H2O is 1:99. Thepad nitride film 14 is removed by a thickness of about 200 through 500 Å by performing the wet etch process using a phosphoric acid (H3PO4) solution at a temperature of 110 through 130° C. for 300 through 750 second. At this time, thepad oxide film 12 having a high etch selective ratio with thepad nitride film 14 serves as an etch barrier to prevent damage of theunderlying semiconductor substrate 10. - By removing in the lateral direction the portion of the
pad nitride film 14 exposed between thescreen oxide film 16 and thepad oxide film 12 by means of the etch process, a recessed shape (see portion ‘K’ in FIG. 2D) is formed below thescreen oxide film 16. Thereby, thepad oxide film 12 exposed by the field region ‘B’ defined by thephotoresist pattern 18 is further exposed in the active region ‘A’ direction. At this time, the width of thepad oxide film 12 by the wet etch process is more exposed by about 400 through 1000 Å being the width of the removedpad nitride film 14. By removing thepad nitride film 14 of a given width in the active region a direction, a field oxide film to be removed in a given thickness can be supplemented in the field region ‘B’ direction in a subsequent etch process of a gate oxide film. - For example, if the width ‘H1’ of the
pad oxide film 12 exposed by thephotoresist pattern 18 is 1000 Å and the width ‘L1’ and ‘L2’ exposed by the wet etch process for thepad nitride film 14 is 400 through 1000 Å, the total width ‘H2’ of the exposedpad oxide film 12 is about 1400 through 2000 Å, which is same to the sum (H1+L1+L2) of the width ‘H1’ exposed by thephotoresist pattern 18 and the width ‘L1’ and ‘L2’ exposed by etching of thepad nitride film 14. - Referring now to FIG. 2E, portions of the
pad oxide film 12 and thesemiconductor substrate 10 are removed by a dry etch process using thescreen oxide film 16 as an etch mask. In concrete, thepad oxide film 12 in the field region ‘B’ exposed by thescreen oxide film 16 is removed using the straightness of the dry etch process, and the portion of thesemiconductor substrate 10 exposed by removing thepad oxide film 12 is removed to atrench 30. At this time, thepad oxide film 12 on the active region ‘A’, which is exposed by removing the portion of thepad nitride film 14 below thescreen oxide film 16, is not removed but only thepad oxide film 12 on the field region ‘B’ is removed. Also, thetrench 30 is formed by etching thesemiconductor substrate 10 by 3500 through 4000 Å from the upper surface of thesubstrate 10. - By reference to FIG. 2F, the
screen oxide film 16 used as the etch mask for forming thetrench 30 is removed. In detail, the surface of thesemiconductor substrate 10 is experienced by a post-cleaning process for preventing problems such as contamination, etc. that may occur in a next process is performed using SC-1 (standard cleaning-1; NH4OH:H2O2:H2O=1:5:50) at a temperature of 50° C. for 10 minutes. In order to remove thescreen oxide film 16 on thepad nitride film 14, an etch process using an aqueous solution of HF:H2O=1:99 through HF:H2O=1:19 for 100 through 200 seconds is performed. However, it should be noted that the etch conditions are not limited to the mentioned conditions. Thescreen oxide film 16 on thepad nitride film 14 may be removed by means of various etch methods such as an etch method using plasma, a dry etch method, or the like. At this time, a portion of thesemiconductor substrate 10 on the active region ‘A’ is also exposed by removing the exposed portion of thepad oxide film 12 below thepad nitride film 14. - Referring now to FIG. 2G, a rounding
oxide film 20 is formed on thesemiconductor substrate 10 by means of an oxidization process. In concreter, the roundingoxide film 20 having a thickness of 90 through 110 Å is formed within thetrench 30, at the upper corner portion of thetrench 30 and the exposed portion of thesemiconductor substrate 10 on an upper portion of the active region ‘A’, by means of a dry oxidization process at a temperature of 950 through 1150° C. Thereby, the upper corner portion of thetrench 30 has a rounding shape (see portion ‘R’ in FIG. 2G). However, it should be noted that the oxidization conditions are not limited to the mentioned oxidization process. Instead, various oxidization methods may be used. The upper corner portion of thetrench 30 has the round shape (see portion ‘R’ in FIG. 2G) through the oxidization process. - By reference to FIG. 2H, a high-density plasma (HDP)
oxide film 22 is deposited on the entire structure to bury thetrench 30. A high-temperature annealing process is then performed. In concrete, theHDP oxide film 22 having a thickness of 4000 through 6000 Å is buried to bury thetrench 30. The annealing process is performed at a temperature of 900 through 1000° C. for 25 through 35 minutes. - Referring to FIG. 21, the
HDP oxide film 22 on thepad nitride film 14 and a portion of thepad nitride film 14 are moved by a CMP process. At this time, theHDP oxide film 22 is left in thickness of about 400 through 600 Å from the surface of thesemiconductor substrate 10 on the active region ‘A’. Also, the height of theHDP oxide film 22 is adjusted using thepad nitride film 14 as a stop layer of the CMP process. - Referring to FIG. 2J, the
pad nitride film 14 on an upper side of the active region ‘A’ is removed to expose thepad oxide film 12. At this time, theHDP oxide film 22 on upper side of thetrench 30 has a nipple shape that is protruded by about 200 through 500 Å in the active region ‘A’ direction at both sides of the field region ‘B’ as well as the field region ‘B’ and protruded by about 400 through 600 Å from thesemiconductor substrate 10. The critical dimension of the active region ‘A’ is reduced due to the above shape. However, a target critical dimension can be obtained by removing theHDP oxide film 22 on an upper side of the active region ‘A’ by the etch process for forming a subsequent gate oxide film. - An ion implantation for forming a well (not shown) is performed to form the well. At this time, a passivation oxide film (not shown) for preventing damage of the
underlying semiconductor substrate 10 due to ion implantation without removing the exposedpad oxide film 12 and protecting thesemiconductor substrate 10 after thepad oxide film 12 is removed is deposited in order to prevent damage of the surface of thesemiconductor substrate 10 when the ion implantation process for forming the well is performed. - By reference to FIG. 2K, the
pad oxide film 12 is removed to expose thesemiconductor substrate 10. In concrete, thepad oxide film 12 is completely removed by performing a pre-cleaning process using SC-1 at a temperature of 50 through 80° C. for 5 through 15 minutes and then performing an etch process using a diluted solution of HF:H2O=1:19 through HF:H2O=1:99 for 10 through 60 seconds. At this time, the upper side and the sidewall of theHDP oxide film 22 of the nipple shape as well as thepad oxide film 12 are removed by an isotropic etch process using a HF solution. In other words, if the etch process is performed under the above conditions, theHDP oxide film 22 at the lateral direction of the field region ‘B’ is not removed but theHDP oxide film 22 protruded on the upper side of the active region ‘A’ is removed. As the HDP oxide film is protruded in the active region, formation of a moat formed since the HDP oxide film at the lateral direction of the field region was removed in the prior art can be reduced. - FIG. 3 is a TEM photography of the semiconductor device in which the device isolation film is formed according to the present invention.
- Referring now to FIG. 3, a gate electrode consisting of a gate oxide film and a polysilicon layer is formed by the process of manufacturing the semiconductor device. An ion implantation process is then performed to form source and drain. Examining the semiconductor device formed by the technology, it can be seen that a moat is not formed around the upper corner of the device isolation film where the active region ‘A’ and the field region ‘B’ meet and the upper comer portion of the device isolation film is rounded (see portion ‘N’ in FIG. 3).
- As mentioned above, according to the present invention, when a trench of a STI structure is formed, a portion of a pad nitride film on an active region is removed. Therefore, the present invention has an advantageous effect that it can prevent formation of a moat around an upper comer portion of the trench of the STI structure.
- Further, the present invention has outstanding effects that it can prevent a parasitic effect, degradation in gate oxide integrity, an inverse narrow effect and a sub-threshold hump phenomenon.
- The present invention has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof.
- It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the present invention.
Claims (6)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2002-62419 | 2002-10-14 | ||
KR10-2002-0062419 | 2002-10-14 | ||
KR10-2002-0062419A KR100473731B1 (en) | 2002-10-14 | 2002-10-14 | Method of manufacturing a semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040072451A1 true US20040072451A1 (en) | 2004-04-15 |
US6723617B1 US6723617B1 (en) | 2004-04-20 |
Family
ID=32064941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/310,867 Expired - Lifetime US6723617B1 (en) | 2002-10-14 | 2002-12-06 | Method of manufacturing a semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (1) | US6723617B1 (en) |
KR (1) | KR100473731B1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040147090A1 (en) * | 2003-01-23 | 2004-07-29 | Silterra Malaysia Sdn. Bhd. | Shallow trench isolation |
US20070272971A1 (en) * | 2003-05-28 | 2007-11-29 | Chang-Hyun Lee | Non-Volatile Memory Device and Method of Fabricating the Same |
US20080057670A1 (en) * | 2003-05-28 | 2008-03-06 | Kim Jung H | Semiconductor Device and Method of Fabricating the Same |
CN102148182A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
CN110880503A (en) * | 2018-09-05 | 2020-03-13 | 三星电子株式会社 | Integrated circuit device |
CN114023648A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing trench gate semiconductor device |
CN114078739A (en) * | 2020-08-19 | 2022-02-22 | 和舰芯片制造(苏州)股份有限公司 | Method for improving filling effect of deep trench isolation groove |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100546852B1 (en) * | 2002-12-28 | 2006-01-25 | 동부아남반도체 주식회사 | Method For Manufacturing Semiconductor Devices |
US6974755B2 (en) * | 2003-08-15 | 2005-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure with nitrogen-containing liner and methods of manufacture |
US6905943B2 (en) * | 2003-11-06 | 2005-06-14 | Texas Instruments Incorporated | Forming a trench to define one or more isolation regions in a semiconductor structure |
US7081397B2 (en) * | 2004-08-30 | 2006-07-25 | International Business Machines Corporation | Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow |
KR101051180B1 (en) * | 2004-12-30 | 2011-07-21 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
US20060231908A1 (en) * | 2005-04-13 | 2006-10-19 | Xerox Corporation | Multilayer gate dielectric |
US7179717B2 (en) * | 2005-05-25 | 2007-02-20 | Micron Technology, Inc. | Methods of forming integrated circuit devices |
KR100707803B1 (en) * | 2005-10-28 | 2007-04-17 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device with recess gate |
KR100700284B1 (en) * | 2005-12-28 | 2007-03-26 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
US7601607B2 (en) * | 2006-05-15 | 2009-10-13 | Chartered Semiconductor Manufacturing, Ltd. | Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects |
KR100869845B1 (en) * | 2006-12-04 | 2008-11-21 | 주식회사 하이닉스반도체 | Method for forming oxide pattern and patterning method of semiconductor device |
WO2009047588A1 (en) * | 2007-10-09 | 2009-04-16 | Freescale Semiconductor, Inc. | Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method |
KR100955935B1 (en) * | 2007-12-21 | 2010-05-03 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semicontuctor device |
US8785291B2 (en) | 2011-10-20 | 2014-07-22 | International Business Machines Corporation | Post-gate shallow trench isolation structure formation |
US8466496B2 (en) | 2011-11-17 | 2013-06-18 | International Business Machines Corporation | Selective partial gate stack for improved device isolation |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6080637A (en) * | 1998-12-07 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Shallow trench isolation technology to eliminate a kink effect |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980027696A (en) * | 1996-10-17 | 1998-07-15 | 김광호 | Device isolation method of semiconductor memory device using trench |
KR19980085035A (en) * | 1997-05-27 | 1998-12-05 | 윤종용 | Trench Forming Method with Rounded Profile and Device Separation Method of Semiconductor Device Using the Same |
KR100275730B1 (en) * | 1998-05-11 | 2000-12-15 | 윤종용 | Trench isolating method |
KR100327656B1 (en) * | 1998-06-29 | 2002-07-02 | 박종섭 | Device Separation Method of Semiconductor Device |
JP3439387B2 (en) * | 1999-07-27 | 2003-08-25 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
2002
- 2002-10-14 KR KR10-2002-0062419A patent/KR100473731B1/en active IP Right Grant
- 2002-12-06 US US10/310,867 patent/US6723617B1/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6080637A (en) * | 1998-12-07 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Shallow trench isolation technology to eliminate a kink effect |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040147090A1 (en) * | 2003-01-23 | 2004-07-29 | Silterra Malaysia Sdn. Bhd. | Shallow trench isolation |
US7091104B2 (en) * | 2003-01-23 | 2006-08-15 | Silterra Malaysia Sdn. Bhd. | Shallow trench isolation |
US20070272971A1 (en) * | 2003-05-28 | 2007-11-29 | Chang-Hyun Lee | Non-Volatile Memory Device and Method of Fabricating the Same |
US20080057670A1 (en) * | 2003-05-28 | 2008-03-06 | Kim Jung H | Semiconductor Device and Method of Fabricating the Same |
US7812375B2 (en) | 2003-05-28 | 2010-10-12 | Samsung Electronics Co., Ltd. | Non-volatile memory device and method of fabricating the same |
US7833875B2 (en) * | 2003-05-28 | 2010-11-16 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9595612B2 (en) | 2003-05-28 | 2017-03-14 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US9847422B2 (en) | 2003-05-28 | 2017-12-19 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
CN102148182A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
CN110880503A (en) * | 2018-09-05 | 2020-03-13 | 三星电子株式会社 | Integrated circuit device |
CN114078739A (en) * | 2020-08-19 | 2022-02-22 | 和舰芯片制造(苏州)股份有限公司 | Method for improving filling effect of deep trench isolation groove |
CN114023648A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing trench gate semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR20040033361A (en) | 2004-04-28 |
US6723617B1 (en) | 2004-04-20 |
KR100473731B1 (en) | 2005-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6723617B1 (en) | Method of manufacturing a semiconductor device | |
US7029989B2 (en) | Semiconductor device and method of manufacturing the same | |
KR100322531B1 (en) | Method for Trench Isolation using a Dent free layer &Semiconductor Device thereof | |
US6261921B1 (en) | Method of forming shallow trench isolation structure | |
US7611950B2 (en) | Method for forming shallow trench isolation in semiconductor device | |
US6964913B2 (en) | Method for forming floating gate in flash memory device | |
US20070232019A1 (en) | Method for forming isolation structure in nonvolatile memory device | |
US6346457B1 (en) | Process for manufacturing semiconductor device | |
KR100764742B1 (en) | Semiconductor device and method for fabricating the same | |
US6955957B2 (en) | Method of forming a floating gate in a flash memory device | |
KR100311708B1 (en) | Semiconductor device having a shallow isolation trench | |
US20040110377A1 (en) | Method of forming a contact in a semiconductor device | |
KR100377833B1 (en) | Semiconductor device with borderless contact structure and method of manufacturing the same | |
KR100950749B1 (en) | Method for forming element isolation film of semiconductor device | |
US20040048442A1 (en) | Method of forming shallow trench isolation in a semiconductor substrate | |
JP2005197652A (en) | Method for manufacturing semiconductor device | |
US6720235B2 (en) | Method of forming shallow trench isolation in a semiconductor substrate | |
US6900112B2 (en) | Process for forming shallow trench isolation region with corner protection layer | |
KR100575343B1 (en) | Method for manufacturing flash memory device | |
US11417736B2 (en) | Dual shield oxide damage control | |
KR20000015466A (en) | Trench isolation method | |
KR100419754B1 (en) | A method for forming a field oxide of a semiconductor device | |
US7192883B2 (en) | Method of manufacturing semiconductor device | |
KR20060000483A (en) | Method for manufacturing semiconductor device | |
KR100734088B1 (en) | Method of manufacturing transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHOI, MYUNG GYU;REEL/FRAME:013549/0979 Effective date: 20021118 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR, INC.;REEL/FRAME:016216/0649 Effective date: 20041004 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUS Free format text: AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:022277/0133 Effective date: 20090217 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: MAGNACHIP SEMICONDUCTOR LTD.,KOREA, DEMOCRATIC PEO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION;REEL/FRAME:024563/0807 Effective date: 20100527 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: MAGNACHIP SEMICONDUCTOR LTD., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY;ASSIGNOR:US BANK NATIONAL ASSOCIATION;REEL/FRAME:034469/0001 Effective date: 20100527 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: KEY FOUNDRY CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:053703/0227 Effective date: 20200828 |