US20040058494A1

US20040058494A1 - Split-gate flash memory cell and manufacturing method thereof

Info

Publication number: US20040058494A1
Application number: US10/316,904
Authority: US
Inventors: Tae Choi; Jae Kim
Original assignee: Anam Semiconductor Inc
Current assignee: DongbuAnam Semiconductor Inc; Cavium International; Marvell Asia Pte Ltd
Priority date: 2002-09-19
Filing date: 2002-12-12
Publication date: 2004-03-25
Anticipated expiration: 2022-12-12
Also published as: US6709925B1; KR20040025241A; JP2004111891A; KR100509828B1

Abstract

A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

Description

FIELD OF THE INVENTION

The present invention relates to a split-gate flash memory cell and manufacturing method thereof; and, more particularly, to a split-gate flash memory cell with a peak floating gate and manufacturing method thereof.

BACKGROUND OF THE INVENTION

The shape and size of different portions of memory cells affects the performance of the memory cells differently. Thus, with the one-transistor memory cell, which contains one transistor and one capacitor, many variations of this simple cell have been advanced for the purposes for shrinking the size of the cell and, at the same time, improve its performance. The variations include different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.

Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drain regions that are aligned to a floating gate or aligned to spacers.

Referring to FIG. 1, there is shown a conventional split-gate flash memory cell disclosed in U.S. Pat. No. 5,970,371.

On a

substrate

10 with a plurality of active regions, e.g., a source 11 and a drain 13, already defined, a tunnel oxide layer 20 is formed. A polysilicon layer 30 is next deposited over the tunnel oxide layer 20. A portion of the polysilicon layer 30 is oxidized by employing a local oxidation of silicon (LOCOS) process to form a LOCOS polyoxide 35. The LOCOS polyoxide 35 is used as a hard mask to etch the remaining portion of the polysilicon layer 30 not covered by the LOCOS polyoxide 35. Since the shape of the LOCOS polyoxide 35 is generally rounded even after performing over-etch, the polysilicon layer 30 is modified as a floating gate 30 with a sharp beak 37. After an inter-gate oxide layer 60 is deposited, a control gate 70 of polisilicon is formed over a portion of the inter-gate oxide layer 60.

In order to program the split-gate flash memory cell, charges in the

source

11 are transferred through the tunnel oxide layer 20 to the floating gate 30. On the other hand, in order to erase the split-gate flash memory cell, charges in the floating gate 30 are removed through the inter-gate oxide layer 60 to the control gate 70.

Since, however, the LOCOS

polioxide

35 is rounded to form the sharp beak 37 of the floating gate 30, the thickness of oxide between the floating gate 30 and the control gate 70 is not uniform. Further, since the control gate 70 and the floating gate 30 are formed separately, the control gate 70 dose not cover the floating gate 30 completely to reduce a coupling ratio between the floating gate 30 and the control gate 70 and, therefore, the programming/erasing efficiency of the split-gate flash memory cell is considerably reduced.

SUMMARY OF THE INVENTION

It is, therefore, a primary object of the present invention to provide a split-gate flash memory cell with a peak floating gate and manufacturing method thereof to improve a coupling ratio between the peak floating gate and the control gate.

In accordance with one aspect of the present invention, there is provided a method for manufacturing a split-gate flash memory cell, the method comprising the steps of:

(a) providing a substrate;

(b) forming a tunnel oxide layer over the substrate;

(c) forming a peak floating gate layer of conducting material over a portion of the tunnel oxide layer, wherein the peak floating gate layer has a peak structure thereon;

(d) coating an inter-gate insulating layer over the peak floating gate layer and the remaining portion of the tunnel oxide layer and spreading a control gate layer of conducting material over the inter-gate insulating layer;

(e) defining a control gate pattern over the control gate layer;

(f) etching down the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer sequentially to the substrate by using the control gate pattern to generate a control gate, a inter-gate insulating region, a peak floating gate and a tunnel oxide region; and

(g) defining a source and a drain adjoining the tunnel oxide region by using a self-align technique.

In accordance with another aspect of the present invention, there is provided a split-gate flash memory cell comprising:

a substrate defined with a source, a drain and a channel region between the source and the drain;

a tunnel oxide region formed over the channel region;

a peak floating gate of conducting material over a portion of the tunnel oxide region, wherein the peak floating gate has a peak structure thereon;

an inter-gate insulating region formed over the peak floating gate and the remaining portion of the tunnel oxide region; and

a control gate of conducting material formed over the inter-gate insulating region,

wherein the control gate, the inter-gate insulating region, the peak floating gate and the tunnel oxide region are defined with a mask which has a same size as the channel region.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: [0024]
FIG. 1 represents a cross-sectional view of a conventional split-gate flash memory cell; [0025]
FIGS. 2[0026] a to 2 k show cross-sectional views for illustrating a manufacturing process of a split-gate flash memory cell in accordance with the present invention; and
FIG. 3 describes a cross-sectional view of a split-gate flash memory cell in accordance with the present invention.[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 2[0028] a to 2 k, there is shown a method for fabricating a split-gate flash memory cell in accordance with a preferred embodiment of the present invention.
Referring to FIG. 2[0029] a, a substrate 100, preferably a silicon substrate, is provided and a tunnel oxide layer 102 is thermally grown over the substrate 100. Specifically, the tunnel oxide layer 102 may be formed by employing a thermal oxidation process or an atmospheric or low pressure chemical vapor deposition (LPCVD) process.
A [0030] floating gate layer 104 of conducting material, e.g., polysilicon, is deposited over the tunnel oxide layer 102 through reduction of SiH₄by using LPCVD. A first insulating layer 106 of insulating material, e.g., silicon nitride, is deposited over the floating gate layer 104.
Referring to FIG. 2[0031] b, a photoresist layer is spun over the first insulating layer 106 and then the photoresist layer is developed as a first photoresist pattern 107 having patterns corresponding to areas where floating gate layers are to be defined later. The first photoresist pattern 107 is used to etch down a portion of the first insulating layer 106 to the floating gate layer 104 so that an insulating pattern layer 106 a may be formed. Then, the first photoresist pattern 107 is removed.
Referring to FIG. 2[0032] c, the insulating pattern layer 106 a is used as a mask in a dry etching process to etch down steeply a predetermined portion of the floating gate layer 104 to the tunnel oxide layer 102 so that a sloping-patterned floating gate layer 104 a with a sloping sidewall 110 a may be formed with a portion of top surface of the tunnel oxide layer 102 exposed.
Referring to FIG. 2[0033] d, a second insulating layer 108 of insulating material, e.g., silicon nitride, is deposited conformally all over the top surface and the sidewall of the insulating pattern layer 106 a, the sloping sidewall 110 a of the sloping-patterned floating gate layer 104 a and the exposed top surface of the tunnel oxide layer 102. Then, referring to FIG. 2e, the second insulating layer 108 is dry-etched so that an insulating spacer 108 a of insulating material is formed covering at least the sloping sidewall 110 a of the sloping-patterned floating gate layer 104 a. If necessary, the insulating spacer 108 a may also be formed on the sidewall of the insulating pattern layer 106 a. It is preferable that the insulating spacer 108 a is made of a material with an etching selectivity different from that of the insulating pattern layer 106 a.
Referring to FIG. 2[0034] f, the insulating pattern layer 106 a is removed away by using a wet etching process.
Referring to FIG. 2[0035] g, the sloping-patterned floating gate layer 104 a is etched down steeply with a predetermined depth by using a dry etching process so that a peak floating gate layer 104 b with a peak 110 may be formed. In order to form the peak 110 steeply, the nearer the insulating spacer 108 a, the less etched is the sloping-patterned floating gate layer 104 a.
Referring to FIG. 2[0036] h, if the insulating spacer 108 a is removed away by using a wet etching process, the peak floating gate layer 104 b with the peak 110 thereon is formed on a portion of the tunnel oxide layer 102. It is preferable that the peak 110 is formed around the middle of the split-gate flash memory cell to be defined. It is more preferable that the peak 110 is formed near the drain as defined later.
Referring to FIG. 2[0037] i, an inter-gate insulating layer 112 of insulating material is conformally coated all over the exposed top surface of the tunnel oxide layer 102 and the peak floating gate layer 104 b. It is preferable that the inter-gate insulating layer 112 is uniformly thin. Then, a control gate layer 114 of conducting material is conformally deposited over the inter-gate insulating layer 112. It is preferable that the inter-gate insulating layer 112 is made of one or more complex dielectric films, e.g., of oxide/nitride/oxide and the control gate layer 114 is made of single or complex polysilicons or metals.
Referring to FIG. 2[0038] j, a second photoresist pattern 116 is defined over the control gate layer 114. It is preferable that the second photoresist pattern 116 is of a same size as that of a channel region, wherein the channel region is a region between a source and a drain in a split-gate flash memory cell as illustrated later. Accordingly, it is natural that the second photoresist pattern 116 is located over the peak 110 of peak floating gate layer 104 b.
Referring to FIG. 2[0039] k, the second photoresist pattern 116 is used to etch down the control gate layer 114, the inter-gate insulating layer 112, the peak floating gate layer 104 b and the tunnel oxide layer 102 to the substrate 100 so that a control gate 114 a, an inter-gate insulating region 112 a, a peak floating gate 104 c and a tunnel oxide region 102 a may be formed in sequence, e.g., by employing a dry etching process. Since it is natural the second photoresist pattern 116 is of a same size as that of the control gate 114 a, the second photoresist pattern 116 may be read as a control gate pattern.
The [0040] tunnel oxide region 102 a is used to define a drain 118 a and a source 118 b within the substrate 100 by using a self-align ion injection process, wherein the substrate 100 is sectioned with the drain 118 a, the source 118 b and a channel region 118 c between the drain 118 a and the source 118 b. Specifically, in an n channel split-gate flash memory cell, n type dopant, e.g., P or As, of a higher concentration is injected to form n⁺ drain 118 a and n⁺ source 118 b.
Since the inter-gate [0041] insulating region 112 a is formed uniformly thin by using a deposition process and the control gate 114 a covers the peak floating gate 104 c completely, the coupling ratio between the control gate 114 a and the peak floating gate 104 c may be increased to thereby improve the erasing efficiency of the split-gate flash memory cell.
Referring to FIG. 3, there is shown a split-gate flash memory cell manufactured by using a manufacturing process of a split-gate flash memory cell in accordance with the present invention. [0042]
The [0043] tunnel oxide region 102 a is defined over a portion of the substrate 100. The tunnel oxide region 102 a is used as a self-aligning mask to define the source 118 b and the drain 118 a with the self-align ion injection process. Since, the portion of the substrate 100 under the tunnel oxide region 102 a corresponds to the channel region 118 c, two end points of the channel region 118 c adjoin the source 118 b and the drain 118 a, respectively.
The [0044] peak floating gate 104 c of conduction material with the peak 110 is formed over a portion of the tunnel oxide region 102 a. It is preferable that the peak 110 is located around the middle point of the tunnel oxide region 102 a. It is more preferable that the peak 110 is located near the drain 118 a.
Over the remaining portion of the [0045] tunnel oxide region 102 a and the top surface of the peak floating gate 104 c, the inter-gate insulating region 112 a is conformally formed with a thin thickness. The inter-gate insulating region 112 a is totally covered with the control gate 114 a.
The [0046] drain 118 a, the source 118 b and the control gate 114 a are connected with a drain voltage D, a source voltage S and a control voltage G, respectively. If the control gate is applied with a high voltage G, a high electric field is formed around the peak 110 so that charges may be transmitted from the peak floating gate 104 c to the control gate 114 a to increase the erasing speed.
While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. [0047]

Claims

What is claimed is:

1. A method for manufacturing a split-gate flash memory cell, the method comprising the steps of:

(a) providing a substrate;

(b) forming a tunnel oxide layer over the substrate;

(e) defining a control gate pattern over the control gate layer;

2. The method of claim 1, wherein the step (c) includes the steps of:

(c1) depositing a floating gate layer of conducting material over the tunnel oxide layer;

(c2) forming a mask layer of insulating material over the floating gate layer;

(c3) using the mask layer to etch down a predetermined portion of the floating gate layer steeply to the tunnel oxide layer so that a sloping-patterned floating gate layer with a sloping sidewall is formed;

(c4) forming a spacer of insulating material to cover at least the sloping sidewall of the sloping-patterned floating gate layer therewith and removing the mask layer; and

(c5) using the spacer to etch down the sloping-patterned floating gate layer steeply with a predetermined depth so that the peak floating gate layer with the peak structure thereon is formed and removing the spacer.

3. The method of claim 1, wherein the peak structure is located around the drain.

4. The method of claim 2, wherein the mask layer has an etching selectivity different from that of the spacer.

5. A split-gate flash memory cell comprising:

a tunnel oxide region formed over the channel region;

6. The split-gate flash memory cell of claim 5, wherein the peak structure is located around the drain.

7. A split-gate flash memory cell manufactured by the method of claim 1, the split-gate flash memory cell comprising:

the substrate defined with a source, a drain and a channel region between the source and the drain;

the tunnel oxide region formed over the channel region;

the peak floating gate of conducting material over a portion of the tunnel oxide region, wherein the peak floating gate has a peak structure thereon;

the inter-gate insulating region formed over the peak floating gate and the remaining portion of the tunnel oxide region;

the control gate of conducting material formed over the inter-gate insulating region,

8. The split-gate flash memory cell of claim 7, wherein the step (c) includes the steps of:

(c2) forming a mask layer of insulating material over the floating gate layer;

9. The split-gate flash memory cell of claim 7, wherein the peak structure is located around the drain.

10. The split-gate flash memory cell of claim 8, wherein the mask layer has an etching selectivity different from that of the spacer.