US20040005776A1 - Methods for forming a fuse in a semiconductor device - Google Patents
Methods for forming a fuse in a semiconductor device Download PDFInfo
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- US20040005776A1 US20040005776A1 US10/188,528 US18852802A US2004005776A1 US 20040005776 A1 US20040005776 A1 US 20040005776A1 US 18852802 A US18852802 A US 18852802A US 2004005776 A1 US2004005776 A1 US 2004005776A1
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 238000007664 blowing Methods 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 11
- 229910052715 tantalum Inorganic materials 0.000 claims description 8
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 230000007547 defect Effects 0.000 claims 2
- 230000000873 masking effect Effects 0.000 claims 1
- 230000004888 barrier function Effects 0.000 description 8
- 230000015654 memory Effects 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
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- 230000001681 protective effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
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- 239000000758 substrate Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Definitions
- This invention relates generally to the field of electronic devices and more particularly to an improved method for forming a fuse in a semiconductor device.
- DRAMs dynamic random access memories
- SRAMs static random access memories
- DRAMs dynamic random access memories
- SRAMs static random access memories
- a conducting fuse is made of a polysilicon or metal film formed on a dielectric layer. A laser is used to ablate the fuse material and any protective dielectric layer that is covering the fuse material.
- fuses in semiconductor structures requires depositing, patterning, and etching a polysilicon or metal layer. Blowing the fuses formed from performing such steps may increase contamination because particles of the blown fuse and the protective dielectric material may be scattered to other columns/rows. Further, for the case of a damascene structure, empty trenches may result from removal of the fuse material, which may create difficult topography for any subsequent dielectric deposition and may lead to reliability problems.
- a method includes lining, with a conductive liner, a surface of a dielectric layer.
- the surface defines at least two trenches separated by a platform.
- Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches.
- the conductor is electrically coupled to the conductive liner.
- the method also includes covering the portion of the conductive liner overlying the platform after lining the surface.
- the method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
- Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, the fabrication of semiconductor devices requiring fuses is simplified by avoiding extra deposition steps and instead forming the fuses using an existing liner or barrier of the semiconductor structure. According to another embodiment, the blowing of the fuse is facilitated because the material used to form the fuse is relatively thin. According to another embodiment, having a thin fuse allows the blowing of the fuse using electrical current as well as laser exposure, which reduces the level of contamination, improves reliability and greatly simplifies electrical programming at test. According to another embodiment, the coverage requirement for any protective dielectric layer is reduced because of the amount of topology, such as trenches, that results from blowing fuses using laser exposure is reduced.
- FIGS. 1A through 1D are a series of schematic cross-sectional diagrams illustrating one embodiment of a semiconductor device constructed according to the teachings of the present invention
- FIG. 2 is a schematic top view diagram illustrating one embodiment of a semiconductor device constructed according to the teachings of the present invention.
- FIG. 3 is a schematic cross-sectional diagram illustrating one embodiment of a semiconductor device constructed according to the teachings of the present invention, wherein a fuse is blown.
- FIGS. 1A through 3 of the drawings like numerals being used for like and corresponding parts of the various drawings.
- FIG. 1A is a schematic cross-sectional diagram illustrating one embodiment of a semiconductor device 10 that may benefit from the teachings of the present invention.
- Device 10 includes a substrate 20 and a dielectric layer 30 that overlies substrate 20 .
- the surface of dielectric layer 30 defines a plurality of trenches 34 that are separated by a platform 38 . Trenches 34 may also be referred to as grooves or holes.
- FIG. 1A shows only two trenches 34
- device 10 may have more than two trenches 34 where each trench 34 is separated from a neighboring trench 34 by a particular platform 38 .
- the surface of dielectric layer 30 may define more than one platform 38 .
- Device 10 also comprises a conductive layer 40 that lines the surface of dielectric layer 30 .
- Each defined trench 34 that is lined with a portion of conductive liner 40 includes a conductor 60 .
- each lined trench 34 is filled with a conductor 60 , where conductor 60 overlies the portion of conductive liner 40 that lines the lined trench 34 and is positioned within the lined trench 34 .
- damascene structure One example of device 10 described at FIG. 1A is referred to as a damascene structure.
- the term “damascene structure” will be used hereinafter as an example to refer to device 10 shown in FIG. 1A.
- any semiconductor device having a liner or a barrier between its active regions, such as conductors 60 , and its dielectric layer, such as dielectric layer 30 may be device 10 .
- Dielectric layer 30 may be any suitable electrical insulator.
- dielectric layer 30 may be formed from a layer of oxide.
- Conductive liner 40 may be formed from any suitable conductive material, such as tantalum, Tungsten, Ruthenium, Cobalt, TaN, WN, COWP, or a suitable combination of such materials.
- Conductor 60 may be formed from any suitable conductive material, such as copper or aluminum.
- the materials for forming conductor 60 and conductive liner 40 may be chosen so that the material for liner 40 has a lower conductivity than that of the material for conductors 60 .
- tantalum is a conductive material, it has a lower conductivity than copper.
- tantalum may be used to form liner 40 and copper may be used to form conductor 60 so that liner 40 has a lower conductivity than conductor 60 .
- a damascene structure such as damascene structure 10
- PVD liners are typically around 20-100 nanometers thick on a surface pedestal, such as platforms 38 , but may be thinner (approximately 5-25 nm) along the wall of trenches 34 due to non-conformal deposition.
- CVD liners are typically conformal; thus, a liner having a relatively uniform thickness of approximately 10-20 nanometers may be on both platforms 38 and walls of trenches 34 . However, CVD liners may be thinner than 5 nanometers.
- a diffusion barrier such as liner 40
- liner 40 may be necessary where the material that is used to fill trenches 34 has a tendency to diffuse into dielectric layer 30 .
- One such material is copper.
- liner 40 is used to line the surface of dielectric layer 30 as a barrier against copper diffusion, a thin copper seed layer (not explicitly shown) is deposited and copper is electroplated onto the cooper seed overlying liner 40 so that lined trenches 34 may be filled with copper to form copper conductors 60 .
- Copper is used herein as an example material for forming conductors 60 that has a tendency to diffuse into dielectric layer 30 ; however, other conductive material that may benefit from having a barrier or adhesion layer may also be used.
- the copper seed layer may be omitted and copper electroplating is performed directly onto liner 40 .
- the electroplating of copper generally overflows trenches 34 and deposits the copper onto the entire surface of liner 40 , including the portions that overlie platforms 38 .
- the deposition of material for liner 40 such as tantalum, also deposits excess tantalum onto platforms 38 .
- the excess copper and tantalum may be removed using any suitable process, such as polishing back the excess material using a chemical-mechanical polishing tool (“CMP”) or an electropolish.
- CMP chemical-mechanical polishing tool
- the process of polishing back includes a first slurry to remove the excess copper so that copper is removed from the top of platform 38 and conductors 60 without eroding conductor 60 in trench 34 .
- a second slurry is used to remove the excess liner that lines platforms 38 .
- the portions of liner 40 that overlie platforms 38 are conventionally removed so that conductors 60 are not electrically coupled to each other by conductive liner 40 .
- fuses are formed after removing the excess materials that overlie platforms 38 .
- the formation of fuses requires separate processing steps. For example, after conductors 60 of damascene structure 10 are formed, separate deposition and patterning steps are required to form fuses.
- a dielectric barrier such as SiN or SiC, is deposited on structure 10 and bond pad openings are patterned and etched to allow electrical probing. After defective bits (memory cells) are identified by the electrical probe, a laser is used to ablate the dielectric barrier over selected fuses.
- Conductor 60 and liner 40 are then removed by wet etch, and another dielectric barrier is deposited to seal the breached fuse region of structure 10 .
- methods are provided for forming fuses by patterning and etching an existing conductive liner instead of using a separately added layer of material. This is advantageous because, according to one embodiment, the fabrication of semiconductor devices requiring fuses is simplified by avoiding extra manufacturing steps. According to another embodiment, the blowing of the fuse is facilitated because the material used to form the fuse is relatively thin. According to another embodiment, having a thin fuse allows the removal of the fuse using electrical current as well as laser exposure, which improves reliability and greatly simplifies electrical programming at test. According to another embodiment, contamination of the semiconductor structure associated with the blowing of the fuses is reduced.
- the coverage requirement for any protective dielectric layer is reduced because of the amount of topology, such as trenches, that results from blowing fuses using laser exposure is reduced. Additional details of example embodiments of the methods are described in greater detail below in conjunction with portions of FIG. 1A and FIGS. 1B through 3.
- Damascene structure 10 of FIG. 1A shows liner 40 that is left in place by omitting the step of removing portions of liner 40 that overlie platforms 38 .
- more than one liner 40 having various levels of conductivity may overlie dielectric layer 30 .
- a mask 50 is used to protect portions of liner 40 that may serve as fuses for conductors 60 .
- a portion of liner 40 that overlies platform 38 is protected by mask 50 that covers lined platform 38 .
- FIG. 1B shows one lined platform 38 that is positioned between two conductors 60 , more than two conductors 60 may be defined by dielectric layer 30 that are separated by other platforms 38 .
- Mask 50 may be formed from any suitable material for protecting liner 38 , such as photoresist. In one embodiment, as shown in FIG. 1B, the length of mask 50 exceeds the length of lined platform 38 so that portions of conductors 60 that are separated by lined platform 38 are also covered. Having a slightly excessive coverage of lined platform 38 may be desirable where a less precise etching process, such as wet etching, is used.
- FIG. 1C the portions of liner 40 that were not protected by mask 50 are etched away using any suitable processes, such as wet etching or dry/plasma etching.
- mask 50 is removed from lined platform 38 . The removal of mask 50 exposes the portion of liner 40 that was protected. The protected portion of liner 40 may now serve as a fuse 40 a .
- FIG. 2 which is a schematic top view of a plurality of fuses 40 a , formed fuses 40 a electrically couple their respective conductors 60 through remaining portions of liner 40 that overlie trenches 34 .
- fuse 40 a may be configured to electrically uncouple conductors 60 .
- the electrical uncoupling may be accomplished by blowing a portion of fuse 40 a so that fuse 40 a is inoperable to carry electrical current between conductors 60 .
- “Blowing” a fuse refers to destroying a portion or all of fuse 40 a by disturbing the integrity of fuse 40 a in any manner so that fuse 40 a is no longer operable to carry electrical current.
- fuse 40 a may be blown by burning off, removing, severing, ablating, etching, or sputtering any part of fuse 40 a .
- the uncoupling of fuse 40 a may be accomplished by blowing fuse 40 a using any suitable method.
- a surge of electrical current may be used to create a space 70 in fuse 40 a , thereby blowing fuse 40 a .
- a manufacturer may blow fuse 40 a during final test of a memory, such as an SRAM, and avoid the initial electrical probe that is needed for laser trim of fuses.
- a laser beam may burn off a portion of fuse 40 a to create space 70 that electrically decouples conductors 60 .
- blowing fuse 40 a does not generate additional topology, such as trenches, that may need to be covered by an additional layer of dielectric material to keep out contaminants. In some embodiments where fuse 40 a is relatively thin, the level of particle contamination caused by blowing fuse 40 a is reduced.
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Abstract
According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
Description
- This invention relates generally to the field of electronic devices and more particularly to an improved method for forming a fuse in a semiconductor device.
- Certain semiconductor devices, such as dynamic random access memories (“DRAMs”) and static random access memories (“SRAMs”), are designed with redundant rows and/or columns of memory cells. If a memory cell of a row/cell is found to be defective during a test, then the defective memory cell is disconnected by blowing a conductive fuse of the row or column containing the defective cell. Having the redundant rows and/or columns allows a designer to disconnect a defective memory cell without reducing the number of rows/columns below the required number. Typically, a conducting fuse is made of a polysilicon or metal film formed on a dielectric layer. A laser is used to ablate the fuse material and any protective dielectric layer that is covering the fuse material.
- Traditionally, the formation of fuses in semiconductor structures, including a damascene structure, requires depositing, patterning, and etching a polysilicon or metal layer. Blowing the fuses formed from performing such steps may increase contamination because particles of the blown fuse and the protective dielectric material may be scattered to other columns/rows. Further, for the case of a damascene structure, empty trenches may result from removal of the fuse material, which may create difficult topography for any subsequent dielectric deposition and may lead to reliability problems.
- According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The surface defines at least two trenches separated by a platform. Each of the defined trenches includes a conductor that overlies the conductive liner and is positioned within the each of the defined trenches. The conductor is electrically coupled to the conductive liner. The method also includes covering the portion of the conductive liner overlying the platform after lining the surface. The method also includes removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
- Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, the fabrication of semiconductor devices requiring fuses is simplified by avoiding extra deposition steps and instead forming the fuses using an existing liner or barrier of the semiconductor structure. According to another embodiment, the blowing of the fuse is facilitated because the material used to form the fuse is relatively thin. According to another embodiment, having a thin fuse allows the blowing of the fuse using electrical current as well as laser exposure, which reduces the level of contamination, improves reliability and greatly simplifies electrical programming at test. According to another embodiment, the coverage requirement for any protective dielectric layer is reduced because of the amount of topology, such as trenches, that results from blowing fuses using laser exposure is reduced.
- Other technical advantages may be readily ascertained by one of skill in the art.
- Reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numbers represent like parts, in which:
- FIGS. 1A through 1D are a series of schematic cross-sectional diagrams illustrating one embodiment of a semiconductor device constructed according to the teachings of the present invention;
- FIG. 2 is a schematic top view diagram illustrating one embodiment of a semiconductor device constructed according to the teachings of the present invention; and
- FIG. 3 is a schematic cross-sectional diagram illustrating one embodiment of a semiconductor device constructed according to the teachings of the present invention, wherein a fuse is blown.
- Embodiments of the invention are best understood by referring to FIGS. 1A through 3 of the drawings, like numerals being used for like and corresponding parts of the various drawings.
- FIG. 1A is a schematic cross-sectional diagram illustrating one embodiment of a
semiconductor device 10 that may benefit from the teachings of the present invention.Device 10 includes asubstrate 20 and adielectric layer 30 that overliessubstrate 20. The surface ofdielectric layer 30 defines a plurality oftrenches 34 that are separated by aplatform 38.Trenches 34 may also be referred to as grooves or holes. Although FIG. 1A shows only twotrenches 34,device 10 may have more than twotrenches 34 where eachtrench 34 is separated from a neighboringtrench 34 by aparticular platform 38. Also, the surface ofdielectric layer 30 may define more than oneplatform 38.Device 10 also comprises aconductive layer 40 that lines the surface ofdielectric layer 30. “Lining” refers to providing a layer that directly overlies the surface and the elements that are defined by the surface. Eachdefined trench 34 that is lined with a portion ofconductive liner 40 includes aconductor 60. In one embodiment, each linedtrench 34 is filled with aconductor 60, whereconductor 60 overlies the portion ofconductive liner 40 that lines the linedtrench 34 and is positioned within the linedtrench 34. - One example of
device 10 described at FIG. 1A is referred to as a damascene structure. The term “damascene structure” will be used hereinafter as an example to refer todevice 10 shown in FIG. 1A. However, any semiconductor device having a liner or a barrier between its active regions, such asconductors 60, and its dielectric layer, such asdielectric layer 30, may bedevice 10. -
Dielectric layer 30 may be any suitable electrical insulator. For example,dielectric layer 30 may be formed from a layer of oxide.Conductive liner 40 may be formed from any suitable conductive material, such as tantalum, Tungsten, Ruthenium, Cobalt, TaN, WN, COWP, or a suitable combination of such materials.Conductor 60 may be formed from any suitable conductive material, such as copper or aluminum. In one embodiment, the materials for formingconductor 60 andconductive liner 40 may be chosen so that the material forliner 40 has a lower conductivity than that of the material forconductors 60. For example, although tantalum is a conductive material, it has a lower conductivity than copper. In one embodiment, tantalum may be used to formliner 40 and copper may be used to formconductor 60 so thatliner 40 has a lower conductivity thanconductor 60. - A damascene structure, such as
damascene structure 10, may be fabricated as follows:Trenches 34 are patterned and etched intodielectric layer 30. Thenliner 40 is deposited onto the surface ofdielectric layer 30 to line the surface using any suitable process, such as physical vapor deposition (“PVD”) or chemical vapor deposition (“CVD”). PVD liners are typically around 20-100 nanometers thick on a surface pedestal, such asplatforms 38, but may be thinner (approximately 5-25 nm) along the wall oftrenches 34 due to non-conformal deposition. CVD liners are typically conformal; thus, a liner having a relatively uniform thickness of approximately 10-20 nanometers may be on bothplatforms 38 and walls oftrenches 34. However, CVD liners may be thinner than 5 nanometers. - A diffusion barrier, such as
liner 40, may be necessary where the material that is used to filltrenches 34 has a tendency to diffuse intodielectric layer 30. One such material is copper. Afterliner 40 is used to line the surface ofdielectric layer 30 as a barrier against copper diffusion, a thin copper seed layer (not explicitly shown) is deposited and copper is electroplated onto the cooperseed overlying liner 40 so that linedtrenches 34 may be filled with copper to formcopper conductors 60. Copper is used herein as an example material for formingconductors 60 that has a tendency to diffuse intodielectric layer 30; however, other conductive material that may benefit from having a barrier or adhesion layer may also be used. In some embodiments, the copper seed layer may be omitted and copper electroplating is performed directly ontoliner 40. The electroplating of copper generally overflowstrenches 34 and deposits the copper onto the entire surface ofliner 40, including the portions that overlieplatforms 38. The deposition of material forliner 40, such as tantalum, also deposits excess tantalum ontoplatforms 38. - The excess copper and tantalum may be removed using any suitable process, such as polishing back the excess material using a chemical-mechanical polishing tool (“CMP”) or an electropolish. The process of polishing back includes a first slurry to remove the excess copper so that copper is removed from the top of
platform 38 andconductors 60 without erodingconductor 60 intrench 34. A second slurry is used to remove the excess liner that linesplatforms 38. The portions ofliner 40 that overlieplatforms 38 are conventionally removed so thatconductors 60 are not electrically coupled to each other byconductive liner 40. - Conventionally, fuses are formed after removing the excess materials that overlie
platforms 38. The formation of fuses requires separate processing steps. For example, afterconductors 60 ofdamascene structure 10 are formed, separate deposition and patterning steps are required to form fuses. A dielectric barrier, such as SiN or SiC, is deposited onstructure 10 and bond pad openings are patterned and etched to allow electrical probing. After defective bits (memory cells) are identified by the electrical probe, a laser is used to ablate the dielectric barrier over selected fuses.Conductor 60 andliner 40 are then removed by wet etch, and another dielectric barrier is deposited to seal the breached fuse region ofstructure 10. - According to some embodiments of the present invention, methods are provided for forming fuses by patterning and etching an existing conductive liner instead of using a separately added layer of material. This is advantageous because, according to one embodiment, the fabrication of semiconductor devices requiring fuses is simplified by avoiding extra manufacturing steps. According to another embodiment, the blowing of the fuse is facilitated because the material used to form the fuse is relatively thin. According to another embodiment, having a thin fuse allows the removal of the fuse using electrical current as well as laser exposure, which improves reliability and greatly simplifies electrical programming at test. According to another embodiment, contamination of the semiconductor structure associated with the blowing of the fuses is reduced. In another embodiment, the coverage requirement for any protective dielectric layer is reduced because of the amount of topology, such as trenches, that results from blowing fuses using laser exposure is reduced. Additional details of example embodiments of the methods are described in greater detail below in conjunction with portions of FIG. 1A and FIGS. 1B through 3.
-
Damascene structure 10 of FIG. 1A showsliner 40 that is left in place by omitting the step of removing portions ofliner 40 that overlieplatforms 38. In other embodiments, more than oneliner 40 having various levels of conductivity may overliedielectric layer 30. Referring to FIG. 1B, amask 50 is used to protect portions ofliner 40 that may serve as fuses forconductors 60. For example, a portion ofliner 40 that overliesplatform 38 is protected bymask 50 that covers linedplatform 38. Although FIG. 1B shows one linedplatform 38 that is positioned between twoconductors 60, more than twoconductors 60 may be defined bydielectric layer 30 that are separated byother platforms 38. Some, none, or all of theseother platforms 38 may be protected by different portions ofmask 50, depending on where fuses are needed.Mask 50 may be formed from any suitable material for protectingliner 38, such as photoresist. In one embodiment, as shown in FIG. 1B, the length ofmask 50 exceeds the length of linedplatform 38 so that portions ofconductors 60 that are separated by linedplatform 38 are also covered. Having a slightly excessive coverage of linedplatform 38 may be desirable where a less precise etching process, such as wet etching, is used. - Referring to FIG. 1C, the portions of
liner 40 that were not protected bymask 50 are etched away using any suitable processes, such as wet etching or dry/plasma etching. Referring to FIG, 1D,mask 50 is removed from linedplatform 38. The removal ofmask 50 exposes the portion ofliner 40 that was protected. The protected portion ofliner 40 may now serve as a fuse 40 a. Referring to FIG. 2, which is a schematic top view of a plurality of fuses 40 a, formed fuses 40 a electrically couple theirrespective conductors 60 through remaining portions ofliner 40 that overlietrenches 34. - Referring to FIG. 3, after forming fuse40 a, fuse 40 a may be configured to electrically uncouple
conductors 60. The electrical uncoupling may be accomplished by blowing a portion of fuse 40 a so that fuse 40 a is inoperable to carry electrical current betweenconductors 60. “Blowing” a fuse refers to destroying a portion or all of fuse 40 a by disturbing the integrity of fuse 40 a in any manner so that fuse 40 a is no longer operable to carry electrical current. For example, fuse 40 a may be blown by burning off, removing, severing, ablating, etching, or sputtering any part of fuse 40 a. The uncoupling of fuse 40 a may be accomplished by blowing fuse 40 a using any suitable method. In some embodiments where fuse 40 a is relatively thin, a surge of electrical current may be used to create aspace 70 in fuse 40 a, thereby blowing fuse 40 a. This is advantageous because a manufacturer may blow fuse 40 a during final test of a memory, such as an SRAM, and avoid the initial electrical probe that is needed for laser trim of fuses. In another example, a laser beam may burn off a portion of fuse 40 a to createspace 70 that electrically decouplesconductors 60. Because fuse 40 a is positioned onplatform 38, which, in some embodiments, is the planar surface ofdevice 10, blowing fuse 40 a does not generate additional topology, such as trenches, that may need to be covered by an additional layer of dielectric material to keep out contaminants. In some embodiments where fuse 40 a is relatively thin, the level of particle contamination caused by blowing fuse 40 a is reduced. - Although the present invention has been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
1. A method comprising:
lining, with a conductive liner, a surface of a dielectric layer, the surface defining at least two trenches separated by a platform, each of the defined trenches including a conductor that overlies the conductive liner and is positioned within the each of the defined trenches, the conductor electrically coupled to the conductive liner;
after lining the surface, covering the portion of the conductive liner overlying the platform; and
removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
2. The method of claim 1 , wherein lining the surface of the dielectric layer with the conductive liner comprises:
depositing the conductive liner over the surface;
depositing a material over the conductive liner, the material used to form the conductor; and
removing a portions of the material that overlies the platform.
3. The method of claim 1 , and further comprising forming the conductive liner from tantalum.
4. The method of claim 1 , wherein the conductors are formed from copper.
5. The method of claim 1 , wherein lining the surface of the dielectric layer comprises depositing, on the surface of the dielectric layer, the conductive liner so that the thickness of the conductive liner is less than 100 nanometers.
6. The method of claim 1 , wherein covering the portion of the conductive liner comprises providing, on the portion of the conductive liner, a mask formed from photoresist.
7. The method of claim 1 , wherein covering the portion of the conductive liner comprises providing, on the portion of the conductive liner, a cover, and further comprising removing the cover from the portion of the conductive liner.
8. The method of claim 1 , and further comprising blowing the portion of the conductive liner that was covered so that the portion of the conductive liner that was covered is not operable to carry electric current.
9. The method of claim 1 , and further comprising:
determining that a defect exists in a semiconductor device in which the conductive liner is disposed; and
blowing the portion of the conductive liner that was covered so that the portion of the conductive liner that was covered is not operable to carry electric current.
10. A method comprising:
lining, with a conductive liner, a surface of a dielectric layer, the surface defining a first trench, a second trench, and a third trench, the first and the second trenches separated by a first platform, the second and the third trenches separated by a second platform, each of the first, second, and third trenches including a conductor that overlies the conductive liner and is positioned within the each of the first, second, and third trenches, the conductor electrically coupled to the conductive liner;
after lining the surface, covering the portion of the conductive liner overlying the first platform; and
removing the uncovered portion of the conductive liner overlying the second platform while leaving in place the covered portion of the conductive liner overlying the first platform.
11. The method of claim 10 , wherein the conductor is conductive, and further comprising providing the conductive liner having a lower level of conductivity than the conductivity of the conductor.
12. The method of claim 10 , and further comprising forming the conductive liner from tantalum.
13. The method of claim 10 , wherein the conductors are formed from copper.
14. The method of claim 10 , wherein lining the surface of the dielectric layer comprises depositing, on the surface of the dielectric layer, the conductive liner so that the thickness of the conductive liner is less than 100 nanometers.
15. The method of claim 10 , wherein covering the portion of the conductive liner comprises providing a mask overlying the first platform, the mask formed from photoresist.
16. The method of claim 10 , wherein covering the portion of the conductive liner comprises masking, with a mask, the portion of the conductive liner, and further comprising removing the mask from the portion of the conductive liner.
17. The method of claim 10 , and further comprising blowing the portion of the conductive liner that was covered so that the portion of the conductive liner that was covered is not operable to carry electric current.
18. The method of claim 10 , and further comprising:
determining that a defect exists in a semiconductor device in which the conductive liner is disposed; and
blowing the portion of the conductive liner that was covered so that the portion of the conductive liner that was covered is not operable to carry electric current.
19. A method for forming a fuse for a semiconductor device, comprising:
providing a dielectric layer having a surface that defines at least two trenches separated by a particular one of a plurality of platforms;
lining, with a conductive liner, the surface of the dielectric layer;
depositing a conductive material on the conductive liner, the conductive material filling the trenches;
removing the conductive material from the plurality of platforms;
after removing the conductive material, covering the portion of the conductive liner overlying the particular one of the plurality of platforms; and
forming a fuse with the portion of the conductive liner that was covered by removing any uncovered portions of the conductive liner while leaving in place the portion of the conductive liner that was covered.
20. The method of claim 19 , and further comprising blowing the fuse.
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US10/188,528 US6677188B1 (en) | 2002-07-03 | 2002-07-03 | Methods for forming a fuse in a semiconductor device |
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US10/188,528 US6677188B1 (en) | 2002-07-03 | 2002-07-03 | Methods for forming a fuse in a semiconductor device |
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US20080079160A1 (en) * | 2006-10-02 | 2008-04-03 | Gunther Ruhl | System for separation of an electrically conductive connection |
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US20050250256A1 (en) * | 2004-05-04 | 2005-11-10 | Bing-Chang Wu | Semiconductor device and fabricating method thereof |
Citations (1)
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US6498385B1 (en) * | 1999-09-01 | 2002-12-24 | International Business Machines Corporation | Post-fuse blow corrosion prevention structure for copper fuses |
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US6498385B1 (en) * | 1999-09-01 | 2002-12-24 | International Business Machines Corporation | Post-fuse blow corrosion prevention structure for copper fuses |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080079160A1 (en) * | 2006-10-02 | 2008-04-03 | Gunther Ruhl | System for separation of an electrically conductive connection |
DE102006046790A1 (en) * | 2006-10-02 | 2008-04-10 | Infineon Technologies Ag | Integrated component and method for separating an electrically conductive connection |
US7799583B2 (en) | 2006-10-02 | 2010-09-21 | Infineon Technologies Ag | System for separation of an electrically conductive connection |
DE102006046790B4 (en) * | 2006-10-02 | 2014-01-02 | Infineon Technologies Ag | Integrated component and method for separating an electrically conductive connection |
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