US20040004265A1 - Flash memory devices having self aligned shallow trench isolation structures and methods of fabricating the same - Google Patents
Flash memory devices having self aligned shallow trench isolation structures and methods of fabricating the same Download PDFInfo
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- US20040004265A1 US20040004265A1 US10/455,679 US45567903A US2004004265A1 US 20040004265 A1 US20040004265 A1 US 20040004265A1 US 45567903 A US45567903 A US 45567903A US 2004004265 A1 US2004004265 A1 US 2004004265A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to integrated circuit devices and methods of fabricating the same, and, more particularly, to flash memory devices and methods of fabricating the same.
- Integrated circuit devices using self-aligned shallow trench isolation technology may provide a reduced number of fabrication steps during manufacture of the integrated circuit device, enhanced reliability of a gate oxide layer and/or narrower threshold voltage distribution in a cell array. Accordingly, to improve performance of conventional flash memory devices, self-aligned shallow trench isolation technology has been applied to highly integrated flash memory devices typically requiring low fabrication costs and high reliability.
- FIG. 1 is a top plan view illustrating conventional flash memory devices
- FIGS. 2 and 3 are cross-sectional views illustrating conventional flash memory devices, taken along lines A-A′ and B-B′ of FIG. 1, respectively.
- a plurality of device isolation patterns are provided on an integrated circuit substrate 2 to define a plurality of active regions.
- a control gate electrode 16 crosses over the device isolation patterns.
- a floating gate pattern 9 is disposed between the control gate electrode 16 and the active regions.
- the flash memory device further includes a trench oxide layer 6 , an insulating pattern 14 and an intergate dielectric pattern 13 .
- the device isolation pattern includes the trench oxide layer 6 and the insulating pattern 14 .
- the trench oxide layer 6 is provided on sidewalls of a trench region provided in the integrated circuit substrate.
- the insulating pattern 14 is provided in the trench region.
- the floating gate pattern 9 includes a lower gate pattern 4 a and an upper gate pattern 8 .
- the lower gate pattern 4 a is provided between the device isolation patterns, and the upper gate pattern 8 is provided on the lower gate pattern 4 a .
- a portion of the upper gate pattern 8 may extend on a surface of the device isolation pattern.
- the intergate dielectric pattern 13 is disposed between the control gate electrode 16 and the floating gate pattern 9 .
- the intergate dielectric pattern 13 typically includes first 10 , second 11 and third 12 layers of silicon oxide, silicon nitride and silicon oxide, respectively.
- the control gate electrode 16 typically includes first and second layers, for example, a polysilicon layer 14 on the intergate dielectric pattern 13 and a metal silicide layer 15 on the polysilicon layer 14 .
- the flash memory device further includes a tunnel insulating pattern 3 and source/drain regions S/D.
- the tunnel insulating pattern 3 is provided between the floating gate pattern 9 and the integrated circuit substrate 2 .
- the source/drain regions S/D are provided in the integrated circuit substrate 2 adjacent to the floating gate pattern 9 to be aligned to sidewalls of the floating gate pattern 9 .
- conventional flash memory devices may include a bird's beak 7 (thickening of the trench oxide layer 6 ) at the edge of the tunnel insulating pattern 3 adjacent to the trench oxide layer 6 .
- methods of forming conventional devices include forming the tunnel insulating pattern 3 , a lower conductive pattern 4 and a hard mask pattern 5 on the integrated circuit substrate 2 .
- a trench may be formed on the integrated circuit substrate and may be aligned to sidewalls of the hard mask pattern 5 .
- a thermal oxidization process may be applied to the integrated circuit substrate 2 including having the trench to form the trench oxide layer 6 on sidewalls and a bottom of the trench.
- the sidewalls of the lower conductive pattern 4 may be oxidized resulting in the bird's beak 7 at the edge of the tunnel insulating pattern 3 caused by an oxygen atom diffused through an interface of the tunnel insulating pattern 3 and the lower conductive pattern 4 .
- the flash memory device includes a gate sidewall oxide layer 19 on the sidewalls of the control gate electrode 16 and the floating gate pattern 9 .
- the gate sidewall oxide layer 19 may reduce the amount of etch damage of the sidewalls of the control gate electrode 16 and the floating gate pattern 9 .
- oxygen atoms may be diffused through an interface of the intergate dielectric pattern 13 to oxidize the control gate electrode 16 and the floating gate pattern 9 .
- the silicon oxide layer at the edge 18 of the intergate dielectric pattern 13 may become thicker (form a bird's beak) relative to the other portions of the intergate dielectric pattern 13 .
- the oxygen atom may be diffused through the interface of the tunnel insulating pattern 3 adjacent to the source/drain regions S/D.
- the edge 17 of the tunnel insulating pattern adjacent to the source/drain region S/D may also become thicker (form a bird's beak).
- the presence of the bird's beak on the tunnel insulating pattern and the intergate dielectric pattern may cause the reliability of the flash memory device to deteriorate and may cause an increase in the distribution of the threshold voltage in the cell array.
- the presence of the bird's beak on the intergate dielectric pattern may lower a coupling ratio of the flash memory device, an erase speed of the flash memory device and a write speed of the flash memory device.
- Some embodiments of the present invention provide flash memory devices including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate.
- a trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure.
- a portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer.
- the flash memory device further comprises a tunnel insulating pattern between the integrated circuit substrate and the stack gate structure.
- the stack gate structure may be a floating gate.
- the floating gate may include a lower gate pattern on the tunnel insulating layer and an upper gate pattern on the lower gate pattern.
- the first nitrogen doped layer may extend on a sidewall of the lower gate pattern and/or a sidewall of the tunnel insulating layer.
- the trench isolation region may include a trench floor.
- the flash memory device may further include a trench insulating layer on the trench floor and a lower portion of the trench sidewall and the first nitrogen doped layer may extend on an upper portion of the trench sidewall.
- the flash memory device may further include a control gate electrode on the upper gate pattern of the floating gate.
- An intergate dielectric pattern may be provided between the upper gate pattern of the floating gate and the control gate electrode.
- the intergate dielectric pattern may include first, second and third layers.
- Second, third, fourth and fifth nitrogen doped layers may be provided on a surface of the upper gate pattern, a surface of the first layer, a surface of the second layer and a surface of the third layer, respectively.
- the first layer may include silicon oxide
- the second layer may include silicon nitride
- the third layer may include silicon oxide.
- the flash memory device further includes an insulating pattern in the trench isolation region.
- the insulating pattern may contact the first nitrogen doped layer on the sidewall of the lower gate pattern and the sidewall of the tunnel insulating pattern.
- the second nitrogen doped layer may extend onto a surface of the insulating pattern.
- the upper gate pattern may be wider than the lower gate pattern such that the upper gate pattern extends on a surface of the insulating pattern.
- FIG. 1 is a top plan view illustrating conventional flash memory devices
- FIG. 2 is a cross-sectional view taken along the line A-A′ of FIG. 1 of conventional flash memory devices
- FIG. 3 is a cross-sectional view taken along the line B-B′ of FIG. 1 of conventional flash memory devices
- FIG. 4 is a cross-sectional view taken along the line A-A′ of FIG. 1 of conventional flash memory devices
- FIG. 5 is a perspective view of flash memory device according to some embodiments of the present invention.
- FIGS. 6 through 14 are cross sectional views illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention.
- FIGS. 15 through 19 and FIGS. 20A through 24A are cross sectional views taken along a line A-A′ of the FIG. 5 illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention.
- FIGS. 20B through 24B and FIGS. 25 and 26 are cross sectional views, taken along a line B-B′ of FIG. 5 illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention.
- first, second etc. are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.
- Embodiments of the present invention will be described below with respect to FIGS. 5 through 26.
- Embodiments of the present invention provide flash memory devices including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate.
- a trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure.
- a portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer.
- certain embodiments of the present invention provide nitrogen doped layers on other surfaces of the flash memory devices. The presence of the nitrogen doped layers may reduce the likelihood of oxygen atoms diffusing into a control gate pattern and/or a floating gate pattern of the flash memory device. Accordingly, flash memory devices according to embodiments of the present invention may provide improved device characteristics as discussed further below.
- flash memory devices include device isolation patterns disposed parallel to an integrated circuit substrate 100 .
- the device isolation patterns may include, for example, a trench oxide layer 118 and an insulating pattern 120 .
- the trench oxide layer 118 may be provided on sidewalls and a bottom of a trench region 113 a and the insulating pattern 120 is provided in the trench region 113 a .
- the trench oxide layer 118 is not formed on an entire surface of the sidewalls of the trench region 113 a .
- an upper portion of the sidewall of the trench region 113 a that is does not include the trench oxide layer 118 may contact the insulating pattern 120 .
- flash memory devices may further include a control gate electrode 148 and a floating gate pattern 150 .
- the control gate electrode 148 crosses over the device isolation patterns.
- the control gate electrode 148 may include one or more layers without departing from the teachings of the present invention.
- the control gate electrode 148 may include a single conductive layer or may include a polycide layer having a polysilicon layer 144 and a metal silicide layer 146 on the polysilicon layer as illustrated in FIG. 5.
- the floating gate pattern 150 is provided between the control gate electrode 148 and the integrated circuit substrate 100 .
- the floating gate pattern 150 is further provided on the integrated circuit substrate between the device isolation patterns.
- the floating gate pattern 150 may include a lower gate pattern 108 b and an upper gate pattern 112 a .
- the upper gate pattern 112 a is provided on the lower gate pattern 108 b .
- the edge of the upper gate pattern 112 a may contact a surface of the insulating pattern 120 as illustrated in FIG. 5.
- flash memory devices further include an intergate dielectric pattern 142 a and a tunnel insulating pattern 102 a .
- the intergate dielectric pattern 142 a is provided between the control gate electrode 148 and the floating gate pattern 150 .
- the intergate dielectric pattern 142 a may included first 128 a , second 134 a and third 136 a layers, for example, a first silicon oxide layer, a silicon nitride layer on the first silicon layer and a second silicon oxide layer on the silicon nitride layer.
- the tunnel insulating pattern 102 a is provided between the floating gate pattern 150 and the integrated circuit substrate 100 .
- the intergate dielectric pattern 142 a may be provided on the floating gate pattern 150 and the control gate electrode 148 may be provided on the intergate dielectric pattern 142 a . Accordingly, together the floating gate pattern 150 , the intergate dielectric pattern 142 a and the control gate electrode may provide a stack gate.
- the insulating pattern 120 may have sidewalls that become wider at a top portion, i.e. are vertically protruded.
- the lower gate pattern 108 b is provided between the protruded sidewalls of adjacent insulating patterns 120 as illustrated in FIG. 5. Accordingly, sidewalls of the floating gate pattern 150 may contact the sidewalls of the insulating pattern 120 , i.e. the device isolation pattern.
- the flash memory device further includes source and drain regions 156 .
- the source and drain regions 156 are provided in the integrated circuit substrate adjacent to the floating gate pattern 150 and may be aligned to the sidewalls of the floating gate pattern 150 .
- the flash memory device includes further includes nitrogen doped layers N/L.
- the nitrogen doped layers N/L may block a diffusion route of oxygen during a fabrication process, which may improve the overall functionality of the device.
- a first nitrogen doped layer N/L may be provided on the upper sidewall of the trench region 113 a , sidewalls of the tunnel insulating pattern 102 a and/or sidewalls of the lower gate pattern 108 b , which may be sequentially aligned to be in contact with the insulating pattern 120 . Accordingly, it may be possible to reduce the likelihood of the formation of a bird's beak as discussed above at the edge of the tunnel insulating layer 102 a adjacent to the device isolation pattern.
- the flash memory device may have a uniform tunnel insulating layer 102 a , i.e. no thickening of the tunnel insulating layer 102 a.
- second, third, fourth and fifth nitrogen doped layers N/L may be provided on an upper surface of the upper gate pattern 112 a of the floating gate pattern 150 , the first layer 128 a of the intergate dielectric pattern 142 a , the second layer 134 a of the intergate dielectric pattern 142 a and the third layer 136 a of the intergate dielectric pattern 142 a , respectively.
- the nitrogen doped layers N/L provided on the surface of the floating gate pattern 150 , the first silicon oxide layer 128 a and the second silicon oxide layer 136 a may reduce the amount of oxygen atoms diffused into the floating gate pattern 150 and/or the control gate electrode 148 . Accordingly, it may be possible to reduce the likelihood that the edge of the floating gate pattern 150 and/or the control gate electrode 148 will be oxidized. Therefore, the intergate dielectric pattern 142 a may have a uniform thickness.
- a sixth nitrogen doped layer N/L may be formed on sidewalls of the stack gate pattern and on an upper surface of the tunnel insulating pattern 102 a .
- the nitrogen doped layer N/L formed on the upper surface of the tunnel insulating pattern 102 a may reduce the likelihood that oxygen atoms will penetrate through interfaces between the tunnel insulating pattern 102 a and the floating gate pattern 150 .
- the tunnel insulating pattern 102 a may be provided on the integrated circuit substrate between the stack gate patterns or may be provided between the floating gate pattern 150 and the integrated circuit substrate 100 .
- the sixth nitrogen doped layer N/L formed on the sidewalls of the stack gate pattern may be provided before the gate sidewall oxidization process.
- the sixth nitrogen doped layer N/L may be provided on the sidewalls of the tunnel insulating pattern 102 a adjacent to the source/drain region 156 .
- oxygen atoms will be diffused through the sidewalls of the tunnel insulating pattern 102 a.
- FIG. 5 the perspective view of the flash memory device illustrated in FIG. 5 is provided for exemplary purposes only and that embodiments of the present invention are not limited to this configuration. Features may be added and/or deleted from the flash memory device illustrated in FIG. 5 without departing from the teachings of the present invention.
- flash memory devices include a tunnel insulating layer on an integrated circuit substrate 20 , a lower conductive layer on the tunnel insulating layer and a mask layer, for example, a hard mask layer, on the lower conductive layer in order to form a self-aligned shallow trench isolation structure.
- the mask layer, the lower conductive layer and the tunnel insulating layer may be successively patterned to form a tunnel insulating pattern 22 on the integrated circuit substrate 20 , a lower conductive pattern 28 on the tunnel insulating pattern 22 and a mask pattern 30 , for example, a hard mask pattern, on the lower conductive pattern.
- the lower conductive pattern 28 may include, for example, polysilicon.
- the integrated circuit substrate 20 may be partially etched using, for example, the hard mask pattern 30 as an etch mask, to form a pre-trench region 32 aligned to sidewalls of the hard mask pattern 30 .
- a nitrogen doped layer 36 may be formed on the sidewalls of the lower conductive pattern 28 , the sidewalls of the tunnel insulating pattern 22 and the pre-trench region 32 .
- the nitrogen doped layer 36 may be formed by a plasma nitridation process.
- the integrated circuit substrate 20 including the pre-trench region 32 may be disposed in a process chamber.
- a plasma 34 may be generated in the process chamber using, for example, N 2 , NH 3 , NO and/or N 2 O, as a source gas.
- a plasma density within the process chamber may be set to about 1 ⁇ 10 10 cm ⁇ 3 to about 1 ⁇ 10 12 cm ⁇ 3 and a pressure within the process chamber may be set to about 1 ⁇ 300 mT.
- a temperature of the substrate may be set from about 300° C. to about 900° C. and a plasma exposure time may be set to from about 10 seconds to about 60 seconds.
- the nitrogen doped layer 36 may be formed by applying a remote plasma nitridation process (RPN).
- RPN process is a method of jetting a nitrogen plasma into the process chamber after forming the plasma in remote chamber.
- the plasma exposure time of the substrate may be adjusted and the nitrogen doped layer with a high concentration may be formed at a surface of target materials.
- the plasma density within the process chamber of the RPN process may be set to from about 1 ⁇ 10 10 cm ⁇ 3 to about 1 ⁇ 10 12 cm ⁇ 3
- the pressure within the process chamber of the RPN process may be set to about 1 ⁇ 300 mT.
- the temperature of the substrate may be set to from about 300° C. to about 900° C.
- the plasma exposure time may be set to from about 10 seconds to about 60 seconds.
- the nitrogen doped layer 36 may be formed by annealing the integrated circuit substrate 20 including the pre-trench region 32 in a gas including a nitrogen ambient.
- nitrogen atoms combine with silicon atoms of the tunnel insulating pattern 22 , the lower conductive pattern 28 and the integrated circuit substrate 20 to form the nitrogen doped layer 36 .
- the integrated circuit substrate may be heated at a temperature of from about 300° C. to about 900° C.
- the gas including nitrogen may be, for example, N 2 , NH 3 , NO and/or N 2 O.
- the substrate 20 including the nitrogen doped layer 36 is etched using, for example, the hard mask pattern 30 as the etch mask, to form a trench region 32 a aligned to the sidewalls of the hard mask pattern 30 .
- the nitrogen doped layer 36 may remain on the sidewalls of the lower conductive pattern 28 , the sidewalls of the tunnel insulating pattern 22 and upper sidewalls of the trench region 32 a as illustrated in FIG. 7.
- a thermal oxidization process may be applied to the integrated circuit substrate to, for example, cure etch damage that may have occurred during etch of the trench region 32 a .
- a trench insulating layer 38 is formed at sidewalls and a bottom of the trench region 32 a .
- the trench insulating layer 38 may, for example, be an oxide layer.
- the trench insulating layer 38 is not formed on the nitrogen doped layer 36 .
- the nitrogen doped layer 36 may reduce the likelihood that oxygen atoms will react with the silicon atom of the substrate 20 and the silicon atom of the lower conductive pattern 28 .
- the nitrogen doped layer 36 formed on the sidewalls of the tunnel insulating pattern 22 may reduce the likelihood that oxygen atoms will be diffused through interfaces of the tunnel insulating layer 22 .
- it may be possible to reduce the likelihood that a bird's beak will form, i.e. that the edge of the tunnel insulating pattern 22 will become thicker.
- an insulating layer is formed on the surface of the substrate.
- the insulating layer may be planarized by, for example, a chemical mechanical polishing (CMP) process and the hard mask pattern 30 may be removed to form an insulating pattern 40 in the trench region 32 a .
- the insulating pattern 40 and the trench insulating layer 38 constitute a device isolation pattern.
- the insulating pattern 40 may include a single layer or multiple layers.
- the insulating layer may include a silicon oxide layer, for example, a high-density plasma oxide layer or a plasma enhanced oxide layer (PEOX).
- a PEOX typically has excellent burial characteristic.
- a thin silicon nitride layer may be formed before the oxide layer is formed.
- a conductive layer is formed on the surface of the integrated circuit substrate 20 where the hard mask pattern 30 has been removed.
- the conductive layer is patterned to form an upper conductive pattern 42 on the lower conductive pattern 28 .
- the upper conductive pattern 42 may include, for example, a similar material to the material of the lower conductive pattern 28 , for example, polysilicon. As illustrated in FIG. 9, an edge of the upper conductive pattern 42 may extend onto a surface of the insulating pattern 40 , for example, an oxide pattern. This overlap may reduce the likelihood that the lower conductive pattern 28 will be damaged by inadvertent misalignment of aspects of the device.
- one or more nitrogen doped layers may reduce the likelihood that oxygen atoms will be diffused through the interfaces of the tunnel insulating pattern 22 during thermal oxidization. Thus, it may be possible to reduce the likelihood that a bird's beak will be formed at the edge of the tunnel insulating pattern adjacent to the device isolation pattern.
- FIGS. 10 through 12 cross sectional views illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention will be discussed.
- a nitrogen doped layer 46 is formed on an upper surface of the upper conductive pattern 42 and on an upper surface of the insulating pattern 40 .
- a first layer 48 is formed on a surface of the integrated circuit substrate 20 on the layer 48 .
- a second layer 54 for example, a silicon nitride layer, is formed on the first layer 48 and a nitrogen doped layer 55 is formed on an upper surface of the second layer 54 .
- a third layer 56 for example, a second silicon oxide layer, is formed on the second layer 54 and a nitrogen doped layer 60 is formed on an upper surface of the third layer 56 .
- An intergate dielectric layer 58 includes the first 46 , the second 54 and third 56 layers.
- the nitrogen doped layers 46 , 52 and 60 may be formed using at least one of the methods discussed above with respect to the nitrogen doped layer 36 .
- the nitrogen doped layers 46 , 52 and 60 may be formed by the plasma nitridation process, the RPN process, and/or by annealing the substrate in the gas including the nitrogen ambient.
- a gate conductive layer 68 is formed on the second silicon oxide layer 56 .
- the gate conductive layer 68 , the intergate dielectric layer 58 , the upper conductive pattern 42 , and the lower conductive pattern 28 are successively patterned to form a stack gate that crosses over the device isolation patterns.
- the stack gate may include a floating gate pattern, an intergate dielectric pattern and a control gate pattern, which are sequentially stacked.
- the tunnel insulating pattern 22 between the stack gate patterns may be etched during formation of the gate stack pattern.
- the gate conductive layer 68 may include polysilicon and/or a polycide layer including a polysilicon layer 64 and a metal silicide layer 66 as illustrated in FIG. 12.
- nitrogen doped layers according to embodiments of the present invention are formed at oxygen diffusion routes such as the interfaces between the first silicon oxide layer and the conductive pattern, the interfaces between the first silicon oxide layer and the silicon nitride layer, and the interfaces between the second silicon oxide layer and the polysilicon layer. Accordingly, for example, during the thermal oxidization process, it may be possible to reduce the possibility of a reaction between the silicon atoms of the gate conductive layer and the upper conductive pattern and the oxygen atoms diffused through the interfaces of the intergate dielectric layer. Thus, the likelihood that the edge of the intergate dielectric layer, for example, the edge of the first silicon oxide layer and the second silicon oxide layer, will become thicker may be reduced.
- the tunnel insulating layer 22 is formed on the integrated circuit substrate 20 .
- the stack gate is formed on the tunnel insulating layer 22 .
- the stack gate includes a floating gate pattern 90 , an intergate dielectric pattern 88 on the floating gate pattern 90 and a control gate pattern 94 on the floating gate pattern 90 .
- the floating gate pattern 90 may include a lower gate pattern 78 and an upper gate pattern 82 . It will be understood that the floating gate pattern 90 may also include a single pattern without departing from the teachings of the present invention.
- the control gate pattern 94 may include a polysilicon layer 84 or a metal polycide layer that includes the polysilicon layer 84 and a metal silicide layer 86 as illustrated in FIG. 13.
- a nitrogen doped layer 96 is formed on sidewalls of the stack gate and on a surface of the tunnel insulating layer 22 .
- the nitrogen doped layer 96 may be formed using the plasma nitridation process, using the RPN process, or by annealing the substrate in the gas including nitrogen ambient as discussed above.
- the integrated circuit substrate 20 may be annealed to, for example, cure damage of the sidewalls of the stack gate pattern caused by the etch of the stack gate.
- Source and drain regions 98 may be formed in the integrated circuit substrate adjacent to the stack gate pattern.
- the tunnel insulating layer 22 is patterned to remain only at a lower portion of the floating gate pattern 90 during formation of the stack gate pattern.
- the nitrogen doped layer 96 may be formed on the sidewalls of the tunnel insulating layer interposed between the floating gate pattern 90 and the integrated circuit substrate 20 .
- the nitrogen doped layer 96 may reduce the likelihood that the silicon atoms of the integrated circuit substrate 20 , the floating gate pattern 90 and the control gate electrode 94 will react with the oxygen atom and form an oxide layer.
- FIGS. 15 through 26 cross sectional views of processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention will be discussed.
- FIGS. 15 through 19 and FIGS. 20A through 24A are cross sectional views taken along a line A-A′ of the FIG. 5.
- FIGS. 20B through 24B and FIGS. 25 and 26 are cross-sectional views taken along a line B-B′ of the FIG. 5
- a tunnel insulating layer 102 is formed on the integrated circuit substrate 100 .
- Nitrogen 104 may be implanted into the tunnel insulating layer 102 to form a nitrogen doped layer 106 on an upper surface of the tunnel insulating layer 102 .
- the nitrogen doped layer 106 may be eliminated without departing from the teachings of the present invention.
- the nitrogen doped layer 106 may be formed by a plasma nitration process, a remote plasma nitridation process (RPN) and/or by annealing the integrated circuit substrate in a gas including nitrogen ambient as discussed above.
- RPN remote plasma nitridation process
- a lower conductive layer 108 and a hard mask layer 110 are sequentially stacked on the tunnel insulating layer 102 .
- the lower conductive layer 108 may include, for example, polysilicon, and the hard mask layer 110 may, for example, include silicon nitride.
- the hard mask layer 110 , the lower conductive layer 108 and the tunnel insulating layer 102 are successively patterned to form a tunnel insulating pattern 102 a , a lower conductive pattern 108 a and a hard mask pattern 110 a , which are sequentially stacked on the integrated circuit substrate 100 .
- the lower conductive pattern 108 a may include, for example, polysilicon.
- the integrated circuit substrate 100 is partially etched using, for example, the hard mask pattern 110 a , as an etch mask to form a pre-trench region 113 aligned to sidewalls of the hard mask pattern 110 a .
- a nitrogen doped layer 116 is formed on sidewalls and a bottom of the lower conductive pattern 108 a , the tunnel insulating pattern 102 a and the pre-trench region 113 .
- the nitrogen doped layer 116 may be formed by the plasma nitridation process, the RPN process and/or by annealing the substrate in a gas including nitrogen ambient as discussed above.
- the integrated circuit substrate 100 is etched using, for example, the hard mask pattern 10 a as the etch mask, to form a trench region 113 a aligned to the sidewalls of the hard mask pattern 110 a .
- the nitrogen doped layer 116 remains on the sidewalls of the lower conductive pattern 108 a , the sidewalls of the tunnel insulating pattern 102 a and the upper sidewalls of the trench region 1113 a.
- a thermal oxidization process is applied to the integrated circuit substrate 100 to, for example, cure etch damage that may have occurred during a the etch of the trench region 113 a .
- a trench oxide layer 118 is formed on the sidewalls and the bottom of the trench region 113 a . As illustrated, the trench oxide layer 118 is not formed on an upper portion of the sidewalls of the trench region 113 a , i.e. the trench oxide layer is not formed on the nitrogen doped layer 116 .
- the nitrogen doped layer 116 may reduced the likelihood that oxygen atoms will react with the silicon atoms of the integrated circuit substrate 100 and the lower conductive pattern 108 a .
- the nitrogen doped layer 116 formed on the upper surface of the tunnel insulating pattern 102 a may reduce the likelihood that the lower conductive pattern 108 a will be oxidized.
- the lower conductive pattern 108 a may include polysilicon, which may be oxidized more easily as compared with a single crystalline silicon.
- an insulating layer is formed on a surface of the integrated circuit substrate 100 .
- the insulating layer is planarized by, for example, a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the hard mask pattern 110 a may be removed to form an insulating pattern 120 in the trench region 113 a .
- the insulating pattern 120 and the trench oxide layer 118 constitute a device isolation pattern.
- the insulating layer may be include a single layer or multiple layers.
- the insulating layer may include a silicon oxide layer such as a high-density plasma oxide layer or a plasma enhanced oxide layer (PEOX). PEOX typically has an excellent burial characteristic.
- a thin silicon nitride layer may be formed before the oxide layer is formed.
- a conductive layer is formed on the surface of the integrated circuit substrate 100 .
- the conductive layer is patterned to form an upper conductive pattern 122 on the lower conductive pattern 108 a .
- the upper conductive pattern 122 may include, for example, polysilicon, similar to the lower conductive pattern 108 a .
- the edge of the upper conductive pattern 122 may extend on a surface of the insulating pattern 120 , for example, an oxide pattern.
- a nitrogen doped layer 126 is formed on an upper surface of the upper conductive pattern 122 and an upper surface of the insulating pattern 120 .
- a first silicon oxide layer 128 is formed on the nitrogen doped layer 126 .
- a nitrogen doped layer 132 is formed on an upper surface of the first silicon oxide layer 128 .
- a silicon nitride layer 134 is formed on the first silicon oxide layer 128 and a nitrogen doped layer 135 is formed on an upper surface of the silicon nitride layer 134 .
- a second silicon oxide layer 136 is formed on the silicon nitride layer 134 and a nitrogen doped layer 140 is formed on an upper surface of the second silicon oxide layer 136 .
- An intergate dielectric layer 142 includes the first silicon oxide layer 128 , the silicon nitride layer 134 and the second silicon oxide layer 136 .
- the nitrogen doped layers 126 , 132 , 135 , and 140 may be formed using the plasma nitridation process, using the RPN process and/or by annealing the substrate in the gas including nitrogen ambient as discussed above.
- a gate conductive layer is formed on the second silicon oxide layer 136 .
- the gate conductive layer, the intergate dielectric layer 142 , the upper conductive pattern 122 and the lower conductive pattern 108 a are successively patterned to form a stack gate crossing over the device isolation patterns.
- the stack gate includes a floating gate pattern 150 , an intergate dielectric pattern 142 a on the floating gate pattern 150 and a control gate pattern 148 on the intergate dielectric pattern 142 a .
- the tunnel insulating layer 102 a between the stack gate patterns may be etched during formation of the stack gate pattern.
- the control gate electrode 148 may include polysilicon or a polycide layer that includes a polysilicon layer 144 and a metal silicide layer 146 as illustrated in the Figures.
- the floating gate pattern 150 may include a lower gate electrode 108 b and an upper gate electrode 112 a on the lower gate electrode.
- a nitrogen doped layer 154 is formed on sidewalls of the stack gate and on the surface of the tunnel insulating layer 102 a .
- the nitrogen doped layer 154 may be formed using the plasma nitridation process, using the RPN process, and/or by annealing the substrate in the gas including nitrogen ambient.
- the tunnel insulating layer 102 a may be patterned to remain only at a lower portion of the floating gate pattern 150 during formation of the gate stack pattern.
- the nitrogen doped layer 154 may be formed on the sidewalls of the tunnel insulating layer interposed between the floating gate pattern 150 and the integrated circuit substrate 100 .
- Source and drain regions S/D may be formed in the integrated circuit substrate adjacent to the stack gate pattern. It will be understood that any subsequent process may be performed using conventional methods.
- flash memory devices include nitrogen doped layers formed in diffusion routes of oxygen atoms to reduce the likelihood of the formation of a bird's beak, i.e, the thickening of the edge of the tunnel insulating pattern and the intergate dielectric pattern. Accordingly, it may be possible to improve endurance and data retention characteristics of the integrated circuit device as well as to reduce a distribution of a threshold voltage in a cell array.
- a uniform edge of the intergate dielectric pattern may provide a lower coupling ratio, enhanced erase speed and enhanced write speed of the flash memory device.
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Abstract
Description
- This application is related to and claims priority from Korean Application No. 2002-38826, filed Jul. 5, 2002, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety.
- The present invention relates to integrated circuit devices and methods of fabricating the same, and, more particularly, to flash memory devices and methods of fabricating the same.
- Integrated circuit devices using self-aligned shallow trench isolation technology may provide a reduced number of fabrication steps during manufacture of the integrated circuit device, enhanced reliability of a gate oxide layer and/or narrower threshold voltage distribution in a cell array. Accordingly, to improve performance of conventional flash memory devices, self-aligned shallow trench isolation technology has been applied to highly integrated flash memory devices typically requiring low fabrication costs and high reliability.
- FIGS. 1 through 4 illustrate aspects of conventional flash memory devices. FIG. 1 is a top plan view illustrating conventional flash memory devices, FIGS. 2 and 3 are cross-sectional views illustrating conventional flash memory devices, taken along lines A-A′ and B-B′ of FIG. 1, respectively.
- Referring now to FIGS. 1 through 3, a plurality of device isolation patterns are provided on an integrated
circuit substrate 2 to define a plurality of active regions. Acontrol gate electrode 16 crosses over the device isolation patterns. Afloating gate pattern 9 is disposed between thecontrol gate electrode 16 and the active regions. As illustrated in FIG. 2, the flash memory device further includes atrench oxide layer 6, aninsulating pattern 14 and an intergatedielectric pattern 13. - The device isolation pattern includes the
trench oxide layer 6 and theinsulating pattern 14. Thetrench oxide layer 6 is provided on sidewalls of a trench region provided in the integrated circuit substrate. Theinsulating pattern 14 is provided in the trench region. Thefloating gate pattern 9 includes alower gate pattern 4 a and anupper gate pattern 8. Thelower gate pattern 4 a is provided between the device isolation patterns, and theupper gate pattern 8 is provided on thelower gate pattern 4 a. A portion of theupper gate pattern 8 may extend on a surface of the device isolation pattern. The intergatedielectric pattern 13 is disposed between thecontrol gate electrode 16 and thefloating gate pattern 9. The intergatedielectric pattern 13 typically includes first 10, second 11 and third 12 layers of silicon oxide, silicon nitride and silicon oxide, respectively. Thecontrol gate electrode 16 typically includes first and second layers, for example, apolysilicon layer 14 on the intergatedielectric pattern 13 and ametal silicide layer 15 on thepolysilicon layer 14. - As further illustrated in FIG. 3, the flash memory device further includes a
tunnel insulating pattern 3 and source/drain regions S/D. Thetunnel insulating pattern 3 is provided between thefloating gate pattern 9 and theintegrated circuit substrate 2. The source/drain regions S/D are provided in the integratedcircuit substrate 2 adjacent to thefloating gate pattern 9 to be aligned to sidewalls of thefloating gate pattern 9. Referring again to FIG. 2, conventional flash memory devices may include a bird's beak 7 (thickening of the trench oxide layer 6) at the edge of thetunnel insulating pattern 3 adjacent to thetrench oxide layer 6. - Referring now to FIG. 4, methods of forming conventional devices include forming the
tunnel insulating pattern 3, a lowerconductive pattern 4 and ahard mask pattern 5 on the integratedcircuit substrate 2. A trench may be formed on the integrated circuit substrate and may be aligned to sidewalls of thehard mask pattern 5. A thermal oxidization process may be applied to the integratedcircuit substrate 2 including having the trench to form thetrench oxide layer 6 on sidewalls and a bottom of the trench. The sidewalls of the lowerconductive pattern 4 may be oxidized resulting in the bird'sbeak 7 at the edge of thetunnel insulating pattern 3 caused by an oxygen atom diffused through an interface of thetunnel insulating pattern 3 and the lowerconductive pattern 4. - Referring again to FIG. 3, the flash memory device includes a gate
sidewall oxide layer 19 on the sidewalls of thecontrol gate electrode 16 and thefloating gate pattern 9. The gatesidewall oxide layer 19 may reduce the amount of etch damage of the sidewalls of thecontrol gate electrode 16 and thefloating gate pattern 9. According to conventional methods of fabrication, during formation of the gatesidewall oxide layer 19, oxygen atoms may be diffused through an interface of the intergatedielectric pattern 13 to oxidize thecontrol gate electrode 16 and thefloating gate pattern 9. Accordingly, the silicon oxide layer at theedge 18 of the intergatedielectric pattern 13 may become thicker (form a bird's beak) relative to the other portions of the intergatedielectric pattern 13. Furthermore, the oxygen atom may be diffused through the interface of thetunnel insulating pattern 3 adjacent to the source/drain regions S/D. Thus, theedge 17 of the tunnel insulating pattern adjacent to the source/drain region S/D may also become thicker (form a bird's beak). - The presence of the bird's beak on the tunnel insulating pattern and the intergate dielectric pattern may cause the reliability of the flash memory device to deteriorate and may cause an increase in the distribution of the threshold voltage in the cell array. In particular, the presence of the bird's beak on the intergate dielectric pattern may lower a coupling ratio of the flash memory device, an erase speed of the flash memory device and a write speed of the flash memory device.
- Some embodiments of the present invention provide flash memory devices including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate. A trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure. A portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer.
- In further embodiments of the present invention, the flash memory device further comprises a tunnel insulating pattern between the integrated circuit substrate and the stack gate structure. The stack gate structure may be a floating gate. The floating gate may include a lower gate pattern on the tunnel insulating layer and an upper gate pattern on the lower gate pattern. The first nitrogen doped layer may extend on a sidewall of the lower gate pattern and/or a sidewall of the tunnel insulating layer.
- In still further embodiments of the present invention, the trench isolation region may include a trench floor. The flash memory device may further include a trench insulating layer on the trench floor and a lower portion of the trench sidewall and the first nitrogen doped layer may extend on an upper portion of the trench sidewall.
- In some embodiments of the present invention, the flash memory device may further include a control gate electrode on the upper gate pattern of the floating gate. An intergate dielectric pattern may be provided between the upper gate pattern of the floating gate and the control gate electrode. The intergate dielectric pattern may include first, second and third layers. Second, third, fourth and fifth nitrogen doped layers may be provided on a surface of the upper gate pattern, a surface of the first layer, a surface of the second layer and a surface of the third layer, respectively. In certain embodiments of the present invention, the first layer may include silicon oxide, the second layer may include silicon nitride and the third layer may include silicon oxide.
- In further embodiments of the present invention, the flash memory device further includes an insulating pattern in the trench isolation region. The insulating pattern may contact the first nitrogen doped layer on the sidewall of the lower gate pattern and the sidewall of the tunnel insulating pattern. The second nitrogen doped layer may extend onto a surface of the insulating pattern. The upper gate pattern may be wider than the lower gate pattern such that the upper gate pattern extends on a surface of the insulating pattern.
- While the present invention is described above primarily with reference to flash memory devices, methods of fabricating flash memory devices are also provided.
- FIG. 1 is a top plan view illustrating conventional flash memory devices;
- FIG. 2 is a cross-sectional view taken along the line A-A′ of FIG. 1 of conventional flash memory devices;
- FIG. 3 is a cross-sectional view taken along the line B-B′ of FIG. 1 of conventional flash memory devices;
- FIG. 4 is a cross-sectional view taken along the line A-A′ of FIG. 1 of conventional flash memory devices;
- FIG. 5 is a perspective view of flash memory device according to some embodiments of the present invention;
- FIGS. 6 through 14 are cross sectional views illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention;
- FIGS. 15 through 19 and FIGS. 20A through 24A are cross sectional views taken along a line A-A′ of the FIG. 5 illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention; and
- FIGS. 20B through 24B and FIGS. 25 and 26 are cross sectional views, taken along a line B-B′ of FIG. 5 illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention.
- The present invention now will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, when a layer is referred to as being “on” another layer, it can be directly on the other layer or intervening layers may be present. In contrast, when a layer is referred to as being “directly on” another layer, there are no intervening layers present. Like reference numerals refer to like elements throughout.
- It will be understood that although terms such as first, second etc. are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention.
- Embodiments of the present invention will be described below with respect to FIGS. 5 through 26. Embodiments of the present invention provide flash memory devices including an integrated circuit substrate and a stack gate structure on the integrated circuit substrate. A trench isolation region is provided on the integrated circuit substrate adjacent the stack gate structure. A portion of the stack gate structure adjacent a trench sidewall of the trench isolation region may include a first nitrogen doped layer. Furthermore, certain embodiments of the present invention provide nitrogen doped layers on other surfaces of the flash memory devices. The presence of the nitrogen doped layers may reduce the likelihood of oxygen atoms diffusing into a control gate pattern and/or a floating gate pattern of the flash memory device. Accordingly, flash memory devices according to embodiments of the present invention may provide improved device characteristics as discussed further below.
- Referring now to FIG. 5, a perspective view of flash memory devices according to embodiments of the present invention will be discussed. As illustrated in FIG. 5, flash memory devices according to embodiments of the present invention include device isolation patterns disposed parallel to an
integrated circuit substrate 100. The device isolation patterns may include, for example, atrench oxide layer 118 and aninsulating pattern 120. Thetrench oxide layer 118 may be provided on sidewalls and a bottom of atrench region 113 a and the insulatingpattern 120 is provided in thetrench region 113 a. As illustrated, thetrench oxide layer 118 is not formed on an entire surface of the sidewalls of thetrench region 113 a. Thus, an upper portion of the sidewall of thetrench region 113 a that is does not include thetrench oxide layer 118 may contact the insulatingpattern 120. - As further illustrated in FIG. 5, flash memory devices according to embodiments of the present invention may further include a
control gate electrode 148 and a floatinggate pattern 150. Thecontrol gate electrode 148 crosses over the device isolation patterns. It will be understood that thecontrol gate electrode 148 may include one or more layers without departing from the teachings of the present invention. For example, thecontrol gate electrode 148 may include a single conductive layer or may include a polycide layer having apolysilicon layer 144 and ametal silicide layer 146 on the polysilicon layer as illustrated in FIG. 5. The floatinggate pattern 150 is provided between thecontrol gate electrode 148 and theintegrated circuit substrate 100. The floatinggate pattern 150 is further provided on the integrated circuit substrate between the device isolation patterns. The floatinggate pattern 150 may include alower gate pattern 108 b and anupper gate pattern 112 a. Theupper gate pattern 112 a is provided on thelower gate pattern 108 b. The edge of theupper gate pattern 112 a may contact a surface of the insulatingpattern 120 as illustrated in FIG. 5. - As still further illustrated in FIG. 5, flash memory devices according to embodiments of the present invention further include an
intergate dielectric pattern 142 a and atunnel insulating pattern 102 a. Theintergate dielectric pattern 142 a is provided between thecontrol gate electrode 148 and the floatinggate pattern 150. Theintergate dielectric pattern 142 a may included first 128 a, second 134 a and third 136 a layers, for example, a first silicon oxide layer, a silicon nitride layer on the first silicon layer and a second silicon oxide layer on the silicon nitride layer. Thetunnel insulating pattern 102 a is provided between the floatinggate pattern 150 and theintegrated circuit substrate 100. Theintergate dielectric pattern 142 a may be provided on the floatinggate pattern 150 and thecontrol gate electrode 148 may be provided on theintergate dielectric pattern 142 a. Accordingly, together the floatinggate pattern 150, theintergate dielectric pattern 142 a and the control gate electrode may provide a stack gate. - The insulating
pattern 120 may have sidewalls that become wider at a top portion, i.e. are vertically protruded. Thelower gate pattern 108 b is provided between the protruded sidewalls of adjacent insulatingpatterns 120 as illustrated in FIG. 5. Accordingly, sidewalls of the floatinggate pattern 150 may contact the sidewalls of the insulatingpattern 120, i.e. the device isolation pattern. The flash memory device further includes source and drainregions 156. The source and drainregions 156 are provided in the integrated circuit substrate adjacent to the floatinggate pattern 150 and may be aligned to the sidewalls of the floatinggate pattern 150. - As further illustrated in FIG. 5, the flash memory device includes further includes nitrogen doped layers N/L. The nitrogen doped layers N/L may block a diffusion route of oxygen during a fabrication process, which may improve the overall functionality of the device. In particular, a first nitrogen doped layer N/L may be provided on the upper sidewall of the
trench region 113 a, sidewalls of thetunnel insulating pattern 102 a and/or sidewalls of thelower gate pattern 108 b, which may be sequentially aligned to be in contact with the insulatingpattern 120. Accordingly, it may be possible to reduce the likelihood of the formation of a bird's beak as discussed above at the edge of thetunnel insulating layer 102 a adjacent to the device isolation pattern. Thus, the flash memory device may have a uniformtunnel insulating layer 102 a, i.e. no thickening of thetunnel insulating layer 102 a. - Furthermore, second, third, fourth and fifth nitrogen doped layers N/L may be provided on an upper surface of the
upper gate pattern 112 a of the floatinggate pattern 150, thefirst layer 128 a of the intergatedielectric pattern 142 a, thesecond layer 134 a of the intergatedielectric pattern 142 a and thethird layer 136 a of the intergatedielectric pattern 142 a, respectively. Thus, for example, during a gate sidewall oxidization process for curing etch damage of the stack gate sidewall, the nitrogen doped layers N/L provided on the surface of the floatinggate pattern 150, the firstsilicon oxide layer 128 a and the secondsilicon oxide layer 136 a may reduce the amount of oxygen atoms diffused into the floatinggate pattern 150 and/or thecontrol gate electrode 148. Accordingly, it may be possible to reduce the likelihood that the edge of the floatinggate pattern 150 and/or thecontrol gate electrode 148 will be oxidized. Therefore, theintergate dielectric pattern 142 a may have a uniform thickness. - In certain embodiments, a sixth nitrogen doped layer N/L may be formed on sidewalls of the stack gate pattern and on an upper surface of the
tunnel insulating pattern 102 a. The nitrogen doped layer N/L formed on the upper surface of thetunnel insulating pattern 102 a may reduce the likelihood that oxygen atoms will penetrate through interfaces between thetunnel insulating pattern 102 a and the floatinggate pattern 150. Thetunnel insulating pattern 102 a may be provided on the integrated circuit substrate between the stack gate patterns or may be provided between the floatinggate pattern 150 and theintegrated circuit substrate 100. The sixth nitrogen doped layer N/L formed on the sidewalls of the stack gate pattern may be provided before the gate sidewall oxidization process. Accordingly, in embodiments of the present invention where thetunnel insulating pattern 102 a exists only under the floatinggate pattern 150, the sixth nitrogen doped layer N/L may be provided on the sidewalls of thetunnel insulating pattern 102 a adjacent to the source/drain region 156. Thus, it may be possible to reduce the likelihood that oxygen atoms will be diffused through the sidewalls of thetunnel insulating pattern 102 a. - It will be understood that the perspective view of the flash memory device illustrated in FIG. 5 is provided for exemplary purposes only and that embodiments of the present invention are not limited to this configuration. Features may be added and/or deleted from the flash memory device illustrated in FIG. 5 without departing from the teachings of the present invention.
- Referring now to FIGS. 6 through 9, cross sectional views illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention will be discussed. As illustrated in FIG. 6, flash memory devices according to embodiments of the present invention include a tunnel insulating layer on an
integrated circuit substrate 20, a lower conductive layer on the tunnel insulating layer and a mask layer, for example, a hard mask layer, on the lower conductive layer in order to form a self-aligned shallow trench isolation structure. The mask layer, the lower conductive layer and the tunnel insulating layer may be successively patterned to form atunnel insulating pattern 22 on theintegrated circuit substrate 20, a lowerconductive pattern 28 on thetunnel insulating pattern 22 and amask pattern 30, for example, a hard mask pattern, on the lower conductive pattern. The lowerconductive pattern 28 may include, for example, polysilicon. Theintegrated circuit substrate 20 may be partially etched using, for example, thehard mask pattern 30 as an etch mask, to form apre-trench region 32 aligned to sidewalls of thehard mask pattern 30. A nitrogen dopedlayer 36 may be formed on the sidewalls of the lowerconductive pattern 28, the sidewalls of thetunnel insulating pattern 22 and thepre-trench region 32. - In certain embodiments of the present invention, the nitrogen doped
layer 36 may be formed by a plasma nitridation process. In particular, theintegrated circuit substrate 20 including thepre-trench region 32 may be disposed in a process chamber. Aplasma 34 may be generated in the process chamber using, for example, N2, NH3, NO and/or N2O, as a source gas. A plasma density within the process chamber may be set to about 1×1010 cm−3 to about 1×1012 cm−3 and a pressure within the process chamber may be set to about 1−300 mT. In certain embodiments, a temperature of the substrate may be set from about 300° C. to about 900° C. and a plasma exposure time may be set to from about 10 seconds to about 60 seconds. - In further embodiments of the present invention, the nitrogen doped
layer 36 may be formed by applying a remote plasma nitridation process (RPN). The RPN process is a method of jetting a nitrogen plasma into the process chamber after forming the plasma in remote chamber. The plasma exposure time of the substrate may be adjusted and the nitrogen doped layer with a high concentration may be formed at a surface of target materials. The plasma density within the process chamber of the RPN process may be set to from about 1×1010 cm−3 to about 1×1012 cm−3, and the pressure within the process chamber of the RPN process may be set to about 1−300 mT. Furthermore, the temperature of the substrate may be set to from about 300° C. to about 900° C., and the plasma exposure time may be set to from about 10 seconds to about 60 seconds. - In still further embodiments of the present invention, the nitrogen doped
layer 36 may be formed by annealing theintegrated circuit substrate 20 including thepre-trench region 32 in a gas including a nitrogen ambient. In these embodiments of the present invention, nitrogen atoms combine with silicon atoms of thetunnel insulating pattern 22, the lowerconductive pattern 28 and theintegrated circuit substrate 20 to form the nitrogen dopedlayer 36. The integrated circuit substrate may be heated at a temperature of from about 300° C. to about 900° C. The gas including nitrogen may be, for example, N2, NH3, NO and/or N2O. - Referring now to FIG. 7, the
substrate 20 including the nitrogen dopedlayer 36 is etched using, for example, thehard mask pattern 30 as the etch mask, to form atrench region 32 a aligned to the sidewalls of thehard mask pattern 30. The nitrogen dopedlayer 36 may remain on the sidewalls of the lowerconductive pattern 28, the sidewalls of thetunnel insulating pattern 22 and upper sidewalls of thetrench region 32 a as illustrated in FIG. 7. - Referring now to FIG. 8, a thermal oxidization process may be applied to the integrated circuit substrate to, for example, cure etch damage that may have occurred during etch of the
trench region 32 a. Atrench insulating layer 38 is formed at sidewalls and a bottom of thetrench region 32 a. Thetrench insulating layer 38 may, for example, be an oxide layer. As illustrated, thetrench insulating layer 38 is not formed on the nitrogen dopedlayer 36. As discussed above, the nitrogen dopedlayer 36 may reduce the likelihood that oxygen atoms will react with the silicon atom of thesubstrate 20 and the silicon atom of the lowerconductive pattern 28. Furthermore, the nitrogen dopedlayer 36 formed on the sidewalls of thetunnel insulating pattern 22 may reduce the likelihood that oxygen atoms will be diffused through interfaces of thetunnel insulating layer 22. Thus, it may be possible to reduce the likelihood that a bird's beak will form, i.e. that the edge of thetunnel insulating pattern 22 will become thicker. - Referring now to FIG. 9, an insulating layer is formed on the surface of the substrate. The insulating layer may be planarized by, for example, a chemical mechanical polishing (CMP) process and the
hard mask pattern 30 may be removed to form an insulatingpattern 40 in thetrench region 32 a. The insulatingpattern 40 and thetrench insulating layer 38 constitute a device isolation pattern. The insulatingpattern 40 may include a single layer or multiple layers. In certain embodiments, the insulating layer may include a silicon oxide layer, for example, a high-density plasma oxide layer or a plasma enhanced oxide layer (PEOX). A PEOX typically has excellent burial characteristic. In some embodiments of the present invention, a thin silicon nitride layer may be formed before the oxide layer is formed. A conductive layer is formed on the surface of theintegrated circuit substrate 20 where thehard mask pattern 30 has been removed. The conductive layer is patterned to form an upperconductive pattern 42 on the lowerconductive pattern 28. The upperconductive pattern 42 may include, for example, a similar material to the material of the lowerconductive pattern 28, for example, polysilicon. As illustrated in FIG. 9, an edge of the upperconductive pattern 42 may extend onto a surface of the insulatingpattern 40, for example, an oxide pattern. This overlap may reduce the likelihood that the lowerconductive pattern 28 will be damaged by inadvertent misalignment of aspects of the device. - As discussed above, according to methods of forming flash memory devices according to embodiments of the present invention, one or more nitrogen doped layers may reduce the likelihood that oxygen atoms will be diffused through the interfaces of the
tunnel insulating pattern 22 during thermal oxidization. Thus, it may be possible to reduce the likelihood that a bird's beak will be formed at the edge of the tunnel insulating pattern adjacent to the device isolation pattern. - Referring now to FIGS. 10 through 12, cross sectional views illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention will be discussed. As illustrated in FIG. 10, a nitrogen doped
layer 46 is formed on an upper surface of the upperconductive pattern 42 and on an upper surface of the insulatingpattern 40. As further illustrated in FIG. 11, afirst layer 48, for example, a first silicon oxide layer, is formed on a surface of theintegrated circuit substrate 20 on thelayer 48. - Referring now to FIG. 12, a
second layer 54, for example, a silicon nitride layer, is formed on thefirst layer 48 and a nitrogen doped layer 55 is formed on an upper surface of thesecond layer 54. Athird layer 56, for example, a second silicon oxide layer, is formed on thesecond layer 54 and a nitrogen dopedlayer 60 is formed on an upper surface of thethird layer 56. Anintergate dielectric layer 58 includes the first 46, the second 54 and third 56 layers. - It will be understood that the nitrogen doped layers46, 52 and 60 may be formed using at least one of the methods discussed above with respect to the nitrogen doped
layer 36. In particular, the nitrogen doped layers 46, 52 and 60 may be formed by the plasma nitridation process, the RPN process, and/or by annealing the substrate in the gas including the nitrogen ambient. - A gate
conductive layer 68 is formed on the secondsilicon oxide layer 56. The gateconductive layer 68, theintergate dielectric layer 58, the upperconductive pattern 42, and the lowerconductive pattern 28 are successively patterned to form a stack gate that crosses over the device isolation patterns. Although not shown in the Figures, the stack gate may include a floating gate pattern, an intergate dielectric pattern and a control gate pattern, which are sequentially stacked. Thetunnel insulating pattern 22 between the stack gate patterns may be etched during formation of the gate stack pattern. The gateconductive layer 68 may include polysilicon and/or a polycide layer including apolysilicon layer 64 and ametal silicide layer 66 as illustrated in FIG. 12. - As discussed above, nitrogen doped layers according to embodiments of the present invention are formed at oxygen diffusion routes such as the interfaces between the first silicon oxide layer and the conductive pattern, the interfaces between the first silicon oxide layer and the silicon nitride layer, and the interfaces between the second silicon oxide layer and the polysilicon layer. Accordingly, for example, during the thermal oxidization process, it may be possible to reduce the possibility of a reaction between the silicon atoms of the gate conductive layer and the upper conductive pattern and the oxygen atoms diffused through the interfaces of the intergate dielectric layer. Thus, the likelihood that the edge of the intergate dielectric layer, for example, the edge of the first silicon oxide layer and the second silicon oxide layer, will become thicker may be reduced.
- Referring now to FIGS. 13 and 14, cross sectional views illustrating processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention will be discussed. As illustrated in FIGS. 13 and 14, the
tunnel insulating layer 22 is formed on theintegrated circuit substrate 20. The stack gate is formed on thetunnel insulating layer 22. The stack gate includes a floatinggate pattern 90, anintergate dielectric pattern 88 on the floatinggate pattern 90 and acontrol gate pattern 94 on the floatinggate pattern 90. The floatinggate pattern 90 may include alower gate pattern 78 and anupper gate pattern 82. It will be understood that the floatinggate pattern 90 may also include a single pattern without departing from the teachings of the present invention. Thecontrol gate pattern 94 may include apolysilicon layer 84 or a metal polycide layer that includes thepolysilicon layer 84 and ametal silicide layer 86 as illustrated in FIG. 13. - A nitrogen doped
layer 96 is formed on sidewalls of the stack gate and on a surface of thetunnel insulating layer 22. The nitrogen dopedlayer 96 may be formed using the plasma nitridation process, using the RPN process, or by annealing the substrate in the gas including nitrogen ambient as discussed above. Theintegrated circuit substrate 20 may be annealed to, for example, cure damage of the sidewalls of the stack gate pattern caused by the etch of the stack gate. Source anddrain regions 98 may be formed in the integrated circuit substrate adjacent to the stack gate pattern. - Although not shown in the figure, the
tunnel insulating layer 22 is patterned to remain only at a lower portion of the floatinggate pattern 90 during formation of the stack gate pattern. In these embodiments of the present invention, the nitrogen dopedlayer 96 may be formed on the sidewalls of the tunnel insulating layer interposed between the floatinggate pattern 90 and theintegrated circuit substrate 20. During the process of oxidizing the gate sidewalls, the nitrogen dopedlayer 96 may reduce the likelihood that the silicon atoms of theintegrated circuit substrate 20, the floatinggate pattern 90 and thecontrol gate electrode 94 will react with the oxygen atom and form an oxide layer. Thus, it may be possible to reduce the likelihood that the tunnel insulating layer on the sidewalls of the stack gate pattern and the edge of theintergate dielectric pattern 88 will become thicker. - Referring now to FIGS. 15 through 26, cross sectional views of processing steps in the fabrication of integrated circuit devices according to embodiments of the present invention will be discussed. FIGS. 15 through 19 and FIGS. 20A through 24A are cross sectional views taken along a line A-A′ of the FIG. 5. FIGS. 20B through 24B and FIGS. 25 and 26 are cross-sectional views taken along a line B-B′ of the FIG. 5
- Referring now to FIG. 15, a
tunnel insulating layer 102 is formed on theintegrated circuit substrate 100.Nitrogen 104 may be implanted into thetunnel insulating layer 102 to form a nitrogen dopedlayer 106 on an upper surface of thetunnel insulating layer 102. It will be understood that the nitrogen dopedlayer 106 may be eliminated without departing from the teachings of the present invention. The nitrogen dopedlayer 106 may be formed by a plasma nitration process, a remote plasma nitridation process (RPN) and/or by annealing the integrated circuit substrate in a gas including nitrogen ambient as discussed above. - Referring now to FIG. 16, a lower conductive layer108 and a
hard mask layer 110 are sequentially stacked on thetunnel insulating layer 102. The lower conductive layer 108 may include, for example, polysilicon, and thehard mask layer 110 may, for example, include silicon nitride. As illustrated in FIG. 17, thehard mask layer 110, the lower conductive layer 108 and thetunnel insulating layer 102 are successively patterned to form atunnel insulating pattern 102 a, a lowerconductive pattern 108 a and ahard mask pattern 110 a, which are sequentially stacked on theintegrated circuit substrate 100. The lowerconductive pattern 108 a may include, for example, polysilicon. - The integrated
circuit substrate 100 is partially etched using, for example, thehard mask pattern 110 a, as an etch mask to form apre-trench region 113 aligned to sidewalls of thehard mask pattern 110 a. A nitrogen dopedlayer 116 is formed on sidewalls and a bottom of the lowerconductive pattern 108 a, thetunnel insulating pattern 102 a and thepre-trench region 113. The nitrogen dopedlayer 116 may be formed by the plasma nitridation process, the RPN process and/or by annealing the substrate in a gas including nitrogen ambient as discussed above. - Referring now to FIG. 18, the
integrated circuit substrate 100 is etched using, for example, the hard mask pattern 10 a as the etch mask, to form atrench region 113 a aligned to the sidewalls of thehard mask pattern 110 a. The nitrogen dopedlayer 116 remains on the sidewalls of the lowerconductive pattern 108 a, the sidewalls of thetunnel insulating pattern 102 a and the upper sidewalls of the trench region 1113 a. - Referring now to FIG. 19, a thermal oxidization process is applied to the
integrated circuit substrate 100 to, for example, cure etch damage that may have occurred during a the etch of thetrench region 113 a. Atrench oxide layer 118 is formed on the sidewalls and the bottom of thetrench region 113 a. As illustrated, thetrench oxide layer 118 is not formed on an upper portion of the sidewalls of thetrench region 113 a, i.e. the trench oxide layer is not formed on the nitrogen dopedlayer 116. The nitrogen dopedlayer 116 may reduced the likelihood that oxygen atoms will react with the silicon atoms of theintegrated circuit substrate 100 and the lowerconductive pattern 108 a. Thus, as discussed above, it may be possible to reduce that likelihood of the formation of a bird's beak, i.e. thickening of the edge of thetunnel insulating pattern 102 a. Furthermore, the nitrogen dopedlayer 116 formed on the upper surface of thetunnel insulating pattern 102 a may reduce the likelihood that the lowerconductive pattern 108 a will be oxidized. In certain embodiments of the present invention, the lowerconductive pattern 108 a may include polysilicon, which may be oxidized more easily as compared with a single crystalline silicon. - Referring now to FIGS. 20A and 20B, an insulating layer is formed on a surface of the
integrated circuit substrate 100. The insulating layer is planarized by, for example, a chemical mechanical polishing (CMP) process. Thehard mask pattern 110 a may be removed to form an insulatingpattern 120 in thetrench region 113 a. The insulatingpattern 120 and thetrench oxide layer 118 constitute a device isolation pattern. The insulating layer may be include a single layer or multiple layers. For example, the insulating layer may include a silicon oxide layer such as a high-density plasma oxide layer or a plasma enhanced oxide layer (PEOX). PEOX typically has an excellent burial characteristic. In certain embodiments of the present invention, a thin silicon nitride layer may be formed before the oxide layer is formed. - A conductive layer is formed on the surface of the
integrated circuit substrate 100. The conductive layer is patterned to form an upperconductive pattern 122 on the lowerconductive pattern 108 a. The upperconductive pattern 122 may include, for example, polysilicon, similar to the lowerconductive pattern 108 a. As illustrated, the edge of the upperconductive pattern 122 may extend on a surface of the insulatingpattern 120, for example, an oxide pattern. - Referring to now to FIGS. 21A and 21B, a nitrogen doped
layer 126 is formed on an upper surface of the upperconductive pattern 122 and an upper surface of the insulatingpattern 120. As illustrated in FIGS. 22A and 22B, a firstsilicon oxide layer 128 is formed on the nitrogen dopedlayer 126. A nitrogen dopedlayer 132 is formed on an upper surface of the firstsilicon oxide layer 128. - Referring now to FIGS. 23A and 23B, a
silicon nitride layer 134 is formed on the firstsilicon oxide layer 128 and a nitrogen dopedlayer 135 is formed on an upper surface of thesilicon nitride layer 134. A secondsilicon oxide layer 136 is formed on thesilicon nitride layer 134 and a nitrogen dopedlayer 140 is formed on an upper surface of the secondsilicon oxide layer 136. Anintergate dielectric layer 142 includes the firstsilicon oxide layer 128, thesilicon nitride layer 134 and the secondsilicon oxide layer 136. The nitrogen dopedlayers - Referring now to FIGS. 24A and 24B, a gate conductive layer is formed on the second
silicon oxide layer 136. The gate conductive layer, theintergate dielectric layer 142, the upperconductive pattern 122 and the lowerconductive pattern 108 a are successively patterned to form a stack gate crossing over the device isolation patterns. The stack gate includes a floatinggate pattern 150, anintergate dielectric pattern 142 a on the floatinggate pattern 150 and acontrol gate pattern 148 on theintergate dielectric pattern 142 a. Thetunnel insulating layer 102 a between the stack gate patterns may be etched during formation of the stack gate pattern. Thecontrol gate electrode 148 may include polysilicon or a polycide layer that includes apolysilicon layer 144 and ametal silicide layer 146 as illustrated in the Figures. The floatinggate pattern 150 may include alower gate electrode 108 b and anupper gate electrode 112 a on the lower gate electrode. - Referring now to FIGS. 25 and 26, a nitrogen doped
layer 154 is formed on sidewalls of the stack gate and on the surface of thetunnel insulating layer 102 a. The nitrogen dopedlayer 154 may be formed using the plasma nitridation process, using the RPN process, and/or by annealing the substrate in the gas including nitrogen ambient. Thetunnel insulating layer 102 a may be patterned to remain only at a lower portion of the floatinggate pattern 150 during formation of the gate stack pattern. In this case, the nitrogen dopedlayer 154 may be formed on the sidewalls of the tunnel insulating layer interposed between the floatinggate pattern 150 and theintegrated circuit substrate 100. Source and drain regions S/D may be formed in the integrated circuit substrate adjacent to the stack gate pattern. It will be understood that any subsequent process may be performed using conventional methods. - As discussed above with respect to FIGS. 5 through 26, flash memory devices according to embodiments of the present invention include nitrogen doped layers formed in diffusion routes of oxygen atoms to reduce the likelihood of the formation of a bird's beak, i.e, the thickening of the edge of the tunnel insulating pattern and the intergate dielectric pattern. Accordingly, it may be possible to improve endurance and data retention characteristics of the integrated circuit device as well as to reduce a distribution of a threshold voltage in a cell array. A uniform edge of the intergate dielectric pattern may provide a lower coupling ratio, enhanced erase speed and enhanced write speed of the flash memory device.
- In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (34)
Priority Applications (4)
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US11/371,379 US7445994B2 (en) | 2002-07-05 | 2006-03-09 | Methods of forming non-volatile memory devices using selective nitridation techniques |
US11/471,798 US7566929B2 (en) | 2002-07-05 | 2006-06-21 | Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof |
US12/488,061 US8008153B2 (en) | 2002-07-05 | 2009-06-19 | Methods of fabricating nonvolatile memory devices having gate structures doped by nitrogen |
US13/181,134 US8552488B2 (en) | 2002-07-05 | 2011-07-12 | Nonvolatile memory devices having gate structures doped by nitrogen |
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KR10-2002-0038826A KR100467019B1 (en) | 2002-07-05 | 2002-07-05 | Flash memory device with self aligned shallow trench isolation structure and method of fabricating the same |
KR2002-38826 | 2002-07-05 |
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US11/371,379 Division US7445994B2 (en) | 2002-07-05 | 2006-03-09 | Methods of forming non-volatile memory devices using selective nitridation techniques |
US11/371,379 Continuation US7445994B2 (en) | 2002-07-05 | 2006-03-09 | Methods of forming non-volatile memory devices using selective nitridation techniques |
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US11/371,379 Expired - Lifetime US7445994B2 (en) | 2002-07-05 | 2006-03-09 | Methods of forming non-volatile memory devices using selective nitridation techniques |
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US20070296016A1 (en) * | 2006-06-27 | 2007-12-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
CN111785687A (en) * | 2019-04-03 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
CN116344590A (en) * | 2023-05-23 | 2023-06-27 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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KR100467019B1 (en) * | 2002-07-05 | 2005-01-24 | 삼성전자주식회사 | Flash memory device with self aligned shallow trench isolation structure and method of fabricating the same |
US7566929B2 (en) | 2002-07-05 | 2009-07-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof |
KR100647482B1 (en) * | 2004-09-16 | 2006-11-23 | 삼성전자주식회사 | Semiconductor Device and Method of Manufacturing the same |
KR100644397B1 (en) | 2005-04-07 | 2006-11-10 | 삼성전자주식회사 | Method of Treating Thin Layer and Method of Manufacturing Non-Volatile Memory Cell Using the same |
KR100654554B1 (en) * | 2005-12-29 | 2006-12-05 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
KR100753154B1 (en) * | 2006-02-06 | 2007-08-30 | 삼성전자주식회사 | Non-volatile memory device and method of forming the same |
KR100803663B1 (en) * | 2006-06-29 | 2008-02-19 | 삼성전자주식회사 | Non-volatile memory device and method for manufacturing the same |
KR100749738B1 (en) * | 2006-08-02 | 2007-08-17 | 삼성전자주식회사 | Method of fabricating a non-volatile memory device |
KR101404669B1 (en) * | 2007-09-27 | 2014-06-09 | 삼성전자주식회사 | Nonvolatile memory device and method of forming the same |
KR100936995B1 (en) * | 2007-12-06 | 2010-01-15 | 한양대학교 산학협력단 | Method for making thin film |
DE102008035809B3 (en) * | 2008-07-31 | 2010-03-25 | Advanced Micro Devices, Inc., Sunnyvale | A technique for reducing the silicide inequalities in polysilicon gate electrodes through an intervening diffusion blocking layer |
KR101736246B1 (en) * | 2010-09-14 | 2017-05-17 | 삼성전자주식회사 | Non-volatile memory device and method of manufacturing the same |
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KR20040004797A (en) | 2004-01-16 |
KR100467019B1 (en) | 2005-01-24 |
US20040108570A9 (en) | 2004-06-10 |
US20060151824A1 (en) | 2006-07-13 |
US7445994B2 (en) | 2008-11-04 |
US7041554B2 (en) | 2006-05-09 |
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