US20030197232A1 - Semiconductor device and method of producing the same - Google Patents
Semiconductor device and method of producing the same Download PDFInfo
- Publication number
- US20030197232A1 US20030197232A1 US10/400,583 US40058303A US2003197232A1 US 20030197232 A1 US20030197232 A1 US 20030197232A1 US 40058303 A US40058303 A US 40058303A US 2003197232 A1 US2003197232 A1 US 2003197232A1
- Authority
- US
- United States
- Prior art keywords
- film
- metal nitride
- nitride film
- metal
- annealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 108
- 150000004767 nitrides Chemical class 0.000 claims abstract description 59
- 238000000137 annealing Methods 0.000 claims abstract description 42
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 230000008018 melting Effects 0.000 claims abstract description 25
- 238000002844 melting Methods 0.000 claims abstract description 25
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 abstract description 12
- 230000008025 crystallization Effects 0.000 abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 33
- 239000010410 layer Substances 0.000 description 30
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 23
- 229910052721 tungsten Inorganic materials 0.000 description 23
- 239000010937 tungsten Substances 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000007789 gas Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 7
- 230000007423 decrease Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 5
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- -1 silicon oxide nitride Chemical class 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Definitions
- the present invention relates to a semiconductor device including a conductive film implementing, e.g., a gate electrode included in a MOS (Metal Oxide Semiconductor) transistor or an interconnection or wiring, and a method of producing the same. More particularly, the present invention relates to a semiconductor device capable of lowering the resistance of a conductive film thereof and a method of producing the same.
- MOS Metal Oxide Semiconductor
- Metal having a high melting point and silicon react to form a metal silicide layer having a high melting point and thereby form a polycrystalline silicide structure.
- Even the polycrystalline silicide structure cannot lower the resistivity of the metal silicide having a high melting point beyond a certain limit.
- an interconnection or wiring is 0.2 ⁇ m thick or less and is reduced in width from conventional 0.18 ⁇ m to 0.13 ⁇ m, resistance lower than 4 ⁇ .cm 2 is required as the sheet resistance of the interconnection. Such a low resistance is, however, difficult to achieve with the polycrystalline silicide structure.
- a metal/polysilicon structure in which a film of metal having a high melting point is formed on a polysilicon film is one of recent achievements in the semiconductors device art.
- the metal/polysilicon structure is expected to implement low resistance because a high melting point, metal silicide layer is absent.
- a semiconductor device with, e.g., the tungsten film is annealed.
- a tungsten/polysilicon (W/Si) structure has been formed as the gate electrode of a MOS transistor, ions are implanted in a source and a drain region. This is followed by annealing for activation. Annealing, however, causes polysilicon and tungsten to react with each other and form tungsten silicide (WSi).
- a barrier metal film implemented by a titanium nitride (TiN) film or similar metal nitride film may be formed between the polysilicon film and the tungsten film in order to suppress the reaction of polysilicon and tungsten, as also proposed in the past.
- TiN titanium nitride
- the resistivity of the tungsten film forming part of the W/TiN structure was about seven to eight times as high as the resistivity of bulk tungsten. This is presumably because the crystal structure of the barrier metal film effects the crystallization of the overlying tungsten film and thereby suppresses the crystal growth of the tungsten film, limiting the decrease in the resistivity of the W/TiN structure.
- Japanese Patent Laid-Open Publication No. 10-12869 discloses a conductive film that is a laminate of a tungsten film, a TiN film, and a polysilicon film.
- the TiN film which serves as a barrier metal film, is caused to recrystallize so as to increase the grain size. This improves the crystallization of the tungsten film and thereby lowers resistance.
- Japanese Patent Laid-Open Publication No. 10-289885 (prior art 2 hereinafter) teaches a conductive film in the form of a high melting point metal/TiN/polysilicon laminate structure. This conductive film is characterized in that the barrier metal film is provided with a double-layer structure in order to improve the crystallization of the overlying, high melting point metal film for thereby lowering resistance.
- the prior art 1 needs an additional step for the recrystallization of the barrier metal film while the prior art 2 needs an additional step for providing the barrier metal film with a double-layer structure.
- Such an additional step makes a production line sophisticated when combined with the essential steps of sequentially forming the consecutive layers of the conductive film.
- the recrystallization and double-layer structure both increase the film/thickness of the barrier metal and therefore the overall thickness of the conductive film. This obstructs the implementation of thin electrodes and thin interconnections that is necessary for scaling down semiconductor devices.
- a conductive film formed on a semiconductor substrate for forming an electrode, an interconnection or the like is implemented as a laminate of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point, as named from the bottom to the top of the laminate.
- a method of producing a conductive film included in a semiconductor device includes the steps of sequentially forming a laminate made up of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on an insulation film in this order, and annealing the laminate to thereby lower the resistance of the metal nitride film.
- a method of producing a gate electrode included in a MOS transistor includes the steps of sequentially forming a polysilicon film, a barrier metal film and a metal nitride layer having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure, patterning the conductive film to thereby form the gate electrode, implanting ions in a source and a drain region in a semiconductor layer by using the gate the gate electrode as a mask, and effecting annealing to thereby activate the resulting ion implanted layers and lower the resistance of the metal nitride film at the same time.
- a method of producing a gate electrode included in a MOS transistor includes the steps of sequentially forming a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure, annealing the conductive film to thereby lower the resistance of the metal nitride layer, and patterning the conductive film to thereby form the gate electrode.
- FIG. 1 is a section showing a MOS transistor embodying the present invention
- FIGS. 2A through 2F are sections demonstrating a sequence of steps for producing the MOS transistor of FIG. 1;
- FIG. 3 is a graph showing a relation between resistivity Rs and annealing temperature
- FIG. 4 is a view representative of a relation between annealing temperature and the components of WN;
- FIGS. 5A and 5B are sections each showing a particular alternative lamp annealing step
- FIG. 6 is a section showing a specific DRAM (Dynamic Random Access Memory) cell configuration to which the illustrative embodiment is applied.
- DRAM Dynamic Random Access Memory
- a semiconductor device embodying the present invention is shown and applied to a gate electrode included in a MOS transistor by way of example.
- the semiconductor device includes a p-type or an n-type silicon substrate 1 formed with a p-well 2 .
- a shallow device isolating groove structure (STI) 3 delimits an area in which a MOS transistor is to be formed.
- STI 3 a shallow groove 1 a is formed in the surface of the silicon substrate 1 and then filled with a silicon oxide film 4 .
- a gate insulation film 5 implemented by a silicon oxide film is formed on the surface of the silicon substrate 1 .
- a polysilicon film 7 , a barrier metal film 8 implemented by titanium nitride (TiN) and a tungsten nitride (WN) film 9 are sequentially laminated on the gate insulation film 5 , constituting a gate electrode 6 .
- a silicon oxide film 10 is formed on the top of the gate electrode 6 .
- Side walls 11 are formed on the sides of the gate electrode 6 and implemented by a silicon oxide film.
- the silicon oxide films 10 and 11 cover the gate electrode 6 .
- an LDD (Lightly Doped Drain) region 12 and a source and a drain region 13 are formed in the MOS transistor forming region of the silicon substrate 1 and doped with an n-type impurity lightly and heavily, respectively. In this manner, an n-channel MOS transistor is completed.
- An interlayer dielectric 14 is formed with a contact hole.
- a buried contact 15 is positioned in the contact hole and connected to the source and drain regions 13 .
- FIGS. 2A through 2F demonstrate a sequence of steps for producing the above-described MOS transistor.
- the p-well 2 is formed in the p-type or n-type silicon substrate 1 while the shallow groove 1 a is formed in the device separating region of the substrate 1 .
- the silicon oxide film 4 is buried in the shallow groove 1 a to thereby form the STI 3 .
- the silicon oxide film 4 is formed on the surface of the substrate 1 to a thickness greater than the depth of the groove 1 a.
- the silicon oxide film 4 is then etched back by chemicomechanical polishing (CMP) so as to expose the surface of the silicon substrate 1 .
- CMP chemicomechanical polishing
- the surface of the silicon substrate 1 is cleaned.
- the silicon oxide film 5 is formed on the cleaned surface of the substrate 1 to a thickness of about 10 nm.
- the polysilicon film 7 containing phosphor (P) is formed on the silicon oxide film 5 to a thickness of about 10 nm by CVD (Chemical Vapor Deposition).
- the TiN film 8 is formed on the polysilicon film 7 to a thickness of about 10 nm by sputtering.
- the WN film 9 is formed on the TiN film 8 to a thickness of about 100 nm by CVD, which uses tungsten hexafluoride (WF 6 ) gas and ammonia (NH 3 ) gas.
- WF 6 gas belongs to a family of halogen-based metallic gases having high melting points. More specifically, for CVD of the WN film 9 , a CVD reaction condition richer in nitrogen than a stoichiometric ratio is used, so that the WN film 9 is formed in an amorphous state. For example, WF 6 gas and NH 3 gas are introduced into a reaction chamber such that WF 6 is more than 1/500, but less than 10, with respect to NH 3 . The WF6 gas and NH3 gas are caused to react at a growth temperature of room temperature to 550° C. and a reaction pressure of 0.01 Torr to 5.0 Torr.
- a conductive film 20 having a three-layer structure i.e., a WN/TiN/polysilicon structure is formed.
- the silicon oxide film 5 implementing the gate insulation film may be replaced with a silicon nitride (SiN) film, a silicon oxide nitride (SiOxNy) film or a tantalum oxide (TaO) film, if desired.
- the silicon oxide film 10 having a suitable thickness is formed on the three-layer conductive film 20 .
- a photoresist film not shown, has been formed on the silicon oxide film 10
- the laminate shown in FIG. 2B is exposed to a gate electrode pattern and then developed to form a photoresist mask.
- the WN film 9 , TiN film 8 and polysilicon film 7 constituting the conductive film 20 are sequentially etched via the photoresist mask.
- the gate electrode 6 is formed in a desired pattern, as shown in FIG. 2C.
- the photoresist mask is removed.
- phosphor (P + ) ions are lightly implanted by a self-matching method using the gate electrode 6 , so that a P + ion implanted layer 21 is formed in the major surface of the substrate 1 at both sides of the gate electrode 6 .
- a silicon oxide film 22 having a desired thickness is formed on the entire surface of the laminate, as indicated by a dash-and-dots line in FIG. 2D.
- the silicon oxide film 22 is etched back by anisotropic etching such that the film 22 remains only on the sides of the gate electrode 6 and forms the side walls 11 .
- arsenic (As + ) ions are heavily implanted in the laminate by the self-matching method using the gate electrode 6 and side walls 11 . Consequently, an As + ion implanted layer 23 is formed in the major surface of the silicon substrate 1 at both sides of the side walls 11 .
- the silicon substrate 1 with the As + ion implanted layer 23 is annealed by a lamp annealer implemented by RTA (Rapid Thermal Annealing).
- RTA Radial Thermal Annealing
- Lamp annealing causes the WN film 9 to release nitrogen (N) with the result that the WN film 9 changes into a substantially nitrogen-free WN film, i.e., a W film.
- N nitrogen
- W film is also referred to as a WN film herein because nitrogen is not completely removed from the WN film 9 .
- the crystallization of tungsten in the WN film 9 is improved and increases the crystal size of tungsten.
- the TiN film or barrier metal film 8 between the WN film 9 and the polysilicon film 7 prevents polysilicon from reacting with tungsten, which is present in the WN film 9 , and forming a tungsten silicide layer. In this manner, a metal/polysilicon structure is formed.
- the resistivity of the WN film or upper layer 9 decreases because of improved crystallization, lowering the resistivity of the entire gate electrode 6 .
- lamp annealing activates the P + ion implanted layer 21 and As + ion implanted layer 23 and thereby forms the low density, n-type LDD region 12 and high density, n-type source and drain regions 13 .
- the interlayer dielectric 14 is formed on the silicon substrate 1 in such a manner as to cover the n-channel MOS transistor.
- the buried contact 15 is formed in the contact hole formed in the interlayer dielectric 14 and connected to the source and drain regions 13 , completing the MOS transistor structure shown in FIG. 1.
- the gate electrode 6 of the MOS transistor has a WN/TiN/polysilicon structure and causes the intermediate TiN film 8 to prevent tungsten of the WN film 9 and silicon of the polysilicon layer 7 from reacting with each other and forming a tungsten silicide layer.
- This is successful to implement a metal/polysilicon structure including the WN film 9 and polysilicon film 7 .
- the WN film 9 is formed in an amorphous state and then subjected to lamp annealing in order to remove nitrogen and to promote the crystallization of tungsten at the same time. It follows that tungsten crystallizes toward regions where nitrogen has disappeared, and therefore rapidly increases the grain size thereof.
- the resistivity of the WN film 9 and therefore that of the entire metal/polysilicon structure is reduced. For this reason, even when the WN film 9 is as thin as 0.2 ⁇ m or less and the gate electrode 6 has a gate length as small as about 0.13 ⁇ m, low resistivity required of a semiconductor device is achievable.
- FIG. 3 is a graph showing the result of measurement and in which the ordinate and abscissa indicate resistivity Rs and lamp annealing temperature, respectively.
- W (Bulk) is representative of the resistivity of bulk tungsten.
- W/TiN is representative of a structure including tungsten formed on a TiN film while WN/TiN is representative of the structure of the present invention in which the amorphous WN film is formed on the TiN film.
- the resistivity Rs of the W (Bulk) is constant without regard to the annealing temperature and slightly lower than 10 1 . Although the resistivity Rs of the W/TiN structure decreases little by little in accordance with the rise of the annealing temperature, its slope is small; the resistivity Rs does not decrease below 10 1 even at 1,100° C.
- the resistivity Rs of the WN/TiN structure of the illustrative embodiment sharply decreases in accordance with the rise of the annealing temperature although it is higher than the resistivity Rs of the W/TiN structure by about one figure just after the formation.
- the resistivity Rs of the WN/TiN structure was almost the same as the resistivity Rs of the W/TiN structure when the annealing temperature was 800° C.
- the WN/TiN structure was lower in resistivity Rs than the W/TiN structure when the annealing temperature exceeded 800° C., and was even lower than 10 1 at 900° C.
- the resistivity Rs of 10 1 is substantially 4 ⁇ .cm 2 to 6 ⁇ .cm 2 in terms of sheet resistance. Therefore, the conductive film of the illustrative embodiment has resistivity as low as about one-third to one-fourth of the resistivity of the conventional W/TiN/polysilicon conductive film. Consequently, by effecting lamp annealing at 800° C. or above, preferably 900° C. or above, it is possible to realize an WN/TiN conductive film having sheet resistance of 4 ⁇ .cm 2 or less.
- FIG. 4 shows components contained in the WN film and detected by X-ray analysis at various lamp annealing temperatures. As shown, while the WN film 9 is in an amorphous state just after the deposition, a number of diffraction peaks of W 2 N appear as the annealing temperature rises, proving the polycrystallization of the WN film 9 . At temperatures above 900° C., tungsten occupies substantially the entire WN film 9 . In FIG. 4, parenthesized numerical values indicate crystal face orientations.
- CVD used to form the WN film 9 in the illustrative embodiment may be replaced with sputtering, if desired.
- a tungsten target which is a high purity material, may be used to form a WN film in an argon atmosphere containing nitrogen gas by sputtering.
- a growth temperature of room temperature to 400° C. and a reaction pressure of 10 ⁇ 4 Torr to 10 ⁇ 2 Torr are selected.
- the WN film 9 to be formed by sputtering can be implemented by the same sputtering system as used to form the TiN film 8 , which underlies the WN film 9 , just after the TiN film 8 . Sputtering is therefore desirable from the production efficiency standpoint.
- the conductive film is applied to the gate electrode of a MOS semiconductor.
- the WT/TiN/polysilicon structure is subjected to lamp annealing at the same time as the ion implanted layers of the LDD region and source and drain regions are activated by heat.
- the lamp annealing of the above three-layer conductive film may, of course, be effected in an independent step.
- lamp annealing is effected after the silicon oxide films 10 and 11 have been formed in such a manner as to cover the gate electrode or three-layer conductive film 6 .
- the silicon oxide films 10 and 11 may therefore happen to obstruct the parting of nitrogen from the WN film 9 .
- lamp annealing may be effected in the condition wherein the surface of the WN film 9 is exposed to the outside.
- lamp annealing may be effected just after the three-layer conductive film 20 has been formed, as shown in FIG. 5, or just after the conductive film 20 and silicon oxide layer 10 have been patterned to form the gate electrode 6 , as shown in FIG. 5B.
- Such an alternative scheme is successful to promote the parting of nitrogen from the WN film 9 and to further reduce the lamp annealing time.
- the crux is therefore that lamp annealing should preferably be effected at least before the films expected to cover the conductive film 20 are formed.
- FIG. 6 shows a specific DRAM cell configuration using the MOS transistor of FIG. 1.
- a bit line 16 is formed on the interlayer dielectric 14 and connected to the source region 13 by the buried contact 15 stated earlier.
- the bit line 16 is implemented as a three-layer conductive film made up of a Ti film 7 ′, a TIN film 8 A and a WN film 9 A that are sequentially laminated in the same manner as in the illustrative embodiment.
- the conductive film is patterned and then subjected to lamp annealing in order to lower the resistance of the WN film 9 A and therefore the sheet resistance of the bit line 16 .
- a second interlayer dielectric 17 is formed on the interlayer dielectric 14 .
- a buried contact 18 is formed in the second inter layer dielectric 17 and connected to the drain region 13 .
- a charge store electrode 24 , a capacity insulation film 25 and a counter electrode 26 are sequentially formed on the second interlayer dielectric 17 , constituting a capacitor 19 .
- the buried contact 18 connects the charge store electrode 24 to the drain region 13 .
- the DRAM shown in FIG. 6 has the gate electrode 6 , which serves as a word line, and the bit line 16 each having WT/TiN on the top. This, coupled with the fact that the WN films 9 and 9 A have their resistance lowered by lamp annealing, realizes a high-speed DRAM cell or DRAM circuit.
- a polysilicon film, a barrier metal film and a high melting point, metal nitride film are sequentially laminated to constitute a conductive film.
- the conductive film is annealed to lower the resistance of the metal nitride film.
- Annealing causes the metal nitride film, which is formed in an amorphous state, to release nitrogen and increases the crystal size of metal having a high melting point. This successfully improves the crystallization of the high melting point metal and lowers the resistance of the metal nitride film without regard to the crystallization of the underlying barrier metal film.
- the present invention therefore realizes a high speed, highly integrated semiconductor device.
- the metal having a high melting point which constitutes the metal nitride film, and/or the metal constituting the barrier metal film underlying it may be replaced with any other suitable metal comparable in function.
Abstract
A semiconductor device of the present invention includes a conductive film made up of a polysilicon film, a barrier metal film and a high melting point, metal nitride film sequentially laminated in this order. The conductive film is annealed to lower the resistance of the metal nitride film. Annealing causes the metal nitride film, which is formed in an amorphous state, to release nitrogen and increases the crystal size of metal having a high melting point. This successfully improves the crystallization of the high melting point metal and lowers the resistance of the metal nitride film without regard to the crystallization of the underlying barrier metal film. It is therefore possible to improve the crystallization of the metal nitride film or to obviate the step of providing the barrier metal film with a double-layer structure, i.e., to simplify the production procedure. A method of producing the semiconductor device is also disclosed.
Description
- The present invention relates to a semiconductor device including a conductive film implementing, e.g., a gate electrode included in a MOS (Metal Oxide Semiconductor) transistor or an interconnection or wiring, and a method of producing the same. More particularly, the present invention relates to a semiconductor device capable of lowering the resistance of a conductive film thereof and a method of producing the same.
- In parallel with the trend toward high speed, highly integrated semiconductor devices, there is an increasing demand for a decrease in the size of electrodes included in semiconductor devices and the size of interconnections between the devices. However, a decrease in the size, particularly a width, of electrodes and that of interconnections bring about a problem that the resistance of electrodes and that of interconnections noticeably aggravate signal delay, voltage fall and other circuit factors. Particularly, a polysilicon layer conventionally used as an electrode or an interconnection and lowered in resistance by a dopant aggravates signal delay because polysilicon has relatively high resistivity. To solve this problem, there has been proposed to form a titanium, cobalt, tungsten or similar metal film having a high melting point on a polysilicon film. Metal having a high melting point and silicon react to form a metal silicide layer having a high melting point and thereby form a polycrystalline silicide structure. Even the polycrystalline silicide structure, however, cannot lower the resistivity of the metal silicide having a high melting point beyond a certain limit. Specifically, when an interconnection or wiring is 0.2 μm thick or less and is reduced in width from conventional 0.18 μm to 0.13 μm, resistance lower than 4 Ω.cm2 is required as the sheet resistance of the interconnection. Such a low resistance is, however, difficult to achieve with the polycrystalline silicide structure.
- A metal/polysilicon structure in which a film of metal having a high melting point is formed on a polysilicon film is one of recent achievements in the semiconductors device art. The metal/polysilicon structure is expected to implement low resistance because a high melting point, metal silicide layer is absent. Specifically, after a film of tungsten or similar metal having a high melting point has been formed on a polysilicon film, a semiconductor device with, e.g., the tungsten film is annealed. For example, after a tungsten/polysilicon (W/Si) structure has been formed as the gate electrode of a MOS transistor, ions are implanted in a source and a drain region. This is followed by annealing for activation. Annealing, however, causes polysilicon and tungsten to react with each other and form tungsten silicide (WSi).
- In light of the above, a barrier metal film implemented by a titanium nitride (TiN) film or similar metal nitride film may be formed between the polysilicon film and the tungsten film in order to suppress the reaction of polysilicon and tungsten, as also proposed in the past. However, it is difficult to lower the resistivity of the metal structure, i.e. W/TiN structure even with the barrier metal film. In this connection, we found by measurement that the resistivity of the tungsten film forming part of the W/TiN structure was about seven to eight times as high as the resistivity of bulk tungsten. This is presumably because the crystal structure of the barrier metal film effects the crystallization of the overlying tungsten film and thereby suppresses the crystal growth of the tungsten film, limiting the decrease in the resistivity of the W/TiN structure.
- To implement low resistivity, Japanese Patent Laid-Open Publication No. 10-12869 (
prior art 1 hereinafter) discloses a conductive film that is a laminate of a tungsten film, a TiN film, and a polysilicon film. In this structure, the TiN film, which serves as a barrier metal film, is caused to recrystallize so as to increase the grain size. This improves the crystallization of the tungsten film and thereby lowers resistance. Japanese Patent Laid-Open Publication No. 10-289885 (prior art 2 hereinafter) teaches a conductive film in the form of a high melting point metal/TiN/polysilicon laminate structure. This conductive film is characterized in that the barrier metal film is provided with a double-layer structure in order to improve the crystallization of the overlying, high melting point metal film for thereby lowering resistance. - However, the
prior art 1 needs an additional step for the recrystallization of the barrier metal film while theprior art 2 needs an additional step for providing the barrier metal film with a double-layer structure. Such an additional step makes a production line sophisticated when combined with the essential steps of sequentially forming the consecutive layers of the conductive film. Moreover, the recrystallization and double-layer structure both increase the film/thickness of the barrier metal and therefore the overall thickness of the conductive film. This obstructs the implementation of thin electrodes and thin interconnections that is necessary for scaling down semiconductor devices. - It is therefore an object of the present invention to provide a semiconductor device capable of reducing the resistivity of its top metal film without resorting to a sophisticated production line or increasing the thickness of a barrier metal film.
- In accordance with the present invention, in a semiconductor device, a conductive film formed on a semiconductor substrate for forming an electrode, an interconnection or the like is implemented as a laminate of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point, as named from the bottom to the top of the laminate.
- Also, in accordance with the present invention, a method of producing a conductive film included in a semiconductor device includes the steps of sequentially forming a laminate made up of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on an insulation film in this order, and annealing the laminate to thereby lower the resistance of the metal nitride film.
- Further, in accordance with the present invention, a method of producing a gate electrode included in a MOS transistor includes the steps of sequentially forming a polysilicon film, a barrier metal film and a metal nitride layer having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure, patterning the conductive film to thereby form the gate electrode, implanting ions in a source and a drain region in a semiconductor layer by using the gate the gate electrode as a mask, and effecting annealing to thereby activate the resulting ion implanted layers and lower the resistance of the metal nitride film at the same time.
- Moreover, in accordance with the present invention, a method of producing a gate electrode included in a MOS transistor includes the steps of sequentially forming a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure, annealing the conductive film to thereby lower the resistance of the metal nitride layer, and patterning the conductive film to thereby form the gate electrode.
- The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
- FIG. 1 is a section showing a MOS transistor embodying the present invention;
- FIGS. 2A through 2F are sections demonstrating a sequence of steps for producing the MOS transistor of FIG. 1;
- FIG. 3 is a graph showing a relation between resistivity Rs and annealing temperature;
- FIG. 4 is a view representative of a relation between annealing temperature and the components of WN;
- FIGS. 5A and 5B are sections each showing a particular alternative lamp annealing step; and
- FIG. 6 is a section showing a specific DRAM (Dynamic Random Access Memory) cell configuration to which the illustrative embodiment is applied.
- Referring to FIG. 1 of the drawings, a semiconductor device embodying the present invention is shown and applied to a gate electrode included in a MOS transistor by way of example. As shown, the semiconductor device includes a p-type or an n-
type silicon substrate 1 formed with a p-well 2. A shallow device isolating groove structure (STI) 3 delimits an area in which a MOS transistor is to be formed. Specifically, to implement theSTI 3, ashallow groove 1 a is formed in the surface of thesilicon substrate 1 and then filled with asilicon oxide film 4. In the above MOS transistor forming area, agate insulation film 5 implemented by a silicon oxide film is formed on the surface of thesilicon substrate 1. Apolysilicon film 7, abarrier metal film 8 implemented by titanium nitride (TiN) and a tungsten nitride (WN)film 9 are sequentially laminated on thegate insulation film 5, constituting agate electrode 6. - A
silicon oxide film 10 is formed on the top of thegate electrode 6.Side walls 11 are formed on the sides of thegate electrode 6 and implemented by a silicon oxide film. Thesilicon oxide films gate electrode 6. Further, an LDD (Lightly Doped Drain)region 12 and a source and adrain region 13 are formed in the MOS transistor forming region of thesilicon substrate 1 and doped with an n-type impurity lightly and heavily, respectively. In this manner, an n-channel MOS transistor is completed. An interlayer dielectric 14 is formed with a contact hole. A buriedcontact 15 is positioned in the contact hole and connected to the source anddrain regions 13. - FIGS. 2A through 2F demonstrate a sequence of steps for producing the above-described MOS transistor. First, as shown in FIG. 2A, the p-
well 2 is formed in the p-type or n-type silicon substrate 1 while theshallow groove 1 a is formed in the device separating region of thesubstrate 1. Subsequently, thesilicon oxide film 4 is buried in theshallow groove 1 a to thereby form theSTI 3. To bury thesilicon oxide film 4 in thegroove 1 a, there may be used the following specific method. After thegroove 1 a has been formed in thesilicon substrate 1, thesilicon oxide film 4 is formed on the surface of thesubstrate 1 to a thickness greater than the depth of thegroove 1 a. Thesilicon oxide film 4 is then etched back by chemicomechanical polishing (CMP) so as to expose the surface of thesilicon substrate 1. As a result, thesilicon oxide film 4 is left in thegroove 1 a without being etched. - Subsequently, as shown in FIG. 2B, the surface of the
silicon substrate 1 is cleaned. Thesilicon oxide film 5 is formed on the cleaned surface of thesubstrate 1 to a thickness of about 10 nm. Thepolysilicon film 7 containing phosphor (P) is formed on thesilicon oxide film 5 to a thickness of about 10 nm by CVD (Chemical Vapor Deposition). TheTiN film 8 is formed on thepolysilicon film 7 to a thickness of about 10 nm by sputtering. TheWN film 9 is formed on theTiN film 8 to a thickness of about 100 nm by CVD, which uses tungsten hexafluoride (WF6) gas and ammonia (NH3) gas. WF6 gas belongs to a family of halogen-based metallic gases having high melting points. More specifically, for CVD of theWN film 9, a CVD reaction condition richer in nitrogen than a stoichiometric ratio is used, so that theWN film 9 is formed in an amorphous state. For example, WF6 gas and NH3 gas are introduced into a reaction chamber such that WF6is more than 1/500, but less than 10, with respect to NH3. The WF6 gas and NH3 gas are caused to react at a growth temperature of room temperature to 550° C. and a reaction pressure of 0.01 Torr to 5.0 Torr. As a result, aconductive film 20 having a three-layer structure, i.e., a WN/TiN/polysilicon structure is formed. Thesilicon oxide film 5 implementing the gate insulation film may be replaced with a silicon nitride (SiN) film, a silicon oxide nitride (SiOxNy) film or a tantalum oxide (TaO) film, if desired. - The
silicon oxide film 10 having a suitable thickness is formed on the three-layerconductive film 20. After a photoresist film, not shown, has been formed on thesilicon oxide film 10, the laminate shown in FIG. 2B is exposed to a gate electrode pattern and then developed to form a photoresist mask. Thereafter, theWN film 9,TiN film 8 andpolysilicon film 7 constituting theconductive film 20 are sequentially etched via the photoresist mask. As a result, thegate electrode 6 is formed in a desired pattern, as shown in FIG. 2C. After the etching, the photoresist mask is removed. Subsequently, phosphor (P+) ions are lightly implanted by a self-matching method using thegate electrode 6, so that a P+ ion implantedlayer 21 is formed in the major surface of thesubstrate 1 at both sides of thegate electrode 6. - After the step shown in FIG. 2C, a
silicon oxide film 22 having a desired thickness is formed on the entire surface of the laminate, as indicated by a dash-and-dots line in FIG. 2D. Thesilicon oxide film 22 is etched back by anisotropic etching such that thefilm 22 remains only on the sides of thegate electrode 6 and forms theside walls 11. Subsequently, as shown in FIG. 2E, arsenic (As+) ions are heavily implanted in the laminate by the self-matching method using thegate electrode 6 andside walls 11. Consequently, an As+ ion implantedlayer 23 is formed in the major surface of thesilicon substrate 1 at both sides of theside walls 11. - As shown in FIG. 2F, the
silicon substrate 1 with the As+ ion implantedlayer 23 is annealed by a lamp annealer implemented by RTA (Rapid Thermal Annealing). In the illustrative embodiment, RTA is effected at 850° C. for 60 seconds. Lamp annealing causes theWN film 9 to release nitrogen (N) with the result that theWN film 9 changes into a substantially nitrogen-free WN film, i.e., a W film. It is to be noted that such a W film is also referred to as a WN film herein because nitrogen is not completely removed from theWN film 9. At the same time as theWN film 9 so changes, the crystallization of tungsten in theWN film 9 is improved and increases the crystal size of tungsten. At this instant, the TiN film orbarrier metal film 8 between theWN film 9 and thepolysilicon film 7 prevents polysilicon from reacting with tungsten, which is present in theWN film 9, and forming a tungsten silicide layer. In this manner, a metal/polysilicon structure is formed. It is noteworthy that the resistivity of the WN film orupper layer 9 decreases because of improved crystallization, lowering the resistivity of theentire gate electrode 6. Further, lamp annealing activates the P+ ion implantedlayer 21 and As+ ion implantedlayer 23 and thereby forms the low density, n-type LDD region 12 and high density, n-type source and drainregions 13. - After the above sequence of steps, the
interlayer dielectric 14 is formed on thesilicon substrate 1 in such a manner as to cover the n-channel MOS transistor. The buriedcontact 15 is formed in the contact hole formed in theinterlayer dielectric 14 and connected to the source and drainregions 13, completing the MOS transistor structure shown in FIG. 1. - As stated above, the
gate electrode 6 of the MOS transistor has a WN/TiN/polysilicon structure and causes theintermediate TiN film 8 to prevent tungsten of theWN film 9 and silicon of thepolysilicon layer 7 from reacting with each other and forming a tungsten silicide layer. This is successful to implement a metal/polysilicon structure including theWN film 9 andpolysilicon film 7. Further, theWN film 9 is formed in an amorphous state and then subjected to lamp annealing in order to remove nitrogen and to promote the crystallization of tungsten at the same time. It follows that tungsten crystallizes toward regions where nitrogen has disappeared, and therefore rapidly increases the grain size thereof. Consequently, the resistivity of theWN film 9 and therefore that of the entire metal/polysilicon structure is reduced. For this reason, even when theWN film 9 is as thin as 0.2 μm or less and thegate electrode 6 has a gate length as small as about 0.13 μm, low resistivity required of a semiconductor device is achievable. - To determine a relation between the lamp annealing temperature and the resistivity of the
WN film 9, the resistivity of the portion where theWN film 9 andTiN film 8 are laminated was measured by varying the lamp annealing temperature. FIG. 3 is a graph showing the result of measurement and in which the ordinate and abscissa indicate resistivity Rs and lamp annealing temperature, respectively. Also, W (Bulk) is representative of the resistivity of bulk tungsten. W/TiN is representative of a structure including tungsten formed on a TiN film while WN/TiN is representative of the structure of the present invention in which the amorphous WN film is formed on the TiN film. The resistivity Rs of the W (Bulk) is constant without regard to the annealing temperature and slightly lower than 101. Although the resistivity Rs of the W/TiN structure decreases little by little in accordance with the rise of the annealing temperature, its slope is small; the resistivity Rs does not decrease below 101 even at 1,100° C. - By contrast, the resistivity Rs of the WN/TiN structure of the illustrative embodiment sharply decreases in accordance with the rise of the annealing temperature although it is higher than the resistivity Rs of the W/TiN structure by about one figure just after the formation. Specifically, the resistivity Rs of the WN/TiN structure was almost the same as the resistivity Rs of the W/TiN structure when the annealing temperature was 800° C. However, the WN/TiN structure was lower in resistivity Rs than the W/TiN structure when the annealing temperature exceeded 800° C., and was even lower than 101 at 900° C. It is to be noted that the resistivity Rs of 101 is substantially 4 Ω.cm2 to 6 Ω.cm2 in terms of sheet resistance. Therefore, the conductive film of the illustrative embodiment has resistivity as low as about one-third to one-fourth of the resistivity of the conventional W/TiN/polysilicon conductive film. Consequently, by effecting lamp annealing at 800° C. or above, preferably 900° C. or above, it is possible to realize an WN/TiN conductive film having sheet resistance of 4 Ω.cm2 or less.
- FIG. 4 shows components contained in the WN film and detected by X-ray analysis at various lamp annealing temperatures. As shown, while the
WN film 9 is in an amorphous state just after the deposition, a number of diffraction peaks of W2N appear as the annealing temperature rises, proving the polycrystallization of theWN film 9. At temperatures above 900° C., tungsten occupies substantially theentire WN film 9. In FIG. 4, parenthesized numerical values indicate crystal face orientations. - CVD used to form the
WN film 9 in the illustrative embodiment may be replaced with sputtering, if desired. For example, a tungsten target, which is a high purity material, may be used to form a WN film in an argon atmosphere containing nitrogen gas by sputtering. In this case, a growth temperature of room temperature to 400° C. and a reaction pressure of 10−4 Torr to 10−2 Torr are selected. TheWN film 9 to be formed by sputtering can be implemented by the same sputtering system as used to form theTiN film 8, which underlies theWN film 9, just after theTiN film 8. Sputtering is therefore desirable from the production efficiency standpoint. - In the illustrative embodiment, the conductive film is applied to the gate electrode of a MOS semiconductor. Particularly, the WT/TiN/polysilicon structure is subjected to lamp annealing at the same time as the ion implanted layers of the LDD region and source and drain regions are activated by heat. Alternatively, the lamp annealing of the above three-layer conductive film may, of course, be effected in an independent step.
- Particularly, in the illustrative embodiment, lamp annealing is effected after the
silicon oxide films conductive film 6. Thesilicon oxide films WN film 9. In light of this, lamp annealing may be effected in the condition wherein the surface of theWN film 9 is exposed to the outside. For example, lamp annealing may be effected just after the three-layerconductive film 20 has been formed, as shown in FIG. 5, or just after theconductive film 20 andsilicon oxide layer 10 have been patterned to form thegate electrode 6, as shown in FIG. 5B. Such an alternative scheme is successful to promote the parting of nitrogen from theWN film 9 and to further reduce the lamp annealing time. The crux is therefore that lamp annealing should preferably be effected at least before the films expected to cover theconductive film 20 are formed. - Further, the conductive film of the illustrative embodiment is, of course, applicable even to interconnections between devices. FIG. 6 shows a specific DRAM cell configuration using the MOS transistor of FIG. 1. As shown, after the MOS transistor has been formed by the previously described procedure, a
bit line 16 is formed on theinterlayer dielectric 14 and connected to thesource region 13 by the buriedcontact 15 stated earlier. Thebit line 16 is implemented as a three-layer conductive film made up of aTi film 7′, aTIN film 8A and aWN film 9A that are sequentially laminated in the same manner as in the illustrative embodiment. The conductive film is patterned and then subjected to lamp annealing in order to lower the resistance of theWN film 9A and therefore the sheet resistance of thebit line 16. - Subsequently, a
second interlayer dielectric 17 is formed on theinterlayer dielectric 14. A buriedcontact 18 is formed in the secondinter layer dielectric 17 and connected to thedrain region 13. Thereafter, acharge store electrode 24, acapacity insulation film 25 and acounter electrode 26 are sequentially formed on thesecond interlayer dielectric 17, constituting acapacitor 19. In this configuration, the buriedcontact 18 connects thecharge store electrode 24 to thedrain region 13. - The DRAM shown in FIG. 6 has the
gate electrode 6, which serves as a word line, and thebit line 16 each having WT/TiN on the top. This, coupled with the fact that theWN films - In summary, in accordance with the present invention, a polysilicon film, a barrier metal film and a high melting point, metal nitride film are sequentially laminated to constitute a conductive film. Subsequently, the conductive film is annealed to lower the resistance of the metal nitride film. Annealing causes the metal nitride film, which is formed in an amorphous state, to release nitrogen and increases the crystal size of metal having a high melting point. This successfully improves the crystallization of the high melting point metal and lowers the resistance of the metal nitride film without regard to the crystallization of the underlying barrier metal film. It is therefore possible to improve the crystallization of the metal nitride film or to obviate the step of providing the barrier metal film with a double-layer structure, i.e., to simplify the production procedure. Even when the thickness of the metal nitride film and the width of the conductive film are reduced to promote the integration of the semiconductor device, the above simple production procedure is capable of providing the conductive layer with resistance lower than required resistance. The present invention therefore realizes a high speed, highly integrated semiconductor device.
- Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. For example, the metal having a high melting point, which constitutes the metal nitride film, and/or the metal constituting the barrier metal film underlying it may be replaced with any other suitable metal comparable in function.
Claims (31)
1. In a semiconductor device, a conductive film formed on a semiconductor substrate for forming an electrode, an interconnection or the like comprises a laminate of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point, as named from a bottom to a top of said laminate.
2. A semiconductor device as claimed in claim 1 , wherein said barrier metal film and said metal nitride film comprise a TiN film and a WN film, respectively.
3. A semiconductor device as claimed in claim 2 , wherein said conductive film constitutes a gate electrode included in a MOS transistor.
4. A semiconductor device as claimed in claim 3 , wherein said nitride film is 0.2 μm thick or less while said gate electrode has a dimension of 0.13 μm or less in a direction of gate length.
5. A method of producing a conductive film included in a semiconductor device, comprising the steps of:
(a) sequentially forming a laminate made up of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on an insulation film in this order; and
(b) annealing said laminate to thereby lower a resistance of said metal nitride film.
6. A method as claimed in claim 5 , wherein said metal nitride film is formed in an amorphous state under a condition containing at least 0.1 of nitrogen.
7. A method as claimed in claim 6 , wherein said metal nitride film is formed by CVD or sputtering.
8. A method of producing a gate electrode included in a MOS transistor, comprising the steps of:
(a) sequentially forming a polysilicon film, a barrier metal film and a metal nitride layer having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure;
(b) patterning said conductive film to thereby form the gate electrode;
(c) implanting ions in a source and a drain region in a semiconductor layer by using the gate the gate electrode as a mask; and
(d) effecting annealing to thereby activate resulting ion implanted layers and lower a resistance of said metal nitride film at the same time.
9. A method as claimed in claim 8 , wherein said metal nitride film is formed in an amorphous state under a condition containing at least 0.1 of nitrogen.
10. A method as claimed in claim 9 , wherein said metal nitride film is formed by CVD or sputtering.
11. A method as claimed in claim 10 , wherein said metal nitride film is annealed in order to release nitrogen contained in said metal nitride film.
12. A method as claimed in claim 11 , wherein said metal nitride film is subjected to rapid thermal processing using lamp annealing.
13. A method as claimed in claim 12 , wherein said metal nitride film is annealed at a temperature of 800° C. or above, preferably at 900° C. or above.
14. A method as claimed in claim 9 , wherein said metal nitride film is annealed in order to release nitrogen contained in said metal nitride film.
15. A method as claimed in claim 14 , wherein said metal nitride film is subjected to rapid thermal processing using lamp annealing.
16. A method as claimed in claim 15 , wherein said metal nitride film is annealed at a temperature of 800° C. or above, preferably at 900° C. or above.
17. A method as claimed in claim 8 wherein said metal nitride film is annealed in order to release nitrogen contained in said metal nitride film.
18. A method as claimed in claim 17 , wherein said metal nitride film is subjected to rapid thermal processing using lamp annealing.
19. A method as claimed in claim 18 , wherein said metal nitride film is annealed at a temperature of 800° C. or above, preferably at 900° C. or above.
20. A method of producing a gate electrode included in a MOS transistor, comprising the steps of:
(a) sequentially forming a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure;
(b) annealing said conductive film to thereby lower a resistance of said metal nitride layer; and
(c) patterning said conductive film to thereby form the gate electrode.
21. A method as claimed in claim 20 , wherein said metal nitride film is formed in an amorphous state under a condition containing at least 0.1 of nitrogen.
22. A method as claimed in claim 21 , wherein said metal nitride film is formed by CVD or sputtering.
23. A method as claimed in claim 22 , wherein said metal nitride film is annealed in order to release nitrogen contained in said metal nitride film.
24. A method as claimed in claim 23 , wherein said metal nitride film is subjected to rapid thermal processing using lamp annealing.
25. A method as claimed in claim 24 , wherein said metal nitride film is annealed at a temperature of 800° C. or above, preferably at 900° C. or above.
26. A method as claimed in claim 21 , wherein said metal nitride film is annealed in order to release nitrogen contained in said metal nitride film.
27. A method as claimed in claim 26 , wherein said metal nitride film is subjected to rapid thermal processing using lamp annealing.
28. A method as claimed in claim 27 , wherein said metal nitride film is annealed at a temperature of 800° C. or above, preferably at 900° C. or above.
29. A method as claimed in claim 20 , wherein said metal nitride film is annealed in order to release nitrogen contained in said metal nitride film.
30. A method as claimed in claim 29 , wherein said metal nitride film is subjected to rapid thermal processing using lamp annealing.
31. A method as claimed in claim 30 , wherein said metal nitride film is annealed at a temperature of 800° C. or above, preferably at 900° C. or above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/400,583 US20030197232A1 (en) | 1999-09-30 | 2003-03-28 | Semiconductor device and method of producing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP280126/1999 | 1999-09-30 | ||
JP28012699A JP2001102580A (en) | 1999-09-30 | 1999-09-30 | Semiconductor device and manufacturing method thereof |
US09/670,400 US6607979B1 (en) | 1999-09-30 | 2000-09-27 | Semiconductor device and method of producing the same |
US10/400,583 US20030197232A1 (en) | 1999-09-30 | 2003-03-28 | Semiconductor device and method of producing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/670,400 Division US6607979B1 (en) | 1999-09-30 | 2000-09-27 | Semiconductor device and method of producing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030197232A1 true US20030197232A1 (en) | 2003-10-23 |
Family
ID=17620708
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/670,400 Expired - Fee Related US6607979B1 (en) | 1999-09-30 | 2000-09-27 | Semiconductor device and method of producing the same |
US10/400,583 Abandoned US20030197232A1 (en) | 1999-09-30 | 2003-03-28 | Semiconductor device and method of producing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/670,400 Expired - Fee Related US6607979B1 (en) | 1999-09-30 | 2000-09-27 | Semiconductor device and method of producing the same |
Country Status (4)
Country | Link |
---|---|
US (2) | US6607979B1 (en) |
JP (1) | JP2001102580A (en) |
KR (1) | KR20010039941A (en) |
TW (1) | TW490744B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050161721A1 (en) * | 2001-05-16 | 2005-07-28 | Micron Technology, Inc. | Word lines for memory cells |
US20120080756A1 (en) * | 2009-07-01 | 2012-04-05 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6806123B2 (en) * | 2002-04-26 | 2004-10-19 | Micron Technology, Inc. | Methods of forming isolation regions associated with semiconductor constructions |
US6756619B2 (en) * | 2002-08-26 | 2004-06-29 | Micron Technology, Inc. | Semiconductor constructions |
US7274076B2 (en) | 2003-10-20 | 2007-09-25 | Micron Technology, Inc. | Threshold voltage adjustment for long channel transistors |
KR101570044B1 (en) * | 2009-03-17 | 2015-11-20 | 삼성전자주식회사 | Semiconductor device having low resistance buried metal gate electrode structure and method of manufacturing the same |
CN103094361B (en) * | 2011-11-03 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | PIS capacitor in a kind of SiGe HBT technique and manufacture method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5604140A (en) * | 1995-05-22 | 1997-02-18 | Lg Semicon, Co. Ltd. | Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same |
US5861340A (en) * | 1996-02-15 | 1999-01-19 | Intel Corporation | Method of forming a polycide film |
US6338996B1 (en) * | 1999-04-21 | 2002-01-15 | Nec Corporation | Semiconductor memory device production method |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH061774B2 (en) | 1985-03-29 | 1994-01-05 | 株式会社東芝 | Semiconductor device |
US5652181A (en) * | 1993-11-10 | 1997-07-29 | Micron Display Technology, Inc. | Thermal process for forming high value resistors |
KR0179677B1 (en) * | 1993-12-28 | 1999-04-15 | 사토 후미오 | Semiconductor device wiring or electrode |
JPH0936230A (en) * | 1995-05-15 | 1997-02-07 | Sony Corp | Manufacture of semiconductor device |
US5907188A (en) * | 1995-08-25 | 1999-05-25 | Kabushiki Kaisha Toshiba | Semiconductor device with conductive oxidation preventing film and method for manufacturing the same |
US5798296A (en) * | 1996-05-17 | 1998-08-25 | Micron Technology, Inc. | Method of fabricating a gate having a barrier of titanium silicide |
JP2907126B2 (en) | 1996-06-20 | 1999-06-21 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5923999A (en) * | 1996-10-29 | 1999-07-13 | International Business Machines Corporation | Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device |
US5888588A (en) * | 1997-03-31 | 1999-03-30 | Motorola, Inc. | Process for forming a semiconductor device |
JPH10289885A (en) | 1997-04-14 | 1998-10-27 | Hitachi Ltd | Semiconductor device and manufacture thereof |
US6004869A (en) * | 1997-04-25 | 1999-12-21 | Micron Technology, Inc. | Method for making a low resistivity electrode having a near noble metal |
US5960303A (en) * | 1997-06-23 | 1999-09-28 | Micron Technology, Inc. | Process of forming titanium silicide interconnects |
JPH1126757A (en) | 1997-06-30 | 1999-01-29 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH11233451A (en) * | 1997-10-07 | 1999-08-27 | Texas Instr Inc <Ti> | Cvd based process for manufacturing polymetal gate electrode with stable low resistance |
TW392220B (en) * | 1997-11-24 | 2000-06-01 | United Microelectronics Corp | Structure of barrier layer and glue layer on polysilicon layer and method of manufacturing the same |
TW379371B (en) * | 1997-12-09 | 2000-01-11 | Chen Chung Jou | A manufacturing method of tungsten silicide-polysilicon gate structures |
US6103609A (en) * | 1997-12-11 | 2000-08-15 | Lg Semicon Co., Ltd. | Method for fabricating semiconductor device |
KR100301371B1 (en) * | 1998-07-03 | 2001-10-27 | 윤종용 | Semiconductor memory device and manufacturing method thereof |
US6207568B1 (en) * | 1998-11-27 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer |
US6198144B1 (en) * | 1999-08-18 | 2001-03-06 | Micron Technology, Inc. | Passivation of sidewalls of a word line stack |
JP2002016248A (en) * | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device |
-
1999
- 1999-09-30 JP JP28012699A patent/JP2001102580A/en active Pending
-
2000
- 2000-09-27 US US09/670,400 patent/US6607979B1/en not_active Expired - Fee Related
- 2000-09-29 KR KR1020000057227A patent/KR20010039941A/en not_active Application Discontinuation
-
2001
- 2001-01-02 TW TW089120156A patent/TW490744B/en active
-
2003
- 2003-03-28 US US10/400,583 patent/US20030197232A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5604140A (en) * | 1995-05-22 | 1997-02-18 | Lg Semicon, Co. Ltd. | Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same |
US5861340A (en) * | 1996-02-15 | 1999-01-19 | Intel Corporation | Method of forming a polycide film |
US6338996B1 (en) * | 1999-04-21 | 2002-01-15 | Nec Corporation | Semiconductor memory device production method |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050161721A1 (en) * | 2001-05-16 | 2005-07-28 | Micron Technology, Inc. | Word lines for memory cells |
US7545009B2 (en) * | 2001-05-16 | 2009-06-09 | Micron Technology, Inc. | Word lines for memory cells |
US20120080756A1 (en) * | 2009-07-01 | 2012-04-05 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US8836039B2 (en) * | 2009-07-01 | 2014-09-16 | Panasonic Corporation | Semiconductor device including high-k/metal gate electrode |
Also Published As
Publication number | Publication date |
---|---|
TW490744B (en) | 2002-06-11 |
JP2001102580A (en) | 2001-04-13 |
KR20010039941A (en) | 2001-05-15 |
US6607979B1 (en) | 2003-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5767004A (en) | Method for forming a low impurity diffusion polysilicon layer | |
US7429507B2 (en) | Semiconductor device having both memory and logic circuit and its manufacture | |
US5341016A (en) | Low resistance device element and interconnection structure | |
JP2953404B2 (en) | Semiconductor device and manufacturing method thereof | |
US20050064660A1 (en) | Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects | |
JPH10189966A (en) | Semiconductor device and manufacture thereof | |
JPH07202019A (en) | Semiconductor integrated circuit device and its manufacture | |
KR100763745B1 (en) | A method of producing a semiconductor integrated circuit device | |
JP3022744B2 (en) | Semiconductor device and manufacturing method thereof | |
US20030015748A1 (en) | Semiconductor device including memory cells and manufacturing method thereof | |
US7338871B2 (en) | Method for fabricating semiconductor device | |
JPH06151736A (en) | Semiconductor integrated circuit device and manufacture thereof | |
US6607979B1 (en) | Semiconductor device and method of producing the same | |
US20010052648A1 (en) | Semiconductor device and method of manufacturing the same | |
US20080251824A1 (en) | Semiconductor memory device and manufacturing method thereof | |
US6815762B2 (en) | Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines | |
US6174762B1 (en) | Salicide device with borderless contact | |
JP3367480B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
JP3061117B2 (en) | Method for manufacturing semiconductor device | |
JP3324648B2 (en) | Method for manufacturing semiconductor device | |
US6830991B2 (en) | Method of manufacturing a semiconductor device including a gettering operation | |
US6683357B2 (en) | Semiconductor constructions | |
US20070269974A1 (en) | Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer | |
US6489198B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2000269461A (en) | Semiconductor storage device and its manufacture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |