JP2907126B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a structure of a gate electrode and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices, in particular, MOSFE
Higher performance of T has been realized by higher speed and higher integration by miniaturization. However, since the cross-sectional area of the element is reduced due to miniaturization, the resistance in the depth direction of each of the gate electrode and the source / drain region is increased, and it becomes difficult to increase the speed. For example, according to the conceptual diagram of an example of the layout diagram of the conventional CMOS inverter shown in FIG. 11, the distance between the gate electrode and the portion where the same potential is required is about 50 μm longer than that of the source / drain region. Therefore, it is particularly necessary to reduce the resistance of the gate electrode.

Conventionally, for example, as shown in a conceptual cross-sectional view of an example of a conventional MOSFET having a gate electrode structure in FIG. 12, the gate electrode is made of a polysilicon film. A gate electrode structure in which a tungsten film having a relatively low resistivity is formed on a polysilicon film is effective. For example, FIG. 13 is a conceptual sectional view of an example of a conventional MOSFET having a tungsten film on a gate electrode. Here, the titanium nitride film is a reaction suppression film between the tungsten film and the polysilicon film.

[0004] On the other hand, there is a contact structure as an example of a conventional tungsten film, titanium nitride film, and silicon having low resistance. FIG. 15 is a conceptual cross-sectional view of an example of a conventional contact structure having a tungsten film shown in FIG. 14. Comparing the contact of FIG. 14 with the gate electrode of FIG. 11 described above, it is sufficient to lower the resistance of the contact in the film thickness direction, whereas the lower resistance of the gate electrode It is necessary to reduce the resistance in the width direction. Since the gate width may be about 50 μm, it is necessary to lower the resistance more sufficiently.

Furthermore, the step of forming the contact low-resistance structure is a step after the formation of the source / drain regions. Since the diffusion of the impurities in the source / drain regions occurs, the step of about 650 ° C. or higher cannot be used. . But,
Since the step of forming the low-resistance structure of the gate electrode is a step before forming the source / drain regions, a process at about 650 ° C. or more can be used.

[0006]

Conventionally, as one of the methods for reducing the resistance of a gate electrode, a refractory metal film having a low resistivity (for example, a resistivity of 5 μΩ) is formed on a polysilicon film used as a gate electrode. (Cm tungsten film) is used. However, the polysilicon film and the high melting point metal film react by the subsequent heat treatment, and a high melting point high melting point silicide film (for example, having a resistivity of 30 μm).
The formation of a Ω · cm tungsten silicide film) is a problem. For example, "Silicides for VSI Application, 1983, pp. 40-41, (Silicides for V
LSI Applications, p. 40-41,
1983) ”states that a heat treatment at 600 ° C. or more forms a tungsten silicide film with high resistivity.

On the other hand, in order to realize a high-performance fine CMOS having a gate length of 0.35 μm or less, it is necessary to suppress the short channel effect. To this end, a surface channel type nMOSFET using a pn gate structure and a pMOSF
It is necessary to form a CMOS composed of ET. pn
When a low-resistance structure made of a refractory metal is applied to the gate structure, the tungsten silicide film formed between the tungsten film and the polysilicon film causes interdiffusion of impurities present in the gate electrode, and the performance of the MOSFET is reduced. Has been found to degrade. For example, "198
May 1997, Symposium on VSI Technology Digest of Technical Paper, pp. 29-30, Symposium on VLS
I Technology of Technical
Papers, p. 29-30, May, 1989 "
Describes that the threshold voltage of a pMOSFET is increased by interdiffusion through a tungsten silicide film.

From the above, it is necessary to form a reaction suppression film between the tungsten film and the polysilicon film.
For example, "1988, Solid Solid Film, No. 166, pp. 1-14, (Thin Solid Fi
lms, vol. 166, p. 1-14, 1996) "
Discloses a technique for suppressing a reaction between a tungsten film and a polysilicon film by forming a titanium nitride film and a tungsten film on the polysilicon film. But,
When a titanium nitride film is used as a reaction suppressing film, there has been a problem that the resistance of a tungsten film formed thereon becomes high. For example, FIG. 15 shows “VLSI Multi-Level Interconnection Conference, June 1995, pp. 168-174, (VLSI M
ultralevel Interconnection
Conference, p. 168-174, Jun
e, 1995) ") is an example of a method for manufacturing a gate electrode using a conventional tungsten film. After a device isolation region 2, a gate oxide film 3, and a polysilicon film 4 are formed on a silicon substrate 1, a titanium nitride film 5 is formed, and then a tungsten film 6 is formed. It is described that the sheet resistance in this case is higher than when the base is a silicon substrate or a silicon oxide film.

Next, when a conventional fine CMOS having a pn gate structure is formed, the gate electrode and source / drain regions of the nMOS and pMOS are simultaneously formed by ion implantation and subsequent heat treatment. Only needed twice. On the other hand, when a CMOS having a gate electrode having a stacked structure of a tungsten film, a reaction suppression film, and a polysilicon film is formed, it is difficult to introduce impurities into the gate electrode because the tungsten film and the reaction suppression film are thick. Therefore, since it is necessary to introduce impurities into the gate electrode before the formation of the reaction suppression film and the tungsten film, the step of exposing the resist is required twice. Further, in order to introduce impurities into the source / drain regions, the resist is exposed two more times. There has been a problem that a total of four exposure steps of the resist are required. For example, "December 1994, IEE
International Electron Device Meeting Technical Digest, 497-500
Page, (IEEE International Ele
ctron Devices Meeting Tec
hnical Digest, p. 497-500,1
994) ".

The above-described structure for forming a tungsten film on a titanium nitride film is also used in a technique for contacting a semiconductor layer. In this case, since the contact forming step is performed after the source / drain region forming step, the resistance needs to be reduced by a heat treatment at about 650 ° C. or less. In this case, too, a contrivance has been made to reduce the resistance. However, in the contact technology, the purpose is to reduce the resistance in the film thickness direction. 650 ° C
The following heat treatment was sufficient. On the other hand, the method for reducing the resistance of the gate electrode according to the present invention is to reduce the resistance in the gate width direction, and sometimes the gate width becomes several tens μm or more, which is much lower than the resistance at the contact portion. There is a demand for resistance.

Japanese Patent Application Laid-Open No. 3-155632 discloses a process in which a titanium nitride film is applied to a contact portion, and after forming the titanium nitride film, a heat treatment is performed at 950 ° C., and then an aluminum film is formed. However, the thickness of the titanium nitride film was as thick as 100 nm, and as shown in the examples, it could not be applied in the present invention. The contact formation step by the heat treatment at 950 ° C. is a step after the formation of the source / drain regions. Since the impurity diffusion in the source / drain regions is remarkable, the MOSFET having a fine gate length of 0.35 nm or less is formed. Can not be used.

The above is summarized.

The first problem is that the resistance of the tungsten film formed on the titanium nitride film is increased.

The second problem is that the nMOSFET and p
In order to introduce impurities for forming the gate electrode and the source / drain regions of the MOSFET, four steps of resist exposure are required, which increases the cost.

An object of the present invention is to provide a low-resistance gate electrode using a stacked structure of a tungsten film, a titanium nitride film, and a polysilicon film.

Another object of the present invention is to reduce the number of times of exposure of a resist for introducing impurities for forming the gate electrodes and source / drain regions of the nMOSFET and the pMOSFET, thereby reducing the manufacturing cost.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
The manufacturing method includes at least a titanium nitride film and a refractory metal film.
MOS type semiconductor device having a gate electrode including a laminated structure
Forming a titanium nitride film
Successively recrystallizing the titanium nitride film;
Forming a melting point metal film.
You. More specifically, a step of recrystallizing the titanium nitride film
By heat treatment in nitrogen or ammonia.
And features. This heat treatment is performed at a temperature of 800 ° C.
It is characterized in that it is performed in degrees. As the refractory metal film
Selected from tungsten, molybdenum or platinum
It is preferable that the film is made of a material.

Further, a method of manufacturing a semiconductor device according to the present invention
Titanium nitride in which the gate electrode is formed on a gate insulating film
And a high-melting point metal film formed on the titanium nitride film
It is characterized by having a structure .

Alternatively , a method of manufacturing a semiconductor device according to the present invention.
Means that the gate electrode comprises a polysilicon film and a titanium nitride film.
The titanium nitride film has a laminated structure with a high melting point metal film.
Polysilicon on the gate insulating film prior to the process of forming
Including a step of forming a film or an amorphous silicon film
It is characterized by having. The thickness of the titanium nitride film is 10 n
Preferably, it is less than m. In addition, the high melting point metal
After the step of forming the film, the refractory metal film and titanium nitride
Introducing impurities into the polysilicon film through the polysilicon film
The method may further include a step. In addition, this impurity
During the process of introducing
Also introduces impurities to form source and drain regions.
Can do it. Manufacturing of the semiconductor device of the present invention as described above.
In the method, the MOS type semiconductor device is constituted by CMOS.
Or have a pn gate structure
Especially effective when configured by CMOS
It is.

In the semiconductor device of the present invention, the gate electrode
Silicon film and titanium nitride that has been recrystallized after deposition
Deposited on the titanium nitride film after the recrystallization treatment.
Features a stacked structure with a stacked high-melting metal film
MOS type semiconductor device. This titanium nitride film
After deposition by heat treatment in nitrogen or ammonia.
It is preferably recrystallized. High melting point
Tungsten, molybdenum or platinum as the metal film
It is preferable that the film is made of a material selected more.
Further, the thickness of the titanium nitride film may be less than 10 nm.
It is suitable. Further, the present invention provides a refractory metal film and a nitride film.
Impurity is introduced into the polysilicon film through the titanium oxide film.
At the same time as introducing impurities into the specified region of the semiconductor substrate.
Semiconductor device having source and drain regions formed.
The location is disclosed. This semiconductor device is based on CMOS.
Or CMOS having a pn gate
It is particularly effective to be constituted by

Further, in the semiconductor device of the present invention, the gate electrode is composed of a titanium nitride film and a high melting point metal film on the titanium nitride film. What the titanium nitride film is intended has been subjected to recrystallization treatment after deposition, also refractory metal film is deposited after the recrystallization treatment on the titanium nitride film
It is. More specifically, it is desirable that the titanium nitride film be recrystallized by heat treatment in nitrogen or ammonia after deposition. As a high melting point metal film,
It is preferable that the film is formed of a material selected from tungsten, molybdenum, and platinum. Further, the width of the gate electrode is 0.35μm or less, and it is preferable that the thickness of the titanium nitride film is less than 10 nm.

(Operation) First, the grain size of the titanium nitride film is increased by recrystallization of the titanium nitride film. further,
The resistance of the gate electrode is reduced by the tungsten film formed thereon.

Second, by setting the thickness of the titanium nitride film to less than 10 nm, the impurity can be introduced into the polysilicon film by ion implantation.

[0024]

Embodiments of the present invention will be described in detail with reference to the drawings.

[0025]

First Embodiment A first embodiment will be described in detail with reference to the drawings. Referring to FIG. 1, a method for forming a gate electrode having a first low-resistance tungsten film is as follows. First, an element isolation region 2 and a gate insulating film 3 are formed on a silicon substrate 1. Next, a polysilicon film 4 and a titanium nitride film 5 which will later become gate electrodes are deposited, and recrystallization is performed. Finally, a tungsten film 6 (200 nm or less) is deposited on the recrystallized titanium nitride film 51.

Next, a detailed configuration of a method for forming a gate electrode having a first low-resistance tungsten film according to the first embodiment will be described. First, the polysilicon film 4 (200
nm or less) is doped by p-type in the case of pMOS and n-type in the case of nMOS by ion implantation
A gate electrode is formed. The titanium nitride film 5 (20
The thickness of 0 nm or less is formed in order to suppress the reaction between the polysilicon film 4 and a tungsten film to be formed later and to suppress the formation of a high-resistance tungsten silicide film. Next, the titanium nitride film is recrystallized. For example, referring to FIG.
The recrystallization of the titanium nitride film is performed by heat treatment in nitrogen (600 ° C.
As described above, preferably, the effect is remarkable at 650 ° C. or higher and 800 ° C. or higher, and is performed for 60 seconds or less. Also, for example,
Referring to FIG. 3, recrystallization of the titanium nitride film is performed by heat treatment in an ammonia gas (600 ° C. or higher, preferably 650 ° C.).
The effect is remarkable at a temperature of 800 ° C. or more and 800 ° C. or more and 60 seconds or less). Further, when a tungsten film 6 (200 nm or less) is deposited on these titanium nitride films, a low-resistance tungsten film can be formed reflecting the crystallinity of the titanium nitride films.

[0027]

Second Embodiment Next, a second embodiment will be described in detail with reference to the drawings. Referring to FIG. 4, a method for forming a gate electrode having a second low-resistance tungsten film is as follows. The gate electrode is made of the titanium nitride film 5 instead of the polysilicon film. With this structure, the process of doping the polysilicon film becomes unnecessary, and the manufacturing process can be shortened.

Next, a detailed configuration of a method for forming a gate electrode having a second low-resistance tungsten film according to the second embodiment will be described. First, the titanium nitride film 5 (200
nm or less), and the titanium nitride film is recrystallized. For example, referring to FIG. 5, recrystallization of the titanium nitride film is performed by heat treatment in nitrogen (600 ° C. or higher, preferably 6 ° C. or more).
The effect is remarkable at 50 ° C. or higher and 800 ° C. or higher, and is performed for 60 seconds or less). For example, referring to FIG. 6, recrystallization of the titanium nitride film is performed by heat treatment in an ammonia gas (600 ° C. or higher, preferably 650 ° C. or higher, 800 ° C. or lower).
The effect is remarkable at a temperature of not lower than 60 ° C., and is not more than 60 seconds).
Further, a tungsten film 6 is formed on these titanium nitride films.
By depositing (200 nm or less), a low-resistance tungsten film can be formed reflecting the crystallinity of the titanium nitride film.

[0029]

Third Embodiment Next, a third embodiment will be described in detail with reference to the drawings. Referring to FIG. 9, the structure of a gate electrode having a first low-resistance tungsten film is such that a silicon substrate 1 has an element isolation region 2 (depth of 500 nm or less) with a gap of 2000 nm or less, and a gate insulating film 3 with a gap of 500 nm or less.
(Thickness less than 10 nm), a width of 0.3 on the gate insulating film
A polysilicon film 4 of 5 μm or less (thickness of 200 nm or less),
A titanium nitride film 5 (thickness less than 10 nm) having a width of 0.35 μm or less on the polysilicon film;
A tungsten film 6 having a width of 0.35 μm or less (thickness: 200 nm)
Below).

Next, a detailed structure of the gate electrode having the first low-resistance tungsten film according to the third embodiment will be described. Referring to FIG. 9, element isolation region 2
(A depth of 500 nm or less) suppresses mutual influence between a plurality of MOSFETs. The gate insulating film 3 (with a film thickness of less than 10 nm) is an insulating film of a MOSFET, a polysilicon film 4 (with a film thickness of 200 nm).
nm or less) becomes the gate electrode of the MOSFET. The titanium nitride film 5 (less than 10 nm thick) suppresses the reaction between the polysilicon film 4 and the tungsten film 6 on the titanium nitride film 5.
Further, when the impurity is introduced into the polysilicon film later, if the thickness of the titanium nitride film is less than 10 nm, the impurity diffusion in the vertical direction is not affected, and the impurity can be introduced after the tungsten film is formed. Impurity introduction into the source / drain regions can be realized at the same time. Thereby, the number of times of exposure of the resist can be reduced twice in the CMOS. Further, in the pn gate structure, nM of impurity in the polysilicon film 4 is used.
Mutual diffusion between the OS and the pMOS is suppressed, and fluctuations in MOSFET characteristics such as threshold voltage fluctuations are suppressed. The tungsten film 6 realizes a lower resistance of the gate electrode.

[0031]

Fourth Embodiment Next, a fourth embodiment will be described in detail with reference to the drawings. Referring to FIG.
The structure of the gate electrode having a low-resistance tungsten film of
An element isolation region 2 having a gap of 2000 nm or less (depth of 500 nm or less) and a gate insulating film 3 having a gap of 2000 nm or less
(Thickness less than 10 nm), a width of 0.3 on the gate insulating film
It is composed of a titanium nitride film 5 having a thickness of 5 μm or less (thickness of 10 nm or less) and a tungsten film 6 having a width of 0.35 μm or less (thickness of 400 nm or less) on the titanium nitride film.

Next, a detailed structure of the gate electrode having the second low-resistance tungsten film according to the fourth embodiment will be described. Referring to FIG. 10, the element isolation region 2 (500 nm or less in depth) suppresses mutual influence between a plurality of MOSFETs. Gate insulating film 3 (thickness 10 nm or less)
Represents a MOSFET insulating film, a titanium nitride film 5 (film thickness 100
(less than nm) will be the gate electrode of the MOSFET. Even if the titanium nitride film 5 has a thickness of less than 10 nm, the reaction between the tungsten film 6 and the gate insulating film 3 can be suppressed. Further, since the titanium nitride film is thin, the MOSFET has only the work function of the tungsten film. Is determined.

The third and fourth embodiments are summarized above.
When the thickness of the titanium nitride film is less than 10 nm, when the polysilicon film is formed under the titanium nitride film according to the third embodiment, impurities can be introduced into the polysilicon film after the formation of the tungsten film. . In the fourth embodiment, when the polysilicon film is not formed under the titanium nitride film, the threshold voltage of the MOSFET can be determined only by the work function of the tungsten film because the thickness of the titanium nitride film is as thin as 10 nm or less. . Therefore, the thickness of the titanium nitride film is desirably less than 10 nm.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) A first embodiment will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a part of a method for manufacturing a gate electrode having a low-resistance tungsten film. First, an element isolation region 2 (thickness 300 nm) and a gate insulating film 3 (thickness 6 nm) are formed on a silicon substrate 1.
To form Next, a polysilicon film 4 (thickness: 100 nm) and a titanium nitride film 5 (thickness: 5 nm) to be a gate electrode later are deposited, and a recrystallization process is performed. Finally, a tungsten film 6 (film thickness 4) is formed on the recrystallized titanium nitride film 51.
0 nm). Thus, a low-resistance tungsten film can be obtained on the recrystallized titanium nitride film.

Next, another method of the first embodiment will be described with reference to the drawings. FIG. 2 is a schematic cross-sectional view showing a part of a method for manufacturing a gate electrode having a low-resistance tungsten film. The recrystallization of the titanium nitride film of the first embodiment is performed by a heat treatment in nitrogen (900 ° C., 30 seconds). According to this method, a low-resistance tungsten film can be obtained on the recrystallized titanium nitride film.

Next, another method of the first embodiment will be described with reference to the drawings. FIG. 3 is a schematic cross-sectional view showing a part of a method for manufacturing a gate electrode having a low-resistance tungsten film. The recrystallization of the titanium nitride film of the first embodiment is performed by heat treatment in an ammonia gas (900 ° C., 3
0 seconds). According to this method, a low-resistance tungsten film can be obtained on the recrystallized titanium nitride film.

(Embodiment 2) Next, a second embodiment will be described with reference to the drawings. FIG. 4 is a schematic cross-sectional view showing a part of a method for manufacturing a gate electrode having a low-resistance tungsten film. First, an element isolation region 2 (thickness 300 nm) and a gate insulating film 3 (thickness 6 nm) are formed on a silicon substrate 1. Next, a titanium nitride film 5 (thickness: 5 nm) serving as a gate electrode is deposited, and a recrystallization process is performed. Finally, a tungsten film 6 (40 nm thick) is deposited on the titanium nitride film 51 after the heat treatment in nitrogen. Thus, a low-resistance tungsten film can be obtained on the recrystallized titanium nitride film. In addition, with this structure, the step of doping the polysilicon film becomes unnecessary, and the manufacturing cost can be reduced.

Next, another method of the second embodiment will be described with reference to the drawings. FIG. 5 is a schematic cross-sectional view showing a part of a method for manufacturing a gate electrode having a low-resistance tungsten film. The recrystallization of the titanium nitride film of the second embodiment is performed by a heat treatment in nitrogen (900 ° C., 30 seconds). According to this method, a low-resistance tungsten film can be obtained on the recrystallized titanium nitride film.

Next, another method of the second embodiment will be described with reference to the drawings. FIG. 6 is a schematic cross-sectional view showing a part of a method for manufacturing a gate electrode having a low-resistance tungsten film. The recrystallization of the titanium nitride film of the second embodiment was performed by heat treatment in an ammonia gas (900 ° C., 3
0 seconds). According to this method, a low-resistance tungsten film can be obtained on the recrystallized titanium nitride film.

(Embodiment 3) Next, a third embodiment will be described with reference to the drawings. FIG. 9 is a schematic sectional view showing an embodiment of the structure of the gate electrode having the first low-resistance tungsten film. The structure of the gate electrode having the first low-resistance tungsten film is as follows.
A device isolation region 2 (depth 300 nm) with a gap of 0 nm, a gate insulating film 3 (thickness 6 nm) in the gap, and a polysilicon film 4 with a width of 0.35 μm or less (thickness 10 nm) on the gate insulating film.
0 nm), a titanium nitride film 5 having a width of 0.35 μm or less (thickness: 5 nm) on the polysilicon film, and a tungsten film 6 having a width of 0.35 μm or less (thickness: 40 nm) on the titanium nitride film.
nm). Here, the thickness of the titanium nitride film is sufficiently large so that the polysilicon film and the tungsten film do not react with each other, and when impurities are introduced into the polysilicon film later,
The thickness is 5 nm, which has little influence on the impurity diffusion in the vertical direction. For example, from the example of the dependency of the threshold voltage of the MOSFET having the tungsten film according to the present invention shown in FIG. 8 on the titanium nitride film thickness, the threshold voltage increases as the titanium nitride film becomes thicker. In particular, when the titanium nitride film is 5 nm,
Since the threshold voltage is suppressed to less than 0.2 V, the thickness of the titanium nitride film is desirably less than about 10 nm.

(Embodiment 4) Next, a fourth embodiment will be described with reference to the drawings. FIG. 10 is a schematic sectional view showing an embodiment of the structure of the gate electrode having the first low-resistance tungsten film. The structure of the gate electrode having the first low-resistance tungsten film is as follows.
A device isolation region 2 (depth 300 nm) with a gap of 00 nm, a gate insulating film 3 (thickness 6 nm) in the gap, and a titanium nitride film 5 (thickness 5n) having a width of 0.35 μm or less on the gate insulating film.
m), a tungsten film 6 (thickness: 100 nm) having a width of 0.35 μm or less on the titanium nitride film. Here, the thickness of the titanium nitride film is sufficiently large so that the polysilicon film and the tungsten film do not react with each other, and
The thickness is 5 nm which is sufficiently thin so that the threshold value control of T can be determined by the work function of the tungsten film.

FIG. 7 shows an example of the relationship between the sheet resistance of the tungsten film manufactured by the method shown in the above embodiment and the heat treatment temperature in nitrogen. With the heat treatment in nitrogen according to the present invention, the sheet resistance of the tungsten film decreases as the heat treatment temperature increases. As can be seen from FIG. 7, as the heat treatment temperature of the titanium nitride film prior to the deposition of the tungsten film, the reduction in resistance at 650 ° C. or higher is remarkable, and the temperature is 800 ° C.
If the above heat treatment is performed, the resistivity becomes 1
It can be reduced by 6% or more. The heat treatment time is 6
It is desirably 0 seconds or less. This is to prevent impurity diffusion in the channel.

The case where the uppermost layer of the gate electrode is a tungsten film has been described above. However, it goes without saying that a metal having a high melting point (molybdenum, platinum, or the like) that can withstand heat treatment for forming the gate electrode and the source / drain regions may be freely selected.

Here, the recrystallization of the titanium nitride film at a high temperature prior to the deposition of the tungsten film increases the grain size of the titanium nitride film, thereby increasing the grain size of the tungsten film. It is considered that the low resistivity was realized.

The fact that the thickness of the titanium nitride film is less than 10 nm is the same in both the third and fourth embodiments.

[0047]

The first effect is to reduce the resistance of the tungsten film. The reason is that the reaction between the polysilicon film and the tungsten film is suppressed by the titanium nitride film, and that the titanium nitride film underlying the tungsten film is recrystallized.

The second effect is that when a polysilicon film is not used for a gate electrode, the number of steps for introducing impurities can be reduced. The reason is that the threshold voltage of the MOSFET is determined by the titanium nitride film or the tungsten film for the gate electrode.

The third effect is suppression of mutual diffusion of impurities in the gate electrode. The reason is that the reaction between the polysilicon film and the tungsten film is suppressed by the titanium nitride film.

The fourth effect is a reduction in the number of resist exposure steps. The reason for this is that by making the titanium nitride film thinner and realizing impurity diffusion in the vertical direction, impurities can be introduced into the polysilicon film after the tungsten film is formed, and impurities can be introduced into the gate electrode and the source / drain regions. This is because they can be performed simultaneously. For example, during CMOS formation, two exposure steps can be reduced.

A fifth effect is that when the polysilicon film is not used for the gate electrode and the thickness of the titanium nitride film is less than 10 nm, the controllability of the threshold voltage is improved.
The reason is that only the work function of the tungsten film
This is because the threshold voltage of ET can be controlled.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an example of a method for manufacturing a gate electrode having a tungsten film according to the present invention.

FIG. 2 is a schematic sectional view of an example of a method for manufacturing a gate electrode having a tungsten film according to the present invention.

FIG. 3 is a schematic sectional view of an example of a method for manufacturing a gate electrode having a tungsten film according to the present invention.

FIG. 4 is a schematic sectional view of an example of a method for manufacturing a gate electrode having a tungsten film according to the present invention.

FIG. 5 is a schematic sectional view of an example of a method for manufacturing a gate electrode having a tungsten film according to the present invention.

FIG. 6 is a conceptual sectional view of an example of a method for manufacturing a gate electrode having a tungsten film according to the present invention.

FIG. 7 is an example of the dependence of the sheet resistance of a gate electrode having a tungsten film on the heat treatment temperature in nitrogen according to the present invention.

FIG. 8 shows a MOS having a tungsten film according to the present invention.
4 is an example of the dependency of the threshold voltage of a FET on the thickness of a titanium nitride film.

FIG. 9 is a conceptual cross-sectional view of an example of a structure of a gate electrode having a tungsten film according to the present invention.

FIG. 10 is a sectional structural view of an example of the structure of a gate electrode having a tungsten film according to the present invention.

FIG. 11 is a conceptual sectional view of an example of a layout diagram of a conventional CMOS inverter.

FIG. 12 is a conceptual sectional view of an example of a conventional MOSFET.

FIG. 13 shows a conventional MO having a tungsten film on a gate.
It is a cross section conceptual diagram of an example of SFET.

FIG. 14 is a conceptual sectional view of an example of a conventional contact structure having a tungsten film.

FIG. 15 is a schematic sectional view of an example of a conventional method for manufacturing a gate electrode having a tungsten film.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation region 3 gate insulating film 4 polysilicon film 5 titanium nitride film 51 recrystallized titanium nitride film 52 titanium nitride film after heat treatment in nitrogen 53 titanium nitride film after heat treatment in ammonia 6 tungsten film 7 gate Electrode side wall film 8 source / drain region 9 interlayer insulating film 10 n ⁺ or p ⁺ silicon

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/28 301 H01L 21/20

Claims (22)

(57) [Claims] 1. A method for manufacturing a MOS type semiconductor device having a gate electrode including a laminated structure of at least a titanium nitride film and a refractory metal film, comprising: a step of forming a titanium nitride film; A method for manufacturing a semiconductor device, comprising: a step of recrystallizing; and a step of forming a refractory metal film. 2. The method according to claim 1, wherein the step of recrystallizing the titanium nitride film is performed by heat treatment in nitrogen or ammonia. 3. The method according to claim 2, wherein the heat treatment is performed at a temperature of 800 ° C. or higher. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said high melting point metal film is a film made of a material selected from tungsten, molybdenum and platinum. 5. The semiconductor device according to claim 1, wherein the gate electrode has a two-layer structure of a titanium nitride film formed on a gate insulating film and a high melting point metal film formed on the titanium nitride film.
A method for manufacturing a semiconductor device according to any one of claims 1 to 4. 6. The gate electrode has a laminated structure of a polysilicon film, a titanium nitride film and a refractory metal film, and a polysilicon film or an amorphous silicon film is formed on a gate insulating film prior to the step of forming the titanium nitride film. 5. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a semiconductor device. 7. The method according to claim 6, wherein the thickness of the titanium nitride film is less than 10 nm. 8. The method according to claim 6, further comprising, after the step of forming the refractory metal film, a step of introducing an impurity into the polysilicon film through the refractory metal film and the titanium nitride film. A method for manufacturing a semiconductor device. 9. The method according to claim 8, wherein in the step of introducing an impurity into the polysilicon film, the impurity is simultaneously introduced into a predetermined region of the semiconductor substrate to form a source and a drain region. A method for manufacturing a semiconductor device. 10. The semiconductor device according to claim 1, wherein said MOS type semiconductor device is a CMO.
10. The method of manufacturing a semiconductor device according to claim 9, comprising S. 11. The method according to claim 9, wherein the MOS type semiconductor device is constituted by a CMOS having a pn gate structure. 12. A lamination of a polysilicon film having a gate electrode, a titanium nitride film subjected to a recrystallization process after deposition, and a high melting point metal film deposited on the titanium nitride film after the recrystallization process. A MOS type semiconductor device having a structure. 13. The semiconductor device according to claim 12, wherein said titanium nitride film is recrystallized by heat treatment in nitrogen or ammonia after deposition. 14. The semiconductor device according to claim 12, wherein said high melting point metal film is a film made of a material selected from tungsten, molybdenum and platinum. 15. The semiconductor device according to claim 12, wherein said titanium nitride film has a thickness of less than 10 nm. 16. The source and drain regions are formed by simultaneously introducing impurities into the polysilicon film through the refractory metal film and the titanium nitride film, and simultaneously introducing impurities into a predetermined region of the semiconductor substrate. The semiconductor device according to claim 15. 17. The MOS type semiconductor device is a CMOS device.
17. The method according to claim 12, wherein:
The semiconductor device according to any one of the above. 18. The semiconductor device according to claim 12, wherein said MOS type semiconductor device is constituted by a CMOS having a pn gate. 19. Gate electrode is constructed with a titanium nitride film, a refractory metal film on said titanium nitride film, the Chi nitride
The tan film has been subjected to a recrystallization treatment after deposition,
The refractory metal film is recrystallized on the titanium nitride film.
A semiconductor device deposited after processing . 20. The semiconductor device according to claim 19 , wherein the titanium nitride film has been recrystallized by heat treatment in nitrogen or ammonia after deposition. 21. The semiconductor device according to claim 19, wherein the high melting point metal film is a film made of a material selected from tungsten, molybdenum, and platinum. 22. the width of the gate electrode is 0.35μm or less, and from the claims 19 to thickness of the titanium nitride film is equal to or less than 10nm in any <br/> of claim 21 13. The semiconductor device according to claim 1.