US20030082914A1 - Semiconductor wafer processing apparatus - Google Patents
Semiconductor wafer processing apparatus Download PDFInfo
- Publication number
- US20030082914A1 US20030082914A1 US10/315,976 US31597602A US2003082914A1 US 20030082914 A1 US20030082914 A1 US 20030082914A1 US 31597602 A US31597602 A US 31597602A US 2003082914 A1 US2003082914 A1 US 2003082914A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor wafer
- wafer
- grinding
- cleaning
- damaged layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 276
- 238000000227 grinding Methods 0.000 claims abstract description 149
- 238000004140 cleaning Methods 0.000 claims abstract description 100
- 238000009832 plasma treatment Methods 0.000 claims abstract description 47
- 230000007246 mechanism Effects 0.000 claims abstract description 30
- 238000001312 dry etching Methods 0.000 claims description 15
- 230000001681 protective effect Effects 0.000 claims description 15
- 230000007723 transport mechanism Effects 0.000 claims description 14
- 239000007788 liquid Substances 0.000 claims description 13
- 238000003672 processing method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 361
- 239000007789 gas Substances 0.000 description 22
- 230000009471 action Effects 0.000 description 17
- 239000012530 fluid Substances 0.000 description 16
- 238000001020 plasma etching Methods 0.000 description 10
- 238000001816 cooling Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000003507 refrigerant Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 101001139126 Homo sapiens Krueppel-like factor 6 Proteins 0.000 description 1
- 101000661807 Homo sapiens Suppressor of tumorigenicity 14 protein Proteins 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000004065 wastewater treatment Methods 0.000 description 1
- 210000000707 wrist Anatomy 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67748—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber horizontal transfer of a single workpiece
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/976—Temporary protective layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.
Description
- This invention relates to a semiconductor wafer processing apparatus for grinding a semiconductor wafer to thin it.
- In a process for manufacturing a semiconductor wafer for use in a semiconductor device, grinding is performed to decrease the thickness of the semiconductor wafer as thin semiconductor devices are becoming predominant. The grinding is carried out by mechanical grinding of a back side of the semiconductor wafer opposite to its face side after a circuit pattern has been formed on the face side. On the surface of the semiconductor wafer after mechanical grinding, there is a damaged layer embrittled by microcracks formed by mechanical grinding. The damaged layer is known to include the microcracks and impair the fracture strength of the semiconductor wafer. Thus, a conventional semiconductor has been used with such a thickness that the semiconductor is not affected by a decrease in the fracture strength due to the damaged layer.
- In response to the light weight and compact size of electronic equipment, moves for thinning semiconductor devices to meet demands for their light weight and compact size have become brisk. Along this line, further thinning of semiconductor wafers has also been demanded. To reduce the thickness of the semiconductor wafer, however, the influence of the decrease in the fracture strength due to the damaged layer is becoming nonnegligible. To solve this problem, processing to a small thickness (hereinafter referred to as thinning), including removal of the damaged layer, is necessary. However, any appropriate apparatus, which can perform a series of thinning steps, ranging from mechanical grinding of the semiconductor wafer to removal of the damaged layer, has not existed.
- Under these circumstances, the present invention aims to provide a semiconductor wafer processing apparatus and a semiconductor wafer processing method which can perform a series of thinning steps, ranging from mechanical grinding of a semiconductor wafer to removal of its damaged layer.
- According to the present invention, there is provided a semiconductor wafer processing apparatus for grinding a surface of a semiconductor wafer to thin the semiconductor wafer, comprising a grinding portion for mechanically grinding the semiconductor wafer, a wafer cleaning portion for cleaning the semiconductor wafer after mechanical grinding, a damaged layer removal treatment portion for removing a damaged layer, caused to the semiconductor wafer by mechanical grinding, after cleaning by the wafer cleaning portion, and a wafer transport mechanism for transferring the semiconductor wafer between the grinding portion, the wafer cleaning portion, and the damaged layer removal treatment portion.
- It is preferred to include a precenter portion for centering the semiconductor wafer, and supply the semiconductor wafer, which has been centered by the precenter portion, to the grinding portion by the wafer transport mechanism. An stocker can be provided for accommodating the semiconductor wafer before processing which is to be supplied to the grinding portion and/or the semiconductor wafer after processing which has been withdrawn from the damaged layer removal treatment portion. The wafer transport mechanism preferably includes a robot mechanism on a polar coordinate system. Preferably, the wafer transport mechanism also includes a before-cleaning transport portion for withdrawing the semiconductor wafer after mechanical grinding from the grinding portion, and passing the semiconductor wafer on to the wafer cleaning portion, and an after-cleaning transport portion for withdrawing the semiconductor wafer after cleaning from the wafer cleaning portion, and passing the semiconductor wafer on to the damaged layer removal treatment portion. The damaged layer removal treatment portion may be a plasma treatment portion for etching the damaged layer by plasma treatment. The damaged layer removal treatment portion may be a wet etching treatment portion for etching the damaged layer with a chemical liquid. Preferably, the wafer transport mechanism comprises a first wafer transport portion for holding the semiconductor wafer from the precenter portion and bringing the semiconductor wafer onto the grinding portion, a second wafer transport portion for withdrawing the semiconductor wafer ground by the grinding portion and transporting the semiconductor wafer to the wafer cleaning portion, and a third wafer transport portion having a robot mechanism on a polar coordinate system for transferring the semiconductor wafer between the precenter portion, the wafer cleaning portion, and the damaged layer removal treatment portion, and the damaged layer removal treatment portion is disposed in a third quadrant and a fourth quadrant of an orthogonal coordinate system in which an origin of the polar coordinate system of the robot mechanism is a common origin and a direction of the grinding portion is a Y-axis positive direction, and such that the origin of the polar coordinate system is positioned on a line of extension of a semiconductor wafer carry-in and carry-out center line of the damaged layer removal treatment portion. The stocker for accommodating the semiconductor wafer before processing which is to be supplied to the grinding portion and/or the semiconductor wafer after processing which has been withdrawn from the damaged layer removal treatment portion is preferably provided at a position at which the wafer can be brought in and brought out by the third wafer transport portion. The cleaning portion can be disposed in one of the first quadrant and the second quadrant of the orthogonal coordinate system. The precenter portion can be disposed in a quadrant of the coordinate system on a side opposite to the cleaning portion, with the Y-axis of the coordinate system being interposed between the precenter portion and the cleaning portion.
- According to the present invention, there is further provided a semiconductor wafer processing method for thinning a semiconductor wafer to a target thickness, including the steps of mechanically grinding a side of the semiconductor wafer opposite to a surface thereof, where a circuit has been formed, by a grinding portion; withdrawing the semiconductor wafer after mechanical grinding from the grinding portion, and passing the semiconductor wafer on to the wafer cleaning portion; cleaning the semiconductor wafer passed on to the wafer cleaning portion; withdrawing the semiconductor wafer after cleaning from the wafer cleaning portion and passing the semiconductor wafer on to a damaged layer removal treatment portion; and removing a damaged layer, caused by the mechanical grinding, in the damaged layer removal treatment portion.
- The damaged layer removal treatment portion may be a plasma treatment portion for etching the damaged layer by plasma treatment. It is preferred to grind the semiconductor wafer by mechanical grinding to a thickness being a sum of the target thickness and a dry etching margin set in a range of 3 μm to 50 μm, and remove a remainder of the semiconductor wafer by dry etching using plasma treatment. The semiconductor wafer may consist essentially of silicon. After the semiconductor wafer is ground by the mechanical grinding, the semiconductor wafer is preferably cleaned with a liquid before dry etching is performed. The liquid may be water. The damaged layer removal treatment portion may be a wet etching treatment portion for etching the damaged layer with a chemical liquid. Preferably, mechanical grinding and removal of the damaged layer are performed, with a protective film being formed on the surface of the semiconductor wafer where the circuit has been formed.
- FIG. 1 is a perspective view of a semiconductor wafer processing apparatus as an embodiment of the present invention;
- FIG. 2 is a plan view of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIG. 3 is a perspective view of a wafer stocker of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIG. 4 is a perspective view of the wafer stocker of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIG. 5 is a partial plan view of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIG. 6 is a side view of a grinding portion of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIG. 7 is a sectional view of a wafer cleaning portion of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIG. 8 is a sectional view of a plasma treatment portion of the semiconductor wafer processing apparatus as the embodiment of the present invention;
- FIGS.9(a) and 9(b) are each a process explanation drawing of a semiconductor wafer processing method as an embodiment of the present invention;
- FIGS.10(a) and 10(b) are each a process explanation drawing of a semiconductor wafer processing method as an embodiment of the present invention; and
- FIG. 11 is a flow chart for cleaning of a semiconductor wafer in the semiconductor wafer processing method as the embodiment of the present invention.
- Embodiments of the present invention will be described by reference to the accompanying drawings.
- The entire structure of a semiconductor wafer processing apparatus will be described with reference to FIGS. 1 and 2. In FIGS. 1 and 2, a third
wafer transport portion 3 composed of a robot mechanism on a polar coordinate system is disposed on afront half 1 a of an upper surface of abase portion 1. Awafer stocker 2 having magazines (wafer cassettes) 2A, 2B, a firstplasma treatment portion 4A, a secondplasma treatment portion 4B, aprecenter portion 5, and awafer cleaning portion 10 are disposed radially around the thirdwafer transport portion 3. Themagazines plasma treatment portion 4A, secondplasma treatment portion 4B,precenter portion 5, andwafer cleaning portion 10 are arranged in a range in which a wafer can be brought in and out by the thirdwafer transport portion 3. - The
magazines wafer stocker 2 accommodate a plurality of semiconductor wafers before and after processing. The firstplasma treatment portion 4A and the secondplasma treatment portion 4B remove a damaged layer, caused by mechanical grinding on the surface of asemiconductor wafer 11, by the etching action of a plasma generated in a vacuum atmosphere. Thus, the firstplasma treatment portion 4A and the secondplasma treatment portion 4B constitute a damaged layer removal treatment portion for the semiconductor wafer. - The
precenter portion 5 performs a centering action for preliminarily aligning the semiconductor wafer to be passed on to a grindingportion 6 to be described later on. Thewafer cleaning portion 10 cleans the semiconductor wafer, ground by the grindingportion 6, with a cleaning fluid. - The
grinding portion 6 for mechanically grinding thesemiconductor wafer 11 is disposed on arear half 1 b of the upper surface of thebase portion 1. Thegrinding portion 6 has awall portion 6 a erected on the upper surface of thebase portion 1, and afirst grinding unit 8A and asecond grinding unit 8B are disposed on a front side surface of thewall portion 6 a. Thefirst grinding unit 8A and thesecond grinding unit 8B perform rough grinding and finish grinding, respectively, of thesemiconductor wafer 11. A turn table 7 surrounded by acombing 6 b is disposed below thefirst grinding unit 8A andsecond grinding unit 8B. The turn table 7 makes an index rotation to position the semiconductor wafer, an object to be ground, relative to thefirst grinding unit 8A andsecond grinding unit 8B while holding the semiconductor wafer. - Ahead of the
grinding portion 6, a firstwafer transport portion 9A and a secondwafer transport portion 9B are disposed. The firstwafer transport portion 9A brings the semiconductor wafer, aligned at theprecenter portion 5, into thegrinding portion 6. The secondwafer transport portion 9B brings the semiconductor wafer after mechanical grinding out of thegrinding portion 6. Thus, the aforementioned firstwafer transport portion 9A, secondwafer transport portion 9B, and thirdwafer transport portion 3 constitute a wafer transport mechanism for transferring thesemiconductor wafer 11 between the grindingportion 6,wafer cleaning portion 10, firstplasma treatment portion 4A and secondplasma treatment portion 4B, supplying thesemiconductor wafer 11 to the grindingportion 6, and withdrawing thesemiconductor wafer 11 after dry etching from the firstplasma treatment portion 4A and secondplasma treatment portion 4B. - Layout of the respective members on the
base portion 1 will be described. As shown in FIG. 2, an XY orthogonal coordinate system, having an origin O of the polar coordinate system of the robot mechanism of the thirdwafer transport portion 3 as a common origin, and having a direction of the grindingportion 6 as a Y-axis positive direction, is set on thebase portion 1. In this orthogonal coordinate system, theprecenter portion 5, firstwafer transport portion 9A and first grindingunit 8A are in the first quadrant, thesecond grinding unit 8B, secondwafer transport portion 9B andwafer cleaning portion 10 are in the second quadrant, the firstplasma treatment portion 4A andmagazine 2A are in the third quadrant, and the secondplasma treatment portion 4B andmagazine 2B are in the fourth quadrant. - In this layout, the
magazines plasma treatment portion 4A, secondplasma treatment portion 4B,precenter portion 5 andwafer cleaning portion 10 are arranged such that their wafer carry-in and carry-out directions agree with the direction of the origin O of the polar coordinate system. The firstplasma treatment portion 4A and secondplasma treatment portion 4B, in particular, are required to be directed and positioned accurately during carry-in and carry-out of the wafer. Thus, their positions and directions of disposition are set such that the origin O is accurately positioned on lines of extension La, Lb of their wafer carry-in and carry-out center lines. - The constitutions and functions of the respective members will be described sequentially, starting with the third
wafer transport portion 3. In FIG. 2, the thirdwafer transport portion 3 is mounted in a concave 1 c formed in the center of thefront half 1 a. The robot mechanism on the polar coordinate system is disposed on abase member 3 a of the thirdwafer transport portion 3. Thebase member 3 a can be turned 360 degrees by a drive mechanism (not shown) on thebase portion 1 about the origin O of the polar coordinate system to control the direction of the robot mechanism freely. - The robot mechanism is constituted by coupling a
second turning arm 14 b to afirst turning arm 14 a extending laterally of a vertically expansible arm shaft (not shown) erected on thebase member 3 a, and mounting awafer holding portion 17 to a front end of thesecond turning arm 14 b. Thewafer holding portion 17 has a bifurcated fork-shapedmember 17 b having attraction holes 17 a provided on an upper surface thereof (see FIG. 4). Thewafer holding portion 17 rotates about its axis by ahand rotation mechanism 15, and the inclination of thewafer holding portion 17 is controlled by awrist mechanism 16. Moreover, thewafer holding portion 17 can be moved forward and backward horizontally by turning thefirst turning arm 14 a and thesecond turning arm 14 b. - Upon driving of the respective members of the robot mechanism, the
wafer holding portion 17 moves relative to the objects for transfer of the wafer thereto and therefrom, such as themagazines plasma treatment portion 4A, secondplasma treatment portion 4B,precenter portion 5, andwafer cleaning portion 10. As stated earlier, these respective objects of wafer transfer are arranged such that their wafer carry-in and carry-out directions agree with the direction of the origin O of the polar coordinate system. Thus, thesemiconductor wafer 11 can be transferred between these objects of wafer transfer by thewafer holding portion 17 of the robot mechanism. - That is, the
base member 3 a is turned, whereby thewafer holding portion 17 can be pointed in the wafer carry-in and carry-out directions of the objects of wafer transfer. Thewafer holding portion 17 is moved forward horizontally by thefirst turning arm 14 a orsecond turning arm 14 b, and can thus be accessed to each member. Thewafer holding portion 17 is also moved upward or downward by driving the arm shaft (not shown). By a combination of this upward or downward movement, and switching ON/OFF of vacuum attraction through the attraction holes 17 a of thewafer holding portion 17, thesemiconductor wafer 11 can be attracted to or released from thewafer holding portion 17. By driving thehand rotation mechanism 15, moreover, thesemiconductor wafer 11 attracted to and held by the attraction holes 17 a of the wafer holding portion 17 (see FIG. 4) can be turned upside down. - As described above, the respective members, which the wafer is transferred to and from, are arranged radially around the third
wafer transport portion 3 using the robot mechanism on the polar coordinate system. Employment of this arrangement makes it possible to cover the plurality of the targets of wafer transfer by a single robot mechanism, and actualize a semiconductor wafer processing apparatus with high work efficiency and of a compact size. - Next, the
wafer stocker 2 will be described. As shown in FIGS. 1 and 2, thewafer stocker 2 has twomagazines magazines magazines shelf members 13 are provided in many stages inside ahousing 12, and asemiconductor wafer 11 is borne on each of theshelf members 13. - The
semiconductor wafer 11 consists essentially of silicon, and has a plurality of semiconductor devices built therein. Aprotective film 11 a is formed on the surface of thesemiconductor wafer 11 on which a circuit has been formed (see FIG. 10(b)). Theprotective film 11 a protects the circuit pattern of thesemiconductor wafer 11, and functions to reinforce thesemiconductor wafer 11 and enhance its fracture strength. Theprotective film 11 a is formed by pasting a resin sheet to the circuit-formed surface of thesemiconductor wafer 11. In accommodating thesemiconductor wafer 11 in themagazine semiconductor wafer 11 is borne on theshelf member 13 with theprotective film 11 a facing upward. - The actions of the
wafer holding portion 17 for withdrawing and accommodating thesemiconductor wafer 11 from and into themagazines wafer holding portion 17 is inserted into a space above thesemiconductor wafer 11 accommodated in themagazine 2A (2B), with the attraction holes 17 a facing downward, as shown in FIG. 3. Then, thewafer holding portion 17 is lowered until it contacts the upper surface of thesemiconductor wafer 11. In this state, vacuum attraction through the attraction holes 17 a is carried out, whereby thesemiconductor wafer 11 is attracted to and held by the lower surface of thewafer holding portion 17. Then, thewafer holding portion 17 is raised again, and pulled out of themagazine 2A (2B). As a result, thesemiconductor wafer 11 is withdrawn while being attracted to and held by the lower surface of thewafer holding portion 17. - FIG. 4 shows an accommodating action for returning the
semiconductor wafer 11 into themagazine 2A (2B). For the accommodating action, thesemiconductor wafer 11, which has been attracted to and held by the upper surface of thewafer holding portion 17 with the thinned surface of thesemiconductor wafer 11 facing upward, is turned upside down by rotating thewafer holding portion 17 about its axis. By so doing, theprotective film 11 a is directed upward, and thesemiconductor wafer 11 is accommodated in this posture into themagazine 2A (2B). At this time, thesame semiconductor wafer 11 is returned to the same location where it was accommodated before processing. - This returning is performed by inserting the
wafer holding portion 17, which has held thesemiconductor wafer 11 on its upper surface, into themagazine 2A (2B), then releasing vacuum attraction, and then lowering thewafer holding portion 17. That is, during this lowering action, the fork-shapedmember 17 b of thewafer holding portion 17 passes through anotch 13 a downward, with thesemiconductor wafer 11 being borne on theshelf member 13, as shown in FIG. 4. Thewafer holding portion 17 is pulled out of the magazine, whereby accommodation of thesemiconductor wafer 11 is completed. - Next, the
precenter portion 5 will be described with reference to FIG. 5. Theprecenter portion 5 is designed to align thesemiconductor wafer 11 to be supplied to the grindingportion 6. In FIG. 5, theprecenter portion 5 has a circular bearing table 20. A removed portion 21 (see the hatching) having an upper surface partially removed in correspondence with the shape of thewafer holding portion 17 is formed on the upper surface of the bearing table 20. The depth of the removedportion 21 is set to be a depth in which thewafer holding portion 17 can be accommodated in the removedportion 21. - The
semiconductor wafer 11 is carried into theprecenter portion 5 in the following manner: Thewafer holding portion 17 holding thesemiconductor wafer 11 on its upper surface is moved above the bearing table 20 until the horizontal position of thewafer holding portion 17 aligns with the removedportion 21. Then, thewafer holding portion 17 is lowered to a height position at which it is accommodated into the removedportion 21. By this measure, thesemiconductor wafer 11 is borne on the bearing table 20. Then, thewafer holding portion 17 is retreated from inside the removedportion 21, whereby carry-in of thesemiconductor wafer 11 is completed. - In the bearing table20, a plurality of
grooved portions 22 are provided radially toward the center at 120-degree equal angular positions. Each of thegrooved portions 22 has apositioning pawl 22 a which is movable along the direction of the groove. Thepositioning pawl 22 a is moved toward the center of the bearing table 20, with thesemiconductor wafer 11 being borne on the bearing table 20, whereby thesemiconductor wafer 11 is aligned with the central position of the bearing table 20. That is, theprecenter portion 5 performs centering of thesemiconductor wafer 11 to be supplied to the grindingportion 6. - The first
wafer transport portion 9A is disposed adjacent to theprecenter portion 5. The firstwafer transport portion 9A is constituted by mounting an attractinghead 25A to a front end of atransport arm 24A, which is turned and driven upward or downward by anarm drive mechanism 23, as shown in FIG. 5. When the attractinghead 25A is moved above thesemiconductor wafer 11 of theprecenter portion 5 and then lowered, the attractinghead 25A attracts and holds thesemiconductor wafer 11. Then, thetransport arm 24A is raised and turned toward the grindingportion 6, whereby thesemiconductor wafer 11 is carried into the grindingportion 6, and moved to a wafer transfer station (to be described later on). - Next, the grinding
portion 6 will be described with reference to FIGS. 2 and 6. As shown in FIGS. 2 and 6, the turn table 7 is disposed on the upper surface of thebase portion 1. The turn table 7 can make an index rotation about its central shaft, and has three chuck tables 7 a provided at 120-degree equal angular positions which are index positions. - Each chuck table7 a receives the
semiconductor wafer 11 from thetransport arm 24A of the firstwafer transport portion 9A at the wafer transfer station (a left-hand index position in FIG. 6). The chuck table 7 a has thesemiconductor wafer 11 attracted to and held on an upper surface thereof, and is rotatable about its axis. - The
first grinding unit 8A and thesecond grinding unit 8B are provided on the side surface of thewall portion 6 a erected at the right end of the upper surface of thebase portion 1. Thefirst grinding unit 8A and thesecond grinding unit 8B are arranged in the horizontal direction at positions corresponding to the index positions of the turn table 7. The index positions below thefirst grinding unit 8A and thesecond grinding unit 8B define a rough grinding station and a finish grinding station, respectively. - The
first grinding unit 8A and thesecond grinding unit 8B each have arotary drive portion 30. Agrindstone semiconductor wafer 11 is mounted on the lower surface of therotary drive portion 30. For rough grinding, a grindstone of about #500 is used. For finish grinding, a grindstone of #3000 to #4000 is generally used. Thefirst grinding unit 8A and thesecond grinding unit 8B each ascend and descend by the action of a built-in upwardly and downwardly moving mechanism. - As shown in FIG. 6, the chuck table7 a holding the
semiconductor wafer 11 is moved to the index position (grinding position) below thefirst grinding unit 8A (or second grindingunit 8B). In this state, thegrindstone 31A (or 31B) is lowered to contact the upper surface of thesemiconductor wafer 11. Thegrindstone 31A (or 31B) is rotated by therotary drive portion 30 to grind the upper surface of thesemiconductor wafer 11. - When the chuck table7 a is located at the grinding position below the
first grinding unit 8A or thesecond grinding unit 8B, the chuck table 7 a is rotated by a drive mechanism (not shown). The rotation of the chuck table 7 a and the rotation of thegrindstone semiconductor wafer 11 is ground uniformly during grinding. - During the grinding, a grinding liquid is supplied to the ground surface of the
semiconductor wafer 11 by grinding liquid supply means (not shown). The grinding liquid is accumulated in the combing 6 b provided on the upper surface of thebase portion 1 so as to surround the turn table 7, and is discharged to the outside. Thesemiconductor wafer 11 after grinding is moved to the wafer transfer position by moving the chuck table 7 a by the index rotation of the turn table 7. Then, thesemiconductor wafer 11 is carried out by thetransport arm 24B of the secondwafer transport portion 9B. - Next, the structure of the
wafer cleaning portion 10 will be described with reference to FIG. 7. Thewafer cleaning portion 10 is disposed on a side opposite to theprecenter portion 5, with the Y-axis of the orthogonal coordinate system being interposed between thewafer cleaning portion 10 and theprecenter portion 5. In FIG. 7 showing the BB section of FIG. 2, an opening 35 a is provided in an upper part of a box-shapedcleaning frame portion 35 by partially cutting out the front surface and two side surfaces of theframe portion 35. The opening 35 a has a size which allows the entry and exit of the secondwafer transport portion 9B holding thesemiconductor wafer 11. At the bottom 35 b of thecleaning frame portion 35, there are provided anopening 35 c for drainage, and a bearingboss 35 d of an upwardly protruding shape. A bearing 38 is fitted into the bearingboss 35 d, and arotary support portion 40 is bound to an upper part of avertical shaft portion 39 rotatably supported by the bearing 38. - A plurality of attraction holes40 a are provided in a horizontal upper surface of the
rotary support portion 40, and the attraction holes 40 a communicate with asuction hole 39 a provided in theshaft portion 39. Vacuum suction is performed through thesuction hole 39 a by driving asuction control portion 46 connected to thesuction hole 39 a, with thesemiconductor wafer 11 being borne on the upper surface of therotary support portion 40. By this vacuum suction, thesemiconductor wafer 11 is attracted to and held by the upper surface of therotary support portion 40. - A
pulley 41 is bound to-a lower part of theshaft portion 39, and abelt 42 is looped between thepulley 41 and apulley 43 bound to arotating shaft 44 a of amotor 44. Themotor 44 is driven by amotor drive portion 45. Theshaft portion 39 is rotated by driving themotor 44. Thus, thesemiconductor wafer 11 held by therotary support portion 40 spins. - Inside the
cleaning frame portion 35, atubular cover portion 36 of a shape surrounding thesemiconductor wafer 11 is mounted so as to be movable upward and downward. Arod 37 a of acylinder 37 is bound to aflange portion 36 a provided in an upper part of thecover portion 36. Thecover portion 36 moves upward and downward upon driving of thecylinder 37. When thecover portion 36 has ascended, theflange portion 36 a is located at a position at which it contacts a ceiling surface of thecleaning frame portion 35, whereby the opening 35 a is closed with thecover portion 36. - On the ceiling surface of the
cleaning frame portion 35, a cleaningfluid nozzle 47 and anair nozzle 49 are disposed, with their ejecting direction facing downward. The cleaningfluid nozzle 47 is connected to a cleaningfluid supply portion 48 for supplying a cleaning fluid such as pure water. By driving the cleaningfluid supply portion 48, a cleaning fluid is ejected from the cleaningfluid nozzle 47 toward the upper surface of thesemiconductor wafer 11 supported by therotary support portion 40. - At this time, the
semiconductor wafer 11 is spinning upon driving of themotor 44. The cleaning fluid jetted at the center of thesemiconductor wafer 11 flows toward the outer edge of thesemiconductor wafer 11 by a centrifugal force. As a result, foreign matter adhering to the upper surface of thesemiconductor wafer 11 is removed together with the cleaning fluid, and accumulated on the bottom surface of thecleaning frame portion 35. Then, the foreign matter is guided, together with the cleaning fluid, to waste water treatment equipment (not shown) through theopening 35 c and adrainage pipe 35 e. - The
air nozzle 49 is connected to anair supply portion 50, and air is ejected downward throughair holes 49 a of theair nozzle 49 by driving theair supply portion 50. Thus, drops of the cleaning fluid adhering to and remaining on the upper surface of thesemiconductor wafer 11 after cleaning are removed, so that hydro-extraction and drying are carried out. The above-described actions are performed by controlling thecylinder 37,motor drive portion 45,suction control portion 46, cleaningfluid supply portion 48 andair supply portion 50 by a control portion (not shown) in the body of the apparatus. - Next, the first and second
plasma treatment portions vacuum chamber 51. The opening 51 a is used for carry-in and carry-out of thesemiconductor wafer 11, and has such a size as to allow thewafer holding portion 17 holding thesemiconductor wafer 11 to come in and go out therethrough. The opening 51 a has an up-and-down gate 56, and thegate 56 is bound to arod 57 a of acylinder 57. By driving thecylinder 57, thegate 56 is raised or lowered to open or close the opening 51 a. -
Openings 51 b and 51 c are provided in a ceiling surface and a bottom surface, respectively, of thevacuum chamber 51. Asupport portion 52 a of anupper electrode 52 is inserted into the opening 51 b via a vacuum-tight bearing 51 e so as to be movable upward and downward. Thesupport portion 52 a is bound to an electrode raising and loweringdrive portion 55, and theupper electrode 52 is raised and lowered by driving the electrode raising and loweringdrive portion 55. - Many
gas ejection ports 52 b are provided in a lower surface of theupper electrode 52, and thegas ejection ports 52 b are connected to agas supply portion 54 via aborehole 52 c provided inside thesupport portion 52 a. Thegas supply portion 54 supplies a mixed gas for plasma generation which consists essentially of a fluorine-based gas such as CF4 and oxygen, or a gas mixture of CF6 and He. - A
support portion 58 a of alower electrode 58 is inserted vacuum-tight into theopening 51 c in the bottom surface of thevacuum chamber 51 via aninsulator 53. Many attraction holes 58 b are provided in an upper surface of thelower electrode 58, and the attraction holes 58 b are connected to asuction control portion 60 via a borehole 58 c provided inside thesupport portion 58 a. Thesuction control portion 60 is driven to perform vacuum suction through the attraction holes 58 b, thereby vacuum attracting thesemiconductor wafer 11 to the upper surface of thelower electrode 58 and holding it thereon. On the other hand, thesuction control portion 60 is driven to impart a positive pressure to the attraction holes 58 b, thereby releasing the attracted and heldsemiconductor wafer 11 from the attracted state. - A
cooling hole 58 d is provided inside thelower electrode 58, and thecooling hole 58 d is connected to anelectrode cooling portion 61 via a borehole 58 e inside thesupport portion 58 a. Theelectrode cooling portion 61 is driven to circulate a refrigerant in thecooling hole 58 d, whereby heat generated during plasma treatment is transferred from thelower electrode 58 to the refrigerant. Thus, an abnormal rise in the temperature of thelower electrode 58 is prevented, so that damage to theprotective film 11 a of thesemiconductor wafer 11 borne on thelower electrode 58 due to heat can be prevented. - An
exhaust hole 51 d is provided in thevacuum chamber 51, and theexhaust hole 51 d is connected to agas exhaust portion 59 via apipe connector 51 f. By driving thegas exhaust portion 59, the space inside thevacuum chamber 51 is vacuum exhausted. Thelower electrode 58 is electrically connected to a high frequencypower source portion 62 via thesupport portion 58 a. Theupper electrode 52 is connected to aground portion 52 d via thesupport portion 52 a, and a high frequency voltage is applied between theupper electrode 52 and thelower electrode 58 opposed to each other, by driving the high frequencypower source portion 62. - In plasma treatment, the
vacuum chamber 51 is closed and its interior is vacuum exhausted, with thesemiconductor wafer 11 being borne on and held by thelower electrode 58. Then, a high frequency voltage is applied between theupper electrode 52 and thelower electrode 58, with a mixed gas for plasma generation being supplied from thegas supply portion 54 into thevacuum chamber 51. By this measure, a plasma discharge occurs between theupper electrode 52 and thelower electrode 58. The etching effect of the resulting plasma etches the upper surface of thesemiconductor wafer 11 to thin thesemiconductor wafer 11. - The
gas supply portion 54, electrode raising and loweringdrive portion 55,gas exhaust portion 59,suction control portion 60,electrode cooling portion 61, and high frequencypower source portion 62 are controlled by the control portion (not shown) of the present apparatus, whereby the above-mentioned plasma treatment action is performed. At this time, data on the gas flow rate are transmitted from thegas supply portion 54 to the control portion, data on the chamber internal pressure are transmitted from thegas exhaust portion 59 to the control portion, and data on the refrigerant temperature (i.e., the electrode temperature) are transmitted from thesuction control portion 60 to the control portion. Based on these data, the control portion controls plasma treatment actions. - The semiconductor wafer processing apparatus is constituted as described above, and thinning of the semiconductor wafer will be described. This thinning is performed after the
protective film 11 a is formed on the circuit-formed surface of thesemiconductor wafer 11 having a plurality of semiconductor devices built therein. Thesemiconductor wafer 11 is supplied in a state in which it is accommodated into themagazine 2A (2B), with theprotective film 11 a facing upward, as shown in FIG. 3. Thesemiconductor wafer 11 is withdrawn, with theprotective film 11 a side being vacuum attracted to thewafer holding portion 17, as shown in FIG. 3. Thewafer holding portion 17 having thesemiconductor wafer 11 attracted to and held by its lower surface is moved to theprecenter portion 5 by the robot mechanism of the thirdwafer transport portion 3. - The
wafer holding portion 17 is rotated about its axis to turn thesemiconductor wafer 11, which has been attracted to and held by thewafer holding portion 17, upside down. As a result, thesemiconductor wafer 11 comes into a state in which it is attracted to and held by the upper surface of thewafer holding portion 17, with theprotective film 11 a facing downward, as shown in FIG. 5. Then, thewafer holding portion 17 is lowered, whereby thesemiconductor wafer 11 is borne on the bearing table 20, with theprotective film 11 a facing downward. Then, when thewafer holding portion 17 has retreated from inside thegroove portion 21, thepositioning pawls 22 a push the outer peripheral portion of thesemiconductor wafer 11 toward the center from three directions. In this manner, alignment of thesemiconductor wafer 11, i.e., its centering action, is performed. - Then, the
semiconductor wafer 11 aligned by the centering action is picked up by the attractinghead 25A of the firstwafer transport portion 9A, and passed on to the grindingportion 6 as shown in FIG. 6. That is, the attractinghead 25A is moved to the wafer transfer position, where thesemiconductor wafer 11 is transferred onto the chuck table 7 a. - Then, mechanical grinding by the grinding
portion 6 is carried out. First, the chuck table 7 a holding thesemiconductor wafer 11 is moved to the rough grinding station below thefirst grinding unit 8A, and rough grinding with thegrindstone 31A is performed there. Then, the chuck table 7 a is moved to the finish grinding station, where finish grinding using thegrindstone 31B of finer abrasive grains is performed by thesecond grinding unit 8B. At this time, thesemiconductor wafer 11 is thinned to a dimension greater by a predetermined thickness than a predetermined target thickness dimension, namely, a sum of the target thickness and a dry etching margin set in the range of 3 μm to 50 μm. - When finish grinding is completed, the chuck table7 a holding the
semiconductor wafer 11 is moved again to the wafer transfer station by the index rotation of the turn table 7. Thissemiconductor wafer 11 is picked up by the attractinghead 25B of the secondwafer transport portion 9B, and is moved to thewafer cleaning portion 10 by turning thetransport arm 24B. Thus, the secondwafer transport portion 9B serves as a before-cleaning transport portion for withdrawing thesemiconductor wafer 11 after grinding from the grindingportion 6 and passing it on to thewafer cleaning portion 10. - During the carry-out action for the
semiconductor wafer 11, fracture strength is reinforced even if a mechanical damaged layer has been generated by mechanical grinding, since theprotective film 11 a is formed in thesemiconductor wafer 11 according to the present embodiment. Thus, breakage of thesemiconductor wafer 11 during transport can be prevented. - Next, the cleaning action at the
wafer cleaning portion 10 will be described in accordance with a flow shown in FIG. 11. With thecover portion 36 being lowered in FIG. 7, thetransport arm 24B of the secondwafer transport portion 9B is turned to bring thesemiconductor wafer 11, held by the attractinghead 25B, into thecleaning frame portion 35 and place it on the rotary support portion 40 (ST1). - Then, the
semiconductor wafer 11 is attracted to and held by therotary support portion 40 by vacuum suction through the attraction holes 40 a (ST2), and the attraction of thesemiconductor wafer 11 by the attractinghead 25B is released (ST3). After thetransport arm 24B is retreated to the outside, thecover portion 36 is raised (ST4). As a result, thesemiconductor wafer 11 has its surroundings closed inside thecleaning frame portion 35, so that ejection of the cleaning fluid becomes possible. - Then, the
motor 44 is driven to rotate therotary support portion 40 and spin the semiconductor wafer 11 (ST5). In this state, the cleaning fluid is jetted through the cleaning nozzle 47 (ST6), and ejection of the cleaning fluid is stopped after a lapse of a predetermined cleaning time (ST7). Then, air is blown through the air nozzle 49 (ST8) to carry out hydro-extraction and drying of the upper surface of thesemiconductor wafer 11. After a lapse of a predetermined time, blowing of air is stopped (ST9), whereafter the rotation of therotary support portion 40 is stopped (ST10). By this procedure, cleaning, hydro-extraction, and drying are completed. - Then, the
cover portion 36 is lowered (ST11), whereafter the robot mechanism of the thirdwafer transport portion 3 is driven to admit thewafer holding portion 17 into the cleaning frame portion 35 (ST12). Then, the upper surface of thesemiconductor wafer 11 is attracted by the attraction holes 17 a of thewafer holding portion 17, and the attraction by the attraction holes 40 a of therotary support portion 40 is released (ST13). Then, thewafer holding portion 17 picking up thesemiconductor wafer 11 is raised, and brought out of the cleaning frame portion 35 (ST14). - Then, the
semiconductor wafer 11 rid of foreign matter on the surface by cleaning is moved to the firstplasma treatment portion 4A or the secondplasma treatment portion 4B, where plasma etching (dry etching) is performed. The plasma etching is intended to plasma etch the surface of thesemiconductor wafer 11, which has been thinned by mechanical grinding to the dimension thicker than the target thickness by the dry etching margin set in the range of 3 μm to 50 μm, to remove the dry etching margin, thereby thinning thesemiconductor wafer 11 to the target thickness. - When finish grinding is performed using a #3000 to #4000 grindstone, the dry etching margin is desirably set at about 5 μm to 6 μm. By so doing, the percentage of application of mechanical grinding, which is excellent in the grinding efficiency, can be maximized to improve the work efficiency. Also, a mechanical damaged layer (generally 3 μm to 5 μm) formed by finish grinding can be removed completely. Consequently, the work efficiency and the quality after removal can both be ensured.
- The plasma etching will be described with reference to FIGS.9(a) to 9(b) and 10(a) to 10(b). As shown in FIG. 9(a), the
wafer holding portion 17 having the cleanedsemiconductor wafer 11 attracted to and held by the lower surface thereof is moved from thewafer cleaning portion 10 to a space beside the opening 51 a of thevacuum chamber 51 by the robot mechanism of the thirdwafer transport portion 3. At this time, thegate 56 is lowered to open the opening 51 a, while theupper electrode 52 is raised by the electrode raising and loweringdrive portion 55 to widen the spacing between theupper electrode 52 and thelower electrode 58. The widened spacing between theupper electrode 52 and thelower electrode 58 is intended to avoid an impediment to transport of the wafer by the thirdwafer transport portion 3. The thirdwafer transport portion 3 serves as an after-cleaning transport portion for withdrawing thesemiconductor wafer 11 after cleaning from thewafer cleaning portion 10, and passing it on to theplasma treatment portion - Then, as shown in FIG. 9(b), the
wafer holding portion 17 is admitted into thevacuum chamber 51 via theopening 51 a, and then lowered to place thesemiconductor wafer 11, held by the lower surface of thewafer holding portion 17, on the upper surface of thelower electrode 58. Then, the attraction by thewafer holding portion 17 is released, and at the same time, theprotective film 11 a of thesemiconductor wafer 11 is attracted to and held by the attraction holes 58 b of thelower electrode 58. Theplasma treatment portions semiconductor wafer 11 into and out of theplasma treatment portion origin 0 is located on a line of extension of the carry-in and carry-out center line La or Lb of theplasma treatment portion - Then, the
wafer holding portion 17 is raised and retreated to the outside. Then, as shown in FIG. 10(a), thecylinder 57 is driven to raise thegate 56, shutting thevacuum chamber 51. Then, the electrode raising and loweringdrive portion 55 is driven to lower theupper electrode 52, thereby setting the distance between the lower surface of theupper electrode 52 and the upper surface of thelower electrode 58 at a predetermined interelectrode distance D suitable for plasma etching, as shown in FIG. 10(b). - In this state, the aforementioned plasma etching treatment is performed. That is, after the interior of the
vacuum chamber 51 is evacuated, a mixture of a fluorine-based gas and an oxygen gas, or a mixture of a fluorine gas and a helium gas is ejected as a plasma generation gas from thegas ejection ports 52 b in the lower surface of theupper electrode 52, and the interior of thevacuum chamber 51 is maintained at a predetermined gas pressure. In this state, a high frequency voltage is applied between theupper electrode 52 and thelower electrode 58. By this measure, a plasma discharge is generated in the space between theupper electrode 52 and thelower electrode 58. By the action of active substances formed by the plasma discharge, the silicon on the surface of the semiconductor silicon is removed. - The plasma etching treatment is performed continuously until the
semiconductor wafer 11 reaches a target thickness. By this treatment, the mechanical damaged layer produced on the surface of thesemiconductor wafer 11 during the mechanical grinding step is removed. The microcrack introduction layer is usually formed with a thickness of 3 μm to 5 μm. Thus, thesemiconductor wafer 11 is mechanically ground to a dimension taking into consideration the mechanical damaged layer added to the target thickness as stated earlier. Then, the thickness corresponding to the mechanical damaged layer is removed by plasma etching, whereby the mechanical damaged layer is completely eliminated, and thesemiconductor wafer 11 is processed to the desired thickness. - The
semiconductor wafer 11 after completion of plasma etching is withdrawn by thewafer holding portion 17 of the thirdwafer transport portion 3, and accommodated to the same position of themagazine 2A (or 2B) of thewafer accommodating portion 2 from which thesemiconductor wafer 11 was withdrawn. This action is continuously repeated forother semiconductor wafers 11. In this transport of thesemiconductor wafer 11 after thinning, breakage of thesemiconductor wafer 11 does not occur, because the damaged layer has been completely eliminated as stated above, and thus the fracture strength of thesemiconductor wafer 11 has been improved. - According to the present embodiment, as described above, breakage occurring in the manufacturing process, such as during transport of the
semiconductor wafer 11, due to microcracks, can be prevented, and processing yield can be increased. In the present embodiment, moreover, the respective portions in charge of respective functions, such as mechanical grinding, cleaning, and removal of the damaged layer, are connected by the single robot mechanism. Thus, the area for installation of equipment can be reduced to cut down on the equipment cost. Furthermore, the number of changed grippings of thesemiconductor wafer 11 during transport can be minimized in comparison with a conventional system, i.e., a system for transferring a semiconductor wafer among a plurality of separate devices by use of transport means such as a robot. Hence, the aforementioned processing yield can be further increased by decreasing the probability of breakage occurrence of the semiconductor wafer during handling. - According to the semiconductor wafer processing apparatus illustrated in the present embodiment, moreover, the regions for the grinding
portion 6 and the other respective portions are disposed separately on thecommon base portion 1, and transfer of thesemiconductor wafer 11 is performed between these portions by separate transfer mechanisms. That is, the transport of thesemiconductor wafer 11 in a contaminant-adhered state in the work region (see the rear half lb shown in FIGS. 1 and 2) in which a grinding liquid is used and adhesion of contaminant such as grinding grains is unavoidable, and the transport of thesemiconductor wafer 11 in a clean state in the clean room region (see thefront half 1 a shown in FIGS. 1 and 2) for plasma etching treatment for which a high degree of cleanness is required of the object to be treated are performed separately by separate transport mechanisms. - Thus, the transport mechanism in the clean room region is not contaminated by adhesion of contaminant. In plasma etching treatment aimed at removing the mechanical damaged layer, therefore, the surface of the
semiconductor wafer 11 is free from adhesion of foreign matter which inhibits the etching effect, so that the damaged layer on the surface of thesemiconductor wafer 11 can be completely eliminated, and the fracture strength can be enhanced. - The present invention is not limited to the above-described embodiments, and various changes and modifications may be made. In the present embodiment, for example, mechanical grinding is performed in two stages, the rough grinding step and the finish grinding step, but the finish grinding step may be omitted. In this case, a coarse grindstone is used for grinding, so that the depth of the damaged layer on the upper surface of the wafer is 10 μm or more. Thus, the dry etching margin measuring about 50 μm is left, and the remainder is processed by dry etching to the target thickness. By so doing, the damaged layer can be removed completely. By performing mechanical grinding in a single stage involving only the rough grinding step, the grinding portion can be downsized, and a semiconductor wafer processing apparatus with a small installation floor area can be actualized.
- In the present embodiment, furthermore, the
precenter portion 5 and the firstwafer transport portion 9A are disposed in the first quadrant of the orthogonal coordinate system, while the secondwafer transport portion 9B and thewafer cleaning portion 10 are disposed in the second quadrant. However, these positions may be interchanged, and the secondwafer transport portion 9B and thewafer cleaning portion 10 may be disposed in the first quadrant. - In the present embodiment, moreover, there is shown an example in which the damaged layer removal treatment portion uses dry etching by plasma treatment. However, this example is not limitative, and the removal treatment portion may rely on wet etching for etch removing the damaged layer with the use of a chemical liquid such as hydrofluoric acid or nitric acid. That is, a wet etching treatment portion may be disposed instead of the first and second
plasma treatment portions - According to the present invention, a grinding portion for mechanically grinding a semiconductor wafer, a wafer cleaning portion for receiving and cleaning the semiconductor wafer after grinding, a damaged layer removal treatment portion for removing a damaged layer in the semiconductor wafer after cleaning, and a wafer transport mechanism having a robot mechanism on a polar coordinate system for transferring the semiconductor wafer between the grinding portion, the wafer cleaning portion, and the damaged layer removal treatment portion are provided in the same apparatus. Thus, the number of changed grippings of the semiconductor wafer can be minimized, breakage of the semiconductor wafer can be prevented to increase the processing yield, and the equipment can be made compact.
Claims (19)
1. A semiconductor wafer processing apparatus for grinding a surface of a semiconductor wafer to thin the semiconductor wafer, comprising:
a grinding portion for mechanically grinding the semiconductor wafer;
a wafer cleaning portion for cleaning the semiconductor wafer after mechanical grinding;
a damaged layer removal treatment portion for removing a damaged layer, caused to the semiconductor wafer by mechanical grinding, after cleaning by the wafer cleaning portion; and
a wafer transport mechanism for transferring the semiconductor wafer between the grinding portion, the wafer cleaning portion, and the damaged layer removal treatment portion.
2. The semiconductor wafer processing apparatus of claim 1 , including a precenter portion for centering the semiconductor wafer, and wherein the semiconductor wafer, which has been centered by the precenter portion, is supplied to the grinding portion by the wafer transport mechanism.
3. The semiconductor wafer processing apparatus of claim 1 , including an stocker for accommodating the semiconductor wafer before processing which is to be supplied to the grinding portion and/or the semiconductor wafer after processing which has been withdrawn from the damaged layer removal treatment portion.
4. The semiconductor wafer processing apparatus of claim 1 , wherein the wafer transport mechanism includes a robot mechanism on a polar coordinate system.
5. The semiconductor wafer processing apparatus of claim 1 , wherein the wafer transport mechanism includes a before-cleaning transport portion for withdrawing the semiconductor wafer after mechanical grinding from the grinding portion, and passing the semiconductor wafer on to the wafer cleaning portion, and an after-cleaning transport portion for withdrawing the semiconductor wafer after cleaning from the wafer cleaning portion, and passing the semiconductor wafer on to the damaged layer removal treatment portion.
6. The semiconductor wafer processing apparatus of claim 1 , wherein the damaged layer removal treatment portion is a plasma treatment portion for etching the damaged layer by plasma treatment.
7. The semiconductor wafer processing apparatus of claim 1 , wherein the damaged layer removal treatment portion is a wet etching treatment portion for etching the damaged layer with a chemical liquid.
8. The semiconductor wafer processing apparatus of claim 1 , wherein
the wafer transport mechanism comprises a first wafer transport portion for holding the semiconductor wafer from the precenter portion and bringing the semiconductor wafer onto the grinding portion, a second wafer transport portion for withdrawing the semiconductor wafer ground by the grinding portion and transporting the semiconductor wafer to the wafer cleaning portion, and a third wafer transport portion having a robot mechanism on a polar coordinate system for transferring the semiconductor wafer between the precenter portion, the wafer cleaning portion, and the damaged layer removal treatment portion, and
the damaged layer removal treatment portion is disposed in a third quadrant and a fourth quadrant of an orthogonal coordinate system in which an origin of the polar coordinate system of the robot mechanism is a common origin and a direction of the grinding portion is a Y-axis positive direction, and such that the origin of the polar coordinate system is positioned on a line of extension of a semiconductor wafer carry-in and carry-out center line of the damaged layer removal treatment portion.
9. The semiconductor wafer processing apparatus of claim 8 , wherein the stocker for accommodating the semiconductor wafer before processing which is to be supplied to the grinding portion and/or the semiconductor wafer after processing which has been withdrawn from the damaged layer removal treatment portion is provided at a position at which the wafer can be brought in and brought out by the third wafer transport portion.
10. The semiconductor wafer processing apparatus of claim 8 , wherein the cleaning portion is disposed in one of the first quadrant and the second quadrant of the orthogonal coordinate system.
11. The semiconductor wafer processing apparatus of claim 10 , wherein the precenter portion is disposed in a quadrant of the coordinate system on a side opposite to the cleaning portion, with the Y-axis of the coordinate system being interposed between the presenter portion and the cleaning portion.
12. A semiconductor wafer processing method for thinning a semiconductor wafer to a target thickness, including the steps of:
mechanically grinding a side of the semiconductor wafer opposite to a surface thereof, where a circuit has been formed, by a grinding portion;
withdrawing the semiconductor wafer after mechanical grinding from the grinding portion, and passing the semiconductor wafer on to the wafer cleaning portion;
cleaning the semiconductor wafer passed on to the wafer cleaning portion;
withdrawing the semiconductor wafer after cleaning from the wafer cleaning portion, and passing the semiconductor wafer on to a damaged layer removal treatment portion; and
removing a damaged layer, caused by the mechanical grinding, in the damaged layer removal treatment portion.
13. The semiconductor wafer processing method of claim 12 , wherein the damaged layer removal treatment portion is a plasma treatment portion for etching the damaged layer by plasma treatment.
14. The semiconductor wafer processing method of claim 13 , further comprising grinding the semiconductor wafer by mechanical grinding to a thickness being a sum of the target thickness and a dry etching margin set in a range of 3 μm to 50 μm, and removing a remainder of the semiconductor wafer by dry etching using plasma treatment.
15. The semiconductor wafer processing method of claim 14 , wherein the semiconductor wafer consists essentially of silicon.
16. The semiconductor wafer processing method of claim 13 , wherein after the semiconductor wafer is ground by the mechanical grinding, the semiconductor wafer is cleaned with a liquid before dry etching is performed.
17. The semiconductor wafer processing method of claim 16 , wherein the liquid is water.
18. The semiconductor wafer processing method of claim 12 , wherein the damaged layer removal treatment portion is a wet etching treatment portion for etching the damage layer with a chemical liquid.
19. The semiconductor wafer processing method of claim 12 , wherein mechanical grinding and removal of the damaged layer are performed, with a protective film being formed on the surface of the semiconductor wafer where the circuit has been formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/315,976 US20030082914A1 (en) | 2000-03-13 | 2002-12-11 | Semiconductor wafer processing apparatus |
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-68229 | 2000-03-13 | ||
JP2000-68231 | 2000-03-13 | ||
JP2000068229A JP2001257247A (en) | 2000-03-13 | 2000-03-13 | Machining device of semiconductor wafer |
JP2000-68230 | 2000-03-13 | ||
JP2000068231A JP2001257248A (en) | 2000-03-13 | 2000-03-13 | Device and method for machining semiconductor wafer |
JP2000068230A JP2001257186A (en) | 2000-03-13 | 2000-03-13 | Method of processing semiconductor wafer |
JP2000175312A JP3633854B2 (en) | 2000-06-12 | 2000-06-12 | Semiconductor wafer processing equipment |
JP2000-175312 | 2000-06-12 | ||
US09/791,766 US6511895B2 (en) | 2000-03-13 | 2001-02-26 | Semiconductor wafer turning process |
US10/315,976 US20030082914A1 (en) | 2000-03-13 | 2002-12-11 | Semiconductor wafer processing apparatus |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/791,766 Division US6511895B2 (en) | 2000-03-13 | 2001-02-26 | Semiconductor wafer turning process |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030082914A1 true US20030082914A1 (en) | 2003-05-01 |
Family
ID=27481112
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/791,766 Expired - Lifetime US6511895B2 (en) | 2000-03-13 | 2001-02-26 | Semiconductor wafer turning process |
US10/315,976 Abandoned US20030082914A1 (en) | 2000-03-13 | 2002-12-11 | Semiconductor wafer processing apparatus |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/791,766 Expired - Lifetime US6511895B2 (en) | 2000-03-13 | 2001-02-26 | Semiconductor wafer turning process |
Country Status (4)
Country | Link |
---|---|
US (2) | US6511895B2 (en) |
KR (1) | KR100443879B1 (en) |
DE (1) | DE10108388B4 (en) |
TW (1) | TW492100B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080045015A1 (en) * | 2006-08-16 | 2008-02-21 | Disco Corporation | Method of etching wafer |
US20120231705A1 (en) * | 2011-03-11 | 2012-09-13 | Fuji Electric Co., Ltd. | Method and apparatus for manufacturing a semiconductor device |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW492100B (en) * | 2000-03-13 | 2002-06-21 | Disco Corp | Semiconductor wafer processing apparatus |
US20050163598A1 (en) * | 2002-02-27 | 2005-07-28 | Tokyou Electron Limited | Method for carrying substrate |
KR100447891B1 (en) * | 2002-03-04 | 2004-09-08 | 강효상 | Dry Etching Method For Wafer |
KR100479308B1 (en) * | 2002-12-23 | 2005-03-28 | 삼성전자주식회사 | Apparatus and method for extracting impurities on a substrate |
JP4153325B2 (en) * | 2003-02-13 | 2008-09-24 | 株式会社ディスコ | Semiconductor wafer processing method |
CN100388434C (en) * | 2003-03-12 | 2008-05-14 | 东京毅力科创株式会社 | Substrate supporting structure for semiconductor processing, and plasma processing device |
JP4298523B2 (en) * | 2004-01-09 | 2009-07-22 | 株式会社ディスコ | Etching device |
JP2006108428A (en) * | 2004-10-06 | 2006-04-20 | Disco Abrasive Syst Ltd | Wafer dividing method |
DE102005012446B4 (en) * | 2005-03-17 | 2017-11-30 | Siltronic Ag | Method for material-removing machining of a semiconductor wafer |
US7767145B2 (en) | 2005-03-28 | 2010-08-03 | Toyko Electron Limited | High pressure fourier transform infrared cell |
KR100821781B1 (en) * | 2005-08-05 | 2008-04-11 | 어드밴스드 마이크로 패브리케이션 이큅먼트 인코퍼레이티드 아시아 | Plasma processing apparatus |
JP2007073670A (en) * | 2005-09-06 | 2007-03-22 | Disco Abrasive Syst Ltd | Water-soluble resin coating method |
CN101579838B (en) * | 2008-05-13 | 2015-09-09 | 智胜科技股份有限公司 | Ginding process, grinding pad and grinding system |
JP2014008482A (en) * | 2012-07-02 | 2014-01-20 | Disco Abrasive Syst Ltd | Processing device |
KR101372805B1 (en) * | 2012-11-30 | 2014-03-19 | 로체 시스템즈(주) | Wafer etching process and using the same wafer etching system |
JP5521066B1 (en) * | 2013-01-25 | 2014-06-11 | 東京エレクトロン株式会社 | Joining apparatus and joining system |
JP6093328B2 (en) * | 2013-06-13 | 2017-03-08 | 東京エレクトロン株式会社 | Substrate processing system, substrate processing method, program, and computer storage medium |
US9786592B2 (en) * | 2015-10-30 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit structure and method of forming the same |
US10763153B2 (en) * | 2016-06-23 | 2020-09-01 | Ulvac, Inc. | Holding apparatus |
CN106098598B (en) * | 2016-08-11 | 2018-09-04 | 通威太阳能(合肥)有限公司 | Automatic blanking etching machine for production of polycrystalline silicon wafers |
JP2018085408A (en) * | 2016-11-22 | 2018-05-31 | 株式会社ディスコ | Decompressor |
CN111446153A (en) * | 2020-04-07 | 2020-07-24 | 北京烁科精微电子装备有限公司 | Wafer cleaning equipment |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5693182A (en) * | 1995-02-21 | 1997-12-02 | Siemens Aktiengesellschaft | Method for damage etching the back side of a semiconductor disk having a protected front side |
US6159071A (en) * | 1998-07-02 | 2000-12-12 | Disco Corporation | Semiconductor wafer grinding apparatus |
US6159827A (en) * | 1998-04-13 | 2000-12-12 | Mitsui Chemicals, Inc. | Preparation process of semiconductor wafer |
US6270619B1 (en) * | 1998-01-13 | 2001-08-07 | Kabushiki Kaisha Toshiba | Treatment device, laser annealing device, manufacturing apparatus, and manufacturing apparatus for flat display device |
US6360687B1 (en) * | 1998-11-26 | 2002-03-26 | Speedfam-Ipec Co., Ltd | Wafer flattening system |
US6431807B1 (en) * | 1998-07-10 | 2002-08-13 | Novellus Systems, Inc. | Wafer processing architecture including single-wafer load lock with cooling unit |
US6511895B2 (en) * | 2000-03-13 | 2003-01-28 | Disco Corporation | Semiconductor wafer turning process |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63127531A (en) * | 1986-11-17 | 1988-05-31 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
JPH0810830B2 (en) * | 1987-03-04 | 1996-01-31 | 株式会社東芝 | Analog-digital converter |
JPH05226308A (en) * | 1992-02-18 | 1993-09-03 | Sony Corp | Method and equipment for processing rear surface of semiconductor wafer |
US5885138A (en) * | 1993-09-21 | 1999-03-23 | Ebara Corporation | Method and apparatus for dry-in, dry-out polishing and washing of a semiconductor device |
JP3326642B2 (en) * | 1993-11-09 | 2002-09-24 | ソニー株式会社 | Substrate post-polishing treatment method and polishing apparatus used therefor |
JPH09223680A (en) * | 1996-02-16 | 1997-08-26 | Disco Abrasive Syst Ltd | Polishing apparatus with etching function |
JP3679871B2 (en) * | 1996-09-04 | 2005-08-03 | 株式会社荏原製作所 | Polishing apparatus and transfer robot |
JP3401706B2 (en) * | 1998-01-19 | 2003-04-28 | 株式会社東京精密 | Surface grinding equipment |
JP2000003892A (en) * | 1998-04-13 | 2000-01-07 | Mitsui Chemicals Inc | Manufacture of semiconductor wafer |
JP3987202B2 (en) * | 1998-04-20 | 2007-10-03 | 株式会社岡本工作機械製作所 | Wafer grinding equipment |
JP2000353676A (en) * | 1999-06-14 | 2000-12-19 | Disco Abrasive Syst Ltd | Grinding system |
-
2001
- 2001-02-19 TW TW090103722A patent/TW492100B/en not_active IP Right Cessation
- 2001-02-21 DE DE10108388A patent/DE10108388B4/en not_active Expired - Lifetime
- 2001-02-26 US US09/791,766 patent/US6511895B2/en not_active Expired - Lifetime
- 2001-03-12 KR KR10-2001-0012570A patent/KR100443879B1/en active IP Right Grant
-
2002
- 2002-12-11 US US10/315,976 patent/US20030082914A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5693182A (en) * | 1995-02-21 | 1997-12-02 | Siemens Aktiengesellschaft | Method for damage etching the back side of a semiconductor disk having a protected front side |
US6270619B1 (en) * | 1998-01-13 | 2001-08-07 | Kabushiki Kaisha Toshiba | Treatment device, laser annealing device, manufacturing apparatus, and manufacturing apparatus for flat display device |
US6159827A (en) * | 1998-04-13 | 2000-12-12 | Mitsui Chemicals, Inc. | Preparation process of semiconductor wafer |
US6159071A (en) * | 1998-07-02 | 2000-12-12 | Disco Corporation | Semiconductor wafer grinding apparatus |
US6431807B1 (en) * | 1998-07-10 | 2002-08-13 | Novellus Systems, Inc. | Wafer processing architecture including single-wafer load lock with cooling unit |
US6360687B1 (en) * | 1998-11-26 | 2002-03-26 | Speedfam-Ipec Co., Ltd | Wafer flattening system |
US6511895B2 (en) * | 2000-03-13 | 2003-01-28 | Disco Corporation | Semiconductor wafer turning process |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080045015A1 (en) * | 2006-08-16 | 2008-02-21 | Disco Corporation | Method of etching wafer |
US20120231705A1 (en) * | 2011-03-11 | 2012-09-13 | Fuji Electric Co., Ltd. | Method and apparatus for manufacturing a semiconductor device |
CN102683256A (en) * | 2011-03-11 | 2012-09-19 | 富士电机株式会社 | Method and apparatus for manufacturing a semiconductor device |
US8888557B2 (en) * | 2011-03-11 | 2014-11-18 | Fuji Electric Co., Ltd. | Method and apparatus for manufacturing a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TW492100B (en) | 2002-06-21 |
US6511895B2 (en) | 2003-01-28 |
KR100443879B1 (en) | 2004-08-09 |
KR20010091976A (en) | 2001-10-23 |
DE10108388A1 (en) | 2001-10-11 |
US20010021571A1 (en) | 2001-09-13 |
DE10108388B4 (en) | 2010-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6511895B2 (en) | Semiconductor wafer turning process | |
KR100875788B1 (en) | Substrate Processing Equipment | |
JP4176485B2 (en) | Substrate processing apparatus and method for realizing a process for reducing surface tension | |
CN106847747B (en) | Method for dividing wafer | |
US20060137721A1 (en) | Liquid processing apparatus and liquid processing method | |
TWI759725B (en) | Substrate processing method, semiconductor manufacturing method, and substrate processing apparatus | |
KR101146663B1 (en) | Semiconductor wafer processing method and processing apparatus | |
US7107999B2 (en) | Substrate processing apparatus for removing organic matter by removal liquid | |
US9330898B2 (en) | Separation system, separation method, program and computer storage medium | |
KR102413131B1 (en) | Hybrid substrate processing system for dry and wet process and substrate processing method thereof | |
JP2000150836A (en) | Processing system for sample | |
JP3633854B2 (en) | Semiconductor wafer processing equipment | |
US20230330768A1 (en) | Film removing method, substrate treating method, and substrate treating apparatus | |
US20030164181A1 (en) | Substrate processing apparatus | |
JP2005223359A (en) | Method of processing semiconductor wafer | |
JP4496609B2 (en) | Thin plate thinning device and thinning method | |
JP2009158564A (en) | Substrate treatment apparatus and substrate treatment method | |
JP4227865B2 (en) | Plasma etching method and plasma etching apparatus | |
US20220181142A1 (en) | Methods and apparatus for processing a substrate | |
JP2001257247A (en) | Machining device of semiconductor wafer | |
JP2001257186A (en) | Method of processing semiconductor wafer | |
JP2001257248A (en) | Device and method for machining semiconductor wafer | |
JP7460448B2 (en) | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS | |
KR102397244B1 (en) | Semiconductor hybrid etching apparatus and method | |
JP2019125659A (en) | Substrate processing apparatus and substrate processing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |