US20030002331A1 - Programming a phase-change memory with slow quench time - Google Patents
Programming a phase-change memory with slow quench time Download PDFInfo
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- US20030002331A1 US20030002331A1 US09/895,054 US89505401A US2003002331A1 US 20030002331 A1 US20030002331 A1 US 20030002331A1 US 89505401 A US89505401 A US 89505401A US 2003002331 A1 US2003002331 A1 US 2003002331A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0038—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
Definitions
- This invention is related to techniques for programming a structural phase-change material solid state memory device such as those that use a chalcogenide material which can be programmed into different resistivity states to store data.
- phase-change memories Solid state memory devices that use a structural phase-change material as the data storage mechanism (referred to here simply as ‘phase-change memories’) offer significant advantages in both cost and performance over conventional charge storage based memories.
- the phase-change memory is made of an array of constituent cells where each cell has some structural phase-change material to store the cell's data.
- This material may be, for instance, a chalcogenide alloy that exhibits a reversible structural phase change from amorphous to crystalline.
- a small volume of the chalcogenide alloy is integrated into a circuit that allows the cell to act as a fast switching programmable resistor.
- This programmable resistor can exhibit greater than 40 times dynamic range of resistivity between a relatively crystalline phase (low resistivity) and a relatively amorphous phase (high resistivity).
- the data stored in the cell is read by measuring the cell's resistance.
- the chalcogenide alloy cell is also non-volatile.
- a conventional technique for programming a phase-change memory cell is to apply a rectangular pulse of current (having a constant magnitude throughout the pulse) to the cell, at a voltage greater than a switching threshold for the phase-change material, which leaves the cell in the reset state (the material is relatively amorphous and has high resistivity). To change state, this may be followed by the application of a subsequent rectangular lower current pulse, also at a voltage greater than the switching threshold, which programs the cell to a set state (the material is relatively crystalline and has low resistivity).
- the reset pulse has a higher magnitude of current than the set pulse so that the temperature of the phase change material is raised to T m , the amorphizing temperature, before the material is rapidly cooled down or quenched by the very sharp decrease in current at the trailing edge of the reset pulse, thereby leaving the material in the amorphous phase.
- T opt the temperature of the phase change material
- T opt the optimum temperature
- FIG. 1 illustrates a block diagram of part of a phase-change memory array featuring a cell current pulse having a slowly decaying trailing portion.
- FIG. 2 depicts a circuit schematic of circuitry that may be used to generate the slowly decaying cell current pulse.
- FIG. 3 depicts a circuit schematic of another embodiment of circuitry used to generate the slowly decaying cell current pulse.
- FIG. 4 illustrates a cell current pulse with a stepped, slowly decaying trailing portion obtained using the circuitry of FIG. 3.
- FIG. 5 shows a flow diagram of a phase-change memory programming process.
- FIG. 6 illustrates a block diagram of an integrated circuit device having a phase-change material memory array, including waveshaping and driving circuitry that are designed to provide the voltage and current levels needed to program the constituent cells of the device.
- FIG. 7 depicts a block diagram of an embodiment of a portable application of a phase-change memory that incorporates the programming process.
- the conventional rectangular reset pulses that are applied to some of the cells in the phase-change memory array are modified such that their currents decrease at sufficiently low rates, so as to program those cells to another state.
- the decay during the trailing portion of such pulses can be slow enough to ensure that the phase-change materials in those cells spend the minimum required time interval at a specified temperature, so as to program those cells to the relatively crystalline phase.
- Such a modified reset pulse, having slow quench time may permit faster programming of the entire memory array as a separate set pulse is not needed.
- phase-change memory array 104 featuring a cell current pulse 110 having a slowly decaying trailing portion.
- the array 104 has a number of phase-change memory cells 106 each of which has a structural phase-change material 108 to store data for that cell.
- Each cell may be accessed by a unique pair of bitlines 114 and wordlines 112 to apply the needed current pulses to each cell.
- Each cell 106 in the array 104 may be subjected to a current pulse 109 or 110 .
- the current pulse 109 is rectangular, with rapid increasing and decreasing leading and trailing edges, respectively, as shown.
- the current pulse 109 has a rapidly increasing leading portion followed by a plateau of a given level for a given time interval, and then followed by a rapidly decreasing trailing portion.
- the current is decreased in the trailing portion at a sufficiently high rate that causes the material 118 in the corresponding cell 106 to be quickly quenched and thereby cause the cell to be programmed to a reset state.
- the current pulse 109 may thus be an entirely conventional reset pulse.
- FIG. 1 also illustrates that some of the cells 106 in the array 104 are subjected to a different current pulse 110 , where this pulse results in a slow quench time for the phase-change material 108 in the corresponding cell 106 .
- One or more of the cells 106 such as the one with index (2,1), may be subjected to this current pulse 110 , at the same time.
- the current pulse 110 begins with a relatively low level 120 and rapidly rises to an upper level 122 . This rise may be effectuated by, for instance, the closing of a solid state switch which causes a rapid rise, or it may be implemented in a more controlled manner to rise more slowly. For faster programming, the rapid rise may be more desirable.
- This leading portion may be essentially identical to that of the conventional current pulse 109 that is applied to the cell 106 having index (1,1).
- this upper level may be maintained for a predetermined time interval such as one that is sufficient to insure changing the material 108 into the relatively amorphous phase.
- This interval has the reference number 124 in FIG. 1.
- the current starts to decrease slowly during an interval 132 towards a lower level 130 . This decrease is at a sufficiently low rate as to cause the material 108 in the corresponding cell 106 to program to the relatively crystalline phase.
- the rapid decrease in the trailing edge of the conventional current pulse 109 causes the material 108 in the cell 106 having index (1,1) to program to the amorphous phase.
- the current need not be reduced all the way down to the lower level 130 during the interval 132 , but rather may be decreased to an intermediate level 128 at the sufficiently low rate, prior to its rapid decrease down to the lower level 130 as shown in the figure. This may help shorten the total time interval of the pulse 110 in situations where the material 108 has reached its desired phase by the end of the interval 132 .
- the slope or decay rate 126 in the trailing portion is linear and as such may be entirely defined by specifying the upper level 122 , the intermediate level 128 , and the interval 132 .
- the decay rate 126 may be non linear for a variety of reasons, such as improved phase-change performance in the material 108 or lower cost of implementation using certain types of analog circuitry, as the case may be.
- the lower levels 120 and 130 may be the same and equal to essentially zero current, although different and/or nonzero levels may also be applicable so long as they ensure that the state of the memory cell 106 does not change at those lower levels and power consumption requirements are met.
- the cell is allowed to exhibit at least two states, a first state in which the material 108 is relatively amorphous and a second state in which the material 108 is relatively crystalline. These two may correspond to the conventional reset and set states, respectively, associated with a phase-change memory cell that can store one bit.
- FIG. 2 what is shown is a circuit schematic of waveshaping circuitry that can be used to generate a slowly decaying cell current pulse 410 as shown in FIG. 4.
- This version of the circuitry is designed to cause a programming current I p , enabled by current source 204 which is coupled to a supply node 203 , to be selectively passed through a volume of phase-change material 108 of a given cell, using a switching transistor 208 .
- the transistor 208 is under control of a cell select signal so that when the cell has been selected, the transistor is turned on thereby providing a low impedance path between the material 108 and the current source 204 which cause the current through the cell to increase rapidly to an upper level, such as I p .
- the cell current I cell happens to pass through the material 108 and is returned to the power supply via a return node 205 that may be at circuit ground/zero volts as illustrated.
- the circuitry in FIG. 2 also has a number of current paths that are enabled by a number of switching transistors 210 _ 1 , 210 _ 2 , . . . 210 _K, under control of signals C 1 , C 2 , . . . CK.
- Each of these current paths may be defined by current sources 212 _ 1 , 212 _ 2 , . . . 212 _K. It can be seen that by sequentially enabling these current paths, i.e. by turning on transistors 210 one at a time, the cell current I cell is decreased as some of the programming current I p, is progressively steered into the current paths.
- step sizes of the decay rate 426 are shown to be equal, unequal step sizes may alternatively be used, corresponding to unequal current sources I B1 , I B2 , . . . .
- FIG. 3 shows another version of the waveshaping circuitry that can create the profile of the cell current pulse 410 of FIG. 4.
- the available programming current I p is sunk from a node to which the phase-change material 108 is connected.
- the switching transistor 208 allows the cell to be selected and enables the available programming current through the material 108 , while a number of bypass current paths are blocked via transistors 310 _ 1 , 310 _ 2 , . . . 310 _K.
- These transistors are p-channel metal oxide semiconductor field effect transistors (MOSFETs) in contrast to n-channel transistors 210 in FIG. 2. Similar to the version in FIG. 2, the cell current in FIG.
- control signals C 1 , C 2 , . . . CK and cell select may be digital so as to allow for digital control of the decay rate of the cell current in response to, for instance, a digital code that represents the desired decay rate.
- One of ordinary skill in the art based on this disclosure will be able to design the needed circuitry, in a wide range of different implementations, to achieve the proper timing of the assertion of the control signals so that the pulse 410 is generated with the desired levels.
- operation 504 begins with increasing a number of currents through a number of corresponding cells (such as two or more) of the memory array, where each cell has a structural phase-change material to store data for that cell.
- Each of these currents is increased to an upper level that is sufficiently high to cause the corresponding cell to be in a first state.
- This first state may be the reset state in which the phase-change material is relatively amorphous and has relatively high resistivity.
- operation 508 proceeds with decreasing some of the currents (at least one) to lower levels.
- this second state may be the set state in which the phase-change material is relatively crystalline and has relatively low resistance.
- the technique thus allows, for instance, two different pulses to be created where each has the same leading portion but different trailing portions.
- One of the pulses is conventional in that it has a rapidly decreasing trailing portion, whereas the other pulse is modified to have a slowly decaying trailing portion, where the latter pulse will set its cell and the former pulse will reset its cell.
- FIG. 6 what is shown is a block diagram of an integrated circuit phase-change material memory device 602 , including waveshaping circuitry 608 that is designed to provide the voltage and current levels needed to program the constituent cells of the device according to some of the embodiments described above.
- the device features an array of memory cells 606 where each cell 606 can be accessed by a unique pair of vertical conductors 114 (bitlines) and horizontal conductors 112 (wordlines).
- the horizontal conductors allow a control signal from timing logic 620 to be provided to each cell to close or open a solid state switch therein. This solid state switch is in series with a volume of the phase-change material 108 whose other terminal is connected to a power supply or power return node.
- the sourcing or sinking of the cell current is performed by either the read circuitry 618 or waveshaping circuitry 608 , depending upon whether a write or read operation is being performed.
- the read circuitry 618 may be entirely conventional and is not described any further here.
- the waveshaping circuitry 608 may be designed according to the versions given in FIGS. 2 and 3 above, so as to provide the voltage and current levels that are needed to program the cells 606 according to the pulses 109 and 410 described above.
- the waveshaping circuitry can be implemented using conventional analog waveshaping circuits such as integrator/ramp circuits, exponential and logarithmic circuits, as well as others, to provide the non-stepped version of the cell current pulse 110 (see FIG. 1).
- the timing associated with the generation of the pulses may be determined by timing logic 620 .
- the timing logic 620 provides digital control signals to the waveshaping circuitry 608 and the read circuitry 618 so that the latter circuits either measure the resistance of the memory cell 606 (read operation) or provide the reset and set pulses at the correct timing and to the selected memory cell 606 .
- Accesses to the cell 606 may be in random fashion where each cell can be accessed individually, or it may be orchestrated according to a row by row basis, depending upon the higher level requirements of the memory system.
- the memory device depicted in FIG. 6 may be built using a wide range of different fabrication processes, including a slightly modified version of a conventional complimentary metal oxide semiconductor (CMOS) logic fabrication process.
- CMOS complimentary metal oxide semiconductor
- the array of cells 606 and the timing logic 620 and waveshaping circuitry 608 may be formed in the same integrated circuit (IC) die.
- FIG. 7 illustrates a block diagram of a portable application 704 of the phase-change memory programming process described above.
- a phase-change memory 708 is operated according to an embodiment of the programming process described above.
- the phase-change memory 708 may include one or more integrated circuit dies where each die has a memory array that is programmed according to the various embodiments of the programming techniques described above in FIGS. 1 - 6 .
- These IC dies may be separate, stand alone memory devices that are arranged in modules such as conventional dynamic random access memory (DRAM) modules, or they may be integrated with other on-chip functionalities.
- the phase-change memory 708 may be part of an I/O processor or a microcontroller.
- the application 704 may be for instance a portable notebook computer, a digital still and/or video camera, a personal digital assistant, or a mobile (cellular) hand-held telephone unit.
- an electronic system includes a processor 710 that uses the phase-change memory 708 as program memory to store code and data for its execution.
- the phase-change memory 708 may be used as a mass storage device for nonvolatile storage of code and data.
- the portable application 704 communicates with other devices, such as a personal computer or a network of computers via an I/O interface 714 .
- This I/O interface 714 may provide access to a computer peripheral bus, a high speed digital communication transmission line, or an antenna for unguided transmissions. Communications between the processor and the phase-change memory 708 and between the processor and the I/O interface 714 may be accomplished using conventional computer bus architectures.
- the above-described components of the portable application 704 are powered by a battery 718 via a power supply bus 716 . Since the application 704 is normally battery powered, its functional components including the phase-change memory 708 should be designed to provide the desired performance at low power consumption levels. In addition, due to the restricted size of portable applications, the various components shown in FIG. 7 including the phase-change memory 708 should provide a relatively high density of functionality. Of course, there are other non-portable applications for the phase-change memory 708 that are not shown. These include, for instance, large network servers or other computing devices which may benefit from a non-volatile memory device such as the phase-change memory.
- the phase-change material may be Ge2Sb2Te5.
- An exemplary pulse may have a peak current magnitude of Ireset, where Ireset is sufficiently high to allow the cells of the array to be programmed into the reset state.
- the exemplary pulse may also have a falling edge that decreases from Ireset to zero current in about 200 nsec.
Abstract
Description
- This invention is related to techniques for programming a structural phase-change material solid state memory device such as those that use a chalcogenide material which can be programmed into different resistivity states to store data.
- Solid state memory devices that use a structural phase-change material as the data storage mechanism (referred to here simply as ‘phase-change memories’) offer significant advantages in both cost and performance over conventional charge storage based memories. The phase-change memory is made of an array of constituent cells where each cell has some structural phase-change material to store the cell's data. This material may be, for instance, a chalcogenide alloy that exhibits a reversible structural phase change from amorphous to crystalline. A small volume of the chalcogenide alloy is integrated into a circuit that allows the cell to act as a fast switching programmable resistor. This programmable resistor can exhibit greater than 40 times dynamic range of resistivity between a relatively crystalline phase (low resistivity) and a relatively amorphous phase (high resistivity). The data stored in the cell is read by measuring the cell's resistance. The chalcogenide alloy cell is also non-volatile.
- A conventional technique for programming a phase-change memory cell is to apply a rectangular pulse of current (having a constant magnitude throughout the pulse) to the cell, at a voltage greater than a switching threshold for the phase-change material, which leaves the cell in the reset state (the material is relatively amorphous and has high resistivity). To change state, this may be followed by the application of a subsequent rectangular lower current pulse, also at a voltage greater than the switching threshold, which programs the cell to a set state (the material is relatively crystalline and has low resistivity). The reset pulse has a higher magnitude of current than the set pulse so that the temperature of the phase change material is raised to Tm, the amorphizing temperature, before the material is rapidly cooled down or quenched by the very sharp decrease in current at the trailing edge of the reset pulse, thereby leaving the material in the amorphous phase. To change into the crystalline phase, the material can be heated back up to an optimum temperature Topt, which is lower than Tm, using a rectangular current pulse of smaller magnitude, and then rapidly cooled down again, this time leaving the material in the crystalline (low resistance) phase.
- FIG. 1 illustrates a block diagram of part of a phase-change memory array featuring a cell current pulse having a slowly decaying trailing portion.
- FIG. 2 depicts a circuit schematic of circuitry that may be used to generate the slowly decaying cell current pulse.
- FIG. 3 depicts a circuit schematic of another embodiment of circuitry used to generate the slowly decaying cell current pulse.
- FIG. 4 illustrates a cell current pulse with a stepped, slowly decaying trailing portion obtained using the circuitry of FIG. 3.
- FIG. 5 shows a flow diagram of a phase-change memory programming process.
- FIG. 6 illustrates a block diagram of an integrated circuit device having a phase-change material memory array, including waveshaping and driving circuitry that are designed to provide the voltage and current levels needed to program the constituent cells of the device.
- FIG. 7 depicts a block diagram of an embodiment of a portable application of a phase-change memory that incorporates the programming process.
- According to an embodiment of the invention, the conventional rectangular reset pulses that are applied to some of the cells in the phase-change memory array are modified such that their currents decrease at sufficiently low rates, so as to program those cells to another state. For instance, the decay during the trailing portion of such pulses can be slow enough to ensure that the phase-change materials in those cells spend the minimum required time interval at a specified temperature, so as to program those cells to the relatively crystalline phase. Such a modified reset pulse, having slow quench time, may permit faster programming of the entire memory array as a separate set pulse is not needed.
- Referring to FIG. 1, what's shown is a block diagram of part of a phase-
change memory array 104 featuring a cellcurrent pulse 110 having a slowly decaying trailing portion. Thearray 104 has a number of phase-change memory cells 106 each of which has a structural phase-change material 108 to store data for that cell. Each cell may be accessed by a unique pair ofbitlines 114 andwordlines 112 to apply the needed current pulses to each cell. The cells are arranged in a rectangular array in this embodiment, in which eachcell 106 is given an index (i,j) where i=1 . . . N and j=1 . . . M. - Each
cell 106 in thearray 104 may be subjected to acurrent pulse current pulse 109 is rectangular, with rapid increasing and decreasing leading and trailing edges, respectively, as shown. Thecurrent pulse 109 has a rapidly increasing leading portion followed by a plateau of a given level for a given time interval, and then followed by a rapidly decreasing trailing portion. The current is decreased in the trailing portion at a sufficiently high rate that causes the material 118 in thecorresponding cell 106 to be quickly quenched and thereby cause the cell to be programmed to a reset state. Thecurrent pulse 109 may thus be an entirely conventional reset pulse. - FIG. 1 also illustrates that some of the
cells 106 in thearray 104 are subjected to a differentcurrent pulse 110, where this pulse results in a slow quench time for the phase-change material 108 in thecorresponding cell 106. One or more of thecells 106, such as the one with index (2,1), may be subjected to thiscurrent pulse 110, at the same time. As shown in FIG. 1, thecurrent pulse 110 begins with a relativelylow level 120 and rapidly rises to anupper level 122. This rise may be effectuated by, for instance, the closing of a solid state switch which causes a rapid rise, or it may be implemented in a more controlled manner to rise more slowly. For faster programming, the rapid rise may be more desirable. This leading portion may be essentially identical to that of the conventionalcurrent pulse 109 that is applied to thecell 106 having index (1,1). - Once the cell current of the
pulse 110 has been increased to theupper level 122, this upper level may be maintained for a predetermined time interval such as one that is sufficient to insure changing thematerial 108 into the relatively amorphous phase. This interval has thereference number 124 in FIG. 1. In the trailing portion of thepulse 110, the current starts to decrease slowly during aninterval 132 towards alower level 130. This decrease is at a sufficiently low rate as to cause thematerial 108 in thecorresponding cell 106 to program to the relatively crystalline phase. In contrast, the rapid decrease in the trailing edge of the conventionalcurrent pulse 109 causes thematerial 108 in thecell 106 having index (1,1) to program to the amorphous phase. - The current need not be reduced all the way down to the
lower level 130 during theinterval 132, but rather may be decreased to anintermediate level 128 at the sufficiently low rate, prior to its rapid decrease down to thelower level 130 as shown in the figure. This may help shorten the total time interval of thepulse 110 in situations where thematerial 108 has reached its desired phase by the end of theinterval 132. - In the embodiment of the
pulse 110 shown in FIG. 1, the slope ordecay rate 126 in the trailing portion is linear and as such may be entirely defined by specifying theupper level 122, theintermediate level 128, and theinterval 132. In other embodiments, however, thedecay rate 126 may be non linear for a variety of reasons, such as improved phase-change performance in thematerial 108 or lower cost of implementation using certain types of analog circuitry, as the case may be. In addition, thelower levels memory cell 106 does not change at those lower levels and power consumption requirements are met. In the embodiments described above, the cell is allowed to exhibit at least two states, a first state in which thematerial 108 is relatively amorphous and a second state in which thematerial 108 is relatively crystalline. These two may correspond to the conventional reset and set states, respectively, associated with a phase-change memory cell that can store one bit. - Referring now to FIG. 2, what is shown is a circuit schematic of waveshaping circuitry that can be used to generate a slowly decaying cell
current pulse 410 as shown in FIG. 4. This version of the circuitry is designed to cause a programming current Ip, enabled bycurrent source 204 which is coupled to asupply node 203, to be selectively passed through a volume of phase-change material 108 of a given cell, using aswitching transistor 208. Thetransistor 208 is under control of a cell select signal so that when the cell has been selected, the transistor is turned on thereby providing a low impedance path between thematerial 108 and thecurrent source 204 which cause the current through the cell to increase rapidly to an upper level, such as Ip. In this embodiment, the cell current Icell happens to pass through thematerial 108 and is returned to the power supply via areturn node 205 that may be at circuit ground/zero volts as illustrated. - The circuitry in FIG. 2 also has a number of current paths that are enabled by a number of switching transistors210_1, 210_2, . . . 210_K, under control of signals C1, C2, . . . CK. Each of these current paths may be defined by current sources 212_1, 212_2, . . . 212_K. It can be seen that by sequentially enabling these current paths, i.e. by turning on
transistors 210 one at a time, the cell current Icell is decreased as some of the programming current Ip, is progressively steered into the current paths. This in effect causes the cellcurrent pulse 410 to be stepped downwards as shown in FIG. 4 with each subsequent turning on of atransistor 210, until the cell current has reached anintermediate level 128 as shown. Although the step sizes of thedecay rate 426 are shown to be equal, unequal step sizes may alternatively be used, corresponding to unequal current sources IB1, IB2, . . . . - FIG. 3 shows another version of the waveshaping circuitry that can create the profile of the cell
current pulse 410 of FIG. 4. In this version, the available programming current Ip is sunk from a node to which the phase-change material 108 is connected. Once again, the switchingtransistor 208 allows the cell to be selected and enables the available programming current through thematerial 108, while a number of bypass current paths are blocked via transistors 310_1, 310_2, . . . 310_K. These transistors are p-channel metal oxide semiconductor field effect transistors (MOSFETs) in contrast to n-channel transistors 210 in FIG. 2. Similar to the version in FIG. 2, the cell current in FIG. 3 can be progressively decreased by sequentially turning ontransistors 310. In both versions of the circuitry shown in FIGS. 2 and 3, the control signals C1, C2, . . . CK and cell select may be digital so as to allow for digital control of the decay rate of the cell current in response to, for instance, a digital code that represents the desired decay rate. One of ordinary skill in the art based on this disclosure will be able to design the needed circuitry, in a wide range of different implementations, to achieve the proper timing of the assertion of the control signals so that thepulse 410 is generated with the desired levels. - Referring now to FIG. 5, a flow diagram of a phase-change memory programming process is depicted. This process essentially summarizes the technique described generally above in which
operation 504 begins with increasing a number of currents through a number of corresponding cells (such as two or more) of the memory array, where each cell has a structural phase-change material to store data for that cell. Each of these currents is increased to an upper level that is sufficiently high to cause the corresponding cell to be in a first state. This first state may be the reset state in which the phase-change material is relatively amorphous and has relatively high resistivity. Next,operation 508 proceeds with decreasing some of the currents (at least one) to lower levels. These currents are decreased at sufficiently high rates that cause their corresponding cells to be programmed to the reset state. Some others (at least one) of the currents in the memory array are also decreased to the lower levels, however these others are decreased at sufficiently low rates that cause their corresponding cells to be programmed to the second state rather than programmed to the first state (operation 512). As mentioned above, this second state may be the set state in which the phase-change material is relatively crystalline and has relatively low resistance. The technique thus allows, for instance, two different pulses to be created where each has the same leading portion but different trailing portions. One of the pulses is conventional in that it has a rapidly decreasing trailing portion, whereas the other pulse is modified to have a slowly decaying trailing portion, where the latter pulse will set its cell and the former pulse will reset its cell. - Turning now to FIG. 6, what is shown is a block diagram of an integrated circuit phase-change
material memory device 602, includingwaveshaping circuitry 608 that is designed to provide the voltage and current levels needed to program the constituent cells of the device according to some of the embodiments described above. The device features an array ofmemory cells 606 where eachcell 606 can be accessed by a unique pair of vertical conductors 114 (bitlines) and horizontal conductors 112 (wordlines). In this embodiment, the horizontal conductors allow a control signal from timinglogic 620 to be provided to each cell to close or open a solid state switch therein. This solid state switch is in series with a volume of the phase-change material 108 whose other terminal is connected to a power supply or power return node. Current is thus sourced or sunk, in this embodiment through the phase-change material 108, when the switch is closed. This cell current is provided only through thevertical conductors 114. In other embodiments (not shown), however, the cell current passes through both bitlines and wordlines. The sourcing or sinking of the cell current is performed by either theread circuitry 618 orwaveshaping circuitry 608, depending upon whether a write or read operation is being performed. Theread circuitry 618 may be entirely conventional and is not described any further here. - The
waveshaping circuitry 608 may be designed according to the versions given in FIGS. 2 and 3 above, so as to provide the voltage and current levels that are needed to program thecells 606 according to thepulses - The timing associated with the generation of the pulses may be determined by timing
logic 620. In the embodiment of FIG. 6, thetiming logic 620 provides digital control signals to thewaveshaping circuitry 608 and theread circuitry 618 so that the latter circuits either measure the resistance of the memory cell 606 (read operation) or provide the reset and set pulses at the correct timing and to the selectedmemory cell 606. Accesses to thecell 606 may be in random fashion where each cell can be accessed individually, or it may be orchestrated according to a row by row basis, depending upon the higher level requirements of the memory system. - The memory device depicted in FIG. 6 may be built using a wide range of different fabrication processes, including a slightly modified version of a conventional complimentary metal oxide semiconductor (CMOS) logic fabrication process. The array of
cells 606 and thetiming logic 620 andwaveshaping circuitry 608 may be formed in the same integrated circuit (IC) die. - FIG. 7 illustrates a block diagram of a
portable application 704 of the phase-change memory programming process described above. A phase-change memory 708 is operated according to an embodiment of the programming process described above. The phase-change memory 708 may include one or more integrated circuit dies where each die has a memory array that is programmed according to the various embodiments of the programming techniques described above in FIGS. 1-6. These IC dies may be separate, stand alone memory devices that are arranged in modules such as conventional dynamic random access memory (DRAM) modules, or they may be integrated with other on-chip functionalities. In the latter embodiments, the phase-change memory 708 may be part of an I/O processor or a microcontroller. - The
application 704 may be for instance a portable notebook computer, a digital still and/or video camera, a personal digital assistant, or a mobile (cellular) hand-held telephone unit. In all of these applications, an electronic system includes aprocessor 710 that uses the phase-change memory 708 as program memory to store code and data for its execution. Alternatively, the phase-change memory 708 may be used as a mass storage device for nonvolatile storage of code and data. Theportable application 704 communicates with other devices, such as a personal computer or a network of computers via an I/O interface 714. This I/O interface 714 may provide access to a computer peripheral bus, a high speed digital communication transmission line, or an antenna for unguided transmissions. Communications between the processor and the phase-change memory 708 and between the processor and the I/O interface 714 may be accomplished using conventional computer bus architectures. - The above-described components of the
portable application 704 are powered by abattery 718 via apower supply bus 716. Since theapplication 704 is normally battery powered, its functional components including the phase-change memory 708 should be designed to provide the desired performance at low power consumption levels. In addition, due to the restricted size of portable applications, the various components shown in FIG. 7 including the phase-change memory 708 should provide a relatively high density of functionality. Of course, there are other non-portable applications for the phase-change memory 708 that are not shown. These include, for instance, large network servers or other computing devices which may benefit from a non-volatile memory device such as the phase-change memory. - As an example, the phase-change material may be Ge2Sb2Te5. An exemplary pulse may have a peak current magnitude of Ireset, where Ireset is sufficiently high to allow the cells of the array to be programmed into the reset state. The exemplary pulse may also have a falling edge that decreases from Ireset to zero current in about 200 nsec. These specifics, however, are merely exemplary and the programming technique may work with a wide range of different phase-change materials and pulse shapes having relatively slow falling edges.
- To summarize, various embodiments of a technique for programming a phase-change memory with slow quench time, have been described. In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005196954A (en) * | 2003-12-30 | 2005-07-21 | Samsung Electronics Co Ltd | Set programming method and write driver circuit for phase change memory array |
US20080130352A1 (en) * | 2005-01-19 | 2008-06-05 | Sandisk Corporation | Structure and Method for Biasing Phase Change Memory Array for Reliable Writing |
US20090080241A1 (en) * | 2007-09-26 | 2009-03-26 | Gutala Ravi P | Programming a phase change memory |
US20090231912A1 (en) * | 2008-03-14 | 2009-09-17 | Micron Technology, Inc. | Phase change memory adaptive programming |
JP2009217908A (en) * | 2008-03-11 | 2009-09-24 | Toshiba Corp | Nonvolatile semiconductor memory device |
WO2009120275A2 (en) | 2008-03-26 | 2009-10-01 | Micron Technology, Inc. | Phase change memory |
US20100020594A1 (en) * | 2008-07-28 | 2010-01-28 | Stmicroelectronics S.R.L. | Device for programming a pcm cell with discharge of capacitance and method for programming a pcm cell |
US20100314601A1 (en) * | 2009-06-15 | 2010-12-16 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US20110128774A1 (en) * | 2008-04-25 | 2011-06-02 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8634235B2 (en) | 2010-06-25 | 2014-01-21 | Macronix International Co., Ltd. | Phase change memory coding |
US20140215124A1 (en) * | 2013-01-28 | 2014-07-31 | Infineon Technologies Ag | System and method for adaptive bit rate programming of a memory device |
US8891293B2 (en) | 2011-06-23 | 2014-11-18 | Macronix International Co., Ltd. | High-endurance phase change memory devices and methods for operating the same |
US8964442B2 (en) | 2013-01-14 | 2015-02-24 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US9001550B2 (en) | 2012-04-27 | 2015-04-07 | Macronix International Co., Ltd. | Blocking current leakage in a memory array |
US9412939B2 (en) * | 2006-10-12 | 2016-08-09 | Carlow Innovations Llc | Forming sublithographic heaters for phase change memories |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
Families Citing this family (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6638820B2 (en) | 2001-02-08 | 2003-10-28 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices |
US6734455B2 (en) * | 2001-03-15 | 2004-05-11 | Micron Technology, Inc. | Agglomeration elimination for metal sputter deposition of chalcogenides |
US7102150B2 (en) | 2001-05-11 | 2006-09-05 | Harshfield Steven T | PCRAM memory cell and method of making same |
US6570784B2 (en) * | 2001-06-29 | 2003-05-27 | Ovonyx, Inc. | Programming a phase-change material memory |
US6955940B2 (en) | 2001-08-29 | 2005-10-18 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices |
US20030047765A1 (en) | 2001-08-30 | 2003-03-13 | Campbell Kristy A. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US6815818B2 (en) * | 2001-11-19 | 2004-11-09 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US6791859B2 (en) | 2001-11-20 | 2004-09-14 | Micron Technology, Inc. | Complementary bit PCRAM sense amplifier and method of operation |
EP1450373B1 (en) * | 2003-02-21 | 2008-08-27 | STMicroelectronics S.r.l. | Phase change memory device |
US6625054B2 (en) * | 2001-12-28 | 2003-09-23 | Intel Corporation | Method and apparatus to program a phase change memory |
US20030143782A1 (en) | 2002-01-31 | 2003-07-31 | Gilton Terry L. | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
US6791885B2 (en) | 2002-02-19 | 2004-09-14 | Micron Technology, Inc. | Programmable conductor random access memory and method for sensing same |
US6809362B2 (en) | 2002-02-20 | 2004-10-26 | Micron Technology, Inc. | Multiple data state memory cell |
US7151273B2 (en) | 2002-02-20 | 2006-12-19 | Micron Technology, Inc. | Silver-selenide/chalcogenide glass stack for resistance variable memory |
US6890790B2 (en) | 2002-06-06 | 2005-05-10 | Micron Technology, Inc. | Co-sputter deposition of metal-doped chalcogenides |
US7015494B2 (en) | 2002-07-10 | 2006-03-21 | Micron Technology, Inc. | Assemblies displaying differential negative resistance |
US6768665B2 (en) * | 2002-08-05 | 2004-07-27 | Intel Corporation | Refreshing memory cells of a phase change material memory device |
US7163837B2 (en) * | 2002-08-29 | 2007-01-16 | Micron Technology, Inc. | Method of forming a resistance variable memory element |
US6864521B2 (en) | 2002-08-29 | 2005-03-08 | Micron Technology, Inc. | Method to control silver concentration in a resistance variable memory element |
US7010644B2 (en) | 2002-08-29 | 2006-03-07 | Micron Technology, Inc. | Software refreshed memory device and method |
US7364644B2 (en) | 2002-08-29 | 2008-04-29 | Micron Technology, Inc. | Silver selenide film stoichiometry and morphology control in sputter deposition |
US6856002B2 (en) | 2002-08-29 | 2005-02-15 | Micron Technology, Inc. | Graded GexSe100-x concentration in PCRAM |
US6831856B2 (en) * | 2002-09-23 | 2004-12-14 | Ovonyx, Inc. | Method of data storage using only amorphous phase of electrically programmable phase-change memory element |
US7242019B2 (en) * | 2002-12-13 | 2007-07-10 | Intel Corporation | Shunted phase change memory |
US7589343B2 (en) * | 2002-12-13 | 2009-09-15 | Intel Corporation | Memory and access device and method therefor |
DE10310573A1 (en) * | 2003-03-11 | 2004-09-30 | Infineon Technologies Ag | Non-volatile, integrated memory cell and method for writing or reading information into / from the memory cell |
US6813178B2 (en) | 2003-03-12 | 2004-11-02 | Micron Technology, Inc. | Chalcogenide glass constant current device, and its method of fabrication and operation |
KR100546322B1 (en) * | 2003-03-27 | 2006-01-26 | 삼성전자주식회사 | Phase-change memory device capable of being operated in both non-volatile memory and volatile memory and method thereof |
US7050327B2 (en) | 2003-04-10 | 2006-05-23 | Micron Technology, Inc. | Differential negative resistance memory |
US7085154B2 (en) * | 2003-06-03 | 2006-08-01 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
DE60315613T2 (en) * | 2003-06-16 | 2008-05-08 | Stmicroelectronics S.R.L., Agrate Brianza | Write circuit for phase change memory |
US6930909B2 (en) * | 2003-06-25 | 2005-08-16 | Micron Technology, Inc. | Memory device and methods of controlling resistance variation and resistance profile drift |
US6961277B2 (en) | 2003-07-08 | 2005-11-01 | Micron Technology, Inc. | Method of refreshing a PCRAM memory device |
DE102004039977B4 (en) * | 2003-08-13 | 2008-09-11 | Samsung Electronics Co., Ltd., Suwon | Programming method and driver circuit for a phase change memory cell |
KR100505701B1 (en) * | 2003-08-13 | 2005-08-03 | 삼성전자주식회사 | Programming method of reducing set time of Phase-Change memory and writing driver circuit thereof |
US6937507B2 (en) * | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US7153721B2 (en) * | 2004-01-28 | 2006-12-26 | Micron Technology, Inc. | Resistance variable memory elements based on polarized silver-selenide network growth |
US7105864B2 (en) | 2004-01-29 | 2006-09-12 | Micron Technology, Inc. | Non-volatile zero field splitting resonance memory |
KR100733147B1 (en) * | 2004-02-25 | 2007-06-27 | 삼성전자주식회사 | Phase-changeable memory device and method of manufacturing the same |
KR100574975B1 (en) * | 2004-03-05 | 2006-05-02 | 삼성전자주식회사 | Set programming method of phase-change memory array and writing driver circuit |
US7583551B2 (en) | 2004-03-10 | 2009-09-01 | Micron Technology, Inc. | Power management control and controlling memory refresh operations |
US6944041B1 (en) * | 2004-03-26 | 2005-09-13 | Bae Systems Information And Electronic Systems Integration, Inc. | Circuit for accessing a chalcogenide memory array |
US7630233B2 (en) * | 2004-04-02 | 2009-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and driving method of the same |
KR100618836B1 (en) * | 2004-06-19 | 2006-09-08 | 삼성전자주식회사 | Semiconductor memory device and programming method thereof |
KR100587702B1 (en) | 2004-07-09 | 2006-06-08 | 삼성전자주식회사 | Phase change memory device having characteristic of peak current decrease and data writing method therefor |
US7354793B2 (en) | 2004-08-12 | 2008-04-08 | Micron Technology, Inc. | Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element |
US7326950B2 (en) | 2004-07-19 | 2008-02-05 | Micron Technology, Inc. | Memory device with switching glass layer |
US7365411B2 (en) | 2004-08-12 | 2008-04-29 | Micron Technology, Inc. | Resistance variable memory with temperature tolerant materials |
KR100610014B1 (en) * | 2004-09-06 | 2006-08-09 | 삼성전자주식회사 | Semiconductor memory device capable of compensating for leakage current |
US7453716B2 (en) * | 2004-10-26 | 2008-11-18 | Samsung Electronics Co., Ltd | Semiconductor memory device with stacked control transistors |
KR100564636B1 (en) * | 2004-10-26 | 2006-03-28 | 삼성전자주식회사 | Semiconductor memory device |
KR100564637B1 (en) * | 2004-10-26 | 2006-03-29 | 삼성전자주식회사 | Semiconductor memory device and programming method thereof |
US8179711B2 (en) * | 2004-10-26 | 2012-05-15 | Samsung Electronics Co., Ltd. | Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell |
US7646630B2 (en) * | 2004-11-08 | 2010-01-12 | Ovonyx, Inc. | Programmable matrix array with chalcogenide material |
KR100576369B1 (en) * | 2004-11-23 | 2006-05-03 | 삼성전자주식회사 | Method for programming a non-volatile memory device employing a transition metal oxide layer as a data storage material layer |
US7374174B2 (en) | 2004-12-22 | 2008-05-20 | Micron Technology, Inc. | Small electrode for resistance variable devices |
US7317200B2 (en) | 2005-02-23 | 2008-01-08 | Micron Technology, Inc. | SnSe-based limited reprogrammable cell |
KR100688540B1 (en) * | 2005-03-24 | 2007-03-02 | 삼성전자주식회사 | Semiconductor memory device with improved memory cell density |
KR100855959B1 (en) * | 2005-04-04 | 2008-09-02 | 삼성전자주식회사 | Programming method using current pulse with variable pulse width |
KR100699837B1 (en) * | 2005-04-04 | 2007-03-27 | 삼성전자주식회사 | Semiconductor memory device and programming method thereof |
US7709289B2 (en) | 2005-04-22 | 2010-05-04 | Micron Technology, Inc. | Memory elements having patterned electrodes and method of forming the same |
US7427770B2 (en) | 2005-04-22 | 2008-09-23 | Micron Technology, Inc. | Memory array for increased bit density |
KR100688553B1 (en) * | 2005-06-22 | 2007-03-02 | 삼성전자주식회사 | Phase Change Random Access Memory device having reduced core layout size |
US7274034B2 (en) | 2005-08-01 | 2007-09-25 | Micron Technology, Inc. | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication |
US7332735B2 (en) | 2005-08-02 | 2008-02-19 | Micron Technology, Inc. | Phase change memory cell and method of formation |
US7579615B2 (en) | 2005-08-09 | 2009-08-25 | Micron Technology, Inc. | Access transistor for memory device |
US7251154B2 (en) | 2005-08-15 | 2007-07-31 | Micron Technology, Inc. | Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance |
KR100674992B1 (en) * | 2005-09-08 | 2007-01-29 | 삼성전자주식회사 | Phase change random access memory device capable of changing driving voltage |
CN101180683B (en) * | 2005-09-21 | 2010-05-26 | 株式会社瑞萨科技 | Semiconductor device |
KR100674997B1 (en) * | 2005-10-15 | 2007-01-29 | 삼성전자주식회사 | Phase-change random access memory device and method of controlling read operation using the same |
DE102006052397B4 (en) * | 2005-11-07 | 2009-12-31 | Samsung Electronics Co., Ltd., Suwon | Non-volatile semiconductor memory, nonvolatile semiconductor memory device, method of reading a phase change memory cell and system |
KR100773095B1 (en) * | 2005-12-09 | 2007-11-02 | 삼성전자주식회사 | Phase change memory device and program method thereof |
KR100773398B1 (en) * | 2005-12-14 | 2007-11-05 | 삼성전자주식회사 | Phase change memory device having otp cell array |
GB2433647B (en) | 2005-12-20 | 2008-05-28 | Univ Southampton | Phase change memory materials, devices and methods |
US7499316B2 (en) * | 2006-03-31 | 2009-03-03 | Samsung Electronics Co., Ltd. | Phase change memory devices and program methods |
KR100857742B1 (en) * | 2006-03-31 | 2008-09-10 | 삼성전자주식회사 | Phase Change Memory Device and Method applying Program Current Thereof |
US7457146B2 (en) * | 2006-06-19 | 2008-11-25 | Qimonda North America Corp. | Memory cell programmed using a temperature controlled set pulse |
US7560723B2 (en) | 2006-08-29 | 2009-07-14 | Micron Technology, Inc. | Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication |
US7885102B2 (en) * | 2006-09-15 | 2011-02-08 | Renesas Electronics Corporation | Semiconductor device |
KR100819106B1 (en) | 2006-09-27 | 2008-04-02 | 삼성전자주식회사 | Method for write operating for use in PRAM |
KR100827703B1 (en) * | 2006-12-14 | 2008-05-07 | 삼성전자주식회사 | Method for testing for use in pram |
US20080148677A1 (en) * | 2006-12-20 | 2008-06-26 | Huber Engineered Woods Llc | Reinforced Wood Panel |
KR100801084B1 (en) | 2007-01-08 | 2008-02-05 | 삼성전자주식회사 | Nonvolatile memory device using variable resistive element and fabricating method thereof |
US7606111B2 (en) * | 2007-04-26 | 2009-10-20 | Super Talent Electronics, Inc. | Synchronous page-mode phase-change memory with ECC and RAM cache |
US7577023B2 (en) * | 2007-05-04 | 2009-08-18 | Qimonda North America Corp. | Memory including write circuit for providing multiple reset pulses |
US7852657B2 (en) * | 2007-06-29 | 2010-12-14 | Qimonda Ag | Multiple write configurations for a memory cell |
KR20090016199A (en) * | 2007-08-10 | 2009-02-13 | 주식회사 하이닉스반도체 | Phase change memory device and operating method the same |
US7787291B2 (en) * | 2007-09-26 | 2010-08-31 | Intel Corporation | Programming a multilevel phase change memory cell |
KR101437397B1 (en) * | 2007-10-31 | 2014-09-05 | 삼성전자주식회사 | Data management method and mapping table update method in nonvolatile memory device |
TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
KR101339288B1 (en) * | 2007-12-14 | 2013-12-09 | 삼성전자 주식회사 | Nonvolatile memory device using variable resistive element |
US8964488B2 (en) | 2007-12-14 | 2015-02-24 | Samsung Electronics Co., Ltd. | Non-volatile memory device using variable resistance element with an improved write performance |
JP5023395B2 (en) * | 2007-12-18 | 2012-09-12 | 株式会社東芝 | Magnetic random access memory and writing method thereof |
US7920414B2 (en) * | 2008-06-06 | 2011-04-05 | Ovonyx, Inc. | Asymmetric-threshold three-terminal switching device |
US8467236B2 (en) | 2008-08-01 | 2013-06-18 | Boise State University | Continuously variable resistor |
US20100067290A1 (en) * | 2008-09-15 | 2010-03-18 | Savransky Semyon D | Method of programming of phase-change memory and associated devices and materials |
US8040719B2 (en) * | 2008-11-26 | 2011-10-18 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices having bit line discharge control circuits therein that provide equivalent bit line discharge control |
US8031516B2 (en) * | 2008-12-12 | 2011-10-04 | Stephen Tang | Writing memory cells exhibiting threshold switch behavior |
TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
KR100909744B1 (en) | 2009-05-18 | 2009-07-29 | 주식회사 하이닉스반도체 | Phase change memory device and operating method the same |
KR20110015256A (en) * | 2009-08-07 | 2011-02-15 | 삼성전자주식회사 | Variable resistance memory device and program method thereof |
KR20110102734A (en) * | 2010-03-11 | 2011-09-19 | 삼성전자주식회사 | Nonvolatile semiconductor memory device including otp lock bit register |
US10090029B2 (en) * | 2016-06-30 | 2018-10-02 | SK Hynix Inc. | Electronic device for suppressing read disturbance and method of driving the same |
US10622049B1 (en) * | 2017-04-28 | 2020-04-14 | SK Hynix Inc. | Electronic device including a semiconductor memory that includes a circuit for changing a waveform of a write pulse |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US5781557A (en) | 1996-12-31 | 1998-07-14 | Intel Corporation | Memory test mode for wordline resistive defects |
US6141241A (en) | 1998-06-23 | 2000-10-31 | Energy Conversion Devices, Inc. | Universal memory element with systems employing same and apparatus and method for reading, writing and programming same |
US5912839A (en) * | 1998-06-23 | 1999-06-15 | Energy Conversion Devices, Inc. | Universal memory element and method of programming same |
US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
-
2001
- 2001-06-29 US US09/895,054 patent/US6487113B1/en not_active Expired - Lifetime
Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005196954A (en) * | 2003-12-30 | 2005-07-21 | Samsung Electronics Co Ltd | Set programming method and write driver circuit for phase change memory array |
US8102698B2 (en) | 2005-01-19 | 2012-01-24 | Sandisk 3D Llc | Structure and method for biasing phase change memory array for reliable writing |
US20080130352A1 (en) * | 2005-01-19 | 2008-06-05 | Sandisk Corporation | Structure and Method for Biasing Phase Change Memory Array for Reliable Writing |
US7859884B2 (en) | 2005-01-19 | 2010-12-28 | Sandisk 3D Llc | Structure and method for biasing phase change memory array for reliable writing |
US20110110149A1 (en) * | 2005-01-19 | 2011-05-12 | Scheuerlein Roy E | Structure and method for biasing phase change memory array for reliable writing |
US8385141B2 (en) | 2005-01-19 | 2013-02-26 | Sandisk 3D Llc | Structure and method for biasing phase change memory array for reliable writing |
KR100987503B1 (en) * | 2005-01-19 | 2010-10-13 | 샌디스크 쓰리디 엘엘씨 | Structure and method for biasing phase change memory array for reliable writing |
US9412939B2 (en) * | 2006-10-12 | 2016-08-09 | Carlow Innovations Llc | Forming sublithographic heaters for phase change memories |
US8027186B2 (en) * | 2007-09-26 | 2011-09-27 | Intel Corporation | Programming a phase change memory |
US20090080241A1 (en) * | 2007-09-26 | 2009-03-26 | Gutala Ravi P | Programming a phase change memory |
US20090244953A1 (en) * | 2008-03-11 | 2009-10-01 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP2009217908A (en) * | 2008-03-11 | 2009-09-24 | Toshiba Corp | Nonvolatile semiconductor memory device |
US7978497B2 (en) | 2008-03-11 | 2011-07-12 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP4719233B2 (en) * | 2008-03-11 | 2011-07-06 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US7821810B2 (en) | 2008-03-14 | 2010-10-26 | Micron Technology, Inc. | Phase change memory adaptive programming |
US8644052B2 (en) | 2008-03-14 | 2014-02-04 | Micron Technology, Inc. | Phase change memory adaptive programming |
US20110032754A1 (en) * | 2008-03-14 | 2011-02-10 | Micron Technology, Inc.. | Phase change memory adaptive programming |
US8477523B2 (en) | 2008-03-14 | 2013-07-02 | Micron Technology, Inc. | Phase change memory adaptive programming |
US20090231912A1 (en) * | 2008-03-14 | 2009-09-17 | Micron Technology, Inc. | Phase change memory adaptive programming |
US9093142B2 (en) | 2008-03-14 | 2015-07-28 | Micron Technology, Inc. | Phase change memory adaptive programming including pulse transition time adjustment |
EP2260492A4 (en) * | 2008-03-26 | 2011-03-30 | Micron Technology Inc | Phase change memory |
US20100202195A1 (en) * | 2008-03-26 | 2010-08-12 | Micron Technology, Inc. | Phase change memory |
EP2260492A2 (en) * | 2008-03-26 | 2010-12-15 | Micron Technology, Inc. | Phase change memory |
US8233318B2 (en) | 2008-03-26 | 2012-07-31 | Micron Technology, Inc. | Phase change memory |
WO2009120275A2 (en) | 2008-03-26 | 2009-10-01 | Micron Technology, Inc. | Phase change memory |
TWI423263B (en) * | 2008-03-26 | 2014-01-11 | Micron Technology Inc | Phase change memory |
US8149611B2 (en) * | 2008-04-25 | 2012-04-03 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8432722B2 (en) | 2008-04-25 | 2013-04-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US20110128774A1 (en) * | 2008-04-25 | 2011-06-02 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US8054698B2 (en) | 2008-07-28 | 2011-11-08 | Stmicroelectronics S.R.L. | Device for programming a PCM cell with discharge of capacitance and method for programming a PCM cell |
US20100020594A1 (en) * | 2008-07-28 | 2010-01-28 | Stmicroelectronics S.R.L. | Device for programming a pcm cell with discharge of capacitance and method for programming a pcm cell |
US8809829B2 (en) * | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US20100314601A1 (en) * | 2009-06-15 | 2010-12-16 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8634235B2 (en) | 2010-06-25 | 2014-01-21 | Macronix International Co., Ltd. | Phase change memory coding |
US9336867B2 (en) | 2010-06-25 | 2016-05-10 | Macronix International Co., Ltd. | Phase change memory coding |
US8891293B2 (en) | 2011-06-23 | 2014-11-18 | Macronix International Co., Ltd. | High-endurance phase change memory devices and methods for operating the same |
US9001550B2 (en) | 2012-04-27 | 2015-04-07 | Macronix International Co., Ltd. | Blocking current leakage in a memory array |
US8964442B2 (en) | 2013-01-14 | 2015-02-24 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US20140215124A1 (en) * | 2013-01-28 | 2014-07-31 | Infineon Technologies Ag | System and method for adaptive bit rate programming of a memory device |
US9032140B2 (en) * | 2013-01-28 | 2015-05-12 | Infineon Technologies Ag | System and method for adaptive bit rate programming of a memory device |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
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