US20020182887A1 - Method and apparatus of forming a sputtered doped seed layer - Google Patents
Method and apparatus of forming a sputtered doped seed layer Download PDFInfo
- Publication number
- US20020182887A1 US20020182887A1 US10/198,437 US19843702A US2002182887A1 US 20020182887 A1 US20020182887 A1 US 20020182887A1 US 19843702 A US19843702 A US 19843702A US 2002182887 A1 US2002182887 A1 US 2002182887A1
- Authority
- US
- United States
- Prior art keywords
- copper
- layer
- substrate
- seed layer
- deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/18—Metallic material, boron or silicon on other inorganic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to the deposition of a layer on a substrate. More specifically, the invention relates to deposition of a doped layer on a substrate.
- Aluminum has traditionally been the choice of conductive materials used in metallization. However, smaller feature sizes have created a need for a conductive material with lower resistivity than aluminum. Copper is now being considered as an interconnect material to replace or complement aluminum because copper has a lower resistivity (1.7 ⁇ -cm compared to 3.1 ⁇ -cm for aluminum) and higher current carrying capacity.
- Electroplating processes are being developed for deposition of conductive material, particularly copper, to fill small features on a substrate.
- electroplating has its own challenges in depositing uniformly on a substrate.
- Electroplating uses an electrically conductive seed layer, such as a copper layer conformally deposited by CVD or PVD, to initiate the electroplating deposition process on the substrate.
- CVD chemical vapor deposition
- PVD is the current choice for depositing the seed layer conformally over the feature.
- PVD of copper tends to agglomerate across the deposition surface and in the lines and vias due to surface diffusion of the copper material.
- a high surface diffusivity of copper which is a function of the deposition temperature, causes the deposited copper film to agglomerate such that the film will either dewet, thereby becoming discontinuous, and/or roughen such that the agglomeration reduces the overall surface energy of the exposed copper surface.
- This agglomeration has the adverse effect on a subsequent electroplating process such that either the discontinuous film will lead to micro-voids in the electroplated copper or the roughened surface will provide a localized electrical field, also resulting in micro-voids and other nonuniformities.
- the electroplated layer such as a seed layer, is nonuniformly deposited on the substrate, then the current will not be evenly distributed over the surface of the seed layer and may result in nonuniform deposition of a subsequent electroplated layer on the substrate.
- copper is highly susceptible to oxidation, which increases the resistivity of a copper feature. Oxidation can occur when the substrate is moved between chambers and exposed to ambient conditions or in a particular process that exposes the copper to an oxygen source. Oxidation of copper increases the resistivity of the lines and vias formed.
- the present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover.
- the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material.
- the conductive material such as copper
- a dopant such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material.
- a dopant such as phosphorus
- stabilizes the conductive material surface such as a copper surface, and lessens the surface diffusivity of the conductive material.
- the overall surface diffusivity of copper is reduced such that the tendency to agglomerate or to become discontinuous is reduced, thereby allowing the deposition of a smoother conductive film and thereby reducing localized agglomeration of the conductive material.
- the smoother film is highly desirable for subsequent deposition processes.
- a conductive material, such as copper can be deposited on the deposited doped layer by a variety of processes including PVD, chemical vapor deposition (CVD), electroplating, electroless deposition and other deposition processes.
- the present invention provides an apparatus for depositing a material on a substrate, comprising a processing chamber and a doped conductive target.
- the target comprises a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- the invention provides a doped conductive target for sputtering a layer on a substrate.
- the doped conductive target comprises a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- the invention provides a substrate having a doped seed layer deposited by a sputtering process on the substrate.
- the doped seed layer comprises a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- the invention provides a method of sputtering a layer on a substrate, comprising generating a plasma in a substrate processing chamber, sputtering material from a doped conductive target, the target comprising a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof, and depositing the sputtered doped material on the substrate.
- a conductive layer of copper can be deposited over the sputtered doped material, preferably, by an electroplating process.
- FIG. 1 is a schematic cross-sectional view of an IMP chamber.
- FIG. 2 is a schematic cross-sectional view of a substrate with a seed layer formed on the substrate.
- the present invention provides a method and apparatus for forming a doped layer on a substrate, preferably using a sputtering process.
- the doped layer preferably comprises copper doped with phosphorus.
- FIG. 1 is a schematic cross-sectional view of an IMP chamber 100 , capable of generating a relatively high density plasma, i.e., one with a capability to ionize a significant fraction of both the process gas (typically argon) and the sputtered target material.
- a sputtering chamber known as an IMP VectraTM chamber, is available from Applied Materials, Inc. of Santa Clara, Calif.
- the IMP chamber can be integrated into an EnduraTM platform, also available from Applied Materials, Inc.
- the IMP process provides a higher density plasma than standard PVD that causes the sputtered target material to become ionized as the sputtered material passes therethrough.
- the ionization enables the sputtered material to be attracted in a substantially perpendicular direction to a biased substrate surface and to deposit a thin layer even in high aspect ratio features.
- the high density plasma is supported by a coil 122 internal to the chamber through which AC current is passed. The current couples with the atoms of gas and sputtered material to ionize a significant portion thereof.
- the chamber 100 includes sidewalls 101 , lid 102 , and bottom 103 .
- the lid 102 includes a target backing plate 104 which supports a target 105 of the material to be deposited.
- the target 105 is preferably made of a conductive material and a doping material.
- the conductive material is selected from a group of copper, tungsten, aluminum or combinations thereof.
- the doping material is selected from a group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- the conductive material is copper and the doping material is phosphorus.
- the percentage by weight of the doping material is from about 0.01% to about 15%, preferably about 0.01% to about 0.5%.
- the target can be prepared, for example, by uniformly mixing a phosphorus oxide into a molten copper material where the oxygen is thermally or chemically released and the remaining phosphorus and copper formed into a target. A number of processes known to metallurgists are possible to produce a doped target.
- An opening 108 in the chamber 100 provides access for a robot (not shown) to deliver and retrieve substrates 110 to and from the chamber 100 .
- a substrate support 112 supports the substrate 110 in the chamber and is typically grounded.
- the substrate support 112 is mounted on a lift motor 114 that raises and lowers the substrate support 112 and a substrate 110 disposed thereon.
- a lift plate 116 connected to a lift motor 118 is mounted in the chamber 100 and raises and lowers pins 120 a, 120 b mounted in the substrate support 112 .
- the pins 120 a, 120 b raise and lower the substrate 110 from and to the surface of the substrate support 112 .
- a coil 122 is mounted between the substrate support 112 and the target 105 and provides inductively-coupled magnetic fields in the chamber 100 to assist in generating and maintaining a plasma between the target 105 and substrate 110 .
- the coil 122 is sputtered due to its location between the target and the substrate 110 and preferably is made of similar constituents as the target 105 .
- the coil 122 could be made of copper and phosphorus.
- the doping percentage of the coil 122 could vary compared to the target doping percentage depending on the desired layer composition and is empirically determined by varying the relative doping percentages. Power supplied to the coil 122 densifies the plasma which ionizes the sputtered material. The ionized material is then directed toward the substrate 110 and deposited thereon.
- a power supply 130 delivers preferably DC power to the target 105 to cause the processing gas to form a plasma, although RF power can be used.
- Magnets 106 a, 106 b disposed behind the target backing plate 104 increase the density of electrons adjacent to the target 105 , thus increasing ionization at the target to increase the sputtering efficiency.
- the magnets 106 a, 106 b generate magnetic field lines generally parallel to the face of the target, around which electrons are trapped in spinning orbits to increase the likelihood of a collision with, and ionization of, a gas atom for sputtering.
- a power supply 132 preferably a RF power supply, supplies electrical power to the coil 122 to couple with and increase the density of the plasma.
- Another power supply 134 typically a DC power supply, biases the substrate support 112 with respect to the plasma and provides directional attraction (or repulsion) of the ionized sputtered material toward the substrate 110 .
- Processing gas such as an inert gas of argon or helium or a reactive gas such as nitrogen, is supplied to the chamber 100 through a gas inlet 136 from gas sources 138 , 140 as metered by respective mass flow controllers 142 , 144 .
- a vacuum pump 146 is connected to the chamber 100 at an exhaust port 148 to exhaust the chamber 100 and maintain the desired pressure in the chamber 100 .
- a controller 149 generally controls the functions of the power supplies, lift motors, mass flow controllers for gas injection, vacuum pump, and other associated chamber components and functions.
- the controller 149 controls the power supply 130 coupled to the target 105 to cause the processing gas to form a plasma and sputter the target material.
- the controller 149 also controls the power supply 132 coupled to the coil 122 to increase the density of the plasma and ionize the sputtered material.
- the controller 149 also controls the power supply 134 to provide directional attraction of the ionized sputtered material to the substrate surface.
- the controller 149 executes system control software stored in a memory, which in the preferred embodiment is a hard disk drive, and can include analog and digital input/output boards, interface boards, and stepper motor controller boards (not shown). Optical and/or magnetic sensors (not shown) are generally used to move and determine the position of movable mechanical assemblies.
- a noble gas such as helium or argon
- the power supply 130 delivers about 200 watts (W) to about 6 kW, preferably about 750 W to about 1.5 kW to the target 105 .
- the power supply 132 delivers about 500 W to about 5 kW, preferably about 1.5 kW to about 2.5 kW AC to the coil 122 .
- the power supply 134 delivers about 0 W to about 600 W, preferably about 350 W to about 500 W to the substrate support 112 with a duty cycle between 0% to 100% and preferably about 50% to about 75%.
- a surface temperature between about ⁇ 50° C. to about 150° C., preferably below 50° C. is useful for processing during the seed layer deposition.
- the copper/phosphorus material is deposited on the substrate to a thickness of about 500 ⁇ to about 4000 ⁇ , preferably about 2000 ⁇ .
- FIG. 2 is a schematic cross-sectional view of an exemplary substrate 110 formed according to a process of the invention.
- a dielectric layer 204 is deposited on an underlying layer 202 and etched to form the feature 200 , such as a via, contact, trench or line.
- the term “substrate” is broadly defined as the underlying material and can include a series of underlying layers.
- the dielectric layer 204 can be a pre-metal dielectric layer deposited over a silicon wafer or an interlevel dielectric layer.
- a liner layer 206 such as a Ta layer, is deposited on the dielectric layer 204 as a transition layer to promote adhesion to the underlying material and reduce contact/via resistance.
- the liner layer 206 is preferably deposited using a IMP PVD process and can be deposited by other PVD processes, such as collimated or long throw sputtering or other methods such as CVD.
- Collimated sputtering is generally performed by placing a collimator (not shown) between the target and the substrate to filter sputtered material traveling obliquely through the collimator.
- Long throw sputtering is generally performed by increasing the spacing between the target and the substrate.
- a barrier layer 208 of tantalum nitride (TaN) is deposited on the liner layer 206 using PVD, and preferably an IMP PVD process, especially for high aspect ratio features.
- the barrier layer prevents diffusion of copper into adjacent layers. While Ta/TaN are preferred, other liner and/or barrier layers that can be used are titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN) and other refractory metals and their nitrided counterparts.
- a doped seed layer 210 is deposited over the TaN barrier layer 208 , using PVD and preferably IMP PVD.
- the seed layer 210 is deposited by sputtering a conductive target preferably doped with phosphorus.
- the conductive material is selected from the group of copper, tungsten, aluminum or combinations thereof.
- the doping material is selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- the conductive material is copper and the doping material is phosphorus.
- the percentage by weight of the doping material is from about 0.01% to about 15%, preferably about 0.01% to about 0.5%.
- the copper/phosphorus material is deposited over the barrier layer 208 as a seed layer for a subsequent copper layer 212 .
- the copper layer 212 can be deposited by PVD, IMP, CVD, electroplating, electroless deposition, evaporation, or other known methods. Preferably, copper layer 212 is deposited using electroplating techniques.
- An exemplary electroplating system is described in co-pending U.S. patent application Ser. No. 09/350,877, filed on Jul. 9, 1999, and in co-pending U.S. patent application Ser. No. 09/289,074, filed on Apr. 8, 1999, and are incorporated herein by reference.
- a description of an electroplating chemistry, particularly the composition of the electrolyte and additives, is provided in co-pending U.S. patent application. Ser. No. 09/245,780, filed on Feb. 5, 1999 and is incorporated herein by reference.
- Subsequent processing can include planarization by chemical mechanical polishing (CMP), additional deposition of layers, etching, and other processes known to substrate manufacturing.
- CMP chemical mechanical polishing
- the doping material is believed to reduce surface diffusivity of the sputtered conductive material, such as copper, as the sputtered material is deposited. Less agglomeration occurs with the doping and the sputtered conductive layer is deposited more conformally with less voids. For a subsequent process, such as electroplating, that is affected by the integrity of an underlying seed layer, the doped layer yields a more uniform subsequent layer deposited thereon.
- Phosphorus and other doping materials also reduce copper oxidation due to their generally greater affinity for oxygen than copper at processing temperatures. It is believed that oxygen reaching the substrate surface prefers initiating bonds with the dopant, leaving the copper less likely to be oxidized. A lower level of oxidation reduces the resistance of both the target material and the deposited layer of the target material. Reduced oxidation also assists in reducing corrosion in post-deposition processing such as wet CMP processing. The phosphorus is also believed to harden the target and the deposited layer. Empirical evidence suggests that harder targets result in reduced arcing between the target and an adjacent structure, where the arcing dislodges unwanted pieces of the target (splats) that are deposited on the substrate and contaminates the deposition. The phosphorus is also believed to lower the melting temperature of the copper, so that surface mobility and planarization can occur at lower temperatures.
Abstract
The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material. The overall surface diffusivity of copper is reduced such that the tendency to agglomerate or to become discontinuous is reduced, thereby allowing the deposition of a smoother conductive film and thereby reducing localized agglomeration of the conductive material. The smoother film is highly desirable for subsequent deposition processes. A conductive material, such as copper, can be deposited on the deposited doped layer by a variety of processes including PVD, chemical vapor deposition (CVD), electroplating, electroless deposition and other deposition processes.
Description
- 1. Field of the Invention
- The present invention relates to the deposition of a layer on a substrate. More specifically, the invention relates to deposition of a doped layer on a substrate.
- 2. Background of the Related Art
- Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) and other electronic devices. The shrinking dimensions of features, presently in the sub-quarter micron and smaller range, such as horizontal interconnects (typically referred to as lines) and vertical interconnects (typically referred to as contacts or vias; contacts extend to a device on the underlying substrate, while vias extend to an underlying metal layer, such as M1, M2, etc.) in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology, has increased the importance of reducing capacitive coupling between interconnect lines and reducing resistance in the conductive features.
- Aluminum has traditionally been the choice of conductive materials used in metallization. However, smaller feature sizes have created a need for a conductive material with lower resistivity than aluminum. Copper is now being considered as an interconnect material to replace or complement aluminum because copper has a lower resistivity (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum) and higher current carrying capacity.
- Despite the desirability of using copper for semiconductor device fabrication, choices of methods for depositing copper into features having a high aspect ratio above about 4:1 in sub-quarter micron features are limited. In the past, chemical vapor deposition (CVD) and physical vapor deposition (PVD) were the preferred processes for depositing electrically conductive material, typically aluminum, to fill the contacts, vias, lines, or other features formed on the substrate. However, precursors for CVD processes for depositing copper are currently under development and PVD processes for filling copper features can bridge the openings of very small features and leave voids in the features.
- As a result of CVD and PVD challenges, electroplating processes, previously used primarily for circuit board fabrication, are being developed for deposition of conductive material, particularly copper, to fill small features on a substrate. However, electroplating has its own challenges in depositing uniformly on a substrate. Electroplating uses an electrically conductive seed layer, such as a copper layer conformally deposited by CVD or PVD, to initiate the electroplating deposition process on the substrate. As stated, the CVD of copper is being developed and thus, PVD is the current choice for depositing the seed layer conformally over the feature.
- However, PVD of copper tends to agglomerate across the deposition surface and in the lines and vias due to surface diffusion of the copper material. As the copper is deposited on a substrate, a high surface diffusivity of copper, which is a function of the deposition temperature, causes the deposited copper film to agglomerate such that the film will either dewet, thereby becoming discontinuous, and/or roughen such that the agglomeration reduces the overall surface energy of the exposed copper surface. This agglomeration has the adverse effect on a subsequent electroplating process such that either the discontinuous film will lead to micro-voids in the electroplated copper or the roughened surface will provide a localized electrical field, also resulting in micro-voids and other nonuniformities. If the electroplated layer, such as a seed layer, is nonuniformly deposited on the substrate, then the current will not be evenly distributed over the surface of the seed layer and may result in nonuniform deposition of a subsequent electroplated layer on the substrate.
- Furthermore, copper is highly susceptible to oxidation, which increases the resistivity of a copper feature. Oxidation can occur when the substrate is moved between chambers and exposed to ambient conditions or in a particular process that exposes the copper to an oxygen source. Oxidation of copper increases the resistivity of the lines and vias formed.
- Therefore, there is a need for an improved deposition process that reduces the voids in features produced from a conductive material deposition and reduces unwanted oxidation effects on the substrate.
- The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material. The overall surface diffusivity of copper is reduced such that the tendency to agglomerate or to become discontinuous is reduced, thereby allowing the deposition of a smoother conductive film and thereby reducing localized agglomeration of the conductive material. The smoother film is highly desirable for subsequent deposition processes. A conductive material, such as copper, can be deposited on the deposited doped layer by a variety of processes including PVD, chemical vapor deposition (CVD), electroplating, electroless deposition and other deposition processes.
- In one aspect, the present invention provides an apparatus for depositing a material on a substrate, comprising a processing chamber and a doped conductive target. The target comprises a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- In another aspect, the invention provides a doped conductive target for sputtering a layer on a substrate. The doped conductive target comprises a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- In another aspect, the invention provides a substrate having a doped seed layer deposited by a sputtering process on the substrate. The doped seed layer comprises a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
- In another aspect, the invention provides a method of sputtering a layer on a substrate, comprising generating a plasma in a substrate processing chamber, sputtering material from a doped conductive target, the target comprising a conductive material selected from the group of copper, tungsten, aluminum or combinations thereof and a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof, and depositing the sputtered doped material on the substrate. A conductive layer of copper can be deposited over the sputtered doped material, preferably, by an electroplating process.
- So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
- It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
- FIG. 1 is a schematic cross-sectional view of an IMP chamber.
- FIG. 2 is a schematic cross-sectional view of a substrate with a seed layer formed on the substrate.
- The present invention provides a method and apparatus for forming a doped layer on a substrate, preferably using a sputtering process. The doped layer preferably comprises copper doped with phosphorus.
- FIG. 1 is a schematic cross-sectional view of an
IMP chamber 100, capable of generating a relatively high density plasma, i.e., one with a capability to ionize a significant fraction of both the process gas (typically argon) and the sputtered target material. A sputtering chamber, known as an IMP Vectra™ chamber, is available from Applied Materials, Inc. of Santa Clara, Calif. The IMP chamber can be integrated into an Endura™ platform, also available from Applied Materials, Inc. The IMP process provides a higher density plasma than standard PVD that causes the sputtered target material to become ionized as the sputtered material passes therethrough. The ionization enables the sputtered material to be attracted in a substantially perpendicular direction to a biased substrate surface and to deposit a thin layer even in high aspect ratio features. The high density plasma is supported by acoil 122 internal to the chamber through which AC current is passed. The current couples with the atoms of gas and sputtered material to ionize a significant portion thereof. Thechamber 100 includessidewalls 101,lid 102, andbottom 103. Thelid 102 includes atarget backing plate 104 which supports atarget 105 of the material to be deposited. - The
target 105 is preferably made of a conductive material and a doping material. The conductive material is selected from a group of copper, tungsten, aluminum or combinations thereof. The doping material is selected from a group of phosphorus, boron, indium, tin, beryllium or combinations thereof. Preferably, the conductive material is copper and the doping material is phosphorus. The percentage by weight of the doping material is from about 0.01% to about 15%, preferably about 0.01% to about 0.5%. The target can be prepared, for example, by uniformly mixing a phosphorus oxide into a molten copper material where the oxygen is thermally or chemically released and the remaining phosphorus and copper formed into a target. A number of processes known to metallurgists are possible to produce a doped target. - An
opening 108 in thechamber 100 provides access for a robot (not shown) to deliver and retrievesubstrates 110 to and from thechamber 100. Asubstrate support 112 supports thesubstrate 110 in the chamber and is typically grounded. Thesubstrate support 112 is mounted on alift motor 114 that raises and lowers thesubstrate support 112 and asubstrate 110 disposed thereon. Alift plate 116 connected to alift motor 118 is mounted in thechamber 100 and raises and lowerspins substrate support 112. Thepins substrate 110 from and to the surface of thesubstrate support 112. Acoil 122 is mounted between thesubstrate support 112 and thetarget 105 and provides inductively-coupled magnetic fields in thechamber 100 to assist in generating and maintaining a plasma between thetarget 105 andsubstrate 110. Thecoil 122 is sputtered due to its location between the target and thesubstrate 110 and preferably is made of similar constituents as thetarget 105. For instance, thecoil 122 could be made of copper and phosphorus. The doping percentage of thecoil 122 could vary compared to the target doping percentage depending on the desired layer composition and is empirically determined by varying the relative doping percentages. Power supplied to thecoil 122 densifies the plasma which ionizes the sputtered material. The ionized material is then directed toward thesubstrate 110 and deposited thereon. Ashield 124 is disposed in thechamber 100 to shield the chamber sidewalls 101 from the sputtered material. Theshield 124 also supports thecoil 122 by coil supports 126. The coil supports 126 electrically insulate thecoil 122 from theshield 124 and thechamber 100 and can be made of similar material as the coil. Theclamp ring 128 is mounted between thecoil 122 and thesubstrate support 112 and shields an outer edge and backside of the substrate from sputtered materials when thesubstrate 110 is raised into a processing position to engage the lower portion of theclamp ring 128. In some chamber configurations, theshield 124 supports theclamp ring 128 when thesubstrate 110 is lowered below theshield 124 to enable substrate transfer. - Three power supplies are used in this type of sputtering chamber. A
power supply 130 delivers preferably DC power to thetarget 105 to cause the processing gas to form a plasma, although RF power can be used.Magnets 106 a, 106 b disposed behind thetarget backing plate 104 increase the density of electrons adjacent to thetarget 105, thus increasing ionization at the target to increase the sputtering efficiency. Themagnets 106 a, 106 b generate magnetic field lines generally parallel to the face of the target, around which electrons are trapped in spinning orbits to increase the likelihood of a collision with, and ionization of, a gas atom for sputtering. Apower supply 132, preferably a RF power supply, supplies electrical power to thecoil 122 to couple with and increase the density of the plasma. Anotherpower supply 134, typically a DC power supply, biases thesubstrate support 112 with respect to the plasma and provides directional attraction (or repulsion) of the ionized sputtered material toward thesubstrate 110. - Processing gas, such as an inert gas of argon or helium or a reactive gas such as nitrogen, is supplied to the
chamber 100 through agas inlet 136 fromgas sources mass flow controllers vacuum pump 146 is connected to thechamber 100 at anexhaust port 148 to exhaust thechamber 100 and maintain the desired pressure in thechamber 100. - A
controller 149 generally controls the functions of the power supplies, lift motors, mass flow controllers for gas injection, vacuum pump, and other associated chamber components and functions. Thecontroller 149 controls thepower supply 130 coupled to thetarget 105 to cause the processing gas to form a plasma and sputter the target material. Thecontroller 149 also controls thepower supply 132 coupled to thecoil 122 to increase the density of the plasma and ionize the sputtered material. Thecontroller 149 also controls thepower supply 134 to provide directional attraction of the ionized sputtered material to the substrate surface. Thecontroller 149 executes system control software stored in a memory, which in the preferred embodiment is a hard disk drive, and can include analog and digital input/output boards, interface boards, and stepper motor controller boards (not shown). Optical and/or magnetic sensors (not shown) are generally used to move and determine the position of movable mechanical assemblies. - An exemplary process regime for a copper seed layer doped with phosphorus on a 200 mm wafer will now be described. A noble gas, such as helium or argon, is flown into the chamber at a rate sufficient to produce a chamber pressure of about 5 to about 100 Mtorr, preferably about 20 Mtorr to about 50 mTorr. The
power supply 130 delivers about 200 watts (W) to about 6 kW, preferably about 750 W to about 1.5 kW to thetarget 105. Thepower supply 132 delivers about 500 W to about 5 kW, preferably about 1.5 kW to about 2.5 kW AC to thecoil 122. Thepower supply 134 delivers about 0 W to about 600 W, preferably about 350 W to about 500 W to thesubstrate support 112 with a duty cycle between 0% to 100% and preferably about 50% to about 75%. When the substrate temperature is controlled, a surface temperature between about −50° C. to about 150° C., preferably below 50° C. is useful for processing during the seed layer deposition. The copper/phosphorus material is deposited on the substrate to a thickness of about 500 Å to about 4000 Å, preferably about 2000 Å. - FIG. 2 is a schematic cross-sectional view of an
exemplary substrate 110 formed according to a process of the invention. Adielectric layer 204 is deposited on anunderlying layer 202 and etched to form thefeature 200, such as a via, contact, trench or line. The term “substrate” is broadly defined as the underlying material and can include a series of underlying layers. Thedielectric layer 204 can be a pre-metal dielectric layer deposited over a silicon wafer or an interlevel dielectric layer. - A
liner layer 206, such as a Ta layer, is deposited on thedielectric layer 204 as a transition layer to promote adhesion to the underlying material and reduce contact/via resistance. Theliner layer 206 is preferably deposited using a IMP PVD process and can be deposited by other PVD processes, such as collimated or long throw sputtering or other methods such as CVD. Collimated sputtering is generally performed by placing a collimator (not shown) between the target and the substrate to filter sputtered material traveling obliquely through the collimator. Long throw sputtering is generally performed by increasing the spacing between the target and the substrate. The increased distance increases the probability that the sputtered material reaching the substrate is directed normal to the substrate surface. Abarrier layer 208 of tantalum nitride (TaN) is deposited on theliner layer 206 using PVD, and preferably an IMP PVD process, especially for high aspect ratio features. The barrier layer prevents diffusion of copper into adjacent layers. While Ta/TaN are preferred, other liner and/or barrier layers that can be used are titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN) and other refractory metals and their nitrided counterparts. - A doped
seed layer 210 is deposited over theTaN barrier layer 208, using PVD and preferably IMP PVD. Theseed layer 210 is deposited by sputtering a conductive target preferably doped with phosphorus. The conductive material is selected from the group of copper, tungsten, aluminum or combinations thereof. The doping material is selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof. Preferably, the conductive material is copper and the doping material is phosphorus. The percentage by weight of the doping material is from about 0.01% to about 15%, preferably about 0.01% to about 0.5%. The copper/phosphorus material is deposited over thebarrier layer 208 as a seed layer for asubsequent copper layer 212. - The
copper layer 212 can be deposited by PVD, IMP, CVD, electroplating, electroless deposition, evaporation, or other known methods. Preferably,copper layer 212 is deposited using electroplating techniques. An exemplary electroplating system is described in co-pending U.S. patent application Ser. No. 09/350,877, filed on Jul. 9, 1999, and in co-pending U.S. patent application Ser. No. 09/289,074, filed on Apr. 8, 1999, and are incorporated herein by reference. A description of an electroplating chemistry, particularly the composition of the electrolyte and additives, is provided in co-pending U.S. patent application. Ser. No. 09/245,780, filed on Feb. 5, 1999 and is incorporated herein by reference. - Subsequent processing can include planarization by chemical mechanical polishing (CMP), additional deposition of layers, etching, and other processes known to substrate manufacturing.
- The doping material is believed to reduce surface diffusivity of the sputtered conductive material, such as copper, as the sputtered material is deposited. Less agglomeration occurs with the doping and the sputtered conductive layer is deposited more conformally with less voids. For a subsequent process, such as electroplating, that is affected by the integrity of an underlying seed layer, the doped layer yields a more uniform subsequent layer deposited thereon.
- Phosphorus and other doping materials also reduce copper oxidation due to their generally greater affinity for oxygen than copper at processing temperatures. It is believed that oxygen reaching the substrate surface prefers initiating bonds with the dopant, leaving the copper less likely to be oxidized. A lower level of oxidation reduces the resistance of both the target material and the deposited layer of the target material. Reduced oxidation also assists in reducing corrosion in post-deposition processing such as wet CMP processing. The phosphorus is also believed to harden the target and the deposited layer. Empirical evidence suggests that harder targets result in reduced arcing between the target and an adjacent structure, where the arcing dislodges unwanted pieces of the target (splats) that are deposited on the substrate and contaminates the deposition. The phosphorus is also believed to lower the melting temperature of the copper, so that surface mobility and planarization can occur at lower temperatures.
- Variations in the orientation of the chambers and other system components are possible. Additionally, all movements and positions, such as “above”, “top”, “below”, “under”, “bottom”, “side”, described herein are relative to positions of objects such as the target, substrate, and coil. Accordingly, it is contemplated by the present invention to orient any or all of the components to achieve the desired support of substrates in a processing system.
- While foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof and the scope thereof is determined by the claims that follow.
Claims (25)
1. A method for forming a conductive feature, comprising:
a) sputtering material from a target comprising copper and phosphorus;
b) ionizing the sputtered material;
c) depositing a seed layer comprising copper and phosphorous over a surface of a substrate.
2. The method of claim 1 , further comprising depositing a copper layer on at least a portion of the seed layer on the substrate by physical vapor deposition, ionized metal plasma deposition, chemical vapor deposition, electroplating, electroless deposition, or evaporation.
3. The method of claim 1 , further comprising depositing copper on at least a portion of the seed layer by an electroplating process.
4. The method of claim 1 , wherein the target further comprises tungsten, aluminum, or a combination thereof.
5. The method of claim 1 , further comprising sputtering material from a doped coil comprising:
a) copper, tungsten, aluminum or combinations thereof; and
b) a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
6. The method of claim 5 , wherein the doped coil comprises copper and phosphorous.
7. The method of claim 1 , wherein the sputtered material comprises about 0.01% to about 15% by weight of phosphorous.
8. The method of claim 1 , wherein the seed layer comprises about 0.01% to about 15% by weight of phosphorous.
9. A method for forming a conductive feature, comprising:
a) positioning a substrate to have the feature formed thereon within a processing chamber, wherein the processing chamber includes a target comprising copper and phosphorus;
b) sputtering material from the target;
c) ionizing the sputtered material;
d) depositing a seed layer comprising copper and phosphorous over a surface of the substrate; and
e) depositing a copper layer on at least a portion of the seed layer.
10. The method of claim 9 , wherein the sputtered material comprises about 0.01% to about 15% by weight of phosphorous.
11. The method of claim 9 , wherein the copper layer is deposited by physical vapor deposition, ionized metal plasma deposition, chemical vapor deposition, electroplating, electroless deposition, or evaporation.
12. The method of claim 9 , wherein the copper layer is deposited by an electroplating process.
13. The method of claim 9 , further comprising sputtering material from a doped coil comprising:
a) copper, tungsten, aluminum or combinations thereof; and
b) a doping material selected from the group of phosphorus, boron, indium, tin, beryllium or combinations thereof.
14. The method of claim 13 , wherein the doped coil comprises copper and phosphorous.
15. The method of claim 9 , further comprising depositing a refractory metal liner layer prior to depositing the seed layer.
16. The method of claim 15 , wherein the refractory metal liner layer comprises one or more materials selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, and tungsten nitride.
17. The method of claim 9 , wherein the target further comprises tungsten, aluminum, or a combination thereof.
18. The method of claim 9 , wherein the seed layer further comprises tungsten, aluminum, or a combination thereof.
19. A method for facilitating deposition of an electrochemical copper bulk layer onto a semiconductor substrate, comprising:
a) positioning a semiconductor substrate to be processed within a processing chamber, wherein the processing chamber includes a target comprising copper and phosphorus;
b) sputtering material from the target;
c) ionizing the sputtered material;
d) depositing a seed layer comprising copper and phosphorous over a surface of a substrate; and
e) depositing a copper layer on at least a portion of the seed layer.
20. The method of claim 19 , wherein the sputtered material comprises about 0.01% to about 15% by weight of phosphorous.
21. The method of claim 19 , further comprising depositing a refractory metal liner layer prior to depositing the seed layer.
22. The method of claim 21 , wherein the refractory metal liner layer comprises one or more materials selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, and tungsten nitride.
23. The method of claim 19 , wherein the target further comprises tungsten, aluminum, or a combination thereof.
24. The method of claim 19 , wherein the seed layer further comprises tungsten, aluminum, or a combination thereof.
25. The method of claim 19 , wherein the seed layer comprises about 0.01% to about 15% by weight of phosphorous.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/198,437 US20020182887A1 (en) | 1999-09-27 | 2002-07-16 | Method and apparatus of forming a sputtered doped seed layer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/406,325 US6432819B1 (en) | 1999-09-27 | 1999-09-27 | Method and apparatus of forming a sputtered doped seed layer |
US10/198,437 US20020182887A1 (en) | 1999-09-27 | 2002-07-16 | Method and apparatus of forming a sputtered doped seed layer |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/406,325 Division US6432819B1 (en) | 1999-09-27 | 1999-09-27 | Method and apparatus of forming a sputtered doped seed layer |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020182887A1 true US20020182887A1 (en) | 2002-12-05 |
Family
ID=23607481
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/406,325 Expired - Fee Related US6432819B1 (en) | 1999-09-27 | 1999-09-27 | Method and apparatus of forming a sputtered doped seed layer |
US10/198,437 Abandoned US20020182887A1 (en) | 1999-09-27 | 2002-07-16 | Method and apparatus of forming a sputtered doped seed layer |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/406,325 Expired - Fee Related US6432819B1 (en) | 1999-09-27 | 1999-09-27 | Method and apparatus of forming a sputtered doped seed layer |
Country Status (5)
Country | Link |
---|---|
US (2) | US6432819B1 (en) |
EP (1) | EP1087431A3 (en) |
JP (1) | JP2001220667A (en) |
KR (1) | KR20010030504A (en) |
SG (1) | SG86443A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050098427A1 (en) * | 2003-11-11 | 2005-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | RF coil design for improved film uniformity of an ion metal plasma source |
US20070158179A1 (en) * | 2006-01-11 | 2007-07-12 | Anthony Ciancio | Method and apparatus for improving symmetry of a layer deposited on a semiconductor substrate |
US20110192719A1 (en) * | 2008-10-24 | 2011-08-11 | Mitsubishi Materials Corporation | Sputtering target for forming thin film transistor wiring film |
WO2012040733A2 (en) * | 2010-09-24 | 2012-03-29 | Intel Corporation | Barrier layers |
CN111952263A (en) * | 2019-05-16 | 2020-11-17 | 上海交通大学 | Micron-sized single crystal copper interconnection structure and preparation method thereof |
Families Citing this family (199)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569751B1 (en) * | 2000-07-17 | 2003-05-27 | Lsi Logic Corporation | Low via resistance system |
US6355561B1 (en) * | 2000-11-21 | 2002-03-12 | Micron Technology, Inc. | ALD method to improve surface coverage |
US6979646B2 (en) * | 2000-12-29 | 2005-12-27 | Intel Corporation | Hardening of copper to improve copper CMP performance |
JP2002217292A (en) * | 2001-01-23 | 2002-08-02 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacturing method |
US6951804B2 (en) | 2001-02-02 | 2005-10-04 | Applied Materials, Inc. | Formation of a tantalum-nitride layer |
US6740221B2 (en) | 2001-03-15 | 2004-05-25 | Applied Materials Inc. | Method of forming copper interconnects |
KR100499557B1 (en) * | 2001-06-11 | 2005-07-07 | 주식회사 하이닉스반도체 | method for fabricating the wire of semiconductor device |
TWI223867B (en) * | 2001-10-26 | 2004-11-11 | Applied Materials Inc | Method for forming a metal interconnect on a substrate |
US7521366B2 (en) * | 2001-12-12 | 2009-04-21 | Lg Display Co., Ltd. | Manufacturing method of electro line for liquid crystal display device |
US7239747B2 (en) * | 2002-01-24 | 2007-07-03 | Chatterbox Systems, Inc. | Method and system for locating position in printed texts and delivering multimedia information |
US7138014B2 (en) | 2002-01-28 | 2006-11-21 | Applied Materials, Inc. | Electroless deposition apparatus |
US6824666B2 (en) * | 2002-01-28 | 2004-11-30 | Applied Materials, Inc. | Electroless deposition method over sub-micron apertures |
US6905622B2 (en) * | 2002-04-03 | 2005-06-14 | Applied Materials, Inc. | Electroless deposition method |
US20030188974A1 (en) * | 2002-04-03 | 2003-10-09 | Applied Materials, Inc. | Homogeneous copper-tin alloy plating for enhancement of electro-migration resistance in interconnects |
US6899816B2 (en) * | 2002-04-03 | 2005-05-31 | Applied Materials, Inc. | Electroless deposition method |
AU2003219505A1 (en) | 2002-04-11 | 2003-10-27 | Moshe Ben-Chorin | Color display devices and methods with enhanced attributes |
JP3797317B2 (en) * | 2002-05-30 | 2006-07-19 | 住友金属鉱山株式会社 | Target for transparent conductive thin film, transparent conductive thin film and manufacturing method thereof, electrode material for display, organic electroluminescence element |
US20040118699A1 (en) * | 2002-10-02 | 2004-06-24 | Applied Materials, Inc. | Homogeneous copper-palladium alloy plating for enhancement of electro-migration resistance in interconnects |
US6821909B2 (en) * | 2002-10-30 | 2004-11-23 | Applied Materials, Inc. | Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application |
US7827930B2 (en) * | 2004-01-26 | 2010-11-09 | Applied Materials, Inc. | Apparatus for electroless deposition of metals onto semiconductor substrates |
US7654221B2 (en) * | 2003-10-06 | 2010-02-02 | Applied Materials, Inc. | Apparatus for electroless deposition of metals onto semiconductor substrates |
US7064065B2 (en) * | 2003-10-15 | 2006-06-20 | Applied Materials, Inc. | Silver under-layers for electroless cobalt alloys |
US7465358B2 (en) * | 2003-10-15 | 2008-12-16 | Applied Materials, Inc. | Measurement techniques for controlling aspects of a electroless deposition process |
US20070111519A1 (en) * | 2003-10-15 | 2007-05-17 | Applied Materials, Inc. | Integrated electroless deposition system |
WO2005038084A2 (en) * | 2003-10-17 | 2005-04-28 | Applied Materials, Inc. | Selective self-initiating electroless capping of copper with cobalt-containing alloys |
US20060003570A1 (en) * | 2003-12-02 | 2006-01-05 | Arulkumar Shanmugasundram | Method and apparatus for electroless capping with vapor drying |
US20050230350A1 (en) | 2004-02-26 | 2005-10-20 | Applied Materials, Inc. | In-situ dry clean chamber for front end of line fabrication |
US20050266173A1 (en) * | 2004-05-26 | 2005-12-01 | Tokyo Electron Limited | Method and apparatus of distributed plasma processing system for conformal ion stimulated nanoscale deposition process |
US7651934B2 (en) | 2005-03-18 | 2010-01-26 | Applied Materials, Inc. | Process for electroless copper deposition |
US20060246217A1 (en) * | 2005-03-18 | 2006-11-02 | Weidman Timothy W | Electroless deposition process on a silicide contact |
TW200707640A (en) | 2005-03-18 | 2007-02-16 | Applied Materials Inc | Contact metallization scheme using a barrier layer over a silicide layer |
US7285496B2 (en) * | 2005-04-28 | 2007-10-23 | Intel Corporation | Hardening of copper to improve copper CMP performance |
JP4923450B2 (en) * | 2005-07-01 | 2012-04-25 | 富士ゼロックス株式会社 | Batch processing support apparatus and method, program |
US20070012559A1 (en) * | 2005-07-13 | 2007-01-18 | Applied Materials, Inc. | Method of improving magnetron sputtering of large-area substrates using a removable anode |
US20070012663A1 (en) * | 2005-07-13 | 2007-01-18 | Akihiro Hosokawa | Magnetron sputtering system for large-area substrates having removable anodes |
US20070012558A1 (en) * | 2005-07-13 | 2007-01-18 | Applied Materials, Inc. | Magnetron sputtering system for large-area substrates |
US20070084720A1 (en) * | 2005-07-13 | 2007-04-19 | Akihiro Hosokawa | Magnetron sputtering system for large-area substrates having removable anodes |
US20070051616A1 (en) * | 2005-09-07 | 2007-03-08 | Le Hienminh H | Multizone magnetron assembly |
US7588668B2 (en) | 2005-09-13 | 2009-09-15 | Applied Materials, Inc. | Thermally conductive dielectric bonding of sputtering targets using diamond powder filler or thermally conductive ceramic fillers |
US20070056843A1 (en) * | 2005-09-13 | 2007-03-15 | Applied Materials, Inc. | Method of processing a substrate using a large-area magnetron sputtering chamber with individually controlled sputtering zones |
US20070056850A1 (en) * | 2005-09-13 | 2007-03-15 | Applied Materials, Inc. | Large-area magnetron sputtering chamber with individually controlled sputtering zones |
US20070071888A1 (en) * | 2005-09-21 | 2007-03-29 | Arulkumar Shanmugasundram | Method and apparatus for forming device features in an integrated electroless deposition system |
US7749361B2 (en) * | 2006-06-02 | 2010-07-06 | Applied Materials, Inc. | Multi-component doping of copper seed layer |
US8791018B2 (en) | 2006-12-19 | 2014-07-29 | Spansion Llc | Method of depositing copper using physical vapor deposition |
US7867900B2 (en) | 2007-09-28 | 2011-01-11 | Applied Materials, Inc. | Aluminum contact integration on cobalt silicide junction |
JP5420328B2 (en) | 2008-08-01 | 2014-02-19 | 三菱マテリアル株式会社 | Sputtering target for forming wiring films for flat panel displays |
JP5651298B2 (en) * | 2008-10-24 | 2015-01-07 | シチズン時計マニュファクチャリング株式会社 | Plasma-assisted reactive thin film forming apparatus and thin film forming method using the same |
JP5457754B2 (en) * | 2009-08-07 | 2014-04-02 | 株式会社日立ハイテクノロジーズ | Plasma processing apparatus using transmissive electrode body |
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8771539B2 (en) | 2011-02-22 | 2014-07-08 | Applied Materials, Inc. | Remotely-excited fluorine and water vapor etch |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US8771536B2 (en) | 2011-08-01 | 2014-07-08 | Applied Materials, Inc. | Dry-etch for silicon-and-carbon-containing films |
US8679982B2 (en) | 2011-08-26 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and oxygen |
US8679983B2 (en) | 2011-09-01 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and nitrogen |
US8927390B2 (en) | 2011-09-26 | 2015-01-06 | Applied Materials, Inc. | Intrench profile |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
WO2013070436A1 (en) | 2011-11-08 | 2013-05-16 | Applied Materials, Inc. | Methods of reducing substrate dislocation during gapfill processing |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
US9034770B2 (en) | 2012-09-17 | 2015-05-19 | Applied Materials, Inc. | Differential silicon oxide etch |
US9023734B2 (en) | 2012-09-18 | 2015-05-05 | Applied Materials, Inc. | Radical-component oxide etch |
US9390937B2 (en) | 2012-09-20 | 2016-07-12 | Applied Materials, Inc. | Silicon-carbon-nitride selective etch |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US8765574B2 (en) | 2012-11-09 | 2014-07-01 | Applied Materials, Inc. | Dry etch process |
US8969212B2 (en) | 2012-11-20 | 2015-03-03 | Applied Materials, Inc. | Dry-etch selectivity |
US8980763B2 (en) | 2012-11-30 | 2015-03-17 | Applied Materials, Inc. | Dry-etch for selective tungsten removal |
US9064816B2 (en) | 2012-11-30 | 2015-06-23 | Applied Materials, Inc. | Dry-etch for selective oxidation removal |
US9111877B2 (en) | 2012-12-18 | 2015-08-18 | Applied Materials, Inc. | Non-local plasma oxide etch |
US8921234B2 (en) | 2012-12-21 | 2014-12-30 | Applied Materials, Inc. | Selective titanium nitride etching |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
US9040422B2 (en) | 2013-03-05 | 2015-05-26 | Applied Materials, Inc. | Selective titanium nitride removal |
US8801952B1 (en) | 2013-03-07 | 2014-08-12 | Applied Materials, Inc. | Conformal oxide dry etch |
US10170282B2 (en) | 2013-03-08 | 2019-01-01 | Applied Materials, Inc. | Insulated semiconductor faceplate designs |
US20140271097A1 (en) | 2013-03-15 | 2014-09-18 | Applied Materials, Inc. | Processing systems and methods for halide scavenging |
US8895449B1 (en) | 2013-05-16 | 2014-11-25 | Applied Materials, Inc. | Delicate dry clean |
US9114438B2 (en) | 2013-05-21 | 2015-08-25 | Applied Materials, Inc. | Copper residue chamber clean |
US9493879B2 (en) | 2013-07-12 | 2016-11-15 | Applied Materials, Inc. | Selective sputtering for pattern transfer |
US9773648B2 (en) | 2013-08-30 | 2017-09-26 | Applied Materials, Inc. | Dual discharge modes operation for remote plasma |
US8956980B1 (en) | 2013-09-16 | 2015-02-17 | Applied Materials, Inc. | Selective etch of silicon nitride |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9236265B2 (en) | 2013-11-04 | 2016-01-12 | Applied Materials, Inc. | Silicon germanium processing |
US9576809B2 (en) | 2013-11-04 | 2017-02-21 | Applied Materials, Inc. | Etch suppression with germanium |
US9520303B2 (en) | 2013-11-12 | 2016-12-13 | Applied Materials, Inc. | Aluminum selective etch |
US9245762B2 (en) | 2013-12-02 | 2016-01-26 | Applied Materials, Inc. | Procedure for etch rate consistency |
US9117855B2 (en) | 2013-12-04 | 2015-08-25 | Applied Materials, Inc. | Polarity control for remote plasma |
US9263278B2 (en) | 2013-12-17 | 2016-02-16 | Applied Materials, Inc. | Dopant etch selectivity control |
US9287095B2 (en) | 2013-12-17 | 2016-03-15 | Applied Materials, Inc. | Semiconductor system assemblies and methods of operation |
US9190293B2 (en) | 2013-12-18 | 2015-11-17 | Applied Materials, Inc. | Even tungsten etch for high aspect ratio trenches |
US9287134B2 (en) | 2014-01-17 | 2016-03-15 | Applied Materials, Inc. | Titanium oxide etch |
US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
US9293568B2 (en) | 2014-01-27 | 2016-03-22 | Applied Materials, Inc. | Method of fin patterning |
US9385028B2 (en) | 2014-02-03 | 2016-07-05 | Applied Materials, Inc. | Air gap process |
US9499898B2 (en) | 2014-03-03 | 2016-11-22 | Applied Materials, Inc. | Layered thin film heater and method of fabrication |
US9299575B2 (en) | 2014-03-17 | 2016-03-29 | Applied Materials, Inc. | Gas-phase tungsten etch |
US9299538B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9299537B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9136273B1 (en) | 2014-03-21 | 2015-09-15 | Applied Materials, Inc. | Flash gate air gap |
US9903020B2 (en) | 2014-03-31 | 2018-02-27 | Applied Materials, Inc. | Generation of compact alumina passivation layers on aluminum plasma equipment components |
US9269590B2 (en) | 2014-04-07 | 2016-02-23 | Applied Materials, Inc. | Spacer formation |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9847289B2 (en) | 2014-05-30 | 2017-12-19 | Applied Materials, Inc. | Protective via cap for improved interconnect performance |
US9378969B2 (en) | 2014-06-19 | 2016-06-28 | Applied Materials, Inc. | Low temperature gas-phase carbon removal |
US9406523B2 (en) | 2014-06-19 | 2016-08-02 | Applied Materials, Inc. | Highly selective doped oxide removal method |
US9425058B2 (en) | 2014-07-24 | 2016-08-23 | Applied Materials, Inc. | Simplified litho-etch-litho-etch process |
US9496167B2 (en) | 2014-07-31 | 2016-11-15 | Applied Materials, Inc. | Integrated bit-line airgap formation and gate stack post clean |
US9378978B2 (en) | 2014-07-31 | 2016-06-28 | Applied Materials, Inc. | Integrated oxide recess and floating gate fin trimming |
US9159606B1 (en) | 2014-07-31 | 2015-10-13 | Applied Materials, Inc. | Metal air gap |
US9165786B1 (en) | 2014-08-05 | 2015-10-20 | Applied Materials, Inc. | Integrated oxide and nitride recess for better channel contact in 3D architectures |
US9659753B2 (en) | 2014-08-07 | 2017-05-23 | Applied Materials, Inc. | Grooved insulator to reduce leakage current |
US9553102B2 (en) | 2014-08-19 | 2017-01-24 | Applied Materials, Inc. | Tungsten separation |
US9355856B2 (en) | 2014-09-12 | 2016-05-31 | Applied Materials, Inc. | V trench dry etch |
US9478434B2 (en) | 2014-09-24 | 2016-10-25 | Applied Materials, Inc. | Chlorine-based hardmask removal |
US9368364B2 (en) | 2014-09-24 | 2016-06-14 | Applied Materials, Inc. | Silicon etch process with tunable selectivity to SiO2 and other materials |
US9613822B2 (en) | 2014-09-25 | 2017-04-04 | Applied Materials, Inc. | Oxide etch selectivity enhancement |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US9299583B1 (en) | 2014-12-05 | 2016-03-29 | Applied Materials, Inc. | Aluminum oxide selective etch |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US9502258B2 (en) | 2014-12-23 | 2016-11-22 | Applied Materials, Inc. | Anisotropic gap etch |
US9343272B1 (en) | 2015-01-08 | 2016-05-17 | Applied Materials, Inc. | Self-aligned process |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9373522B1 (en) | 2015-01-22 | 2016-06-21 | Applied Mateials, Inc. | Titanium nitride removal |
US9449846B2 (en) | 2015-01-28 | 2016-09-20 | Applied Materials, Inc. | Vertical gate separation |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US9881805B2 (en) | 2015-03-02 | 2018-01-30 | Applied Materials, Inc. | Silicon selective removal |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US9865484B1 (en) | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US10062575B2 (en) | 2016-09-09 | 2018-08-28 | Applied Materials, Inc. | Poly directional etch by oxidation |
TWI680496B (en) * | 2016-09-13 | 2019-12-21 | 美商應用材料股份有限公司 | Thick tungsten hardmask films deposition on high compressive/tensile bow wafers |
US9721789B1 (en) | 2016-10-04 | 2017-08-01 | Applied Materials, Inc. | Saving ion-damaged spacers |
US10062585B2 (en) | 2016-10-04 | 2018-08-28 | Applied Materials, Inc. | Oxygen compatible plasma source |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US9947549B1 (en) | 2016-10-10 | 2018-04-17 | Applied Materials, Inc. | Cobalt-containing material removal |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10043684B1 (en) | 2017-02-06 | 2018-08-07 | Applied Materials, Inc. | Self-limiting atomic thermal etching systems and methods |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10049891B1 (en) | 2017-05-31 | 2018-08-14 | Applied Materials, Inc. | Selective in situ cobalt residue removal |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
TWI766433B (en) | 2018-02-28 | 2022-06-01 | 美商應用材料股份有限公司 | Systems and methods to form airgaps |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
US11430692B2 (en) * | 2020-07-29 | 2022-08-30 | Taiwan Semiconductor Manufacturing Company Limited | Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same |
Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4094761A (en) | 1977-07-25 | 1978-06-13 | Motorola, Inc. | Magnetion sputtering of ferromagnetic material |
DE3142541C2 (en) | 1981-10-27 | 1986-07-31 | Demetron Gesellschaft für Elektronik-Werkstoffe mbH, 6540 Hanau | Multi-component alloy for targets in cathode sputtering systems |
US4620872A (en) | 1984-10-18 | 1986-11-04 | Mitsubishi Kinzoku Kabushiki Kaisha | Composite target material and process for producing the same |
FR2601175B1 (en) | 1986-04-04 | 1993-11-12 | Seiko Epson Corp | CATHODE SPRAYING TARGET AND RECORDING MEDIUM USING SUCH A TARGET. |
DE3631830A1 (en) | 1986-09-19 | 1988-03-31 | Demetron | MULTI-MATERIAL ALLOY FOR TARGETS OF CATHODE SPRAYING SYSTEMS AND THEIR USE |
JPS63130770A (en) * | 1986-11-21 | 1988-06-02 | Koujiyundo Kagaku Kenkyusho:Kk | Target material for vapor deposition |
US4885029A (en) | 1987-03-09 | 1989-12-05 | Scm Metal Products, Inc. | Thin section dispersion strengthened copper body and method of making same |
JP2602276B2 (en) | 1987-06-30 | 1997-04-23 | 株式会社日立製作所 | Sputtering method and apparatus |
JP2511289B2 (en) * | 1988-03-30 | 1996-06-26 | 株式会社日立製作所 | Semiconductor device |
JPH03196620A (en) * | 1989-12-26 | 1991-08-28 | Nippon Mining Co Ltd | Formation of copper wiring and target used therefor |
JPH03289156A (en) | 1990-04-06 | 1991-12-19 | Hitachi Ltd | Semiconductor device and manufacture thereof |
US5039570A (en) | 1990-04-12 | 1991-08-13 | Planar Circuit Technologies, Inc. | Resistive laminate for printed circuit boards, method and apparatus for forming the same |
JPH0430530A (en) * | 1990-05-28 | 1992-02-03 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of thin film for wiring |
US5130274A (en) | 1991-04-05 | 1992-07-14 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
JPH05214523A (en) * | 1992-02-05 | 1993-08-24 | Toshiba Corp | Sputtering target and its manufacture |
JP3220760B2 (en) * | 1992-03-19 | 2001-10-22 | 株式会社日立製作所 | Semiconductor device |
JPH06112009A (en) * | 1992-09-28 | 1994-04-22 | Ulvac Japan Ltd | High resistance film and manufacture thereof |
DE69330702T2 (en) * | 1992-10-05 | 2002-07-11 | Canon Kk | Process for the production of an optical storage medium, atomization method |
FR2698882B1 (en) | 1992-12-04 | 1995-02-03 | Castolin Sa | Method for forming a protective coating on a substrate. |
EP0601509A1 (en) | 1992-12-07 | 1994-06-15 | Nikko Kyodo Co., Ltd. | Semiconductor devices and method of manufacturing the same |
US5330629A (en) | 1992-12-15 | 1994-07-19 | At&T Bell Laboratories | Method for depositing aluminum layers on insulating oxide substrates |
US5551970A (en) | 1993-08-17 | 1996-09-03 | Otd Products L.L.C. | Dispersion strengthened copper |
US5590389A (en) | 1994-12-23 | 1996-12-31 | Johnson Matthey Electronics, Inc. | Sputtering target with ultra-fine, oriented grains and method of making same |
US5685491A (en) | 1995-01-11 | 1997-11-11 | Amtx, Inc. | Electroformed multilayer spray director and a process for the preparation thereof |
US5599740A (en) | 1995-11-16 | 1997-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Deposit-etch-deposit ozone/teos insulator layer method |
JPH09199976A (en) | 1996-01-18 | 1997-07-31 | Hitachi Ltd | Surface acoustic wave device |
US5997699A (en) | 1996-04-08 | 1999-12-07 | Micron Technology Inc. | Insitu faceting during deposition |
US6368469B1 (en) * | 1996-05-09 | 2002-04-09 | Applied Materials, Inc. | Coils for generating a plasma and for sputtering |
WO1997047783A1 (en) | 1996-06-14 | 1997-12-18 | The Research Foundation Of State University Of New York | Methodology and apparatus for in-situ doping of aluminum coatings |
US5693565A (en) | 1996-07-15 | 1997-12-02 | Dow Corning Corporation | Semiconductor chips suitable for known good die testing |
US5686335A (en) | 1996-07-22 | 1997-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel |
US6514390B1 (en) * | 1996-10-17 | 2003-02-04 | Applied Materials, Inc. | Method to eliminate coil sputtering in an ICP source |
KR100269287B1 (en) | 1996-11-22 | 2000-11-01 | 윤종용 | A method for forming hemi-spherical grain |
US5803342A (en) | 1996-12-26 | 1998-09-08 | Johnson Matthey Electronics, Inc. | Method of making high purity copper sputtering targets |
US5801100A (en) | 1997-03-07 | 1998-09-01 | Industrial Technology Research Institute | Electroless copper plating method for forming integrated circuit structures |
US6387805B2 (en) | 1997-05-08 | 2002-05-14 | Applied Materials, Inc. | Copper alloy seed layer for copper metallization |
US5891802A (en) * | 1997-07-23 | 1999-04-06 | Advanced Micro Devices, Inc. | Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects |
JP3616724B2 (en) | 1997-09-25 | 2005-02-02 | アルプス電気株式会社 | Manufacturing method of semiconductor device |
US6130156A (en) * | 1998-04-01 | 2000-10-10 | Texas Instruments Incorporated | Variable doping of metal plugs for enhanced reliability |
US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
US6165567A (en) * | 1999-04-12 | 2000-12-26 | Motorola, Inc. | Process of forming a semiconductor device |
US6113761A (en) * | 1999-06-02 | 2000-09-05 | Johnson Matthey Electronics, Inc. | Copper sputtering target assembly and method of making same |
US6099705A (en) * | 1999-09-08 | 2000-08-08 | United Microelectronics Corp. | Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer |
-
1999
- 1999-09-27 US US09/406,325 patent/US6432819B1/en not_active Expired - Fee Related
-
2000
- 2000-09-26 EP EP00308436A patent/EP1087431A3/en not_active Withdrawn
- 2000-09-27 SG SG200005556A patent/SG86443A1/en unknown
- 2000-09-27 JP JP2000335227A patent/JP2001220667A/en active Pending
- 2000-09-27 KR KR1020000056675A patent/KR20010030504A/en not_active Application Discontinuation
-
2002
- 2002-07-16 US US10/198,437 patent/US20020182887A1/en not_active Abandoned
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050098427A1 (en) * | 2003-11-11 | 2005-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | RF coil design for improved film uniformity of an ion metal plasma source |
US20070158179A1 (en) * | 2006-01-11 | 2007-07-12 | Anthony Ciancio | Method and apparatus for improving symmetry of a layer deposited on a semiconductor substrate |
WO2007102905A2 (en) * | 2006-01-11 | 2007-09-13 | Freescale Semiconductor Inc. | Method and apparatus for improving symmetry of a layer deposited on a semiconductor substrate |
WO2007102905A3 (en) * | 2006-01-11 | 2008-01-10 | Freescale Semiconductor Inc | Method and apparatus for improving symmetry of a layer deposited on a semiconductor substrate |
US20110192719A1 (en) * | 2008-10-24 | 2011-08-11 | Mitsubishi Materials Corporation | Sputtering target for forming thin film transistor wiring film |
WO2012040733A2 (en) * | 2010-09-24 | 2012-03-29 | Intel Corporation | Barrier layers |
WO2012040733A3 (en) * | 2010-09-24 | 2012-06-21 | Intel Corporation | Barrier layers |
CN111952263A (en) * | 2019-05-16 | 2020-11-17 | 上海交通大学 | Micron-sized single crystal copper interconnection structure and preparation method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR20010030504A (en) | 2001-04-16 |
EP1087431A3 (en) | 2003-05-21 |
US6432819B1 (en) | 2002-08-13 |
JP2001220667A (en) | 2001-08-14 |
SG86443A1 (en) | 2002-02-19 |
EP1087431A2 (en) | 2001-03-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6432819B1 (en) | Method and apparatus of forming a sputtered doped seed layer | |
US6391163B1 (en) | Method of enhancing hardness of sputter deposited copper films | |
KR100743330B1 (en) | Barrier applications for aluminum planarization | |
US6797620B2 (en) | Method and apparatus for improved electroplating fill of an aperture | |
US6562715B1 (en) | Barrier layer structure for copper metallization and method of forming the structure | |
US6627542B1 (en) | Continuous, non-agglomerated adhesion of a seed layer to a barrier layer | |
KR101031617B1 (en) | Aluminum sputtering while biasing wafer | |
US7645696B1 (en) | Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer | |
TW546393B (en) | PVD-IMP tungsten and tungsten nitride as a liner, barrier and/or seed layer for tungsten, aluminum and copper applications | |
US20040031680A1 (en) | One or more shields for use in a sputter reactor | |
US20060251872A1 (en) | Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof | |
US6200433B1 (en) | IMP technology with heavy gas sputtering | |
WO2002039500A2 (en) | Use of a barrier sputter reactor to remove an underlying barrier layer | |
KR100501460B1 (en) | Method of filling holes in a semiconductor structure using an adhesion layer deposited from ionized metal | |
US6528180B1 (en) | Liner materials | |
US20020093101A1 (en) | Method of metallization using a nickel-vanadium layer | |
US6429524B1 (en) | Ultra-thin tantalum nitride copper interconnect barrier | |
US6268284B1 (en) | In situ titanium aluminide deposit in high aspect ratio features | |
JP2000306862A (en) | Stepwise coating of sidewall of contact hole | |
US20020137338A1 (en) | Method for depositing copper films having controlled morphology and semiconductor wafers produced thereby |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: APPLIED MATERIALS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PAVATE, VIKRAM;NARASIMHAN, MURALI;REEL/FRAME:013122/0810 Effective date: 19990924 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |